A watchdog circuit with automatic configuration of timing cycle and control method thereof

Abstract

The present invention discloses a watchdog circuit for automatically configuring a timing cycle and a control method thereof. On the one hand, the present invention provides a watchdog circuit for automatically configuring a timing cycle, comprising a processor, the processor is connected to a synchronous output timer signal, the timer overflow signal output end of the synchronous output timer is connected to an external reset module signal for resetting the synchronous output timer, the synchronous output timer is also connected to a timer cycle configuration module signal for the processor to detect the timing cycle size control, thereby forming a watchdog circuit; the processor is connected to the timer cycle configuration module signal through a trigger module, thereby forming a watchdog timer cycle time automatic selection circuit. On the other hand, the present invention provides a control method for a watchdog circuit for automatically configuring a timing cycle. The present invention can effectively enhance the stability of the system circuit, improve the intelligence of the control, and meet the use needs.

Description

Technical Field

[0001] The invention belongs to the field of embedded electronic communication, and in particular relates to a watchdog circuit for automatically configuring a timing cycle, and also relates to a control method for the watchdog circuit for automatically configuring a timing cycle. Background Art

[0002] In the embedded field, the stability of the processor usually needs to be monitored by peripheral circuits. Most of the practices are to add a watchdog circuit to the peripheral circuit of the processor in the circuit. Therefore, the watchdog timer is a peripheral device often used to detect whether the microprocessor is abnormal. After being set, the watchdog timer monitors the signal from the microprocessor periodically. If the watchdog does not receive the trigger signal from the processor, it is considered that the microprocessor is abnormal in the working software or hardware, and the microprocessor circuit is forced to reset after the timing time is exceeded.

[0003] At present, watchdogs are divided into built-in watchdogs and external circuit hardware watchdogs. Most circuits use external hardware watchdog circuits. External hardware watchdogs need to be fed periodically and need to be controlled by software in a timely manner. The current watchdog circuit has a fixed timing period, generally between a few hundred milliseconds and a few seconds. In embedded systems and multi-task systems where user application tasks have strict real-time requirements, the software needs to feed the dog in a short interval and on time, which is quite difficult; some complex programs also require the ability to flexibly handle the watchdog timing period. Another existing method is to use an additional GPIO port to control the watchdog circuit with an unlock code. Specifically, before the microprocessor runs other real-time programs or when it is powered on, the watchdog output is turned off or the watchdog output signal is blocked. This method not only occupies hardware GPIO resources, but also turns off the watchdog for specific reasons or startup waiting. It cannot be reset and recovered after the software runs away, which is a serious hidden danger. Therefore, the current watchdog circuit control method still needs to be improved in design. The existing solution uses RC delay to enable the tri-state gate to delay the watchdog time circuit. The RC delay circuit is not suitable for restarting and resetting with power on. If the chip program is lost with power on, the RC delay is invalid in the reset state, and it is only effective when powered on for the first time. Therefore, there is an obvious imperfect design, and a new design is urgently needed to meet the needs of use. Summary of the invention

[0004] The first object of the present invention is to provide a watchdog circuit with automatic configuration timing cycle, which can effectively enhance the stability of the system circuit, improve the intelligence of control, and meet the use needs.

[0005] A second objective of the present invention is to provide a control method for the above circuit.

[0006] To achieve the first objective, the present invention provides a watchdog circuit for automatically configuring a timing cycle, comprising a processor, wherein the processor is connected to a synchronous output timer signal for monitoring the operation of the processor, wherein the dog feeding signal output end of the processor is connected to the clear signal end of the synchronous output timer, the synchronous signal output end of the synchronous output timer is connected to one end of the processor, the timer overflow signal output end of the synchronous output timer is connected to the reset end of the processor, the timer overflow signal output end of the synchronous output timer is also connected to an external reset module signal for resetting the synchronous output timer, the output end of the external reset module is connected to the reset end of the synchronous output timer, and the synchronous output timer is also connected to a timer cycle configuration module signal for processor detection timing cycle size control, thereby forming a watchdog circuit; the processor is connected to the timer cycle configuration module signal through a trigger module, thereby forming a watchdog timer cycle time automatic selection circuit.

[0007] Preferably, the timer period configuration module is a resistor or a capacitor or a register.

[0008] Preferably, the trigger module is provided with at least one trigger.

[0009] To achieve the second objective, the present invention provides a watchdog circuit control method for automatically configuring a timing cycle, comprising the following processing steps:

[0010] Step 1: The system is powered on, the processor is loaded and started, the synchronous output timer obtains the initialization cycle through the timer cycle configuration module, and the watchdog is turned on. If the processor loads the program normally within the initialization cycle and sends a watchdog feeding signal to the synchronous output timer, it will work normally. Otherwise, the synchronous output timer outputs a reset signal to the processor and the external reset module, so that the synchronous output timer and the processor are reset and restarted;

[0011] Step 2: After the processor starts working normally, it receives a synchronization signal with the initialization period as a period sent by the synchronous output timer, thereby determining the initialization period;

[0012] Step 3: When the initialization cycle needs to be changed, the processor sends a control signal to the trigger module according to the required cycle length, so that the trigger module selects the configuration combination in the timer cycle configuration module to obtain a new detection timing cycle and locks it through the trigger module;

[0013] Step 4: The processor controls to stop sending the dog feeding signal to the synchronous output timer, so that the synchronous output timer outputs a reset signal to the processor and the external reset module, so that the synchronous output timer and the processor are reset and restarted. When restarting, the trigger module is used to enable the synchronous output timer to obtain a new detection timing period through the timer period configuration module.

[0014] Preferably, the timer cycle configuration module is provided with a plurality of combination options corresponding to different cycle durations, and the trigger module is provided with a plurality of triggers accordingly.

[0015] Preferably, the initialization period preset by the timer period configuration module is greater than the time required for normal system startup.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] In the present invention, a synchronous output timer and a timer cycle configuration module and a trigger module are used to realize the watchdog operation and automatically configure the timing cycle as needed, which can effectively enhance the stability of the system circuit, improve the intelligence of the control, and meet the use needs. In the present invention, by sending a synchronization signal to the processor, the processor can obtain the configured timing cycle in real time, and can make real-time changes according to the use needs of the sleep or low-power mode, improve intelligence, and meet the use needs. In the present invention, the processor can independently select the watchdog timer cycle of the sleep operation, which is suitable for various situations such as the watchdog timer cycle needs to be adjusted after the program is upgraded to adapt to the requirements of the new program system. The present invention can reliably monitor the working status of the processor, and adopts a synchronous signal instead of RC or GPIO control to close the watchdog, thereby preventing the hidden danger that the watchdog cannot be automatically restored when it is closed under abnormal programs or running away. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of the present invention;

[0019] Figure 2 It is a control flow chart in the present invention. DETAILED DESCRIPTION

[0020] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0021] like Figure 1As shown, the present invention provides a watchdog circuit for automatically configuring a timing cycle, comprising a processor 105, the processor 105 is signal-connected to a synchronous output timer 103 for monitoring the operation of the processor 105, wherein the dog feeding signal output end of the processor 105 is connected to the clear signal end of the synchronous output timer 103, the synchronous signal output end of the synchronous output timer 103 is connected to one end of the processor 105, the timer overflow signal output end of the synchronous output timer 103 is connected to the reset end of the processor 105, the timer overflow signal output end of the synchronous output timer 103 is also signal-connected to an external reset module 101 for resetting the synchronous output timer 103, the output end of the external reset module 101 is connected to the reset end of the synchronous output timer 103, and the synchronous output timer 103 is also signal-connected to a timer cycle configuration module 102 for the processor 105 to detect the timing cycle size control, thereby forming a watchdog circuit; the processor 105 is signal-connected to the timer cycle configuration module 102 through the trigger module 104, thereby forming a watchdog timer cycle time automatic selection circuit.

[0022] The timer cycle configuration module 102 is a resistor or a capacitor or a register. The trigger module 104 is provided with at least one trigger. In this embodiment, the clock signal of the trigger in the trigger module 104 is provided by the processor. The timer cycle configuration module 102 is a resistor and forms a combination corresponding to different cycle durations through different resistance values ​​for use selection. Several triggers are set in the trigger module 104 corresponding to different resistance value combinations. After receiving the overflow signal of the synchronous output timer 103, the external reset module 101 sends a reset signal to control the synchronous output timer 103 to reset.

[0023] like Figure 2 The present invention also provides a watchdog circuit control method for automatically configuring a timing cycle, comprising the following processing steps:

[0024] Step 1: The system is powered on, the processor 105 is loaded and started, the synchronous output timer 103 obtains the initialization cycle through the timer cycle configuration module 102, and the watchdog operation is started. If the processor 105 loads the program normally within the initialization cycle and sends a watchdog feeding signal to the synchronous output timer 103, it will work normally. Otherwise, the synchronous output timer 103 outputs a reset signal to the processor 105 and the external reset module 101, so that the synchronous output timer 103 and the processor 105 are reset and restarted;

[0025] Step 2: After the processor 105 starts working normally, it receives a synchronization signal with the initialization period as a period sent by the synchronization output timer 103, thereby determining the initialization period;

[0026] Step 3: When the initialization cycle needs to be changed, the processor 105 sends a control signal to the trigger module 104 according to the required cycle length, so that the trigger module 104 selects the configuration combination in the timer cycle configuration module 102 to obtain a new detection timing cycle and locks it through the trigger module 104;

[0027] Step 4: The processor 105 controls to stop sending the dog feeding signal to the synchronous output timer 103, so that the synchronous output timer 103 outputs a reset signal to the processor 105 and the external reset module 101, so that the synchronous output timer 103 and the processor 105 are reset and restarted. When restarting, the trigger module 104 is used to make the synchronous output timer 103 obtain a new detection timing period through the timer period configuration module 102.

[0028] Several groups of combination selections corresponding to different cycle durations are set in the timer cycle configuration module 102, and several triggers are set accordingly in the trigger module 104. The initialization cycle preset in the timer cycle configuration module 102 is greater than the time required for the normal startup of the system. The system power-on in step 1 is the first power-on operation of the system of the present invention. In step 4, the processor 105 stops feeding the dog through software operation, and the configuration combination selection in the timer cycle configuration module 102 is locked through the trigger module 104, so as to meet the need to change the timing cycle of the watchdog timer in sleep or low power consumption mode. At the same time, the use of a synchronous signal can replace the RC or GPIO control in the prior art to turn off the watchdog, preventing the hidden danger of abnormal program or runaway, and turning off the watchdog cannot automatically recover, thereby effectively improving reliability and meeting usage needs.

[0029] In this embodiment, the initialization period reserved by the timer period configuration module 102 is long enough to meet the time required for system startup. The synchronization signal output by the synchronization output timer 103 periodically outputs a square wave pulse signal after power-on and the period is consistent with the configuration on the timer period configuration module 102.

[0030] The above are only preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the present invention through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A watchdog circuit control method for automatically configuring a timing period, characterized in that: The method relates to a watchdog circuit, the watchdog circuit comprising a processor (105), the processor (105) being connected to a synchronous output timer (103) signal for monitoring the operation of the processor (105), wherein a feeding signal output terminal of the processor (105) is connected to a clear signal terminal of the synchronous output timer (103), a synchronous signal output terminal of the synchronous output timer (103) is connected to one terminal of the processor (105), a timer overflow signal output terminal of the synchronous output timer (103) is connected to a reset terminal of the processor (105), and a timer overflow signal output terminal of the synchronous output timer (103) is connected to a reset terminal of the processor (105). The signal output end is also connected to an external reset module (101) for resetting the synchronous output timer (103) by signal, the output end of the external reset module (101) is connected to the reset end of the synchronous output timer (103), and the synchronous output timer (103) is also connected to a timer cycle configuration module (102) for detecting the timing cycle size control by a processor (105), thereby forming a watchdog circuit; the processor (105) is connected to the timer cycle configuration module (102) by signal through a trigger module (104), thereby forming a watchdog timer cycle time automatic selection circuit; The method comprises the following processing steps, Step 1: The system is powered on, the processor (105) is loaded and started, the synchronous output timer (103) obtains the initialization cycle through the timer cycle configuration module (102), and the watchdog operation is started. If the processor (105) loads the program normally within the initialization cycle and sends a watchdog feeding signal to the synchronous output timer (103), it will work normally. Otherwise, the synchronous output timer (103) outputs a reset signal to the processor (105) and the external reset module (101), so that the synchronous output timer (103) and the processor (105) are reset and restarted; Step 2: After the processor (105) starts working normally, it receives a synchronization signal with an initialization period as a period sent by the synchronization output timer (103), thereby determining the initialization period; Step 3: When the initialization cycle needs to be changed, the processor (105) sends a control signal to the trigger module (104) according to the required cycle length, so that the trigger module (104) selects the configuration combination in the timer cycle configuration module (102) to obtain a new detection timing cycle and locks it through the trigger module (104); Step 4: The processor (105) controls to stop sending the dog feeding signal to the synchronous output timer (103), so that the synchronous output timer (103) outputs a reset signal to the processor (105) and the external reset module (101), so that the synchronous output timer (103) and the processor (105) are reset and restarted. When restarting, the trigger module (104) is used to enable the synchronous output timer (103) to obtain a new detection timing period through the timer period configuration module (102).

2. A watchdog circuit control method for automatically configuring a timing period according to claim 1, characterized in that: The timer cycle configuration module (102) is provided with a plurality of combination options corresponding to different cycle durations, and the trigger module (104) is provided with a plurality of triggers correspondingly.

3. A watchdog circuit control method for automatically configuring a timing period according to claim 1, characterized in that: The initialization period preset by the timer period configuration module (102) is greater than the time required for normal system startup.

4. A watchdog circuit control method for automatically configuring a timing cycle according to claim 1, characterized in that: The timer period configuration module (102) is a resistor or a capacitor or a register.

5. The method for controlling a watchdog circuit with automatic configuration of a timing cycle according to claim 1, characterized in that: The trigger module (104) is provided with at least one trigger.

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