Semiconductor device and semiconductor system having the same

Abstract

Embodiments of the present disclosure relate to semiconductor devices and semiconductor systems having the same. A semiconductor device includes: a pulse signal output circuit that provides a pulse signal to a transmitting electrode of an electrode pair; a current converter that converts a first current generated at a receiving electrode into a second current; a current-controlled oscillator that outputs an oscillation signal whose frequency depends on the second current; and a counter that counts the number of oscillations of the oscillation signal within each predetermined period; wherein the current converter includes a first constant current source and outputs a combined current of a first constant current source and the first current as the second current in response to the pulse signal, so that the semiconductor device suppresses an increase in circuit size.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-098605 filed on May 27, 2019 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a semiconductor system including the same, and also relates to a semiconductor device suitable for suppressing an increase in circuit scale, for example, and a semiconductor system including the same. Background Art

[0004] In the technical field of touch keys and touch screens, capacitive touch sensor circuits are generally used. Japanese Unexamined Patent Application Publication No. 2017-204900 (Patent Document 1) discloses a configuration of a mutual capacitive touch sensor for detecting whether a touch electrode is touched by a finger.

[0005] The touch sensor includes a power supply voltage step-down circuit for generating a constant voltage applied to a pair of touch electrodes to generate an electric field in the pair of touch electrodes; a current-controlled oscillator for outputting a clock signal having a frequency corresponding to the value of the flowing current when the constant voltage is applied from the power supply voltage step-down circuit to the touch electrodes; and a counter for counting the number of oscillations within each predetermined cycle of the clock signal output from the current-controlled oscillator. The touch sensor is provided with a tank capacitor for suppressing variations in the constant voltage generated by the power supply voltage step-down circuit. Summary of the Invention

[0006] However, conventional touch sensor configurations require a pair of power supply voltage drop circuits and box capacitors for each touch electrode pair, leading to an increase in circuit size. In particular, when sensing multiple touch electrode pairs in parallel, conventional touch sensor configurations require multiple sets of power supply voltage drop circuits and box capacitors corresponding to the multiple touch electrode pairs, significantly increasing circuit size. Other objects and novel features will become apparent from the description and accompanying drawings of this specification.

[0007] According to one embodiment, a semiconductor device includes: a pulse signal output circuit that provides a pulse signal to a transmitting electrode in an electrode pair, the electrode pair including a transmitting electrode and a receiving electrode; a current converter that converts a first current generated at the receiving electrode into a second current; a current-controlled oscillator that outputs an oscillation signal whose frequency depends on the second current; and a counter that counts the number of oscillations of the oscillation signal within each predetermined cycle. The current converter includes: a first constant current source that outputs a first constant current; a first transistor that is diode-connected and has a source-drain path through which a combined current of the first constant current and the first current flows; a second transistor that is a current mirror connected to the first transistor; and a third transistor that is serially coupled to the second transistor and outputs the second current by being turned on and off in response to the pulse signal.

[0008] According to the above-described embodiments, it is possible to provide a semiconductor device capable of suppressing an increase in circuit size and a semiconductor system including the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram showing a configuration example of a semiconductor device according to the first embodiment.

[0010] Figure 2 It is shown in Figure 1 A circuit diagram showing a specific configuration of a current converter provided in a semiconductor device is shown.

[0011] Figure 3 is shown for illustration purposes only. Figure 2 Graph of the current waveform of the operation of the current converter shown in FIG.

[0012] Figure 4 It is shown in Figure 1 A diagram showing the relationship between the input current and the output oscillation frequency of a current controlled oscillator provided in the semiconductor device shown.

[0013] Figure 5 is a circuit diagram showing a specific configuration example of a current converter provided in the semiconductor device according to the second embodiment.

[0014] Figure 6 is shown for illustration purposes only. Figure 5 Graph of current waveforms showing the operation of the current converter shown in FIG.

[0015] Figure 7is a circuit diagram showing a specific configuration example of a current converter provided in the semiconductor device according to the third embodiment.

[0016] Figure 8 is a circuit diagram showing a specific configuration example of a current converter provided in the semiconductor device according to the fourth embodiment.

[0017] Figure 9 is a diagram showing a configuration example of a sensor system to which the semiconductor device according to the first embodiment is applied. DETAILED DESCRIPTION

[0018] For the purpose of clarity, the following description and drawings are appropriately omitted and simplified. In addition, the elements described in the accompanying drawings as function blocks for performing various processes can be configured as a CPU (central processing unit), memory and other circuits in terms of hardware, and can be implemented by a program loaded into the memory in terms of software. Therefore, it will be understood by those skilled in the art that these function blocks can be implemented in various forms only by hardware, only by software or by a combination of hardware and software, and the present invention is not limited to any one of them. In the accompanying drawings, the same elements are represented by the same reference numerals, and their repeated description is omitted when necessary.

[0019] Moreover, the above-mentioned program can be stored and provided to the computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memory, CD-R, CD-R / W), solid-state memories (e.g., mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs, flash ROMs, RAMs (random access memories)). The program can also be supplied to the computer via various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transient computer-readable media can provide the program to the computer via wired or wireless communication paths (such as electrical wires and optical fibers).

[0020] First embodiment

[0021] Figure 1 This figure shows an example configuration of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 according to this embodiment is used as a mutual capacitance touch sensor and has the function of sensing a touch electrode pair without using a power supply voltage drop circuit or a box capacitor. Therefore, the semiconductor device 1 according to this embodiment can suppress an increase in circuit size. A detailed description will be given below.

[0022] like Figure 1As shown, the semiconductor device 1 includes a pulse signal output circuit 11 , a driver 12 , a current converter 13 , a current controlled oscillator (CCO) 14 , a counter 15 , and terminals TX1 and TR1 . Figure 1 The touch electrode pair TP1 is also shown in FIG. Figure 1 Only components of a capacitance detection unit are shown, which detects a change in capacitance of the touch electrode pair TP1 .

[0023] Touch electrode pair TP1 includes a transmitting electrode PX1 and a receiving electrode PR1. Transmitting electrode PX1 is connected to terminal TX1 of semiconductor device 1. Receiving electrode PR1 is connected to terminal TR1 of semiconductor device 1. When semiconductor device 1 applies a voltage between the electrodes of touch electrode pair TP1, capacitance C1 is formed between the electrodes of touch electrode pair TP1.

[0024] For example, when the grounded finger FNG and the touch electrode pair TP1 are sufficiently separated from each other, the capacitance Cf formed between the finger FNG and the electrodes PX1 and PR1 is negligibly small compared to the capacitance C1 formed between the electrodes PX1 and PR1.

[0025] On the other hand, as the distance between finger FNG and touch electrode pair TP1 decreases, the number of electric force lines formed between electrodes PX1 and PR1 that are absorbed by finger FNG increases. Therefore, as the distance between finger FNG and touch electrode pair TP1 decreases, the capacitance C1 formed between electrodes PX1 and PR1 decreases. Semiconductor device 1 can detect that finger FNG is touching (or approaching) touch electrode pair TP1 by detecting this change in capacitance C1.

[0026] In the semiconductor device 1 , the pulse signal output circuit 11 outputs a pulse signal PS1 having a predetermined frequency. The driver 12 outputs the pulse signal PS1 to the terminal TX1 . Thus, the pulse signal PS1 is applied to the transmitter electrode PX1 in the touch electrode pair TP1 via the terminal TX1 .

[0027] The pulse signal switching circuit 16 selects the pulse signal PS1 or its inverted signal based on the switching signal MODE and outputs the selected pulse signal as the pulse signal P1. The pulse signal P1 is input to the current converter 13. In this embodiment, the pulse signal PS1 is selected when MODE is 1, and the inverted signal of the pulse signal PS1 is selected when MODE is 0.

[0028] The current converter 13 converts the current Iin generated in the receiving electrode PR1 by changing the pulse signal PS1 applied to the transmitting electrode PX1 into the current Iout, which has a current value proportional to the capacitance C1 and the amplitude of the pulse signal PS1, and outputs the current Iout.

[0029] <Specific Configuration Example of Current Converter 13>

[0030] Figure 2 1 is a circuit diagram showing a specific configuration example of the current converter 13. Figure 2 As shown, the current converter 13 includes a P-channel MOS transistor (hereinafter simply referred to as a transistor) MP1 and N-channel MOS transistors (hereinafter simply referred to as transistors) MN1 to MN3.

[0031] In transistor MP1, the source is coupled to power supply voltage terminal VDD, the drain is coupled to node N1, and bias voltage VB is applied to the gate. That is, transistor MP1 constitutes a constant current source. Therefore, a constant current (idle current) Iidle flows between the source and drain of transistor MP1.

[0032] In the transistor MN1 (first transistor), the source is coupled to the ground voltage terminal GND, and the drain and gate are coupled to the node N1. That is, the transistor MN1 is diode-connected.

[0033] Terminal TR1 is further connected to node N1. Therefore, constant current Iidle is supplied from transistor MP1 to node N1, current Iin is supplied from receiving electrode PR1 to node N1 via terminal TR1, and a combined current (Iidle+Iin) of constant current Iidle and current Iin flows between the source and drain of transistor MN1.

[0034] In the transistor MN2 (second transistor), the source is coupled to the ground voltage terminal GND, the drain is coupled to the node N2, and the gate is coupled to the node N1. That is, the transistor MN2 is a current mirror connected to the transistor MN1. Therefore, the current flowing between the source and drain of the transistor MN2 is proportional to the current flowing between the source and drain of the transistor MN1. Figure 2 In FIG. 4 , a current (Iidle+Iin) flows between the source and drain of the transistor MN2 , and its current value is the same as the current value of the current flowing between the source and drain of the transistor MN1 .

[0035] In the transistor MN3 (third transistor), a source is connected to the node N2, a drain is connected to the output terminal of the current converter 13, and a gate is applied with the pulse signal P1. The transistor MN3 is turned on and off by the pulse signal P1.

[0036] <Operation of Current Converter 13>

[0037] Next, we will refer to Figure 3 The operation of the current converter 13 is described. Figure 3 1 is a diagram showing a current waveform for explaining the operation of the current converter 13 .

[0038] First, the operation of the current converter 13 when the pulse signal switching circuit 16 outputs the output pulse signal PS1 as it is as the pulse signal P1 (when MODE is 1) will be described.

[0039] For example, when pulse signal PS1 rises, positive current Iin is transiently generated at receiving electrode PR1 (i.e., terminal TR1). At this time, in current converter 13, transistor MN3 switches from off to on in response to the rise of pulse signal P1. Consequently, current Iidle + Iin flows between the source and drain of transistor MN3. When pulse signal P1 is at an H level, current converter 13 outputs current Iidle + Iin as current Iout.

[0040] Thereafter, when pulse signal PS1 falls, negative current Iin transiently generates in receiving electrode PR1 in response to the fall of pulse signal PS1. At this time, in current converter 13, transistor MN3 switches from on to off in response to the fall of pulse signal P1. Consequently, no current flows between the source and drain of transistor MN3. When pulse signal P1 is at an L level, current converter 13 maintains output current Iout at 0 A.

[0041] In other words, the current converter 13 outputs a current obtained by multiplying the current Iidle+Iin by the duty ratio of the pulse signal P1 as the current Iout.

[0042] Next, the operation of the current converter 13 when the pulse signal switching circuit 16 outputs the inverted signal of the pulse signal PS1 as the pulse signal P1 (when MODE is 0) will be described.

[0043] For example, when pulse signal PS1 rises, positive current Iin is transiently generated in receiving electrode PR1 (i.e., terminal TR1). At this time, in current converter 13, transistor MN3 switches from on to off in response to the falling edge of pulse signal P1. Consequently, no current flows between the source and drain of transistor MN3. When pulse signal P1 is at an L level, current converter 13 maintains output current Iout at 0 A.

[0044] Thereafter, when pulse signal PS1 falls, negative current Iin transiently flows through receiving electrode PR1 in response to the falling edge of pulse signal PS1. At this point, in current converter 13, transistor MN3 switches from off to on in response to the rising edge of pulse signal P1. Consequently, current Iidle - Iin flows between the source and drain of transistor MN3. When pulse signal P1 is at an H level, current converter 13 outputs current Iidle - Iin as current Iout.

[0045] In other words, the current converter 13 outputs a current obtained by multiplying the current Iidle−Iin by the duty ratio of the pulse signal P1 as the current Iout.

[0046] The current-controlled oscillator 14 outputs a clock signal (oscillation signal) CLK2, the frequency of which depends on the current Iout output from the current converter 13. Specifically, the current-controlled oscillator 14 includes a ring oscillator and a buffer circuit. In the ring oscillator, multiple inverter circuits are connected in a ring shape, and the delay time of these multiple inverter circuits varies according to the current Iout. The buffer circuit amplifies the output of the last inverter circuit among the multiple inverter circuits and outputs the amplified output as the clock signal CLK2. The counter 15 counts the number of oscillations of the clock signal CLK2 within each predetermined period and outputs a count value NC2.

[0047] Figure 4 is a diagram showing the relationship between the input current and the output oscillation frequency of the current controlled oscillator 14. For example, when the value of the current Iout increases, the delay time of the inverter provided in the current controlled oscillator 14 decreases, causing the frequency of the clock signal CLK2 to increase, and thus, the count value NC2 to increase. On the other hand, when the value of the current Iout decreases, the delay time of the inverter provided in the current controlled oscillator 14 increases, causing the frequency of the clock signal CLK2 to decrease, and thus, the count value NC2 to decrease.

[0048] The semiconductor device 1 can obtain the capacitance value of the capacitance C1 of the touch electrode pair TP1 based on the count value NC2 when the current value of the current Iout is Iidle (i.e., Iin=0) and the current difference Iin of the count value NC2 when the current value of the current Iout is Iidle+Iin (or Iidle-Iin).

[0049] As described above, the semiconductor device 1 according to this embodiment detects changes in the capacitance of the touch electrode pair TP1 by using a current converter 13 that does not include a power supply voltage reduction circuit including an amplifier or the like. The semiconductor device 1 according to this embodiment also does not require a box capacitor. Therefore, the semiconductor device 1 according to this embodiment can suppress increases in circuit size. Therefore, even when implementing a circuit configuration for measuring the capacitances of multiple touch electrode pairs in parallel, the semiconductor device 1 according to this embodiment can suppress increases in circuit size.

[0050] In this embodiment, although the pulse signal PS1 or its inverted signal selected by the pulse signal switching circuit 16 is input to the current converter 13, the present invention is not limited thereto. Only one of the pulse signal PS1 and the inverted pulse signal may be input to the current converter 13. Alternatively, the pulse signal switching circuit 16 may be provided between the pulse signal output circuit 11 and the driver 12, the pulse signal PS1 may be selectively input to the current converter 13, and the pulse signal PS1 and its inverted signal may be selectively input to the driver 12.

[0051] In this embodiment, the following example describes a case where the capacitance value of the capacitance C1 of the touch electrode pair TP1 is obtained by calculating the difference current Iin based on the count value NC2 when the current value of the current Iout indicates Iidle and the count value NC2 when the current value of the current Iout indicates Iidle+Iin (or Iidle-Iin), but the present invention is not limited to this. The capacitance value of the capacitance C1 of the touch electrode pair TP1 can be obtained based on the difference between the count value NC2 when the current value of the current Iout indicates Iidle+Iin and the count value NC2 when the current value of the current Iout indicates Iidle-Iin. In this case, since the difference between the count values ​​corresponds to the difference current 2*Iin and the variation component of the constant current Iidle is eliminated, the measurement accuracy of the variation in the capacitance value of the capacitance C1 is improved.

[0052] Second embodiment

[0053] Next, a semiconductor device 2 according to a second embodiment will be described. Compared to the semiconductor device 1, the semiconductor device 2 according to this embodiment includes a current converter 23 instead of the current converter 13. The remaining configuration of the semiconductor device 2 is the same as that of the semiconductor device 1, and therefore its description is omitted.

[0054] Figure 5 2 is a circuit diagram showing a specific configuration example of the current converter 23. Figure 5As shown, compared with the current converter 13, the current converter 23 further includes a P-channel MOS transistor (hereinafter simply referred to as a transistor) MP2 and N-channel MOS transistors (hereinafter simply referred to as transistors) MN4 to MN7.

[0055] In the transistor MP2, the source is coupled to the power supply voltage terminal VDD, the drain is coupled to the node N3, and the bias voltage VB is applied to the gate. That is, the transistor MP2 constitutes a constant current source. Figure 5 In this case, the current driving capability of the transistor MP2 is twice that of the transistor MP1. Therefore, the constant current (reactive current) 2*Iidle flowing between the source and drain of the transistor MP2 is twice the constant current Iidle flowing between the source and drain of the transistor MP1.

[0056] In the transistor MN4 (fourth transistor), the source is coupled to the ground voltage terminal GND, the drain is coupled to the node N3, and the gate is coupled to the node N1. That is, the transistor MN4 is a current mirror connected to the transistor MN1. Therefore, the current flowing between the source and drain of the transistor MN4 is proportional to the current flowing between the source and drain of the transistor MN1. Figure 5 In FIG. 4 , the current Iidle+Iin flowing between the source and drain of the transistor MN4 has the same current value as the current flowing between the source and drain of the transistor MN1 .

[0057] In transistor MN5 (fifth transistor), the source is coupled to the ground voltage terminal GND, and the drain and gate are coupled to node N3. That is, transistor MN5 is diode-connected. Therefore, the difference current (Iidle-Iin) between the constant current 2*Iidle flowing from transistor MN2 to node N3 and the current (Iidle+Iin) flowing from node N3 to transistor MN4 flows between the source and drain of transistor MN5.

[0058] The transistor MN6 (sixth transistor) has a source coupled to the ground voltage terminal GND, a drain coupled to the node N4, and a gate coupled to the node N3. That is, the transistor MN6 is a current mirror connected to the transistor MN5. Therefore, the current flowing between the source and drain of the transistor MN6 is proportional to the current flowing between the source and drain of the transistor MN5. Figure 5 In FIG. 4 , the current Iidle−Iin flowing between the source and drain of the transistor MN6 has the same current value as the current flowing between the source and drain of the transistor MN5 .

[0059] In transistor MN7 (seventh transistor), the source is connected to node N4, the drain is connected to the output terminal of current converter 23, and the inverted signal PB1 of pulse signal P1 is applied to the gate. Transistor MN7 is turned on and off by pulse signal PB1 in a complementary manner to transistor MN3.

[0060] Since the other configurations of the current converter 23 are the same as those of the current converter 13 , descriptions thereof are omitted.

[0061] <Operation of Current Converter 23>

[0062] Next, we will refer to Figure 6 The operation of the current converter 23 is described. Figure 6 2 is a diagram showing a current waveform for explaining the operation of the current converter 23 .

[0063] First, the operation of the current converter 23 when the pulse signal switching circuit 16 outputs the pulse signal PS1 as it is as the pulse signal P1 (when MODE is 1) will be described.

[0064] For example, when pulse signal PS1 rises, positive current Iin is transiently generated in receiving electrode PR1 (i.e., terminal TR1). At this time, in current converter 23, transistor MN3 is turned on by the rise of pulse signal P1, and transistor MN7 is turned off by the fall of pulse signal PB1. Therefore, current Iidle + Iin flows between the source and drain of transistor MN3. When pulse signal PS1 is at an H level, current converter 23 outputs current Iidle + Iin as current Iout. Since current Iin at this time has positive polarity, current Iout can also be expressed as current Iidle + |Iin|.

[0065] Thereafter, when pulse signal PS1 falls, a negative current Iin is transiently generated in receiving electrode PR1 in response to the falling pulse signal PS1. At this time, in current converter 13, transistor MN3 is turned off by the falling pulse signal P1, and transistor MN7 is turned on by the rising pulse signal PB1. Therefore, current Iidle - Iin flows between the source and drain of transistor MN7. When pulse signal PS1 is at an L level, current converter 23 outputs current Iidle - Iin as current Iout. Since current Iin at this time has a negative polarity, current Iout can also be expressed as current Iidle + |Iin|.

[0066] That is, the current converter 23 outputs the current Iidle+|2*Iin| as the current Iout.

[0067] Next, the operation of the current converter 13 when the pulse signal switching circuit 16 outputs the inverted signal of the pulse signal PS1 as the pulse signal P1 (when MODE is 0) will be described.

[0068] For example, when pulse signal PS1 rises, positive current Iin is transiently generated in receiving electrode PR1 (i.e., terminal TR1). At this time, in current converter 23, transistor MN3 is turned off by the falling pulse signal P1, and transistor MN7 is turned on by the rising pulse signal PB1. Therefore, current Iidle-Iin flows between the source and drain of transistor MN7. When pulse signal PS1 is at an H level, current converter 23 outputs current Iidle-Iin as current Iout. Since current Iin at this time has positive polarity, current Iout can also be expressed as current Iidle-|Iin|.

[0069] Thereafter, when pulse signal PS1 falls, a negative current Iin is transiently generated in receiving electrode PR1 in response to the falling pulse signal PS1. At this time, in current converter 13, transistor MN3 is turned on by the rising pulse signal P1, and transistor MN7 is turned off by the falling pulse signal PB1. Therefore, current Iidle + Iin flows between the source and drain of transistor MN3. When pulse signal PS1 is at an L level, current converter 23 outputs current Iidle + Iin as current Iout. Since current Iin has a negative polarity at this time, current Iout can also be expressed as current Iidle - |Iin|.

[0070] That is, the current converter 23 outputs the current Iidle-|2*Iin| as the current Iout.

[0071] As described above, the semiconductor device 2 according to this embodiment detects changes in the capacitance of the touch electrode pair TP1 by using a current converter 23 that does not include a power supply voltage reduction circuit including an amplifier or other components. The semiconductor device 2 according to this embodiment also does not require a box capacitor. Therefore, the semiconductor device 2 according to this embodiment can suppress increases in circuit size. Therefore, even when a circuit configuration for measuring the capacitances of multiple touch electrode pairs in parallel is implemented, the semiconductor device 2 according to this embodiment can suppress increases in circuit size.

[0072] Furthermore, in the semiconductor device 2 according to this embodiment, the current converter 23 outputs a current Iout that includes both the positive current Iin and the negative current Iin generated at the receiving electrode PR1. Therefore, the semiconductor device 2 according to this embodiment can improve detection accuracy to twice that of the semiconductor device 1. Alternatively, the semiconductor device 2 according to this embodiment can achieve equivalent detection accuracy in approximately half the time compared to the case of the semiconductor device 1.

[0073] In this embodiment, although the pulse signal PS1 or its inverted signal selected by the pulse signal switching circuit 16 is input to the current converter 23 , the present invention is not limited thereto.

[0074] In this embodiment, the following example is described: the capacitance value of the capacitance C1 of the touch electrode pair TP1 is obtained by the difference current |2*Iin| between the count value NC2 when the current value of the current Iout indicates Iidle and the count value NC2 when the current value of the current Iout indicates Iidle + |2*Iin| (or Iidle - |2*Iin|), but the present invention is not limited to this. The capacitance value of the capacitance C1 of the touch electrode pair TP1 can be obtained based on the difference between the count value NC2 when the current value of the current Iout indicates Iidle + |2*Iin| and the count value NC2 when the current value of the current Iout indicates Iidle - |2*Iin|. In this case, since the difference between the count values ​​corresponds to the difference current 4*Iin and the variation component of the constant current Iidle is eliminated, the measurement accuracy of the variation in the capacitance value of the capacitance C1 is improved.

[0075] Third embodiment

[0076] Next, a semiconductor device 3 according to a third embodiment will be described. Compared to the semiconductor device 2, the semiconductor device 3 according to this embodiment includes a current converter 33 instead of the current converter 23. The remaining configuration of the semiconductor device 3 is the same as that of the semiconductor device 2, and therefore its description is omitted.

[0077] Figure 7 3 is a circuit diagram showing a specific configuration example of the current converter 33. Figure 7 As shown, compared with the current converter 23, the current converter 33 further includes P-channel MOS transistors (hereinafter referred to as transistors) MP3 and MP4 and N-channel MOS transistors (hereinafter referred to as transistors) MN8 and MN9. The transistors MP3, MP4, MN8, and MN9 constitute a current mirror circuit.

[0078] In the transistor MN8 (eighth transistor), the source is connected to the ground voltage terminal GND, the drain is connected to the node 5, and the gate is connected to the node N1. That is, the transistor MN8 is a current mirror connected to the transistor MN1. Therefore, the current flowing between the source and drain of the transistor MN8 is proportional to the current flowing between the source and drain of the transistor MN1. Figure 7 In FIG. 4 , the current Iidle+Iin flowing between the source and drain of the transistor MN8 has the same current value as the current flowing between the source and drain of the transistor MN1 .

[0079] In transistor MP3 (ninth transistor), the source is coupled to power supply terminal VDD, and the drain and gate are coupled to node N5. In transistor MP4 (tenth transistor), the source is coupled to power supply terminal VDD, the drain is coupled to node N6, and the gate is coupled to node N5.

[0080] In the transistor MN9 (eleventh transistor), the source is coupled to the ground voltage terminal GND, and the drain and gate are coupled to the node N6. Therefore, the current flowing between the source and drain of the transistor MN9 is proportional to the current flowing between the source and drain of the transistor MN8. Figure 7 In FIG. 4 , the current Iidle+Iin flowing between the source and drain of the transistor MN8 and the current flowing between the source and drain of the transistor MN9 have the same current value.

[0081] Here, the gate of the transistor MN2 is coupled to the node N6 instead of the node N1. That is, the voltage of the node N1 is applied to the gate of the transistor MN2 through the current mirror circuit composed of the transistors MP3, MP4, MN8 and MN9.

[0082] Since the other configurations of the current converter 33 are the same as those of the current converter 23 , descriptions thereof are omitted.

[0083] The semiconductor device 3 of this embodiment is as effective as the semiconductor device 2. Furthermore, in the semiconductor device 3 of this embodiment, the current converter 33 is configured so that the pulse current waveform of the current Iin is not directly applied to the gate of the transistor MN7 by providing a current mirror circuit between the gate of the transistor MN7 and the current input terminal of the current converter 33. Therefore, the current converter 33 can make the current waveform of the current Iout flat (blunt). As a result, the current Iout is suppressed within the input current range of the current-controlled oscillator 14 of the next stage, resulting in improved measurement characteristics.

[0084] In the present embodiment, in addition to the current converter 23 provided in the semiconductor device 2, a current mirror circuit is added between the gate of the transistor MN7 and the current input of the current converter 33. Of course, even in the current converter 13 provided in the semiconductor device 1, the measurement characteristics are improved by adding the current mirror circuit between the gate of the transistor MN7 and the current input of the current converter 33.

[0085] Fourth embodiment

[0086] Next, a semiconductor device 4 according to a fourth embodiment will be described. Compared to semiconductor device 3, semiconductor device 4 according to this embodiment includes a current converter 43 instead of current converter 33, and further includes a dummy transistor MP6. The remaining configuration of semiconductor device 4 is the same as that of semiconductor device 3, and therefore its description will be omitted.

[0087] Figure 8 4 is a circuit diagram showing a specific configuration example of the current converter 43. Figure 8 As shown, the current converter 43 further includes N-channel MOS transistors MN10 and MN11 compared to the current converter 33. The current converter 43 includes an output terminal OUT for outputting the current Iout and an output terminal OUTB for outputting the current IoutB.

[0088] In transistor MN10 (the twelfth transistor), the source is coupled to node N2, the drain is coupled to output terminal OUTB of current converter 43, and the gate is supplied with an inverted signal PB1 of pulse signal P1. Transistor MN10 is turned on and off by pulse signal PB1. In transistor MN11 (the thirteenth transistor), the source is coupled to node N4, the drain is coupled to output terminal OUTB of current converter 43, and the gate is supplied with pulse signal P1. Transistor MN11 is turned on and off by pulse signal P1. That is, transistors MN10 and MN11 are turned on and off in a complementary manner to transistors MN3 and MN7.

[0089] Therefore, when the current value of the current Iout flowing through the output terminal OUT indicates Iidle+|2*Iin|, the current value of the current IoutB flowing through the output terminal OUTB indicates Iidle-|2*Iin|. On the other hand, when the current value of the current Iout flowing through the output terminal OUT indicates Iidle-|2*Iin|, the current value of the current IoutB flowing through the output terminal OUTB indicates Iidle+|2*Iin|.

[0090] The dummy transistor MP6 is a P-channel MOS transistor, and is provided to correspond to the P-channel MOS transistor MP5 provided in the input stage of the current controlled oscillator 14. Preferably, the dummy transistor MP6 has the same size and the same shape as the transistor MP5.

[0091] Specifically, in the transistor MP5 provided in the input stage of the current controlled oscillator 14, the source is coupled to the power supply voltage terminal VDD, and the drain and gate are coupled to the output terminal OUT of the current converter 43. In the dummy transistor MP6, the source is coupled to the power supply voltage terminal VDD, and the drain and gate are coupled to the output terminal OUTB of the current converter 43.

[0092] For example, parasitic capacitances such as junction capacitances and interconnection capacitances of transistors MN2, MN3, and MN10 exist at node N2. For example, parasitic capacitances such as junction capacitances and interconnection capacitances of transistors MN6, MN7, and MN11 exist at node N4.

[0093] Here Figure 7 In the current converter 33 shown, when the transistor MN3 is turned off, the voltage of the node N2 is discharged to the ground level 0 V. Therefore, when the transistor MN3 is switched from off to on, not only the desired current Iidle+Iin but also an additional current for charging and discharging the parasitic capacitance of the node N2 flows between the source and drain of the transistor. Similarly, Figure 7 In the current converter 33 shown in FIG, when transistor MN7 is turned off, the voltage at node N4 is discharged to ground level 0V. Therefore, when transistor MN7 switches from off to on, not only the desired current Idle-Iin but also the additional current for charging and discharging the parasitic capacitance of node N4 flows between the source and drain of transistor MN7. Therefore, the additional current for charging and discharging the parasitic capacitance of nodes N2 and N4 is included in current Iout as an error component. This error component increases in proportion to the increase in the frequency of pulse signal P1.

[0094] On the other hand, Figure 8 In the current converter 43 shown, even if the transistor MN3 is turned off, the transistor MN10 is turned on to supply charge to the node N2, so that the voltage of the node N2 is not discharged to the ground level. Therefore, when the transistor MN3 is switched from off to on, the excess current flowing between the source and drain of the transistor MN3 (the current for charging and discharging the parasitic capacitance) is suppressed. Similarly, in Figure 8In the illustrated current converter 43, even when transistor MN7 is turned off, the voltage at node N4 is not discharged to ground level because transistor MN11 is turned on to supply charge to node N4. Therefore, when transistor MN7 is subsequently switched from off to on, the excess current (current used to charge and discharge the parasitic capacitance) flowing between the source and drain of transistor MN7 is suppressed. Consequently, the error component included in current Iout is suppressed.

[0095] In this embodiment, transistors MN10 and MN11 are added to current converter 33 provided in semiconductor device 3 to prevent nodes N2 and N4 from being discharged to ground level, but the present invention is not limited to this. Of course, transistor MN10 may be added to current converter 13 provided in semiconductor device 1 to prevent node N2 from being discharged to ground level. Alternatively, transistors MN10 and MN11 may be added to current converter 23 provided in semiconductor device 2 to prevent nodes N2 and N4 from being discharged to ground level.

[0096] <Application Example of Semiconductor Device 1>

[0097] Then, use Figure 9 An application example of the semiconductor device 1 will be described. Figure 9 is a diagram illustrating an exemplary configuration of a sensor system (semiconductor system) SYS1 to which the semiconductor device 1 is applied.

[0098] like Figure 9 As shown, the sensor system SYS1 includes a touch screen 100 and a semiconductor device 1a corresponding to the semiconductor device 1. A plurality of touch electrode pairs TP1 having n rows×m columns are arranged on the touch screen 100. The semiconductor device 1a includes a pulse signal output circuit 11, a selector 18, drivers 12_1 to 12_m, current converters 13_1 to 13_n, current controlled oscillators 14_1 to 14_n, counters 15_1 to 15_n, a pulse signal switching circuit 16, and an arithmetic processing unit (CPU) 17.

[0099] The selector 18 selectively outputs the pulse signal PS1 output from the pulse signal output circuit 11 to any one of the drivers 12_1 to 12_m. Each of the drivers 12_1 to 12_m corresponds to the driver 12 and selectively outputs the pulse signal PS1 to the transmitting electrode of the n-th touch electrode pair TP1 in the 1st to m-th columns, respectively.

[0100] Each current converter 13_1 to 13_n corresponds to current converter 13 and converts currents Iin_1 to Iin_n generated in any one of the m touch electrodes in rows 1 to n and the receiving electrode of TP1 into currents Iout_1 to Iout_n. Each current-controlled oscillator 14_1 to 14_n corresponds to current-controlled oscillator 14. Current-controlled oscillators 14_1 to 14_n output clock signals CLK2_1 to CLK2_n, each having a frequency corresponding to currents Iout_1 to Iout_n. Each counter 15_1 to 15_n corresponds to counter 15. Counters 15_1 to 15_n count the number of oscillations of clock signals CLK2_1 to CLK2_n within each predetermined cycle and output count values ​​NC2_1 to NC2_n, respectively. Based on count values ​​NC2_1 to NC2_n, arithmetic processing unit 17 detects which touch electrode pair TP1 is touched by a finger. The other configurations of the semiconductor device 1 a are the same as those of the semiconductor device 1 , and thus descriptions thereof are omitted.

[0101] Here, although a plurality of current converters 13_1 to 13_n are provided in the semiconductor device 1a, the circuit size of each current converter 13_1 is small as described above. Therefore, the sensor system SYS1 can suppress an increase in circuit size.

[0102] In this embodiment, although the pulse signal P1 is input to the corresponding current converters 13_1 to 13_n, similar to the first embodiment, the pulse signal switching circuit 16 to which the pulse signal PS1 is input can be set between the pulse signal output circuit 11 and the selector 18, so that the drivers 12_1 to 12_m are selectively supplied to one of the pulse signal PS1 and its inverted signal.

[0103] Although the configuration of the semiconductor device 1 is applied to the sensor system in this embodiment, the present invention is not limited thereto, and any one of the configurations of the semiconductor devices 2 to 4 may be applied to the sensor system.

[0104] As described above, the semiconductor devices according to the first to fourth embodiments detect changes in the capacitance of the touch electrode pair TP1 by using a current converter that does not include a power supply voltage drop circuit including an amplifier, etc. Furthermore, the semiconductor devices according to the first to fourth embodiments do not require a box capacitor. Therefore, the semiconductor devices according to the first to fourth embodiments can suppress increases in circuit size. Therefore, even when a circuit configuration for measuring the capacitance of each of a plurality of touch electrode pairs in parallel is installed, the semiconductor devices according to the first to fourth embodiments can suppress increases in circuit size.

[0105] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made to the present invention without departing from the gist thereof.

[0106] For example, in the above-described embodiments of the semiconductor device, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconducting layer, the diffusion layer (diffusion region), etc. may be reversed. Thus, when one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type may be p-type and the second conductivity type may be n-type, or conversely, the first conductivity type may be n-type and the second conductivity type may be p-type.

Claims

1. A semiconductor device comprising: a pulse signal output circuit, the pulse signal output circuit providing a pulse signal to a transmitting electrode in an electrode pair, the electrode pair comprising the transmitting electrode and a receiving electrode; a current converter configured to convert a first current generated on the receiving electrode into a second current; a current controlled oscillator that outputs an oscillation signal, the frequency of the oscillation signal being dependent on the second current, and a counter for counting the number of oscillations of the oscillation signal in each predetermined period, wherein the current converter comprises a first constant current source, the first constant current source outputs a first constant current, and the current converter converts a combined current of the first constant current and the first current into the second current; The current converter further comprises: a first transistor, the first transistor being diode-connected and having a source-drain path, the combined current flowing through the source-drain path of the first transistor; a second transistor that is a current mirror connected to the first transistor; and a third transistor that is serially coupled to the second transistor and outputs the second current by being turned on / off in response to the pulse signal.

2. The semiconductor device according to claim 1, further comprising: A pulse signal switching circuit selects the pulse signal or an inverted signal of the pulse signal, and the selected pulse signal or the inverted signal of the pulse signal is output to the current converter and the emitting electrode.

3. The semiconductor device according to claim 2, further comprising an arithmetic processing unit, wherein the arithmetic processing unit detects the capacitance value between the transmitting electrode and the receiving electrode according to the difference between the first count value and the second count value, wherein the first count value is based on the second current when the pulse signal is output from the pulse signal switching circuit, and wherein the second count value is based on the second current when the inverted signal of the pulse signal is output from the pulse signal switching circuit.

4. The semiconductor device according to claim 1, The current converter further includes a current mirror circuit that controls a current flowing through a source-drain path of the second transistor according to a current flowing through the source-drain path of the first transistor.

5. The semiconductor device according to claim 4, The current mirror circuit comprises: an eighth transistor, the eighth transistor being connected to the first transistor by a current mirror; a ninth transistor coupled in series to the eighth transistor and having a conductivity type different from that of the eighth transistor; a tenth transistor connected to the ninth transistor by a current mirror and having the same conductivity type as the ninth transistor; as well as an eleventh transistor coupled in series to the tenth transistor and having the same conductivity type as the eighth transistor, wherein the second transistor is connected to the eleventh transistor by a current mirror.

6. The semiconductor device according to claim 1, The current converter further comprises: a second constant current source, the second constant current source outputting a second constant current, the second constant current being proportional to the first constant current; a fourth transistor coupled in series to the second constant current source and connected to the first transistor by a current mirror; a fifth transistor that is diode-connected and has a source-drain path through which a differential current between the second constant current and a current flowing through the source-drain path of the fourth transistor flows; a sixth transistor connected to the fifth transistor by a current mirror; as well as a seventh transistor that is coupled in series to the sixth transistor and outputs a current flowing by complementarily turning on / off the third transistor as the second current.

7. The semiconductor device according to claim 6, further comprising: a pulse signal switching circuit, wherein the pulse signal switching circuit selects the pulse signal or an inverted signal of the pulse signal, and the selected pulse signal or the inverted signal of the pulse signal is output to the current converter and the emitting electrode; wherein the third transistor of the current converter is turned on / off in response to the output signal of the pulse signal switching circuit, and The seventh transistor of the current converter is turned on / off in response to an inverted signal of the output signal of the pulse signal switching circuit.

8. The semiconductor device according to claim 6, The current converter further includes a current mirror circuit that controls a current flowing through a source-drain path of the second transistor according to the current flowing through the source-drain path of the first transistor.

9. The semiconductor device according to claim 8, The current mirror circuit comprises: an eighth transistor, the eighth transistor being connected to the first transistor by a current mirror; a ninth transistor coupled in series to the eighth transistor and having a conductivity type different from that of the eighth transistor; a tenth transistor connected to the ninth transistor by a current mirror and having the same conductivity type as the ninth transistor; as well as an eleventh transistor, the eleventh transistor being coupled in series to the tenth transistor and having the same conductivity type as the conductivity type of the eighth transistor, The second transistor is connected to the eleventh transistor via a current mirror.

10. The semiconductor device according to claim 8, The current converter further comprises: a twelfth transistor that is turned on / off complementarily to the third transistor and supplies charge to a first node between the second transistor and the third transistor when the twelfth transistor is turned on; and a thirteenth transistor which is turned on / off complementarily to the seventh transistor and supplies charges to a second node between the sixth transistor and the seventh transistor when the thirteenth transistor is turned on.

11. The semiconductor device according to claim 10, further comprising a dummy transistor, wherein the current converter comprises a first output terminal and a second output terminal, and outputs the second current through the first output terminal for use in the current controlled oscillator, wherein the dummy transistor is provided between a power supply voltage terminal and the second output terminal, wherein the twelfth transistor is provided between the first node and the second output terminal, and The thirteenth transistor is provided between the second node and the second output terminal.

12. The semiconductor device according to claim 11, The dummy transistor includes the same conductivity type, the same size, and the same shape as the input stage transistor of the current controlled oscillator.

13. A semiconductor system comprising: electrode pairs, and The semiconductor device according to claim 1.

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