Signal transmission circuit and signal transmission network

Abstract

The present application provides a signal transmission circuit and a signal transmission network, which relate to the field of signal transmission technology. The signal transmission circuit includes a coding module, a transformer, a first comparator, a second comparator and a decoding module, the coding module is electrically connected to the input end of the transformer, the output end of the transformer is electrically connected to the input end of the first comparator and the second comparator respectively, the output end of the first comparator and the second comparator are both electrically connected to the decoding module, the coding module is used to generate a first polarity square wave signal and a second polarity square wave signal according to the input signal, and transmit the first polarity square wave signal and the second polarity square wave signal to the input end of the transformer. The signal transmission circuit and signal transmission network provided by the present application have the advantage of low power consumption.

Description

Technical Field

[0001] The present application relates to the field of signal transmission technology, and in particular, to a signal transmission circuit and a signal transmission network. Background Art

[0002] Isolated signal transmission is widely used in industrial buses, electric vehicle charging piles, smart grids, etc., and can realize the functions of system safety protection, noise isolation, and level conversion. Traditional optocouplers have high power consumption and large delay. The use of transformers can significantly reduce power consumption and delay, while having a longer service life and stability. Therefore, the prior art generally uses transformers for encoding.

[0003] For signal transmission, since a transformer is used, the signal needs to be encoded and decoded. The traditional encoding and decoding method is to use a carrier to achieve level transmission. For example, when the signal to be transmitted is high level, the corresponding carrier is transmitted; when the signal to be transmitted is high level, the corresponding carrier is not transmitted. However, the power consumption of signal transmission using this method is high. Even very low-frequency signals require a high-frequency and high-power carrier for transmission.

[0004] In summary, the power consumption in the prior art is relatively high when performing isolated signal transmission. Summary of the invention

[0005] The purpose of the present application is to provide a signal transmission circuit and a signal transmission network to solve the problem of high power consumption during isolated signal transmission in the prior art.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] On the one hand, an embodiment of the present application provides a signal transmission circuit, which includes a coding module, a transformer, a first comparator, a second comparator and a decoding module, wherein the coding module is electrically connected to the input end of the transformer, the output end of the transformer is electrically connected to the input ends of the first comparator and the second comparator, respectively, and the output ends of the first comparator and the second comparator are both electrically connected to the decoding module; wherein the coding module is used to generate a first polarity square wave signal and a second polarity square wave signal according to an input signal, and transmit the first polarity square wave signal and the second polarity square wave signal to the input end of the transformer, wherein the first polarity square wave signal and the second polarity square wave signal is an opposite signal; the first comparator is used to generate a first signal and a second signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the first signal and the second signal to the decoding module, wherein the second signal is a delayed signal of the first signal; the second comparator is used to generate a third signal and a fourth signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the third signal and the fourth signal to the decoding module, wherein the fourth signal is a delayed signal of the third signal; the decoding module is used to decode according to the first signal, the second signal, the third signal and the fourth signal and output the decoded signal.

[0008] Optionally, when a first polarity square wave signal is input to the input end of the transformer, the output end of the transformer outputs a positive polarity pulse and a negative polarity pulse successively, and when a second polarity square wave signal is input to the input end of the transformer, the output end of the transformer outputs a negative polarity pulse and a positive polarity pulse successively; wherein, the first comparator is used to output a high level signal after receiving the positive polarity pulse, and output a low level signal after receiving the negative polarity pulse; and when the time of the high level signal output by the first comparator reaches a threshold, it automatically switches to output a low level signal, wherein the threshold is greater than the width of the first polarity square wave signal; the second comparator is used to output a low level signal after receiving the negative polarity pulse, and output a high level signal after receiving the positive polarity pulse; and when the time of the low level signal output by the second comparator reaches the threshold, it automatically switches to output a high level signal.

[0009] Optionally, the signal transmission circuit also includes a first delay module and a second delay module, and the output ends of the first comparator and the second comparator both include a first output end and a second output end; the first output end of the first comparator is electrically connected to the decoding module to transmit a first signal to the decoding module; the second output end of the first comparator is electrically connected to the decoding module through the first delay module to transmit a second signal to the decoding module; the first output end of the second comparator is electrically connected to the decoding module to transmit a third signal to the decoding module; the second output end of the second comparator is electrically connected to the decoding module through the second delay module to transmit a fourth signal to the decoding module.

[0010] Optionally, the first delay module and the second delay module include a plurality of delay devices, the plurality of delay devices are connected in sequence, and the delay of each delay device is smaller than the width of the first polarity square wave signal and the second polarity square wave signal.

[0011] Optionally, the decoding module includes a logic processing circuit and a latch, the input end of the logic processing circuit is electrically connected to the first comparator and the second comparator respectively, the output end of the logic processing circuit is electrically connected to the latch, and the logic processing circuit and the latch are used to decode according to the levels of the first signal, the second signal, the third signal and the fourth signal and output the decoded signal.

[0012] Optionally, the logic processing circuit includes a first NOT gate, a second NOT gate, a first AND gate and a second AND gate, the input end of the first NOT gate is used to receive the fourth signal, the output end of the first NOT gate is electrically connected to the first input end of the first AND gate, the second input end of the first AND gate is used to receive the first signal, and the output end of the first AND gate is electrically connected to the first end of the latch; the input end of the second NOT gate is used to receive the third signal, the output end of the first NOT gate is electrically connected to the first input end of the second AND gate, the second input end of the second AND gate is used to receive the second signal, and the output end of the second AND gate is electrically connected to the second end of the latch; wherein the latch is used to output a high level signal when the second signal is a high level signal and the third signal is a low level signal; the latch is also used to output a low level signal when the fourth signal is a low level signal and the first signal is a high level signal.

[0013] Optionally, the latch comprises an RS latch, the first end of the latch is a zero-setting end, and the second end of the latch is a one-setting end.

[0014] Optionally, the encoding module includes an encoding submodule and a driver, the encoding submodule is electrically connected to the driver, and the driver is also electrically connected to the input end of the transformer; wherein, the encoding submodule is used to generate a first polarity square wave signal when a rising edge of the input signal is detected after receiving the input signal, and use the driver to transmit the first polarity square wave signal to the input end of the transformer; the encoding submodule is used to generate a second polarity square wave signal when a falling edge of the input signal is detected after receiving the input signal, and use the driver to transmit the second polarity square wave signal to the input end of the transformer.

[0015] Optionally, the encoding module also includes a timer, which is electrically connected to the encoding submodule, and the timer is used to provide a clock signal for the encoding submodule. The encoding submodule is also used to generate a first refresh signal after a preset time after generating a first polarity square wave signal, wherein the preset time is greater than the width of the first polarity square wave signal; the encoding submodule is also used to generate a second refresh signal after a preset time after generating a second polarity square wave signal, wherein the preset time is greater than the width of the second polarity square wave signal.

[0016] On the other hand, an embodiment of the present application further provides a signal transmission network, which includes the above-mentioned signal transmission circuit.

[0017] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0018] The present application provides a signal transmission circuit and a signal transmission network, the signal transmission circuit includes a coding module, a transformer, a first comparator, a second comparator and a decoding module, the coding module is electrically connected to the input end of the transformer, the output end of the transformer is electrically connected to the input end of the first comparator and the second comparator respectively, the output end of the first comparator and the second comparator are both electrically connected to the decoding module, the coding module is used to generate a first polarity square wave signal and a second polarity square wave signal according to the input signal, and transmit the first polarity square wave signal and the second polarity square wave signal to the input end of the transformer, wherein the first polarity square wave signal and the second polarity square wave signal are electrically connected to each other. The polarity square wave signal is an opposite signal. The first comparator is used to generate the first signal and the second signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the first signal and the second signal to the decoding module, wherein the second signal is a delayed signal of the first signal; the second comparator is used to generate the third signal and the fourth signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the third signal and the fourth signal to the decoding module, wherein the fourth signal is a delayed signal of the third signal; the decoding module is used to decode according to the first signal, the second signal, the third signal and the fourth signal and output the decoded signal. Since the transformer is used for signal transmission in the present application, it can play a role in signal isolation. At the same time, since the signal is divided into the first polarity square wave signal and the second polarity square wave signal for transmission during signal transmission, it does not need to use the carrier to realize signal transmission, thereby effectively reducing power consumption.

[0019] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 This is a schematic diagram of the first type of coded signal in the prior art.

[0022] Figure 2 A schematic diagram of a module of a signal transmission circuit provided in an embodiment of the present application.

[0023] Figure 3 A schematic diagram of submodules of the encoding module provided in an embodiment of the present application.

[0024] Figure 4 A schematic diagram of a coded signal provided in an embodiment of the present application.

[0025] Figure 5 This is a schematic diagram of the second encoding signal in the prior art.

[0026] Figure 6 This is a waveform diagram of the first signal transmission process provided in an embodiment of the present application.

[0027] Figure 7 A circuit diagram of a first signal transmission circuit provided in an embodiment of the present application.

[0028] Figure 8 This is a rendering of the effect of a single delay device provided in an embodiment of the present application.

[0029] Fig. 9 A diagram showing the working principles of multiple delay devices provided in an embodiment of the present application.

[0030] Fig.10 A circuit diagram of a decoding module provided in an embodiment of the present application.

[0031] Fig.11 A circuit diagram of a second signal transmission circuit provided in an embodiment of the present application.

[0032] Fig.12 This is a waveform diagram of the second signal transmission process provided in an embodiment of the present application.

[0033] Fig.13 This is a waveform diagram of the third signal transmission process provided in an embodiment of the present application.

[0034] Fig.14 A schematic diagram of the control signal generation provided in an embodiment of the present application.

[0035] In the figure: 100-signal transmission circuit; 110-encoding module; 120-transformer; 130-first comparator; 140-second comparator; 150-decoding module; 111-encoding submodule; 112-driver; 160-first delay module; 170-second delay module; 151-logic processing circuit; 152-latch. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0038] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0039] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0040] As described in the background technology, in the prior art, isolated signal transmission is generally performed using a transformer. Figure 1 The signal to be transmitted is Figure 1 As shown in a, it contains two square wave pulse signals. Based on this, the existing decoding logic Figure 1 As shown in b, it uses carrier wave to realize signal transmission. Its working principle is that when the signal to be transmitted is at a high level ( Figure 1 The position of 1 in a), the encoded signal corresponds to the transmission carrier ( Figure 1 b in A); and when the signal to be transmitted is low level ( Figure 1 The position of 0 in a), the encoded signal corresponds to no transmission of the carrier ( Figure 1 b) After encoding in this way, decoding is performed on one side of the transformer output end to achieve isolated signal transmission.

[0041] However, the above signal transmission method has the problem of high power consumption, that is, the power consumption of the transmission carrier device system is high. Even if the signal to be transmitted is very low frequency, a high-frequency and high-power carrier is required for transmission. For example, assuming that the signal to be transmitted is always a high-level signal, although the signal to be transmitted has not changed, the entire system needs to continuously transmit a high-frequency carrier, resulting in high power consumption of the system.

[0042] In view of this, the present application provides a signal transmission circuit, which realizes signal transmission by converting the input signal into a positive polarity square wave signal and a negative polarity square wave signal, thereby greatly reducing the power consumption during signal transmission.

[0043] The following is an exemplary description of the signal transmission circuit provided in the embodiment of the present application:

[0044] As an alternative implementation, see Figure 2 The signal transmission circuit 100 includes an encoding module 110, a transformer 120, a first comparator 130, a second comparator 140 and a decoding module 150. The encoding module 110 is electrically connected to the input end of the transformer 120, the output end of the transformer 120 is electrically connected to the input ends of the first comparator 130 and the second comparator 140 respectively, and the output ends of the first comparator 130 and the second comparator 140 are both electrically connected to the decoding module 150.

[0045] The encoding module 110 is used to generate a first polarity square wave signal and a second polarity square wave signal according to the input signal, and transmit the first polarity square wave signal and the second polarity square wave signal to the input end of the transformer 120. Optionally, the width of the positive polarity square wave signal is the same as that of the negative polarity square wave signal, wherein the first polarity square wave signal and the second polarity square wave signal are opposite signals, in other words, when the first polarity square wave signal is a positive polarity square wave signal, the second polarity square wave signal is a negative polarity square wave signal; when the first polarity square wave signal is a negative polarity square wave signal, the second polarity square wave signal is a positive polarity square wave signal.

[0046] At the same time, the first comparator 130 is used to generate a first signal and a second signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the first signal and the second signal to the decoding module 150, and the second signal is a delayed signal of the first signal. The second comparator 140 is used to generate a third signal and a fourth signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the third signal and the fourth signal to the decoding module 150, and the fourth signal is a delayed signal of the third signal. In addition, the decoding module 150 is used to decode according to the first signal, the second signal, the third signal and the fourth signal and output the decoded signal.

[0047] It can be understood that by converting the input signal into the form of a first polarity square wave signal and a second polarity square wave signal, the carrier wave form can be avoided and only a square wave signal needs to be generated, thereby achieving the purpose of reducing power consumption.

[0048] As an implementation, see Figure 3The encoding module 110 includes an encoding submodule 111 and a driver 112, the encoding submodule 111 is electrically connected to the driver 112, and the driver 112 is also electrically connected to the input end of the transformer 120; wherein, the encoding submodule 111 is used to generate a first polarity square wave signal when a rising edge of the input signal is detected after receiving the input signal, and use the driver 112 to transmit the first polarity square wave signal to the input end of the transformer 120, and, when a falling edge of the input signal is detected, generate a second polarity square wave signal, and use the driver 112 to transmit the second polarity square wave signal to the input end of the transformer 120.

[0049] The input signal described in this application is the signal to be transmitted, such as Figure 4 As shown, the input signal is Figure 4 The waveform signal shown in a, and, as an optional implementation, the first polarity square wave signal is a positive polarity square wave signal, and the second polarity square wave signal is a negative polarity square wave signal. After the encoding submodule 111 receives the signal, when a rising edge is detected, a positive polarity square wave signal is generated, and when a falling edge of the input signal is detected, a negative polarity square wave signal is generated. The generated signal is as shown in FIG. Figure 4 As shown in b, for the convenience of explanation, the width of the generated positive polarity square wave signal and the negative polarity square wave signal are both tp. Figure 4 It can be seen that the present application is equivalent to generating signals for transmission only at the rising edge and falling edge of the input signal, thereby greatly reducing power consumption.

[0050] At the same time, in the prior art, there is another encoding method, such as Figure 5 As shown, this encoding method uses two pulses to identify the rising edge (or falling edge), and uses a single pulse to identify the falling edge (or rising edge). The edge is decoded by counting the number of pulses at the receiving end. For example, Figure 5 a is the data to be transmitted, which contains two square wave pulses. When the rising edge of the square wave pulse appears, two pulses are used for encoding, and when the falling edge of the square wave pulse appears, one pulse is used for encoding. The encoded signal is as follows: Figure 5 However, when encoding is performed in this manner, the refresh signal also has the same number of pulses, but the timing of the refresh signal and the encoding signal of the square wave signal is uncertain. Figure 5 As shown in Figure C, when the double-pulse refresh signal is close to the single-pulse edge signal, three pulses are actually transmitted, and the receiver cannot determine the correct information from the three pulses. It is even possible that the refresh signal and the edge signal directly overlap, resulting in output errors. The system delay must be greatly increased to effectively avoid the problem of the refresh signal and the edge signal being close in timing, and the price paid is very high.

[0051] In view of this, the signal transmission circuit provided in the present application can better handle the timing of the refresh signal and the edge signal being close to or colliding, avoiding the introduction of a large delay.

[0052] The transformer 120 includes an input terminal and an output terminal, and the input terminal and the output terminal are coupled through a magnetic field. When the input terminal outputs a square wave signal, a corresponding positive pulse and a negative pulse are generated at the output terminal according to the typical inductor-resistor (LR) charge-discharge circuit characteristics. In other words, when a square wave signal is input to the input terminal, since a square wave signal has a rising edge and a falling edge, a positive polarity pulse and a negative polarity pulse are generated at the output terminal. On this basis, please refer to Figure 6 , Figure 6 a shows the input signal, which is a square wave. Figure 6 b shows the signal after being encoded according to the input and output signals. It can be understood that Figure 6 b and Figure 6 As shown in c, when a positive polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 successively outputs a positive polarity pulse and a negative polarity pulse; when a negative polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 successively outputs a negative polarity pulse and a positive polarity pulse.

[0053] Of course, it should be understood that the above implementation is only an example. In actual use, the polarity of the transformer 120 can also be reversed. For example, when a positive polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 can also output a negative polarity pulse and a positive polarity pulse successively. When a negative polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 can also output a positive polarity pulse and a negative polarity pulse successively. The present application does not limit this. For the convenience of explanation, the following embodiments are all described by taking as an example that when a positive polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 outputs a positive polarity pulse and a negative polarity pulse successively, and when a negative polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 outputs a negative polarity pulse and a positive polarity pulse successively.

[0054] As an implementation method, the first comparator 130 is used to output a high-level signal after receiving a positive polarity pulse, and output a low-level signal after receiving a negative polarity pulse; and when the time of the high-level signal output by the first comparator 130 reaches a threshold, it automatically switches to output a low-level signal, wherein the threshold is greater than the width of the positive polarity square wave signal. Therefore, on this basis, since a positive polarity square wave signal and a negative polarity square wave signal are input to the input end of the transformer 120, when a positive polarity square wave signal is input to the input end of the transformer 120, the output end of the transformer 120 first outputs a positive polarity pulse, and then outputs a negative polarity pulse after the width tp of the positive polarity square wave signal; after a period of time, a negative polarity square wave signal is input to the input end of the transformer 120, and the output end of the transformer 120 first outputs a negative polarity pulse, and then outputs a positive polarity pulse after the threshold time.

[0055] It can be understood that the signal transmitted to the first comparator 130 through the output end of the transformer 120 is essentially "the first positive polarity pulse-the first negative polarity pulse-the second negative polarity pulse-the second positive polarity pulse". Figure 6 d. According to the working principle of the first comparator 130, when the first positive pulse appears, the first comparator 130 outputs a high level; when the first negative pulse appears, the first comparator 130 outputs a low level to form the first pulse. When the second negative pulse signal appears, the first comparator 130 outputs a low level, and the signal remains unchanged. When the second positive pulse signal appears, the first comparator 130 outputs a high level. Since the first comparator 130 does not receive a low level later, it will maintain a high level output until the time of the high level signal output reaches the threshold. At this time, the feature of the first comparator 130 automatically changes the output signal to a low level signal, thereby forming the second pulse. It can be understood that the width of the second pulse is the threshold of the first comparator 130. If the threshold is set to tm, the width of the second pulse is tm. And, it can be understood that since the first pulse is associated with the positive square wave signal, the width of the first pulse signal is theoretically equal to the width of the positive square wave signal, which is tp, and the design needs to satisfy tm>tp.

[0056] Similarly, the second comparator 140 is used to output a high level signal after receiving a negative polarity pulse, and output a high level signal after receiving a negative polarity pulse; and when the time of the low level signal output by the second comparator 140 reaches the threshold, it automatically switches to output a high level signal. The working principle of the second comparator 140 is similar to that of the first comparator 130, so it will not be repeated here. The output signal is as follows Figure 6 f.

[0057] It is understandable that the input signal in the above example only includes one square wave signal, but in actual application, there may be multiple square wave signals in the input signal, and the working principle of outputting them to the first comparator 130 is the same, which will not be repeated here.

[0058] It should be noted that, in order to achieve the effect that the first comparator 130 and the second comparator 140 output different results according to the same signal input to the output terminal of the transformer 120. As an implementation method, please refer to Figure 7 , in the figure, L1 is the signal input terminal of the transformer 120, and L2 is the signal output terminal of the transformer 120. The first comparator 130 and the second comparator 140 both include a first input terminal and a second input terminal, and the first input terminal is a non-inverting input terminal, and the first input terminal is an inverting input terminal. The transformer 120 includes a first output terminal and a second output terminal, and the first output terminal of the transformer 120 is electrically connected to the non-inverting input terminals of the first comparator 130 and the second comparator 140, respectively, and the second output terminal of the transformer 120 is electrically connected to the inverting input terminals of the first comparator 130 and the second comparator 140, respectively. Through this connection method, it can be ensured that the input signals of the first comparator 130 and the second comparator 140 are the same, and because the first comparator 130 and the second comparator 140 process data in different ways, they can output different signals.

[0059] At the same time, the present application sets a corresponding decoding logic based on the above encoding logic, wherein the signal transmission circuit 100 further includes a first delay module 160 and a second delay module 170, and the output ends of the first comparator 130 and the second comparator 140 both include a first output end and a second output end; the first output end of the first comparator 130 is electrically connected to the decoding module 150 to transmit the first signal to the decoding module 150, Figure 7 A in the figure is the first signal; the second output terminal of the first comparator 130 is electrically connected to the decoding module 150 through the first delay module 160 to transmit the second signal to the decoding module 150, Figure 7 AD is the second signal. It can be understood that since the first delay module 160 is provided, the second signal is a delayed signal of the first signal. The first output terminal of the second comparator 140 is electrically connected to the decoding module 150 to transmit the third signal to the decoding module 150. Figure 7 In the figure, B is the third signal. The second output terminal of the second comparator 140 is electrically connected to the decoding module 150 through the second delay module 170 to transmit the fourth signal to the decoding module 150. Figure 7 BD is the fourth signal shown in the figure; similarly, the fourth signal is a delayed signal of the third signal.

[0060] The second signal described in this application is a delayed signal of the first signal, and the fourth signal is a delayed signal of the third signal, which means that the second signal has the same waveform as the first signal, but its pulse appears slightly later than the first signal; similarly, the fourth signal has the same waveform as the third signal, but its pulse appears slightly later than the third signal. Optionally, the delay can be tm; and the design requires that the delay is not less than tp and not greater than tm. On this basis, please combine Figure 6 , Figure 6 d shows the waveform of the first signal, Figure 6 e shows the waveform of the second signal, Figure 6 f shows the waveform of the third signal, Figure 6 g shows the waveform of the fourth signal. As can be seen from the figure, the time when the first square wave pulse appears in the second signal is delayed by tm compared with the time when the first square wave pulse appears in the first signal, and at the same time, the time when the second square wave pulse appears in the second signal is also delayed by tm compared with the time when the second square wave pulse appears in the first signal; the time when the first square wave pulse appears in the fourth signal is delayed by tm compared with the time when the first square wave pulse appears in the third signal, and at the same time, the time when the second square wave pulse appears in the fourth signal is also delayed by tm compared with the time when the second square wave pulse appears in the third signal.

[0061] As an optional implementation, the first delay module 160 and the second delay module 170 each include a plurality of delay devices, the plurality of delay devices are connected in sequence, and the delay of each delay device is smaller than the width of the first polarity square wave signal and the second polarity square wave signal, such as Figure 7 In the signal transmission circuit 100 shown, the first delay module 160 and the second delay module 170 may also include 6 delay devices, and the delay of each delay device is 1ns; or the first delay module 160 and the second delay module 170 may include three delay devices, and the delay of the delay device is 2ns, and it is only necessary to meet that the delay of each delay device does not exceed tp. The reason why the first delay module 160 and the second delay module 170 provided in the present application need to include multiple delay devices is:

[0062] Figure 8 The working principle diagram of a single delay device is shown in FIG. Figure 8 a is the circuit diagram of a single delay device. Figure 8b is the signal transformation diagram of a single delay device. It can be seen from the figure that if a single-stage delay device with a long delay is used, if the input signal Vin pulse is relatively short, then the falling speed of Vo1 is very slow (the long-delay delay device has a large RC time constant). It is possible that when the Vin pulse ends, Vo1 still has not dropped to the threshold corresponding to logic 0 (as shown by the horizontal dotted line). In other words, the input pulse signal is absorbed by the delay device and cannot be output. Therefore, using a single delay device cannot achieve the delay requirement of this application.

[0063] If a delay module with multiple delay stages is used, please refer to Fig. 9 , Fig. 9 The working principle diagram of multiple delay devices is shown, wherein: Fig. 9 a is a circuit diagram of multiple delay devices. Fig. 9 b is the signal transformation diagram of multiple delay devices. It can be seen from the figure that as long as the delay of each stage is less than the pulse width of the input signal, each stage has enough time to reach the threshold of logic flipping, so as to save and output the pulse of the input signal and achieve the delay effect.

[0064] Among them, Fig.10 As shown, the decoding module 150 includes a logic processing circuit 151 and a latch 152. The input end of the logic processing circuit 151 is electrically connected to the first comparator 130 and the second comparator 140 respectively, and the output end of the logic processing circuit 151 is electrically connected to the latch 152. The logic processing circuit 151 and the latch 152 are used to decode according to the levels of the first signal, the second signal, the third signal and the fourth signal and output the decoded signal.

[0065] As an implementation method, the logic processing circuit 151 includes a first NOT gate, a second NOT gate, a first AND gate and a second AND gate, the input end of the first NOT gate is used to receive the fourth signal, the output end of the first NOT gate is electrically connected to the first input end of the first AND gate, the second input end of the first AND gate is used to receive the first signal, and the output end of the first AND gate is electrically connected to the first end of the latch 152; the input end of the second NOT gate is used to receive the third signal, the output end of the first NOT gate is electrically connected to the first input end of the second AND gate, the second input end of the second AND gate is used to receive the second signal, and the output end of the second AND gate is electrically connected to the second end of the latch 152.

[0066] Optionally, the latch 152 described in the present application is an RS latch 152. On this basis, the first end of the latch 152 is a reset end (i.e., the R end in the figure), and the second end of the latch 152 is a set end (i.e., the S end in the figure). R means Reset, i.e., clear to zero; S means Set, i.e., set to 1. Therefore, the logical expression of the input end of the latch 152 is:

[0067] SET = AD AND (NOT B)

[0068] RST = (NOT BD) AND A

[0069] Furthermore, the working principle of the RS latch 152 is that when R is 1, the output Q=0 is forced and the output continues to be 0 after the condition of R=1 ends; when S is 1, the output Q=1 is forced and the output continues to be 1 after the condition of S=1 ends.

[0070] In other words, the latch 152 is used to output a high level signal when the second signal is a high level signal and the third signal is a low level signal; and to output a low level signal when the fourth signal is a low level signal and the first signal is a high level signal. Figure 6 , Figure 6 h shows the signal at the set end of latch 152, Figure 6 FIG. 1 shows the signal at the zero-setting terminal of latch 152. On this basis, the signal output by latch 152 is as follows: Figure 6 As shown in FIG. 1 , the encoding and decoding process is realized. It can be understood that the waveform of the decoded signal is the same as that of the input signal, and the delay does not exceed tm.

[0071] As another implementation, the signal transmission circuit 100 provided in the present application may also introduce DC refresh, wherein DC refresh means that when the input signal maintains a certain potential (0 or 1), the signal is transmitted through the transformer 120 so that the receiver side can confirm the state of the input signal. Different from the above implementation, DC refresh does not occur at the edge of the signal, but occurs during the signal maintenance process.

[0072] On this basis, see Fig.11 The encoding module 110 also includes a timer, which is electrically connected to the encoding submodule 111. The timer is used to provide a clock signal for the encoding submodule 111. The encoding submodule 111 is also used to generate a positive refresh signal after a preset time after generating a positive square wave signal, wherein the preset time is greater than the width of the positive square wave signal; the encoding submodule 111 is also used to generate a negative refresh signal after a preset time after generating a negative square wave signal, wherein the preset time is greater than the width of the positive square wave signal and the delay. That is, when the preset time is set to td, td>tp and td>tm must be satisfied.

[0073] The working principle of the signal transmission circuit 100 for adding a refresh signal is described in detail below. Fig.12 As shown, Fig.12 FIG. 1 shows a signal change diagram of the signal transmission circuit 100 after adding a refresh signal. Fig.12a is the input signal. At the rising edge and falling edge of the input signal, after being encoded by the encoding submodule 111, a positive polarity square wave signal and a negative polarity square wave signal will be generated respectively. At the same time, the encoding submodule 111 will also receive the time signal transmitted by the timer. And according to the timing result of the timer, every time td after the input terminal L1 of the transformer 120 outputs a positive polarity square wave signal, the driver 112 is controlled to output a positive polarity pulse (positive refresh signal) with a width of tp again until a falling edge appears in the input signal. In addition, according to the timing result of the timer, every time td after the input terminal L1 of the transformer 120 outputs a negative polarity pulse, the driver 112 is controlled to output a negative polarity pulse (negative refresh signal) with a width of tp again until a rising edge appears in the input signal. The encoded signal is as follows: Fig.12 As shown in b.

[0074] At the same time, since the signal processing process of the present application is basically the same as the signal processing process of the above embodiment, the present application will not repeat it again. Fig.12 It can be understood that after the R and S terminals of the latch 152 receive the pulse generated according to the input signal, they also receive the pulse generated according to the refresh signal, such as Fig.12 h and Fig.12 As shown in i.

[0075] On the basis of adding a refresh signal, the first delay module 160 and the second delay module 170 provided in the present application can both be implemented by using multiple delay devices. The reason is that:

[0076] The refresh signal always arrives at a certain moment after the corresponding edge occurs, that is, at a moment of an integer multiple of td. For example, a positive refresh signal will appear at td, 2*td, 3*td... after the rising edge, but because the input signal is not certain, the arrival of the falling edge is random, and there may be a problem of collision between the falling edge and the positive refresh signal (similarly, there is a problem of collision between the rising edge and the negative refresh signal). Therefore, it is necessary to ensure from the design that when a collision occurs, the transmission of the signal is not affected. The present application achieves this technical effect by instantly stopping the output of the refresh signal with the edge detection signal and immediately starting the transmission of the edge encoding signal.

[0077] By setting edge signal detection, when the edge and refresh signal collide, the system output waveform. Take the collision between the falling edge and the positive refresh as an example (the analysis of the opposite situation is similar), the waveform is as follows Fig.13 shown.

[0078] If the system is transmitting a refresh signal and an edge signal arrives, the current refresh signal is stopped and the edge signal is transmitted directly, such as Fig.13As shown in b, (the dotted line in the figure is the waveform that the refresh signal should maintain if the refresh signal and the edge signal do not collide). When the edge signal comes, the encoding circuit controls the refresh signal to stop immediately and transmit the edge signal. There are many ways to achieve this function and achieve the same technical effect. The following is one of the optional implementation methods.

[0079] As an implementation, see Fig.14 , the input signal outputs a control signal through a delay and an XNOR gate, which is 0 at the edge and 1 at other positions. This control signal is used as a control signal of the output stage with an enable (EN) terminal. When the edge occurs, EN=0, the output stage is turned off, and the refresh signal will not be transmitted; when EN=1, it means that it is not an edge moment, and the refresh signal can be transmitted normally to the next stage.

[0080] Through the above implementation, it can be effectively achieved that even when the falling edge or the rising edge collides with the refresh signal, it will not affect the normal transmission of the signal.

[0081] Based on the above embodiments, the present application also provides a signal transmission network, which includes the above signal transmission circuit.

[0082] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0083] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A signal transmission circuit, It is characterized in that The signal transmission circuit includes an encoding module, a transformer, a first comparator, a second comparator and a decoding module, wherein the encoding module is electrically connected to the input end of the transformer, the output end of the transformer is electrically connected to the input ends of the first comparator and the second comparator respectively, and the output ends of the first comparator and the second comparator are both electrically connected to the decoding module; wherein, The encoding module is used to generate a first polarity square wave signal and a second polarity square wave signal according to an input signal, and transmit the first polarity square wave signal and the second polarity square wave signal to an input end of the transformer, wherein the first polarity square wave signal and the second polarity square wave signal are opposite signals; The first comparator is used to generate a first signal and a second signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the first signal and the second signal to the decoding module, wherein the second signal is a delayed signal of the first signal; The second comparator is used to generate a third signal and a fourth signal according to the first polarity square wave signal and the second polarity square wave signal, and transmit the third signal and the fourth signal to the decoding module, wherein the fourth signal is a delayed signal of the third signal; The decoding module is used to decode the first signal, the second signal, the third signal and the fourth signal and output the decoded signal; When a square wave signal of the first polarity is input to the input end of the transformer, the output end of the transformer successively outputs a positive polarity pulse and a negative polarity pulse, and when a square wave signal of the second polarity is input to the input end of the transformer, the output end of the transformer successively outputs a negative polarity pulse and a positive polarity pulse; wherein, The first comparator is used to output a high level signal after receiving the positive polarity pulse, and output a low level signal after receiving the negative polarity pulse; and when the time of the high level signal output by the first comparator reaches a threshold, it automatically switches to output a low level signal, wherein the threshold is greater than the width of the first polarity square wave signal; The second comparator is used to output a low level signal after receiving the negative polarity pulse, and output a high level signal after receiving the positive polarity pulse; and when the time of the low level signal output by the second comparator reaches the threshold, it automatically switches to output a high level signal; The decoding module includes a logic processing circuit and a latch, the input end of the logic processing circuit is electrically connected to the first comparator and the second comparator respectively, the output end of the logic processing circuit is electrically connected to the latch, and the logic processing circuit and the latch are used to decode according to the levels of the first signal, the second signal, the third signal and the fourth signal and output the decoded signal.

2. The signal transmission circuit according to claim 1, It is characterized in that The signal transmission circuit further includes a first delay module and a second delay module, and the output ends of the first comparator and the second comparator both include a first output end and a second output end; The first output terminal of the first comparator is electrically connected to the decoding module to transmit a first signal to the decoding module; The second output terminal of the first comparator is electrically connected to the decoding module through the first delay module to transmit a second signal to the decoding module; The first output terminal of the second comparator is electrically connected to the decoding module to transmit a third signal to the decoding module; The second output terminal of the second comparator is electrically connected to the decoding module through the second delay module to transmit a fourth signal to the decoding module.

3. The signal transmission circuit according to claim 2, It is characterized in that The first delay module and the second delay module include a plurality of delay devices, which are connected in sequence, and the delay of each delay device is smaller than the width of the first polarity square wave signal and the second polarity square wave signal.

4. The signal transmission circuit according to claim 1, It is characterized in that The logic processing circuit includes a first NOT gate, a second NOT gate, a first AND gate and a second AND gate, the input end of the first NOT gate is used to receive the fourth signal, the output end of the first NOT gate is electrically connected to the first input end of the first AND gate, the second input end of the first AND gate is used to receive the first signal, and the output end of the first AND gate is electrically connected to the first end of the latch; The input end of the second NOT gate is used to receive the third signal, the output end of the first NOT gate is electrically connected to the first input end of the second AND gate, the second input end of the second AND gate is used to receive the second signal, and the output end of the second AND gate is electrically connected to the second end of the latch; wherein, The latch is used to output a high level signal when the second signal is a high level signal and the third signal is a low level signal; The latch is further configured to output a low level signal when the fourth signal is a low level signal and the first signal is a high level signal.

5. The signal transmission circuit according to claim 4, It is characterized in that The latch comprises an RS latch, a first end of the latch is a zero-setting end, and a second end of the latch is a one-setting end.

6. The signal transmission circuit according to claim 1, It is characterized in that The encoding module includes an encoding submodule and a driver, the encoding submodule is electrically connected to the driver, and the driver is also electrically connected to the input end of the transformer; wherein, The encoding submodule is used for generating a first polarity square wave signal after receiving the input signal and transmitting the first polarity square wave signal to the input end of the transformer by using the driver when a rising edge of the input signal is detected; The encoding submodule is used to generate a second polarity square wave signal after receiving the input signal and to transmit the second polarity square wave signal to the input end of the transformer by using the driver when a falling edge of the input signal is detected.

7. The signal transmission circuit according to claim 6, It is characterized in that The encoding module further includes a timer, the timer is electrically connected to the encoding submodule, the timer is used to provide a clock signal for the encoding submodule, and the encoding submodule is further used to generate a first refresh signal after a preset time after generating a first polarity square wave signal, wherein the preset time is greater than the width of the first polarity square wave signal; The encoding submodule is further configured to generate a second refresh signal after a preset time after generating the second polarity square wave signal, wherein the preset time is greater than a width of the second polarity square wave signal.

8. A signal transmission network, It is characterized in that The signal transmission network comprises the signal transmission circuit according to any one of claims 1 to 7.

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