Page buffer and memory device including the same

Abstract

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharge period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line when the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to the state of the selected memory cell after the precharge period. The selection circuit outputs a control voltage that controls a switching element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharge period based on the data stored in the first storage circuit.

Description

[0001] Cross-referencing of related patents

[0002] This application claims priority to Korean Patent Application No. 10-2019-0062740, filed on May 28, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to page buffers and storage devices including the page buffers. Background Technology

[0004] A storage device may include multiple memory cells for storing data, and these memory cells can be connected to a page buffer via bit lines. The page buffer can use the bit lines to read the data stored in each memory cell. To read the data stored in a memory cell, the page buffer can adjust the voltage of the bit lines connected to the memory cell. Recently, various methods have been proposed in which the page buffer can effectively adjust the voltage of the bit lines. Summary of the Invention

[0005] One aspect of the present invention is to provide a page buffer and a memory device including the page buffer, wherein performance can be improved by reducing the time required for a pre-charge operation to charge bit lines during a read operation to read data from a memory cell.

[0006] According to one aspect of the embodiments, a page buffer is provided, comprising: a charging circuit configured to charge a bit line during a pre-charging period; a first storage circuit configured to determine and store data corresponding to the state of a selected memory cell among a plurality of memory cells connected to the bit line when the charging circuit charges the bit line; a second storage circuit, which is a separate circuit from the first storage circuit, configured to determine and store data corresponding to the state of the selected memory cell after the pre-charging period; and a selection circuit configured to output a control voltage that controls a switching element connected between the bit line and the charging circuit, and to determine the magnitude of the control voltage during the pre-charging period based on the data stored in the first storage circuit.

[0007] According to another aspect of the present invention, a storage device includes: a memory cell array including a plurality of memory cells and a plurality of bit lines connected to the plurality of memory cells; and a memory controller configured to read data corresponding to a threshold voltage of a selected memory cell connected to a selected bit line among the plurality of bit lines, to input a first charging current to the selected bit line during a first time period, and to input a second charging current lower than the first charging current to the selected bit line during a second time period after the threshold voltage of the selected memory cell is higher than a reference voltage.

[0008] According to another aspect of the present invention, a memory device includes: a memory cell array comprising a plurality of memory cells connected to a plurality of bit lines, each of the plurality of memory cells having a first threshold voltage and a second threshold voltage lower than the first threshold voltage; and a memory controller configured to simultaneously charge a first bit line connected to a first memory cell having the first threshold voltage and a second bit line connected to a second memory cell having the second threshold voltage, and configured to simultaneously charge the first bit line and the second bit line by inputting a first charging current to the first bit line and a second charging current different from the first charging current to the second bit line.

[0009] According to another aspect of the present invention, a method of operating a memory device includes: determining, from a plurality of bit lines, a selected bit line connected to a selected memory cell from which data is to be read; pre-charging the selected bit line by inputting a charging current to the selected bit line; reading a threshold voltage of the selected memory cell while the selected bit line is being pre-charged; and maintaining or reducing the charging current based on the threshold voltage of the selected memory cell while the selected bit line is being pre-charged. Attached Figure Description

[0010] The above and other aspects will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a schematic block diagram illustrating a storage device according to an example embodiment;

[0012] Figure 2 This is a schematic circuit diagram illustrating a memory cell array of a memory device according to an example embodiment;

[0013] Figure 3 This is a diagram illustrating the connection relationship between the memory cell array and the page buffer in a memory device according to an example embodiment;

[0014] Figure 4This is a schematic block diagram illustrating a page buffer according to an example embodiment;

[0015] Figure 5 This is a flowchart illustrating the operation of the page buffer according to an example embodiment;

[0016] Figure 6 This is a diagram illustrating a read operation of a storage device according to an example embodiment;

[0017] Figure 7 This is a schematic diagram illustrating a page buffer according to an example embodiment;

[0018] Figures 8 to 10 This is a circuit diagram illustrating the operation of the page buffer according to an example embodiment;

[0019] Figures 11 to 13 It is a graph illustrating the operation of the storage device according to an example embodiment;

[0020] Figures 14 to 16 This is a diagram illustrating the operation of a storage device according to an example embodiment;

[0021] Figure 17 This is a diagram illustrating a read operation of a storage device according to an example embodiment;

[0022] Figure 18 This is a schematic diagram illustrating a page buffer according to an example embodiment;

[0023] Figure 19 This is a schematic block diagram illustrating a storage device according to an example embodiment;

[0024] Figure 20 This is a block diagram schematically illustrating a storage device according to an example embodiment; and

[0025] Figure 21 This is a block diagram illustrating an electronic device including a storage device according to an example embodiment. Detailed Implementation

[0026] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0027] Figure 1 This is a block diagram schematically illustrating a storage device according to an example embodiment.

[0028] First refer to Figure 1The storage device 1 may include a memory cell array 10 and a memory controller 20. The memory cell array 10 may include a plurality of memory cells, and at least a portion of the plurality of memory cells may be interconnected to provide a memory cell string. The memory cell array 10 may include a plurality of memory cell strings, and the plurality of memory cell strings may be divided into a plurality of blocks. The memory controller 20 may include control logic 21, address decoder circuitry 22, page buffer circuitry 23, input / output circuitry 24, etc.

[0029] In the example embodiment, the address decoder circuit 22 can be connected to the memory cell via word line WL, serial select line SSL, and ground select line GSL, and the page buffer circuit 23 can be connected to the memory cell via bit line BL. In the example embodiment, the address decoder circuit 22 can select the memory cell to which data is written or read, and can receive address information to select the memory cell.

[0030] Page buffer circuit 23 can write data to or read data from selected memory cells selected by address decoder circuit 22. In an example embodiment, page buffer circuit 23 can write or read data on a page basis. Page buffer circuit 23 may include multiple page buffers, and each of the multiple page buffers may be connected to at least one bit line BL. Data to be written to or read from memory cell array 10 by page buffer circuit 23 can be input and output via input / output circuit 24. The operation of address decoder circuit 22, page buffer circuit 23, and input / output circuit 24 can be controlled by control logic 21.

[0031] Figure 2 This is a schematic circuit diagram of a memory cell array of a memory device according to an example embodiment.

[0032] refer to Figure 2 The memory cell array of the memory device may include multiple memory cell strings (MCS). Each of the multiple memory cell strings (MCS) may include multiple memory cells MC1 to MCn, a ground selection transistor (GST), a string selection transistor (SST), etc. The number of ground selection transistors (GST) and string selection transistors (SST) included in the memory cell string (MCS) can be varied, and the memory cell string (MCS) may further include virtual memory cells.

[0033] Multiple memory cells MC1 to MCn can be connected to multiple word lines WL1 to WLn (word lines WL). A ground select transistor GST can be connected to the common source line CSL and the ground select line GSL. A string select transistor SST is connected to at least one of the bit lines BL1 to BLm (bit line BL) and can be controlled by a voltage input to the string select line SSL.

[0034] Each word line WL can be shared by two or more memory cell strings (MCS). Each bit line BL can also be shared by two or more memory cell strings (MCS). The channel regions of memory cells MC1 to MCn in each memory cell string (MCS) can be connected to each other, and the bit line BL can be electrically connected to the channel region of the memory cell string (MCS).

[0035] Bit line BL can be connected to the page buffer. The page buffer can perform operations such as reading data from or writing data to selected memory cells MC1 through MCn via bit line BL. References will be made below. Figure 3 Describe the connection relationship between the memory cell array and the page buffer.

[0036] Figure 3 This is a diagram illustrating the connection relationship between the memory cell array and the page buffer in a memory device according to an example embodiment.

[0037] refer to Figure 3 The storage device 2 may include multiple memory cells MC and multiple page buffers PB1 to PBm. Portions of the multiple memory cells MC are interconnected and may provide a memory cell string MCS. The memory cell string MCS may be provided at the intersection of multiple word lines WL1 to WLn and multiple bit lines BL1 to BLm.

[0038] exist Figure 3 In the example embodiment shown, the ground selection transistor GST has a different structure from the memory cell MC, and the string selection transistor SST has the same structure as the memory cell MC, but the example embodiment is not limited thereto. For example, when the memory cell string MCS is formed to have a three-dimensional structure, each of the plurality of bit lines BL1 to BLn includes a plurality of memory cell strings MCS connected to different string selection lines SSL.

[0039] Multiple memory cell strings (MCS) can be included in a memory block 30, and the memory cell array can include multiple memory blocks 30. When the memory cell strings (MCS) included in the memory block 30 are connected to m bit lines BL1 to BLm, the page buffer circuit 40 can include m page buffers PB1 to PBm corresponding to the bit lines BL1 to BLm. For example, in... Figure 3 In the example embodiment, page buffers PB1 to PBm can be connected to bit lines BL1 to BLm respectively, and data to be stored or retrieved can be stored or retrieved through bit lines BL1 to BLm. Page buffers PB1 to PBm may include at least one storage circuit for storing data. The storage circuit can be implemented as a latch circuit, a buffer circuit, etc.

[0040] As an example, in the architecture of storage device 2, page buffers PB1 to PBm connected to a memory block 30 can be in a predetermined direction (e.g., Figure 3 The page buffers PB1 to PBm are arranged vertically. Each of these page buffers also includes, in addition to the storage circuitry, a charging circuit that inputs an voltage to one of the bit lines BL1 to BLm to precharge the sensing node, a selection circuit that controls the operation of the charging circuitry, etc. Each of these page buffers PB1 to PBm may include multiple semiconductor devices to implement the circuitry.

[0041] Figure 4 This is a schematic block diagram of a page buffer according to an example embodiment.

[0042] refer to Figure 4 The page buffer 100 may include multiple storage circuits 110 and 120, a selection circuit 130, a charging circuit 140, a sensing circuit 150, etc. The multiple storage circuits may include a first storage circuit 110 and a second storage circuit 120. As an example, the first storage circuit 110 and the second storage circuit 120 may operate at different times.

[0043] The sensing circuit 150 may include a sensing node connected to the first storage circuit 110 and the second storage circuit 120. In an example embodiment, during a read operation, the data of the selected memory cell may correspond to the voltage of the sensing node, and the first storage circuit 110 and the second storage circuit 120 may detect the voltage of the sensing node to store the data of the selected memory cell.

[0044] Page buffer 100 can be connected via bit line BL to at least a portion of the plurality of memory cells included in memory cell array 200. As an example, charging circuit 140 of page buffer 100 can be connected to bit line BL, and page buffer 100 can use charging circuit 140 to control the voltage of bit line BL to read data from or write data to selected memory cells from the plurality of memory cells. Page buffer 100 can perform a pre-charge operation to charge bit line BL using charging circuit 140.

[0045] The charging circuit 140 can perform a pre-charging operation to supply charge to bit line BL to increase the voltage of bit line BL to a target voltage. For example, the charging circuit 140 can supply charge by inputting a charging current to bit line BL, and the target voltage can be changed depending on the operation performed by the page buffer 100. As an example, the target voltage in a programming operation where the page buffer 100 writes data to a selected memory cell can be different from the target voltage in a read operation where data is read from the selected memory cell.

[0046] In an example embodiment, the selection circuit 130 can modify the charging current input to bit line BL by the charging circuit 140. When a pre-charging operation is performed where the charging circuit 140 inputs the charging current to bit line BL, the page buffer 100 first reads data from the selected memory cell via the sensing circuit 150 to store the data in the storage circuit 110. The selection circuit 130 can adjust the amount of charge supplied to bit line BL via the charging circuit 140 based on the data stored in the first storage circuit 110. For example, the selection circuit 130 can adjust the magnitude of the charging current input to bit line BL by the charging circuit 140.

[0047] For example, the time required for precharging and / or the voltage magnitude of bit line BL after the precharging operation can be varied based on the data stored in the selected memory cell and / or the influence of other bit lines adjacent to the selected bit line BL. The data stored in the selected memory cell can be determined based on the magnitude of the threshold voltage of the selected memory cell. As the threshold voltage of the selected memory cell increases, the time required to precharge bit line BL may increase.

[0048] In the example embodiment, the data of the selected memory cell can be roughly detected during the pre-charge operation, and the magnitude of the charging current input to bit line BL can be maintained or changed accordingly. Page buffer 100 can roughly detect the data of the selected memory cell to store the data in the first storage circuit 110. Selection circuit 130 references the data stored in the first storage circuit 110 to maintain or decrease the magnitude of the charging current input to bit line BL by charging circuit 140.

[0049] In an example embodiment, the magnitude of the charging current input to the bit line BL can be adjusted by using a method in which the magnitude of the charging current output by the charging circuit 140 is maintained or decreased, or by a method in which a switching element between the charging circuit 140 and the bit line BL is controlled while maintaining the magnitude of the charging current output by the charging circuit 140. The charging circuit 140 may include circuitry capable of outputting different charging currents in response to signals from the selection circuit 150.

[0050] Figure 5 This is a flowchart illustrating the operation of the page buffer according to an example embodiment.

[0051] refer to Figure 5 Operation of the page buffer according to the example embodiment can be initiated by charging the bit lines using the page buffer (S10). The page buffer may include a charging circuit connected to the bit lines, and the bit lines can be charged by applying a voltage to the bit lines using the charging circuit. The operation of charging the bit lines can be defined as a pre-charging operation.

[0052] After the precharge operation has started and a first time period has elapsed since the start of the precharge operation, the page buffer can store the data of the selected memory cell connected to the bit line in the first storage circuit (S20). The first storage circuit can be a latch circuit or a buffer circuit included in the page buffer. The first time period can be insufficient time to complete the precharge operation. For example, the page buffer can approximately sense the data of the selected memory cell and store it in the first storage circuit before the precharge operation is completed, causing the bit line to reach a target voltage. In the example, the data of the selected memory cell stored in the first storage circuit can correspond to the threshold voltage of the selected memory cell.

[0053] The page buffer can use data stored in the first storage circuit to determine whether the state of the selected memory cell is OFF (S30). In the example embodiment, depending on the threshold voltage, the selected memory cell can be in an OFF state or an ON state, and the selected memory cell in the OFF state can have a relatively large threshold voltage.

[0054] When the selected memory cell is determined to be OFF in operation S30 (S30, Yes), the page buffer can reduce the magnitude of the input bit line charging current (S40). When the selected memory cell is determined to be ON in operation S30 (S30, No), the page buffer can maintain the input bit line charging current unchanged (S50). In the example embodiment, the page buffer can control the magnitude of the current flowing in the switching element by controlling the control voltage input to the switching element connected between the charging circuit and the bit line. The magnitude of the charging current can be changed by adjusting the magnitude of the current flowing in the switching element. After the bit line charging begins and a first time period has elapsed, the magnitude of the input bit line charging current can be reduced or maintained.

[0055] When a second time period has elapsed after the first time period (i.e., after the data has been stored in the first storage circuit), the page buffer can read the data from the selected memory cell and store the data in the second storage circuit (S60). The sum of the first and second time periods can be a time period sufficient to complete the precharging operation for the bit line so that the voltage of the bit line reaches the target voltage. The first and second time periods can be included in the precharging time period, and as an example, the sum of the first and second time periods can be defined as the precharging period. The first and second time periods can be different, and in an example embodiment, the second time period can be longer than the first time period.

[0056] When the selected memory cell is in the ON state, the charging current can flow through the selected memory cell after the bit line capacitor has been charged by the charging current. Therefore, when the selected memory cell is in the ON state, the bit line voltage can be stabilized after the bit line capacitor has been charged. When the selected memory cell is in the OFF state, the bit line voltage can increase even after the bit line capacitor has been charged by the charging current. Therefore, the pre-charge period can be extended for the bit line connected to the selected memory cell in the OFF state.

[0057] In the example embodiment, after the precharge operation has started and the first time period has elapsed, the state of the selected memory cell can be roughly determined, and the amount of charge input to the bit line can be changed. For example, when it is determined that the selected memory cell is in the OFF state, the amount of charge can be reduced, and the precharge operation can be completed quickly. Therefore, the time required for the precharge operation can be reduced. Furthermore, regardless of the state of the selected memory cell, the voltage of the bit line after the page buffer's precharge operation is completed can be determined to be at the same level.

[0058] Figure 6This is a diagram illustrating a read operation of a storage device according to an example embodiment.

[0059] Figure 6 This is a graph showing the threshold voltage distribution of the memory cells included in a memory device. (Reference) Figure 6 When a memory cell is in the OFF state, its threshold voltage can be higher than the reference voltage V. REF On the other hand, the threshold voltage of a memory cell in the ON state can be lower than the reference voltage V. REF .

[0060] In an example embodiment, the page buffer can read data from a selected memory cell in the memory cell and store that data in a latch circuit, with reference voltage V. REF This could be a trip voltage that can change the latch value stored in the latch circuitry contained in the page buffer. For example, when the voltage of the sensing node connected to the bit line in the page buffer is higher than the reference voltage V... REF When the OFF state is reached, the data corresponding to the OFF state can be stored in the latch circuit of the page buffer. Conversely, when the voltage of the sensing node is lower than the reference voltage V... REF When the ON state is active, the data corresponding to the ON state can be stored in the latch circuit of the page buffer.

[0061] Figure 7 This is a schematic circuit diagram of a page buffer according to an example embodiment.

[0062] refer to Figure 7 The page buffer 300 may include a first storage circuit 310, a second storage circuit 320, a selection circuit 330, a charging circuit 340, a sensing circuit 350, etc. The charging circuit 340 can be connected to the bit line BL via a switching element SW, and the memory cell MC can be connected to the bit line BL. The gate of the memory cell MC can be connected to the word line WL.

[0063] Each of the first storage circuit 310 and the second storage circuit 320 can be implemented as a latch, buffer, etc. The selection circuit 330 may include a first selection device SE1 and a second selection device SE2, and the first selection device SE1 and the second selection device SE2 can be controlled by data stored in the first storage circuit 310. The first selection device SE1 receives a first control voltage SEL_on, and the second selection device SE2 receives a second control voltage SEL_off. In an example embodiment, the first control voltage SEL_on and the second control voltage SEL_off can be constant voltages and can have different magnitudes.

[0064] When the switching element SW is turned on by the selection circuit 330, the charging circuit 340 can input the charging current to the bit line BL and can start the pre-charging operation. In the development operation following the pre-charging operation, the voltage of the sensing node SO included in the sensing circuit 350 can be changed according to the state of the memory cell MC. For example, the voltage of the sensing node SO when the memory cell MC is OFF can be higher than the voltage of the sensing node SO when the memory cell MC is ON.

[0065] During the pre-charge operation, the first storage circuit 310 can roughly determine and store the state of the memory cell MC. The operation of the first selection device SE1 and the second selection device SE2 can be changed based on the state of the memory cell MC roughly determined by the first storage circuit 310, and the magnitude of the charging current input to the bit line BL can be changed. Referring below... Figures 8 to 10 A more detailed description of the page buffer operation.

[0066] Figures 8 to 10 This is a circuit diagram illustrating the operation of the page buffer according to an example embodiment.

[0067] refer to Figures 8 to 10 Both the first storage circuit 310 and the second storage circuit 320 of the page buffer 300 can be implemented as latching circuits. Alternatively, the first storage circuit 310 and the second storage circuit 320 can also be implemented using various other circuits capable of storing data. (See reference...) Figures 8 to 10 In the example embodiment shown, the control signals input to the transistors included in the first storage circuit 310, the selection circuit 330, and the charging circuit 340 can be defined as shown in Table 1 below.

[0068] [Table 1]

[0069]

[0070] When a read operation begins to read data from memory cell MC, transistors PM1, NM1, and PM2 of charging circuit 340 are turned on, and bit line BL can be pre-charged. As an example, when bit line BL is pre-charged, first selection device SE1 can be turned on, while second selection device SE2 can be turned off, such as... Figure 8 As shown. Therefore, the first control voltage SEL_on input to the first selection device SE1 can be selected as the control voltage SEL of the switching element SW. The switching element SW is turned on by the first control voltage SEL_on, and the current flowing in the switching element SW can be the charging current that supplies charge to the bit line BL.

[0071] When the precharge operation for bit line BL begins and the first time period has elapsed, page buffer 300 can coarsely read data from memory cell MC and store the data in first storage circuit 310. Refer to Table 1 and... Figures 8 to 10 The second PMOS transistor PM2 can be turned off to perform a pre-sensing operation that coarsely reads the data from the memory cell MC. In an example embodiment, the first time period can be a period sufficient to charge the self-capacitance of the bit line BL. Therefore, the voltage of the sensing node SO after the first time period has elapsed can be determined by the threshold voltage of the memory cell MC.

[0072] For example, when the threshold voltage of the memory cell MC is low, the current flowing in the memory cell MC can be generated by the charging current input to the bit line BL via the charging circuit 340, and the voltage of the sensing node SO can be relatively low. Conversely, when the threshold voltage of the memory cell MC is high, the magnitude of the current flowing in the memory cell MC is small, and the voltage of the sensing node SO can be relatively high.

[0073] For example, when the threshold voltage of memory cell MC is high, the second NMOS transistor NM2 of sensing circuit 350 can be turned on by the voltage of sensing node SO when memory cell MC is OFF. When the reset signal pRST of first storage circuit 310 is set to a low logic value and the set signal pSET is set to a high logic value, the low logic value is stored in the PD node of first storage circuit 310, and the high logic value can be stored in the nPD node. Therefore, as Figure 9 As shown, in the selection circuit 330, the first selection device SE1 can be turned off and the second selection device SE2 can be turned on, and the control voltage SEL_off can be input to the gate of the switching element SW.

[0074] When the threshold voltage of memory cell MC is low, for example, when memory cell MC is in the ON state, the second NMOS transistor NM2 may not be turned on by the voltage of sensing node SO. Therefore, it is possible to maintain the high logic value stored in the PD node of the first storage circuit 310 and the low logic value stored in the nPD node. Figure 10 As shown, the first selection device SE1 of the selection circuit 330 can be continuously turned on, while the second selection device SE2 can be continuously turned off. The control voltage SEL input to the switching element SW can be maintained at the first control voltage SEL_on.

[0075] In the example embodiment, the second control voltage SEL_off can be lower than the first control voltage SEL_on. When the selection circuit 330 outputs the second control voltage SEL_off, the current flowing in the switching element SW decreases, thus reducing the charging current input to the bit line BL. According to the example embodiment, when the memory cell MC is in the OFF state, the time required to complete the pre-charging operation of the bit line BL can be reduced by changing the output of the selection circuit 330 from the first control voltage SEL_on to the second control voltage SEL_off.

[0076] Data from the memory cell MC read via pre-sensing can be used to determine whether to change the output of the selection circuit 330. After the pre-sensing and pre-charging operations are completed, a main sensing operation can be performed to read data from the memory cell MC and store the data in the second storage circuit 320. The control signals input to the transistors included in the second storage circuit 320, the selection circuit 330, and the charging circuit 340 to perform the main sensing operation can be defined as shown in Table 1 above. (Refer to...) Figures 8 to 10 In the operation of the page buffer 300 described, the voltage input to the word line WL of the memory cell MC can be constant.

[0077] Figures 11 to 13 This is a graph illustrating the operation of a storage device according to an example embodiment. In the following description, reference will be made to... Figure 7 The page buffer 300 shown is used to describe the operation of the storage device.

[0078] Figure 11 This is a graph showing the output of the selection circuit 330 based on the state of the memory cell MC. Figure 12 It can be a graph showing the voltage of bit line BL based on the state of memory cell MC and the output of selection circuit 330. Figure 13 It can be a graph showing the current of the bit line BL based on the state of the memory cell MC and the output of the selection circuit 330.

[0079] Reference Figures 11 to 13 In the described example embodiment, the page buffer 300 approximately reads data from the memory cell MC during or after a first time period T1 to store the data in the first storage circuit 310. The second time period T2 and the third time period T3 may be the time periods required for the page buffer 300 according to the example embodiment to complete the pre-charge operation of the bit line BL.

[0080] Figure 11 This is a graph showing the control voltage SEL of Example Embodiment 402 according to the present invention and its variation compared to Example 401. (See reference) Figure 11In Comparative Example 401, the magnitude of the control voltage SEL is fixed, while in Example Embodiment 402, the control voltage SEL can decrease from a first control voltage SEL_on to a second control voltage SEL_off at a first time point t1. The first time point t1 can be the end point of a first time period T1. Example Embodiment 402 can correspond to the case where the state of the memory cell MC to which the page buffer 300 is to read data is OFF.

[0081] Figure 12 and Figure 13 These are graphs showing the voltage and current of the bit line BL. (Reference) Figure 12 and Figure 13 The first time period T1 may include the charging time TC required to charge the capacitor of bit line BL. The voltage and current of bit line BL may increase during the charging time TC, and the current of bit line BL may decrease after the charging time TC has elapsed.

[0082] Unlike Comparative Example 401, in Example Embodiment 402, the control voltage SEL input to the switching element SW can decrease at a first time point t1. Therefore, after the first time point t1, the current supplied to the bit line BL by the charging circuit 340 through the switching element SW can decrease rapidly, and the voltage of the bit line BL can also decrease after the first time point t1. Meanwhile, in Comparative Example 401, the voltage of the bit line BL may increase even after the first time point t1. In Example Embodiment 402, the voltage of the bit line BL can stabilize relatively faster than the voltage in Comparative Example 401, and the time required for the pre-charging operation of charging the bit line BL can be determined by the sum of the first time period T1 and the second time period T2. Conversely, in Comparative Example 401, the time required for the pre-charging operation can be determined by the sum of the first time period T1 and the third time period T3. In Example Embodiment 402, the pre-charging operation terminates at a second time point t2, while in Comparative Example 401, the pre-charging operation terminates at a third time point t3 after the second time point t2.

[0083] When the memory cell MC is ON, in the example embodiment, similar to Comparative Example 401, the selection voltage SEL can be maintained at the first control voltage SEL_on. When the memory cell MC is ON, a portion of the current supplied to the bit line BL by the charging circuit 340 can flow through the memory cell MC, and the voltage and current of the bit line BL can be stabilized more quickly compared to when the memory cell MC is OFF.

[0084] According to the example embodiment, when the memory cell MC is in the OFF state, the selection voltage SEL decreases to the second control voltage SEL_off at a first time point t1, and when the memory cell MC is in the ON state, the selection voltage SEL can be maintained at the first control voltage SEL_on. Therefore, regardless of the state of the memory cell MC, the time required for the precharge operation can be set to be substantially the same. Furthermore, when charging multiple bit lines BL simultaneously, the precharge operation on multiple bit lines BL can be terminated approximately in the same manner, thereby improving the speed of the memory device's read operation and reducing power consumption.

[0085] Figures 14 to 16 This is a diagram illustrating the operation of a storage device according to an example embodiment.

[0086] refer to Figures 14 to 16 The storage device may include multiple bit lines BL1 to BL5 and multiple memory cells MC1 to MC5 connected to the multiple bit lines BL1 to BL5. In the following description, for ease of description, the case where the page buffer performs a read operation to read data from the third memory cell MC3 via the third bit line BL3 will be described.

[0087] The page buffer can perform a precharge operation to increase the voltage of the third bit line BL3 to a target voltage in order to read data from the third memory cell MC3. Figures 14 to 16 In an example embodiment, bit lines BL1 to BL5 can be charged simultaneously via a pre-charge operation. During the pre-charge operation, in order to increase the voltage of the third bit line BL3 to the required voltage level, current can be supplied to bit lines BL1 to BL5 for a sufficient period of time to charge the coupling capacitors C13, C23, C34, and C35 between bit lines BL1 to BL5.

[0088] The time required for the pre-charge operation can also be varied depending on the state of the adjacent memory cells MC1, MC2, MC4, and MC5 provided around the third memory cell MC3, which is the selected memory cell. As an example, such as... Figure 14 As shown, when the adjacent memory cells MC1, MC2, MC4, and MC5 of the third memory cell MC3 are in the OFF state, the time required for the precharge operation will increase significantly. Since bit lines BL1 to BL5 are charged simultaneously, the time required for the precharge operation to charge adjacent bit lines BL1, BL2, BL4, and BL5 can be increased when adjacent memory cells MC1, MC2, MC4, and MC5 are in the OFF state. On the other hand, as... Figure 15 As shown, when adjacent memory cells MC1, MC2, MC4, and MC5 are in the ON state, the time required for the precharge operation can be relatively reduced. Figure 16As shown, when some of the adjacent memory cells MC1, MC2, MC4, and MC5 are in the OFF state and the remaining memory cells are in the ON state, the time required for the precharge operation is longer than that required for the precharge operation. Figure 14 The example embodiments shown are shorter in time and can be faster than... Figure 15 The exemplary embodiment shown is long.

[0089] In the example embodiment, the states of memory cells MC1 to MC5 are first approximately determined, and the amount of charge applied to bit lines BL1 to BL5 can be adjusted based on these states. For example, the magnitude of the charging current input to each bit line BL1 to BL5 being charged simultaneously can be changed based on the states of memory cells MC1 to MC5. As an example, when the states of memory cells MC1 to MC5 are determined to be OFF, the magnitude of the charging current applied to bit lines BL1 to BL5 during the pre-charge operation can be reduced. Therefore, regardless of the states of memory cells MC1 to MC5, the end timing of the pre-charge operation for the simultaneously charged bit lines BL1 to BL5 can be synchronized, and the time and power consumption required for the pre-charge operation can be reduced.

[0090] Figure 17 This is a diagram illustrating a read operation of a storage device according to an example embodiment.

[0091] exist Figure 17 In the example embodiment shown, the memory cell of the storage device can store two bits of data. The memory cell can be used as a multi-level cell (MLC), so the memory cell can have multiple OFF states (OFF1 to OFF3). When the memory cell is used as a three-level or four-level cell, the number of OFF states that the memory cell may have can be further increased.

[0092] The page buffer can be configured by comparing the threshold voltage of the selected memory cell with multiple reference voltages V. REF1 To V REF3 The data in the selected memory cell is determined through comparison. As an example, the page buffer may include multiple latch circuits, and the latch values ​​of the multiple corresponding latch circuits can be varied by having different trip voltages. In the example embodiment, the trip voltages of the multiple latch circuits may correspond to multiple reference voltages V. REF1 To V REF3 .

[0093] The page buffer can also coarsely detect the state of the selected memory cell to determine whether to change the magnitude of the charging current input to the bit line connected to the selected memory cell. For example, the magnitude of the charging current input to the bit line connected to the selected memory cell having a third OFF state (OFF3) can be less than the magnitude of the charging current input to the bit line connected to the selected memory cell having a first OFF state (OFF1). For example, as the threshold voltage of the selected memory cell increases, the page buffer can increase the decrease in the charging current input to the bit line connected to the selected memory cell.

[0094] Figure 18 This is a schematic diagram illustrating a page buffer according to an example embodiment.

[0095] refer to Figure 18 The page buffer 500 may include a first storage circuit 510, a second storage circuit 520, a selection circuit 530, a charging circuit 540, a sensing circuit 550, etc. The configuration and operation of the second storage circuit 520, the charging circuit 540, and the sensing circuit 550 can be similar to those described in the reference. Figure 7 Those described.

[0096] exist Figure 18 In the illustrated example embodiment, the selection circuit 530 may include first selection devices SE1 to fourth selection devices SE4. The first to fourth selection devices SE1 to SE4 may receive first to fourth control voltages SEL_on to SEL_off3. The first to fourth control voltages SEL_on to SEL_off3 may be constant voltages of different magnitudes. As an example, the first control voltage SEL_on may be the lowest voltage, and the fourth control voltage SEL_off3 may be the highest voltage. The second control voltage SEL_off1 may be lower than the third control voltage SEL_off2.

[0097] The first storage circuit 510 may include multiple latching circuits, and the multiple latching circuits included in the first storage circuit 510 can be operated by different tripping voltages. As an example, the first storage circuit 510 may include a first latching circuit that controls a first selection device SE1 and a second selection device SE2, and a second latching circuit that controls a third selection device SE3 and a fourth selection device SE4.

[0098] The charging circuit 540 can charge the capacitance of the bit line BL by inputting a charging current to the bit line BL during a first time period. During the first time period, the page buffer 500 can use the voltage of the sensing node SO to roughly determine the data in the memory cell MC. The page buffer 500 can use the threshold voltage of the memory cell MC to roughly determine the data stored in the memory cell MC.

[0099] For reference Figure 17 As described, the memory cell MC can have multiple OFF states, OFF1 to OFF3. When the state of the memory cell MC is determined to be the first OFF state, OFF1, the second selection device SE2 of the selection circuit 530 is turned on, and the remaining selection devices SE1, SE3, and SE4 can be turned off, allowing the second control voltage SEL_off1 to be input to the switching element SW as a control voltage. Similarly, when the state of the memory cell MC is determined to be the second OFF state, OFF2, the third selection device SE3 of the selection circuit 530 is turned on, and the remaining selection devices SE1, SE2, and SE4 can be turned off, allowing the third control voltage SEL_off2 to be input to the switching element SW. In the example embodiment, the number of control voltages that the selection circuit 530 can input to the switching element SW can be determined based on the number of states that the memory cell MC can have.

[0100] Figure 19 This is a block diagram schematically illustrating a storage device according to an example embodiment.

[0101] exist Figure 19 In the illustrated example embodiment, the storage device 600 may include a memory cell array 610, a page buffer circuit 620, etc. The memory cell array 610 may include first to fourth bit lines BL1 to BL4, first to fourth word lines WL1 to WL4, and a plurality of memory cells MC. The plurality of memory cells MC may be provided at the points where the first to fourth bit lines BL1 to BL4 and the first to fourth word lines WL1 to WL4 intersect each other. Each memory cell MC may include a switching element and a variable resistor element, and data may be recorded using the resistance change of the variable resistor element.

[0102] exist Figure 19 In the example embodiment shown, the page buffer circuit 620 can read data from a selected memory cell connected to a first word line WL1 and a fourth bit line BL4. The first word line WL1, connected to the selected memory cell, is provided as the selected word line and receives a first bias voltage VB1, while the fourth bit line BL4, also connected to the selected memory cell, is provided as the selected bit line and can receive a second bias voltage VB2. A third bias voltage VB3 can be input to the second to fourth word lines WL2 to WL4 and the first to third bit lines BL1 to BL3 that are not connected to the selected memory cell. The input method of the bias voltages VB1, VB2, and VB3 can be... Figure 21 The methods shown are modified differently.

[0103] For example, the first bias voltage VB1 can be higher than the second bias voltage VB2, and the third bias voltage VB3 can be lower than the first bias voltage VB1 and higher than the second bias voltage VB2. Therefore, the voltage difference applied to the selected memory cell can be greater than the voltage difference applied to the unselected memory cell, and specifically, current can flow only through the selected memory cell. The page buffer circuit 620 can use the current flowing in the selected memory cell and the fourth bit line BL4 to generate a read voltage, and compares the read voltage with a predetermined reference voltage to determine the data written to the selected memory cell.

[0104] In the example embodiment, the page buffer circuit 620 can perform a pre-charge operation using a first bias voltage VB1 input to the first word line WL1, which is the select word line, and a second bias voltage VB2 input to the fourth bit line BL4, which is the selected bit line. Additionally, the page buffer circuit 620 can perform a pre-sensing operation to roughly determine the data of the selected memory cell using the voltage and / or current of the selected memory cell.

[0105] In an example embodiment, when it is determined during the pre-sensing operation that the resistance of the variable resistor element included in the selected memory cell is relatively high, the page buffer circuit 620 may include the difference between the first bias voltage VB1 and the second bias voltage VB2. On the other hand, when it is determined during the pre-sensing operation that the resistance of the variable resistor element included in the selected memory cell is relatively low, the page buffer circuit 620 may maintain the magnitudes of the first bias voltage VB1 and the second bias voltage VB2.

[0106] Figure 20 This is a block diagram schematically illustrating a storage device according to an example embodiment.

[0107] refer to Figure 20 The memory device 700 may include a memory cell array 710 and a page buffer circuit 720, and the page buffer circuit 720 may include a selection circuit 730, a charging circuit 740, a sensing circuit 750, etc. The memory cell array 710 may include a plurality of memory cells MC11 to MC14 and MC21 to MC24 connected to a plurality of word lines WL1 to WL2 and a plurality of bit lines BL1 to BL4.

[0108] When word lines WL1 to WL2 and bit lines BL1 to BL4 are selected, a bias voltage can be input to each of the word lines WL1 to WL2 and bit lines BL1 to BL4 via charging circuit 740 and sensing circuit 750. Due to the bias voltage, voltage differences may occur in the individual memory cells MC11 to MC14 and MC21 to MC24, and the voltage difference occurring in the selected memory cells may be greater than the voltage difference occurring in the unselected memory cells.

[0109] As an example, when the first word line WL1 and the first bit line BL1 are determined as the selected word line and the selected bit line, a bias voltage can be applied to the two terminals of the selected memory cell MC11, resulting in a relatively high voltage difference. When the bias voltage is input by the charging circuit 740 and the sensing circuit 750, the sensing circuit 750 can perform a pre-sensing operation to roughly determine the data of the selected memory cell MC11.

[0110] In the example embodiment, when the resistance of the variable resistor element of the selected memory cell MC11 is determined to be relatively high through a pre-sensing operation, the voltage difference applied to the selected memory cell MC11 by the charging circuit 740 and the sensing circuit 750 can be reduced. When the resistance of the variable resistor element of the selected memory cell MC11 is determined to be relatively low through a pre-sensing operation, the charging circuit 740 and the sensing circuit 750 can maintain the voltage difference applied to the selected memory cell MC11. Therefore, the voltage difference between the selected bit line BL1 and the selected word line WL1, which depends on the data in the selected memory cell MC11, can be significantly reduced, and the speed of the read operation can be improved and power consumption can be reduced.

[0111] Figure 21 This is a block diagram of an electronic device including a storage device according to an example embodiment.

[0112] Figure 21 The illustrated electronic device 1000 may include a display 1010, a sensor 1020, a memory 1030, a processor 1040, a port 1050, etc. The electronic device 1000 may further include wired / wireless communication equipment, a power supply device, etc. Figure 21 Among the components shown, the processor 1040 may be a device provided to allow the electronic device 1000 to communicate with video cards, sound cards, memory cards, USB devices, etc. The electronic device 1000 may be a general concept, including smartphones, tablet PCs, smart wearable devices, as well as general-purpose desktop computers and laptop computers.

[0113] Port 1050 can perform specific operations, commands, tasks, etc. Port 1050 can be a central processing unit (CPU) or a microprocessor unit (MCU), and can communicate with display 1010, sensor 1020 and storage device 1030 via bus 1060, and can also communicate with other devices connected to processor 1040.

[0114] The memory 1030 may be a storage medium for storing data, multimedia data, etc., required for the operation of the electronic device 1000. The memory 1030 may include volatile memory (such as random access memory (RAM)) or non-volatile memory (such as flash memory). The memory 1030 may also include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage device. The memory 1030 may include, according to the above references Figures 1 to 20 Any of the various example embodiments of the described storage device.

[0115] As described above, according to the example embodiment, while increasing the voltage of the bit line, data from the selected memory cell connected to the bit line is read and stored in the storage circuit. The magnitude of the input voltage to the bit line can be adjusted based on the data stored in the storage circuit. Therefore, the time required for the pre-charging operation to charge the bit line can be reduced, thereby improving the performance of the storage device.

[0116] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A page buffer, comprising: The charging circuit is configured to charge the bit line during the pre-charging time period; A first storage circuit is configured to determine and store data corresponding to the state of a selected memory cell among a plurality of memory cells connected to the bit line when the charging circuit charges the bit line; The second storage circuit, which is separate from the first storage circuit, is configured to determine and store data corresponding to the state of the selected memory cell after the precharge period. as well as The selection circuit is configured to output a control voltage to a switching element connected between the bit line and the charging circuit, and to determine the magnitude of the control voltage during the pre-charging time period based on the data stored in the first storage circuit.

2. The page buffer according to claim 1, wherein, The pre-charging time period includes a first time period and a second time period following the first time period, and The selection circuit outputs a first control voltage during the first time period and outputs one of the first control voltage and a second control voltage lower than the first control voltage during the second time period.

3. The page buffer according to claim 2, wherein, When the data stored in the first storage circuit corresponds to the OFF state of the selected memory cell, the selection circuit outputs the second control voltage during the second time period.

4. The page buffer according to claim 2, wherein, When the data stored in the first storage circuit corresponds to the ON state of the selected memory cell, the selection circuit outputs the first control voltage during the second time period.

5. The page buffer according to claim 2, wherein, The first time period is different from the second time period.

6. The page buffer according to claim 2, wherein, The first time period is shorter than the second time period.

7. The page buffer according to claim 1, wherein, The selection circuit includes a first selection device and a second selection device connected to the gate of the switching element.

8. The page buffer according to claim 7, wherein, The first selection device and the second selection device are turned on or off by the data stored in the first storage circuit.

9. The page buffer according to claim 1, wherein, The first storage circuit includes at least one of a latch circuit and a buffer circuit.

10. The page buffer according to claim 1, wherein, The first storage circuit and the second storage circuit share a sensing node connected to the bit line via the switching element.

11. The page buffer according to claim 1, wherein, During the pre-charge period, the first storage circuit is activated and the second storage circuit is deactivated, and When the pre-charging period has elapsed, the first storage circuit is deactivated and the second storage circuit is activated.

12. A storage device comprising: A memory cell array includes a plurality of memory cells and a plurality of bit lines connected to the plurality of memory cells; as well as The memory controller is configured to read data corresponding to a threshold voltage of a selected memory cell connected to a selected bit line among the plurality of bit lines, to input a first charging current to the selected bit line during a first time period, and to input a second charging current lower than the first charging current to the selected bit line during a second time period after the first time period when the threshold voltage of the selected memory cell is higher than a reference voltage.

13. The storage device according to claim 12, wherein, When the threshold voltage of the selected memory cell is lower than the reference voltage, the first charging current is input to the selected bit line during the second time period.

14. The storage device according to claim 12, wherein, The memory controller includes: The charging circuit is connected to the selected bit line via a switching element; The storage circuitry is configured to read and store data from selected memory cells; and The selection circuit is configured to determine the current of the switching element as one of the first charging current and the second charging current based on data stored in the storage circuit.

15. The storage device according to claim 14, wherein, The storage circuit includes: a first storage circuit that reads and stores data corresponding to a threshold voltage of a selected memory cell during a first time period; and a second storage circuit that reads and stores data corresponding to a threshold voltage of a selected memory cell during a second time period; and The selection circuit determines the current of the switching element as either the first charging current or the second charging current during the second time period based on data stored in the first storage circuit.

16. The storage device according to claim 12, wherein, The reference voltage has a first reference voltage and a second reference voltage that is higher than the first reference voltage.

17. The storage device according to claim 16, wherein, When the threshold voltage of the selected memory cell is higher than the first reference voltage and lower than the second reference voltage, the memory controller inputs the second charging current to the selected bit line during the second time period. When the threshold voltage of the selected memory cell is higher than the second reference voltage, during the second time period, the memory controller inputs a third charging current, which is less than the second charging current, to the selected bit line.

18. The storage device according to claim 12, wherein, The selected bit lines include a first selected bit line and a second selected bit line, and the selected memory cells include a first selected memory cell connected to the first selected bit line and a second selected memory cell connected to the second selected bit line; as well as The memory controller is configured to charge both the first selected bit line and the second selected bit line simultaneously.

19. The storage device according to claim 18, wherein, The memory controller determines the charging current input to each of the first selected bit line and the second selected bit line during the second time period based on the threshold voltage of the first selected memory cell and the threshold voltage of the second selected memory cell.

20. A storage device comprising: A memory cell array includes a plurality of memory cells connected to a plurality of bit lines, each of the plurality of memory cells having one of a first threshold voltage and a second threshold voltage lower than the first threshold voltage; as well as A memory controller is configured to simultaneously charge a first bit line connected to a first memory cell having a first threshold voltage and a second bit line connected to a second memory cell having a second threshold voltage, and is configured to simultaneously charge the first bit line and the second bit line by inputting a first charging current to the first bit line and a second charging current different from the first charging current to the second bit line.

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