Semiconductor device package and method for manufacturing the same

Abstract

A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer, and a second substrate. The first substrate has a first surface and a second surface opposite the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and is spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on the first surface of the dielectric layer facing away from the support layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly, to a semiconductor device package including an antenna and a method of manufacturing the same. Background Art

[0002] The development of mobile communication has led to a demand for high data rates and stable communication quality, and high-frequency wireless transmission (e.g., 28 GHz or 60 GHz) has become one of the most important topics in the mobile communication industry. To achieve such high-frequency wireless transmission, signals can be transmitted in a frequency band of about ten millimeters to about one millimeter in wavelength (the "millimeter wave" or "mm wave"). However, one of the problems with millimeter wave transmission is signal attenuation. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer, and a second substrate. The first substrate has a first surface and a second surface opposite the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and is spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on the first surface of the dielectric layer facing away from the support layer.

[0004] According to some embodiments of the present disclosure, a semiconductor device package includes a first substrate, an antenna element, a second substrate, and a foaming agent. The first substrate has a first surface and a second surface opposite the first surface. The antenna element is disposed on the second surface of the first substrate. The second substrate is disposed on the first substrate. The first substrate and the second substrate define a cavity. The foaming agent is disposed in the cavity.

[0005] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device package includes (a) pre-curing a first photosensitive element on a first substrate; (b) pre-curing a second photosensitive element on a second substrate; (c) attaching the first photosensitive element to the second photosensitive element; and (d) fully curing the first photosensitive element and the second photosensitive element. Brief Description of the Drawings

[0006] Figure 1 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0007] Figure 2A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is illustrated.

[0008] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F A semiconductor manufacturing method according to some embodiments of the present disclosure is illustrated.

[0009] Figure 4A , Figure 4B and Figure 4C A semiconductor manufacturing method according to some embodiments of the present disclosure is illustrated.

[0010] Figure 5A , Figure 5B and Figure 5C A semiconductor manufacturing method according to some embodiments of the present disclosure is illustrated.

[0011] Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings. Detailed Description

[0012] Figure 1 A cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 1 includes substrates 10, 12, a dielectric layer 11, an antenna element 13, an electronic component 14, an electrical contact 15, and a package body 16.

[0013] The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. In some embodiments, the substrate 10 may be a single-layer substrate or a multi-layer substrate. The substrate 10 has a surface 101 and a surface 102 opposite to the surface 101.

[0014] The antenna element 13 is disposed on the surface 102 of the substrate 10. In some embodiments, the antenna element 13 penetrates the substrate 10 and is exposed from the surface 101 of the substrate 10. In some embodiments, the antenna element 13 includes a plurality of antenna elements. For example, the antenna element 13 may include an antenna element array. In some embodiments, the antenna element 13 may include an M×N antenna element array, where M and N are integers greater than 0. In some embodiments, the antenna element 13 is formed of or includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more thereof.

[0015] The dielectric layer 11 is disposed on the surface 101 of the substrate 10. The dielectric layer 11 has surfaces 111, 112, 113, and 114. The surface 111 faces away from the substrate 10. The surface 112 is connected to the surface 101 of the substrate 10. The surface 113 faces the substrate 10 and is spaced apart from the substrate 10. The surface 114 extends between the surface 112 and the surface 113. The dielectric layer 11 has a portion 11a (which may also be referred to as a "support element") disposed on the surface 101 of the substrate 10 and a portion 11b disposed on the portion 11a. In some embodiments, the portion 11a of the dielectric layer 11 is chemically bonded to the portion 11b of the dielectric layer 11. The portion 11a is disposed at the periphery of the surface 101 of the substrate 10. In some embodiments, the dielectric layer 11 and the substrate 10 define a cavity 10c (or chamber). For example, the portion 11b of the dielectric layer 11 defines the upper portion of the cavity 10c, the substrate 10 defines the lower portion of the cavity 10c, and the portion 11a of the dielectric layer 11 defines the sidewall of the cavity 10c. For example, the surface 113 of the dielectric layer 11 defines the upper surface of the cavity 10c, the surface 101 of the substrate 10 defines the lower surface of the cavity 10c, and the surface 114 of the dielectric layer 11 defines the sidewall of the cavity 10c.

[0016] The dielectric layer 11 may include a conductive layer 11r disposed therein. In some embodiments, the conductive layer 11r penetrates through the portion 11b of the dielectric layer 11 and is exposed from the surfaces 111 and 113 of the dielectric layer 11 for electrical connection. A conductive element 10p (e.g., a copper pillar) is disposed within the cavity 10c and electrically connects the antenna element 13 to the conductive layer 11r. The conductive element 10p is or includes a conductive material, such as a metal or a metal alloy. Examples of the conductive material include Au, Ag, Cu, Pt, Pd, or an alloy thereof. In some embodiments, the conductive element 10p may be omitted, and signals may be transmitted between the antenna element 13 and the conductive layer 11r by coupling.

[0017] In some embodiments, the dielectric layer 11 includes a photosensitive material. For example, the dielectric layer 11 includes expanded polyolefin (EPO), solder mask, polyimide (PI), epoxy resin, and / or polybenzoxazole (PBO). In some embodiments, the portion 11a and the portion 11b of the dielectric layer 11 are formed of the same material. Alternatively, the portion 11a and the portion 11b of the dielectric layer 11 are formed of different materials.

[0018] The substrate 12 is disposed on the surface 111 of the dielectric layer 11. The substrate 12 can be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 12 can include an interconnect structure 12r, such as a redistribution layer (RDL) or a ground element. In some embodiments, a portion of the interconnect structure 12r is exposed from the substrate 12 to electrically connect to the conductive layer 11r of the dielectric layer 11. The interconnect structure 12r is or includes a conductive material, such as a metal or a metal alloy. Examples of the conductive material include Au, Ag, Cu, Pt, Pd, or alloys thereof. In some embodiments, the substrate 12 can be a single-layer substrate or a multi-layer substrate including a core layer and a conductive material. The conductive material and / or structure can include a plurality of traces. The substrate 12 can include one or more conductive pads 12c that are proximate to, adjacent to, or embedded in and exposed at the surface 121 of the substrate 12. The substrate 12 can include a solder mask 12m (or solder resist) on the surface 121 of the substrate 12 to completely expose or expose at least a portion of the conductive pads 12c for electrical connection. For example, the solder mask 12m can cover a portion of the conductive pads 12c.

[0019] The electronic component 14 is disposed on the surface 121 of the substrate 12 and is electrically connected to the conductive pads 12c of the substrate 12. The electronic component 14 can be an active electronic component, such as an integrated circuit (IC) chip or die. In some embodiments, the conductive pads 12c are directly connected to the conductive terminals (e.g., copper pillars) of the active surface of the electronic component 14. In other embodiments, the electronic component 14 can be electrically connected to the substrate 12 by means of flip-chip or wire bonding techniques.

[0020] The electrical contact 15 is disposed on the substrate 12 (e.g., on the conductive pads of the substrate 12) to provide an electrical connection between the semiconductor device package 1 and any other circuit board (e.g., a substrate, a PCB, a motherboard, etc.) or circuit. In some embodiments, the electrical contact 15 is a solder ball or a conductive pillar.

[0021] The package 16 is disposed on the substrate 12 and covers or encapsulates a portion of the electronic component 14 and the electrical contact 15. The back surface of the electronic component 14 is exposed from the package 16. In some embodiments, the back surface of the electronic component 14 is substantially coplanar with the surface 162 of the package 16. A portion of the electrical contact 15 is exposed from the package 16 for electrical connection. In some embodiments, the package 16 includes an epoxy resin with fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material with silicone dispersed therein, or a combination thereof.

[0022] As Figure 1As shown, since the dielectric layer 11 and the substrate 10 are arranged to define a height, a distance, and one or more cavities (such as air cavities) therebetween, the gain, bandwidth, and radiation efficiency of the antenna element 13 can be improved. In some embodiments, the cavity 10c can be a vacuum cavity (or vacuum chamber) or a near-vacuum cavity, which can prevent delamination between the substrate 10 and the dielectric layer 11 or the substrate 12 due to air expansion during heat treatment and thereby increase the reliability of the semiconductor device package 1.

[0023] Figure 2 A cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 2 is similar to Figure 1 the semiconductor device package 1 in, and the differences therebetween are described below.

[0024] The support structure 22 is disposed on the surface 101 of the substrate 10. The support structure 22 is disposed at the periphery of the surface 101 of the substrate 10. The support structure 22, the substrate 10, and the substrate 12 define a cavity 20c. In some embodiments, the support structure 22 can be the dielectric layer 11 as shown in Figure 1 . Alternatively, the support structure 22 can be or include any other suitable material, such as a solder mask. The support structure 22 is connected to the substrate 12 through an adhesion layer 21 (such as a die attach film (DAF) or tape). In some embodiments, the conductive element 10p can penetrate the adhesion layer 21 to electrically connect to the interconnect structure 12r. In some embodiments, the adhesion layer 21 can include a conductive material. For example, at least a portion of the adhesion layer 21 (such as the portion corresponding to the conductive element 10) is conductive to provide an electrical connection between the substrate 12 and the conductive element 10p.

[0025] The foaming agent 23 is disposed within the cavity 20c. The foaming agent 23 is surrounded by the support structure 22. In some embodiments, the foaming agent 23 is formed of or includes a material having a Dk and a DF that are less than the dielectric constant (Dk) and the dissipation factor (Df) of the dielectric material. For example, the Df of the foaming agent 23 is equal to or less than 3, and the Df of the foaming agent 23 is equal to or less than 0.001.

[0026] According to Figure 2 the embodiments in, since the Dk and Df of the forming agent 23 are less than the Dk and Df of the dielectric material, the gain, bandwidth, and radiation efficiency of the antenna element 13 can be improved. Additionally, the foaming agent 23 is disposed within the cavity 20c to cover the air within the cavity 20c, which can prevent delamination between the substrate 10 and the support structure 22 or the substrate 12 due to air expansion during heat treatment and thereby increase the reliability of the semiconductor device package 2.

[0027] Figure 3A, Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F illustrate a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0028] Referring to Figure 3A , a carrier 39 with an adhesion layer 39h is provided. The substrate 10 is disposed on two surfaces of the carrier 39. In some embodiments, the substrate 10 can be disposed by, for example, lamination. One or more openings 10h penetrating the substrate 10 are formed to expose a part of the carrier 39 (or the adhesion layer 39h). In some embodiments, the openings 10h can be formed by, for example, drilling, etching, or any other suitable process. The patterned photoresist 39p (or photomask) is then disposed on the substrate 10.

[0029] Referring to Figure 3B , the antenna element 13 is formed on the substrate 10 and within the opening 10h. In some embodiments, the antenna element 13 is defined by the patterned photoresist 39p. For example, the antenna element 13 is formed at a position exposed from the patterned photoresist 39p. In some embodiments, the antenna element 13 is formed by, for example, a wet process or any other suitable process. Then, the photoresist 39p is removed.

[0030] Referring to Figure 3C , the carrier 39 and the adhesion layer 39h are removed from the substrate 10 to expose the surface 101 of the substrate 10 and a part of the antenna element 13.

[0031] Referring to Figure 3D , the patterned photoresist 39p1 (or photomask) is disposed on the surface 101 of the substrate 10. The patterned photoresist 39p1 has one or more openings 39ph to expose the antenna element 13.

[0032] Referring to Figure 3E , the conductive element 10p is formed within the opening 39ph defined by the patterned photoresist 39p1 by, for example, a wet process. The patterned photoresist 39p1 is removed. Then, the dielectric layer 11a is formed on the surface 101 of the substrate 10. The dielectric layer 11a and the surface 101 of the substrate 10 define a cavity 10c. In some embodiments, as shown in Figure 3F , the foaming agent 23 is then filled into the cavity 10c.

[0033] Figure 4A , Figure 4B and Figure 4C illustrate a semiconductor manufacturing method according to some embodiments of the present disclosure. In some embodiments, Figure 4A , Figure 4B and Figure 4C The methods described in are used to manufactureFigure 1 Semiconductor device package 1 in

[0034] Reference Figure 4A , a structure as shown in Figure 3E and a dielectric layer 11b having a substrate 12 thereon are provided. A first temperature is provided to the dielectric layer 11a to heat (or soft bake or pre-cure) the dielectric layer 11a (e.g., soft baking process or pre-curing process). A second temperature is provided to the dielectric layer 11b to heat (or soft bake or pre-cure) the dielectric layer 11b (e.g., soft baking process or pre-curing process). In some embodiments, depending on different design requirements, the first temperature may be equal to, greater than, or less than the second temperature.

[0035] Reference Figure 4B , the dielectric layer 11b is attached to the dielectric layer 11a. Then, a third temperature is provided to the dielectric layers 11a and 11b to heat (hard bake or fully cure) the dielectric layers 11a and 11b (e.g., hard baking process or fully curing process) so that the dielectric layer 11a adheres to the dielectric layer 11b. According to Figure 4B the embodiments in

[0036] Reference Figure 4C , an electronic component 14 is disposed on the substrate 12. The electronic component 14 is electrically connected to the conductive pad 12c of the substrate 12. In some embodiments, electrical contacts 15 may be disposed on the substrate 12, and then a package body 16 may be formed on the substrate 12 to form a semiconductor device package 1 as shown in Figure 1 .

[0037] Figure 5A , Figure 5B and Figure 5C illustrate semiconductor manufacturing methods according to some embodiments of the present disclosure. In some embodiments, Figure 5A , Figure 5B and Figure 5C the methods described in Figure 2 are used to manufacture a semiconductor device package 2 in

[0038] Reference Figure 5A , a structure as shown in Figure 3F and a substrate 12 having an adhesion layer 21 are provided. As shown in Figure 5B , the substrate 12 is then attached to the dielectric layer 11a through the adhesion layer 21.

[0039] Reference Figure 5C, an electronic component 14 is disposed on a substrate 12. The electronic component 14 is electrically connected to a conductive pad 12c of the substrate 12. In some embodiments, electrical contacts 15 may be disposed on the substrate 12, and then an encapsulant 16 may be formed on the substrate 12 to form a semiconductor device package 2 as shown in Figure 2 as shown in

[0040] As used herein, the terms “substantially,” “essentially,” “approximately,” and “about” are used to indicate and account for small variations. For example, when used in conjunction with a numerical value, the terms can refer to a variation range of ±10% or less than or equal to the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a thickness of a film or layer being “substantially uniform” can refer to a standard deviation of less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces extending along the same plane within a few micrometers, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane. If an angle between two surfaces or components is, for example, 90° ± 10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°, then the two surfaces or components can be considered “substantially perpendicular.” When used in conjunction with an event or situation, the terms “substantially,” “essentially,” “approximately,” and “about” can refer to instances where the event or situation occurs precisely, as well as instances where the event or situation occurs very nearly.

[0041] As used herein, unless the context clearly dictates otherwise, the singular terms “a / an” and “the” can include plural referents. In the description of some embodiments, a component provided “on” or “above” another component can encompass cases where the former component is directly on the latter component (e.g., in physical contact with the latter component), as well as cases where one or more intermediate components are located between the former component and the latter component.

[0042] As used herein, the terms “conductive,” “conductivity,” and “conductivity rate” refer to the ability to conduct an electric current. Conductive materials generally refer to those materials that present little or no opposition to the flow of an electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than about 10 4 S / m (e.g., at least 10 5 S / m or at least 10 6A material with a conductivity of

[0043] In addition, quantities, ratios, and other numerical values are sometimes presented herein in a range format. It should be understood that such range formats are for convenience and brevity and should be interpreted flexibly to include not only the explicitly specified values as the limits of the range, but also all individual values or sub-ranges subsumed within the said range as if each value and sub-range were explicitly specified.

[0044] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration do not limit the present disclosure. Those skilled in the art will clearly understand that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The drawings may not necessarily be drawn to scale. Due to variables in the manufacturing process and so on, there may be differences between the technical reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The specification and drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present disclosure to form equivalent methods. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limited by the present disclosure.

Claims

1. A semiconductor device package, comprising: A first substrate having a first surface and a second surface opposite to the first surface; An antenna element disposed on the second surface of the first substrate, the antenna element penetrating the first substrate; A support layer disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate, the support layer having a first surface facing away from the first substrate and an inner surface, and the support layer is entirely made of a dielectric material; A dielectric layer disposed on the first surface of the support layer and spaced apart from the first substrate, wherein the dielectric layer is chemically bonded to the support layer and the dielectric layer includes a second surface opposite to the first surface of the support layer, and the inner surface of the support layer, the second surface of the dielectric layer, and the first surface of the first substrate define a cavity; A conductive element penetrating the cavity and electrically connected to the antenna element; And A second substrate disposed on the first surface of the dielectric layer facing away from the support layer.

2. The semiconductor device package according to claim 1, wherein the conductive element is in electrical contact with the antenna element and a conductive layer, and the first surface of the conductive layer and the second surface of the dielectric layer are substantially coplanar.

3. The semiconductor device package according to claim 1, wherein the dielectric layer and the support layer include a photosensitive material, and the support layer is in direct contact with the dielectric layer.

4. The semiconductor device package according to claim 3, wherein the dielectric layer and the support layer include expanded polyolefin EPO, solder mask, polyimide PI, epoxy resin, and / or polybenzoxazole PBO.

5. The semiconductor device package according to claim 1, wherein the conductive element is electrically connected to the second substrate.

6. The semiconductor device package according to claim 5, wherein the cavity is a closed cavity for accommodating a foaming agent therein, The conductive element is disposed in the cavity and surrounded by the foaming agent.

7. The semiconductor device package according to claim 1, further comprising an electronic component disposed on the second substrate, and the second substrate is in direct contact with the dielectric layer.

8. A semiconductor device package, comprising: A first substrate having a first surface and a second surface opposite to the first surface; An antenna element disposed on the second surface of the first substrate; A support element disposed on the first surface of the first substrate; An adhesive layer disposed on the first surface of the support element; A second substrate disposed on the first surface of the adhesive layer, and the first substrate, the support element, and the adhesive layer define a cavity; And A foaming agent disposed in the cavity, Wherein the antenna element penetrates the first substrate and is electrically connected to the adhesive layer through a conductive element.

9. The semiconductor device package according to claim 8, wherein the cavity is a closed cavity for accommodating the foaming agent therein, And the conductive element is surrounded by the foaming agent.

10. The semiconductor device package according to claim 9, wherein the conductive element penetrates the adhesive layer.

11. The semiconductor device package according to claim 8, wherein at least a part of the adhesive layer is conductive, and the conductive element is electrically connected to the at least a part of the adhesive layer.

12. The semiconductor device package according to claim 9, wherein the conductive element is disposed within the cavity, and wherein the dielectric constant (Dk) and dissipation factor (Df) of the material of the foaming agent are less than the dielectric constant (Dk) and dissipation factor (Df) of the dielectric material of the support element.

13. The semiconductor device package according to claim 8, further comprising an electronic component disposed on the second substrate, wherein the adhesion layer covers the entire second substrate.

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