Image sensor and method for forming the same

Abstract

Various embodiments of the present disclosure relate to image sensors. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and located between the photodetector and the storage node, wherein the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate opposite the first side, and wherein the first isolation structure is spaced apart from the first side by a second distance less than the first distance.

Description

Technical Field

[0001] The present disclosure relates to an image sensor and a method of forming the same. Background Art

[0002] Many modern electronic devices (such as smart phones, digital cameras, biomedical imaging devices, automatic imaging devices, etc.) include image sensors. An image sensor includes one or more photodetectors (such as photodiodes, phototransistors, photoresistors, etc.), which are configured to absorb incident radiation and output an electrical signal corresponding to the incident radiation. Some types of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared with CCD image sensors, CMOS image sensors are favored due to advantages such as low power consumption, small size, fast data processing, direct output of data, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and backside illuminated (BSI) image sensors. Summary of the Invention

[0003] In some embodiments, the present disclosure provides an image sensor. The image sensor includes: a photodetector disposed in a semiconductor substrate; an interlayer dielectric (ILD) structure disposed on a first side of the semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; a first isolation structure disposed in the semiconductor substrate and located between the photodetector and the storage node, wherein the first isolation structure extends from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate, and wherein the first isolation structure is spaced apart from the first side by a second distance less than the first distance.

[0004] In some embodiments, the present disclosure provides an image sensor. The image sensor includes: a photodetector disposed in a semiconductor substrate, wherein the photodetector is spaced apart from a first side of the semiconductor substrate by a first distance; an interlayer dielectric (ILD) structure disposed on the first side of the semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a second distance greater than the first distance; and a first vertical transfer gate disposed on the first side and configured to selectively form a first conductive channel between the photodetector and the storage node, wherein a first portion of the first vertical transfer gate extends from the first side into the semiconductor substrate by a third distance, and wherein the third distance is greater than the first distance and less than the second distance.

[0005] In some embodiments, the present disclosure provides a method for forming an image sensor, including: forming a photodetector in a semiconductor substrate; forming a storage node in the semiconductor substrate and spaced apart from the photodetector; forming a first vertical transfer gate and a second vertical transfer gate on a first side of the semiconductor substrate, wherein a portion of the first vertical transfer gate and a portion of the second vertical transfer gate extend from the first side into the semiconductor substrate; forming an interlayer dielectric (ILD) structure on the first side and above the first vertical transfer gate and the second vertical transfer gate; forming an isolation structure in the semiconductor substrate, wherein the isolation structure extends from a second side of the semiconductor substrate opposite the first side into the first semiconductor substrate; and forming a reflective structure on the second side of the semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposite sides of the storage node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A cross-sectional view showing some embodiments of a backside illuminated global shutter (BSIGS) image sensor.

[0008] Figure 2 Showing Figure 1 A cross-sectional view of some other embodiments of the BSIGS image sensor.

[0009] Figure 3 Showing Figure 1 A cross-sectional view of some other embodiments of the BSIGS image sensor.

[0010] Figure 4 ShowingFigure 1 Cross-sectional views of some other embodiments of the BSIGS image sensor.

[0011] Figures 5 to 20 Illustrates a series of cross-sectional views for forming Figure 4 Some embodiments of the BSIGS image sensor.

[0012] Figure 21 Flowcharts showing some embodiments of a method for forming a BSIGS image sensor. Detailed Description

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] Some complementary metal-oxide semiconductor image sensors (CIS) have a pixel sensor array. The pixel sensors use photodetectors to record incident radiation and are assisted in digitizing the readout of the recording with a plurality of pixel devices such as transfer gates, reset transistors, source follower transistors, and / or row-select transistors. Some CIS are global shutter (GS) CIS. The GS CIS is configured to start and stop the exposure in each pixel sensor at the same time. For example, the GS CIS can start exposing the optical image to each pixel sensor at the same first time, and then the GS CIS can stop exposing the optical image to each pixel at the same second time. Some GS CIS are front-side illuminated (FSI) GS CIS. The FSI GS CIS is configured to record incident radiation passing through the front side of the semiconductor substrate. For example, an interlayer dielectric (ILD) structure can be disposed on the front side of the semiconductor substrate, and the FSI GS CIS is configured to record incident radiation passing through the ILD structure and the front side of the semiconductor substrate.

[0016] One challenge of the above FSI GS CIS is to improve the quantum efficiency (QE) and / or angular response (AR) of the FSI GS CIS while maintaining a high shutter efficiency (SE). Since the FSI GS CIS is configured to record incident radiation passing through the front side of the semiconductor substrate, the FSI GS CIS has a relatively long optical path, which has an adverse effect on the QE and / or AR of the FSI GS CIS. In addition, since the FSI GS CIS is configured to record incident radiation passing through the front side of the semiconductor substrate, the interconnect structures disposed in the ILD structure can reflect some of the incident radiation, thereby having an adverse effect on the QE and / or AR of the FSI GS CIS. Although the interconnect structures can have an adverse effect on the QE and / or AR of the FSI GS CIS, the interconnect structures can protect the storage nodes of the FSI GS CIS from most of the incident radiation, thereby having a beneficial effect on the SE.

[0017] Various embodiments of the present disclosure relate to a backside illuminated global shutter (BSIGS) image sensor. The BSIGS image sensor is configured to record incident radiation passing through the backside of a semiconductor substrate. The BSIGS image sensor includes a photodetector disposed in the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced apart from the photodetector. An interconnect structure is disposed on the front side of the semiconductor substrate. A reflective structure is disposed on the backside of the semiconductor substrate opposite the front side. The reflective structure is arranged such that the reflective structure at least partially protects the storage node from incident radiation passing through the backside of the semiconductor substrate.

[0018] Since the BSIGS image sensor is configured to record incident radiation passing through the backside of the semiconductor substrate, when compared with a FSIGSCIS, the BSIGS image sensor may have better QE and / or AR because the BSIGS image sensor has a shorter optical path than the FSIGSCIS. In addition, since the BSIGS image sensor is configured to record incident radiation passing through the backside of the semiconductor substrate, when compared with a FSIGSCIS, the BSIGS image sensor may have better QE and / or AR due to a reduction (or elimination) of incident radiation reflected by the interconnect structure. In addition, since the reflective structure at least partially protects the storage node from incident radiation passing through the backside of the semiconductor substrate, the BSIGS image sensor may have a high SE. Accordingly, the BSIGS image sensor may have improved QE and / or AR compared to a FSIGSCIS while maintaining a high SE.

[0019] Figure 1 A cross-sectional view showing some embodiments of a backside illuminated global shutter (BSIGS) image sensor 100.

[0020] As Figure 1 shown, the BSIGS image sensor 100 includes a first semiconductor substrate 102. The first semiconductor substrate 102 has a front side 102f and a back side 102b opposite the front side 102f. The first semiconductor substrate 102 may include any type of semiconductor body (e.g., single crystal silicon / CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), etc.). The BSIGS image sensor 100 is configured to record incident radiation (e.g., photons) passing through the back side 102b of the first semiconductor substrate 102.

[0021] The photodetector 104 (e.g., a photodiode) is disposed in the first semiconductor substrate 102. The photodetector 104 includes a portion of the first semiconductor substrate 102, which has a first doping type (e.g., n-type / p-type). In some embodiments, the portion of the first semiconductor substrate 102 adjacent to the photodetector 104 may have a second doping type opposite to the first doping type (e.g., p-type / n-type), or may be intrinsic. The photodetector 104 is configured to absorb incident radiation (e.g., light) and generate an electrical signal corresponding to the incident radiation.

[0022] The storage node 106 is disposed in the first semiconductor substrate 102 and is spaced apart from the photodetector 104. The storage node 106 is a region of the first semiconductor substrate 102 having a first doping type. The storage node 106 is configured to store the charge transferred from the photodetector 104 to the storage node 106.

[0023] The floating diffusion node 108 is disposed in the first semiconductor substrate 102 and is laterally spaced apart from the photodetector 104 and the storage node 106. The floating diffusion node 108 is a region of the first semiconductor substrate 102 having a first doping type. The first doped region 110 is disposed in the first semiconductor substrate 102 and is spaced apart from the floating diffusion node 108. The first doped region 110 is a region of the first semiconductor substrate having a first doping type. In some embodiments, the first doped region 110 is the source / drain region for an anti-blooming (AB) gate. The second doped region 112 is disposed in the first semiconductor substrate 102 and is spaced apart from the first doped region 110 and the floating diffusion node 108. The second doped region 112 is a region of the first semiconductor substrate having a first doping type. In some embodiments, the second doped region 112 is the source / drain region of a reset transistor. In still other embodiments, the first isolation structure 114 (e.g., a shallow trench isolation (STI) structure) is disposed in the first semiconductor substrate 102.

[0024] A plurality of gates 116 are disposed on the front side 102f of the first semiconductor substrate 102. For example, a first gate 116a, a second gate 116b, a first vertical transfer gate 116c, and a second vertical transfer gate 116d may be disposed on the front side 102f of the first semiconductor substrate 102. The first vertical transfer gate 116c is configured to selectively form a first conductive channel between the photodetector 104 and the storage node 106 such that charges accumulated in the photodetector 104 (e.g., via absorption of incident radiation) can be transferred to the storage node 106. The second vertical transfer gate 116d is configured to selectively form a second conductive channel between the storage node 106 and the floating diffusion node 108 such that charges stored in the storage node 106 can be transferred to the floating diffusion node 108. In some embodiments, the first gate 116a may be an AB gate, and the second gate 116b may be a reset gate.

[0025] The first vertical transfer gate 116c and the second vertical transfer gate 116d extend from the front side 102f into the first semiconductor substrate 102. For example, a first portion of the first vertical transfer gate 116c is disposed above the front side 102f, and a second portion of the first vertical transfer gate 116c extends from the front side 102f into the first semiconductor substrate 102. The plurality of gates 116 each include a gate dielectric layer 118 and include gate electrodes 120 respectively disposed on the gate dielectric layer 118. For example, the first gate 116a includes a first gate dielectric layer 118a and a first gate electrode 120a disposed on the first gate dielectric layer 118a, the second gate 116b includes a second gate dielectric layer 118b and a second gate electrode 120b disposed on the second gate dielectric layer 118b, the first vertical transfer gate 116c includes a third gate dielectric layer 118c and a third gate electrode 120c disposed on the third gate dielectric layer 118c, and the second vertical transfer gate 116d includes a fourth gate dielectric layer 118d and a fourth gate electrode 120d disposed on the fourth gate dielectric layer 118d.

[0026] A first interlayer dielectric (ILD) structure 122 is disposed above the front side 102f of the first semiconductor substrate 102. A first interconnect structure 124 (e.g., a copper interconnect) is disposed in the first ILD structure 122. The first interconnect structure 124 includes a plurality of conductive contact structures 124a (e.g., metal contacts), a plurality of vias 124b (e.g., metal vias), and a plurality of conductive lines 124c (e.g., metal lines). In some embodiments, the first ILD structure 122 includes one or more stacked ILD layers, and the one or more stacked ILD layers may respectively include a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO 2)) or the like. In another embodiment, the first interconnection structure 124 may include, for example, copper (Cu), aluminum (Al), tungsten (W), gold (Au), some other conductive material, or a combination of the foregoing. In still other embodiments, the conductive contact structure 124a may include a first conductive material (such as W), and the via 124b and the conductive line 124c may include a second conductive material different from the first conductive material (such as copper).

[0027] A second isolation structure 126 (such as a back-side deep trench isolation (BDTI) structure) is disposed in the first semiconductor substrate 102. The second isolation structure 126 is less transparent than the first semiconductor substrate 102. The second isolation structure 126 extends into the first semiconductor substrate 102 from the back side 102b of the first semiconductor substrate 102 and along the storage node 106. As a first part, the second isolation structure 126a extends into the first semiconductor substrate 102 between the storage node 106 and the photodetector 104. As a second part, the second isolation structure 126b extends into the first semiconductor substrate 102 on the opposite side of the storage node 106 as the first part, the second isolation structure 126a. The first part of the second isolation structure 126a may be referred to as a third isolation structure, and the second part of the second isolation structure 126b may be referred to as a fourth isolation structure. Since the second isolation structure 126 extends into the first semiconductor substrate 102 and along the storage node 106, the second isolation structure 126 may at least partially protect the storage node 106 from incident radiation.

[0028] In some embodiments, the first vertical transfer gate 116c and the second vertical transfer gate 116d are at least partially disposed between a second isolation structure 126a (a first portion of the second isolation structure 126) and a second isolation structure 126b (a second portion of the second isolation structure 126). Since the first vertical transfer gate 116c extends into the first semiconductor substrate 102 and since the first vertical transfer gate 116c is at least partially disposed between the second isolation structure 126a (a first portion of the second isolation structure 126) and the second isolation structure 126b (a second portion of the second isolation structure 126), the first vertical transfer gate 116c can improve the charge transfer between the photodetector 104 and the storage node 106. Since the second vertical transfer gate 116d extends into the first semiconductor substrate 102 and since the second vertical transfer gate 116d is at least partially disposed between the second isolation structure 126a (a first portion of the second isolation structure 126) and the second isolation structure 126b (a second portion of the second isolation structure 126), the second vertical transfer gate 116d can improve the charge transfer between the storage node 106 and the floating diffusion node 108. Additionally, since the first vertical transfer gate 116c and the second vertical transfer gate 116d are at least partially disposed between the second isolation structure 126a (a first portion of the second isolation structure 126) and the second isolation structure 126b (a second portion of the second isolation structure 126), the first vertical transfer gate 116c and / or the second vertical transfer gate 116d can at least partially protect the storage node 106 from incident radiation.

[0029] In some embodiments, the second isolation structure 126 is a continuous structure. In other embodiments, the second isolation structure 126 can include discrete portions. For example, the second isolation structure 126a (a first portion of the second isolation structure 126) can be discrete from the second isolation structure 126b (a second portion of the second isolation structure 126). In additional embodiments, the first vertical transfer gate 116c and the second vertical transfer gate 116d are at least partially disposed within the inner perimeter of the second isolation structure 126. In still other embodiments, the floating diffusion nodes 108 are all disposed outside the inner perimeter of the second isolation structure 126. In additional embodiments, the second isolation structure 126 can include an oxide (e.g., SiO 2 ), a nitride (e.g., silicon nitride (SiN)), a oxynitride (e.g., silicon oxynitride (SiO X N Y )), a carbide (e.g., silicon carbide (SiC)), or the like.

[0030] The reflective structure 128 is disposed on the back side 102b of the first semiconductor substrate 102. The reflective structure 128 is less transparent than the first semiconductor substrate 102. In some embodiments, the reflective structure 128 may include, for example, W, Al, Cu, some other metal, or a combination of the foregoing. In additional embodiments, the reflective structure 128 may be embedded in the dielectric structure 130. In still other embodiments, the reflective structure 128 is referred to as a metal structure.

[0031] At least a portion of the reflective structure 128 is offset from the photodetector 104 in a lateral direction. In other words, at least a portion of the photodetector 104 is disposed outside the outer perimeter of the reflective structure 128. At least a portion of the reflective structure 128 is disposed between opposite sides of the storage node 106. In some embodiments, the opposite sides of the storage node 106 are disposed between opposite sidewalls of the reflective structure 128. In additional embodiments, the outer perimeter of the storage node 106 is disposed within the outer perimeter of the reflective structure 128. Because at least a portion of the reflective structure 128 is disposed between opposite sides of the storage node 106, the reflective structure 128 can at least partially protect the storage node 106 from incident radiation.

[0032] Because the BSIGS image sensor 100 is configured to record incident radiation passing through the back side 102b of the first semiconductor substrate 102, the BSIGS image sensor 100 can have better quantum efficiency (QE) and / or angular response (AR) when compared to a front-side illuminated global shutter (FSIGS) image sensor. In addition, because the reflective structure 128 at least partially protects the storage node 106 from incident radiation, the BSIGS image sensor 100 can have a high shutter efficiency (SE). In addition, the second isolation structure 126 can contribute to the BSIGS image sensor 100 having a high SE by at least partially protecting the storage node 106 from incident radiation. In addition, the first vertical transfer gate 116c and / or the second vertical transfer gate 116d can contribute to the BSIGS image sensor 100 having a high SE by at least partially protecting the storage node 106 from incident radiation. Accordingly, the BSIGS image sensor 100 can have better QE and / or AR than the FSIGS image sensor while also having a high SE.

[0033] Figure 2 Shown Figure 1 is a cross-sectional view of some other embodiments of the BSIGS image sensor 100.

[0034] As Figure 2As shown, a filter 202 (such as an infrared filter, a red filter, a blue filter, a green filter, etc.) is disposed on a dielectric structure 130. The filter 202 is configured to transmit incident radiation of a specific wavelength (or a range of wavelengths). It should be understood that in some embodiments, the filter 202 is one of a plurality of filters disposed in a filter array. In such embodiments, the plurality of filters can be configured to transmit specific wavelengths (or specific ranges of wavelengths) respectively. For example, a first filter (such as a red filter) can transmit light having wavelengths within a first range, while a second filter (such as a blue filter) can transmit light having wavelengths within a second range different from the first range.

[0035] In some embodiments, both the dielectric structure 130 and the reflective structure 128 are disposed between the filter 202 and the first semiconductor substrate 102. In other embodiments, the filter 202 can be disposed between the first semiconductor substrate 102, the dielectric structure 130, and the reflective structure 128. The dielectric structure 130 can include, for example, oxides (such as SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), high-k dielectric materials (such as hafnium dioxide (HfO 2 ), zirconium oxide (ZrO 2 ), or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric materials, or a combination of the foregoing. In additional embodiments, the dielectric structure 130 can include a first layer and a second layer. The first layer is stacked on the second layer. The first layer includes an oxide and the second layer includes a high-k dielectric material, or they can be interchanged with each other.

[0036] In some embodiments, the dielectric structure 130 can be a BSI antireflection structure configured to reduce the amount of reflection of the first semiconductor substrate 102 for incident radiation. In other embodiments, the dielectric structure 130 can be different from the BSI antireflection structure. In such embodiments, the BSI antireflection structure can be disposed between the dielectric structure 130 and the first semiconductor substrate 102, or the dielectric structure 130 can be disposed between the antireflection structure and the first semiconductor substrate 102.

[0037] For a FSIGS image sensor having an FSI anti-reflection structure, the FSI anti-reflection structure is disposed on the front side of the semiconductor substrate. However, this orientation limits the ability to optimize the FSI anti-reflection structure to improve QE and / or AR. However, since the BSIGS image sensor 100 is configured to record incident radiation passing through the back side 102b of the first semiconductor substrate 102, the BSI anti-reflection structure is disposed on the back side 102b of the first semiconductor substrate 102. Since the BSI anti-reflection structure is disposed on the back side 102b of the first semiconductor substrate 102, the ability to optimize the BSI anti-reflection structure can be better when compared with the FSIGS image sensor, and the BSIGS image sensor 100 can have better QE and / or AR.

[0038] In some embodiments, the microlens 204 is disposed on the back side 102b of the first semiconductor substrate 102. In additional embodiments, the microlens 204 is disposed on the filter 202. The microlens 204 is configured to focus the incident radiation onto the photodetector 104. It should be understood that in some embodiments, the microlens 204 is one of a plurality of microlenses configured to focus the incident radiation onto a plurality of photodetectors, respectively.

[0039] In some embodiments, the reflective structure 128 includes a reflective structure 128a as a first part, a reflective structure 128b as a second part, and a reflective structure 128c as a third part. In additional embodiments, both the reflective structure 128b as the second part and the reflective structure 128c as the third part are coupled to the reflective structure 128a as the first part such that the reflective structure 128 is a continuous structure. In some embodiments, the reflective structure 128a as the first part may have a circular sidewall.

[0040] The reflective structure 128b as the second part and the reflective structure 128c as the third part extend from the dorsal side 102b into the first semiconductor substrate 102. The reflective structure 128b as the second part can be disposed in the second isolation structure 126a (the first part of the second isolation structure 126). The reflective structure 128c as the third part can be disposed in the second isolation structure 126b (the second part of the second isolation structure 126). In some embodiments, the reflective structure 128 is less transparent than the second isolation structure 126. Since the reflective structure 128b (the second part of the reflective structure 128) and the reflective structure 128c (the third part of the reflective structure 128) extend into the first semiconductor substrate 102 and along the storage node 106, and since the reflective structure 128 is less transparent than the second isolation structure 126, the reflective structure 128 can further protect the storage node 106 from incident radiation. Accordingly, the reflective structure 128 can further increase the SE of the BSIGS image sensor 100.

[0041] In some embodiments, the reflective structure 128b (the second part of the reflective structure 128) and / or the reflective structure 128c (the third part of the reflective structure 128) are at least partially disposed in the dielectric structure 130. In additional embodiments, both the reflective structure 128b (the second part of the reflective structure 128) and the reflective structure 128c (the third part of the reflective structure 128) can be disposed between the opposing sidewalls of the reflective structure 128a (the first part of the reflective structure 128). The reflective structure 128b (the second part of the reflective structure 128) and the reflective structure 128c (the third part of the reflective structure 128) can have inclined sidewalls. In still other embodiments, the second isolation structure 126a (the first part of the second isolation structure 126) and the second isolation structure 126b (the second part of the second isolation structure 126) can have inclined sidewalls.

[0042] A plurality of sidewall spacers 206 are respectively disposed along the sidewalls of the plurality of gates 116. For ease of illustration, only one of the sidewall spacers 206 is labeled. In some embodiments, each of the sidewall spacers 206 is disposed along the sidewalls of a corresponding one of the gate dielectric layers 118 and a corresponding one of the gate electrodes 120. For example, one of the sidewall spacers 206 is disposed on the front side 102f of the first semiconductor substrate 102 and along the sidewalls of the third gate dielectric layer 118c and the third gate electrode 120c. In some embodiments, the sidewall spacers 206 can include, for example, nitrides (such as SiN), oxynitrides (such as SiO X N Y ) or the like. In additional embodiments, the gate dielectric layer 118 can include, for example, oxides (such as SiO 2 ) or high-k dielectric materials (such as HfO 2 , ZrO2 or some other dielectric material having a dielectric constant greater than about 3.9) or the like. In still other embodiments, the gate electrode 120 may include, for example, polysilicon (e.g., doped / undoped polysilicon), metal (e.g., W, Al, titanium (Ti), molybdenum (Mo), or the like), or the like.

[0043] The first ILD structure 122 may include a second ILD structure 208 and a third ILD structure 210. The second ILD structure 208 is disposed above the front side 102f of the first semiconductor substrate 102 and above the plurality of gates 116. The conductive contact structure 124a is disposed in the second ILD structure 208. In some embodiments, the second ILD structure 208 includes one or more ILD layers, which may respectively include a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO 2 ) or the like.

[0044] The third ILD structure 210 is disposed above the second ILD structure 208 and the conductive contact structure 124a. The vias 124b and the conductive lines 124c are disposed in the third ILD structure 210. In some embodiments, the third ILD structure 210 includes one or more ILD layers, which may respectively include a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO 2 ) or the like.

[0045] In some embodiments, a second semiconductor substrate 212 is disposed above the first ILD structure 122, the first interconnect structure 124, and the front side 102f of the first semiconductor substrate 102. The second semiconductor substrate 212 may include any type of semiconductor body (e.g., single-crystalline silicon / CMOS bulk, SiGe, SOI, etc.). In additional embodiments, the second semiconductor substrate 212 is bonded to the first ILD structure 122 via a bonding structure 214. In other embodiments, the second semiconductor substrate 212 is directly bonded to the first ILD structure 122. It should be understood that in some embodiments, a plurality of conductive features (e.g., bonding pads, metal vias, metal lines, substrate vias, etc.) may be disposed in the bonding structure 214 and / or the second semiconductor substrate 212 to provide an electrical connection between the first interconnect structure 124 and one or more input / output (I / O) structures (e.g., contact pads, solder bumps, etc.). In still other embodiments, the second semiconductor substrate 212 may be referred to as a carrier substrate.

[0046] Figure 2It is also shown that the photodetector 104 is spaced apart from the front side 102f of the first semiconductor substrate 102 by a first distance. The storage node 106 is spaced apart from the front side 102f of the first semiconductor substrate 102 by a second distance greater than the first distance. The second isolation structure 126 is spaced apart from the front side 102f of the first semiconductor substrate 102 by a third distance. In some embodiments, the third distance is greater than the first distance and less than the second distance. In other embodiments, the third distance may be less than or equal to the first distance, or greater than or equal to the second distance. In additional embodiments, the reflective structure 128b (the second portion of the reflective structure 128) and / or the reflective structure 128c (the third portion of the reflective structure 128) are spaced apart from the front side 102f of the first semiconductor substrate 102 by a fourth distance greater than the third distance. In still other embodiments, the fourth distance may be greater than or equal to the second distance. In other embodiments, the fourth distance may be greater than the first distance and less than the second distance. In still other additional embodiments, the fourth distance may be less than or equal to the first distance.

[0047] The bottommost surface of the first vertical transfer gate 116c and / or the bottommost surface of the second vertical transfer gate 116d are spaced apart from the front side 102f of the first semiconductor substrate 102 by a fifth distance. In some embodiments, the fifth distance is less than the second distance. The fifth distance may be greater than the third distance and less than the fourth distance. In some embodiments, the fifth distance is less than or equal to the third distance. In other embodiments, the fifth distance is greater than or equal to the third distance.

[0048] Figure 2 It is also shown that the first vertical transfer gate 116c extends into the first semiconductor substrate 102 to a first depth. The first depth is the distance between the front side 102f of the first semiconductor substrate 102 and the bottommost surface of the third gate dielectric layer 118c. In some embodiments, the first depth is between approximately 0.5 micrometers (μm) and approximately 2 micrometers.

[0049] The portion of the first vertical transfer gate 116c disposed in the first semiconductor substrate 102 has a first width. The first width is the width between the outer sidewalls of the third gate dielectric layer 118c disposed in the first semiconductor substrate 102 that face each other. In some embodiments, the first width is the maximum width between the outer sidewalls of the third gate dielectric layer 118c disposed in the first semiconductor substrate 102 that face each other. In additional embodiments, the first width is between approximately 0.1 micrometer and approximately 0.4 micrometer.

[0050] The second vertical transfer gate 116d extends into the first semiconductor substrate 102 to a second depth. The second depth is the distance between the front side 102f of the first semiconductor substrate 102 and the bottommost surface of the fourth gate dielectric layer 118d. In some embodiments, the first depth is between about 0.5 micrometers and about 2 micrometers. In additional embodiments, the second depth is substantially the same as the first depth. In other embodiments, the second depth is different from the first depth.

[0051] The portion of the second vertical transfer gate 116d disposed in the first semiconductor substrate 102 has a second width. The second width is the width between the outer sidewalls of the fourth gate dielectric layer 118d disposed in the first semiconductor substrate 102 that face each other. In some embodiments, the second width is the maximum width between the outer sidewalls of the fourth gate dielectric layer 118d disposed in the first semiconductor substrate 102 that face each other. In additional embodiments, the second width is between about 0.1 micrometer and about 0.4 micrometer. In still other embodiments, the second width is substantially the same as the first width. In other embodiments, the second width is different from the first width.

[0052] Figure 3 Shown Figure 1 is a cross-sectional view of some other embodiments of the BSIGS image sensor 100.

[0053] As Figure 3 shown, in some embodiments, the second gate 116b is disposed directly above the storage node 106. The second gate 116b may be disposed between the first vertical transfer gate 116c and the second vertical transfer gate 116d. In additional embodiments, the floating diffusion node 108 and / or the second doped region 112 may be disposed directly above the storage node 106. The floating diffusion node 108 and / or the second doped region 112 may be disposed between the first vertical transfer gate 116c and the second vertical transfer gate 116d.

[0054] A doped well 302 is disposed in the first semiconductor substrate 102. The doped well 302 is a region of the first semiconductor substrate having a second doping type. In some embodiments, the doped well 302 doped with a second doping type dopant (e.g., a p-type dopant) has a higher doping concentration than the adjacent regions of the first semiconductor substrate 102. In additional embodiments, the second doped region 112 and / or the floating diffusion node 108 are disposed between opposite sides of the doped well 302.

[0055] In some embodiments, the doped well 302 is disposed directly between the second gate 116b and the storage node 106, directly between the second doped region 112 and the storage node 106, and directly between the floating diffusion node 108 and the storage node 106. In some embodiments, the doped well 302 may extend under at least a portion of the first isolation structure 114. In additional embodiments, the doped well 302 may be disposed directly between a portion of the first vertical transfer gate 116c and the storage node 106 and / or between a portion of the second vertical transfer gate 116d and the storage node 106. In other embodiments, the doped well 302 may be spaced apart from the first vertical transfer gate 116c and / or the second vertical transfer gate 116d by a lateral distance. In still other embodiments, the doped well 302 may be spaced apart from the storage node 106.

[0056] A doped isolation region 303 is disposed in the first semiconductor substrate 102. The doped isolation region 303 is a region of the first semiconductor substrate having a second doping type. In some embodiments, the doped isolation region 303 is spaced apart from the storage node 106, the floating diffusion node 108, and the second doped region 112. The doped isolation region 303 may be spaced apart from the first isolation structure 114. The doped isolation region 303 may be disposed directly between the second gate 116b and the storage node 106, directly between the second doped region 112 and the storage node 106, and / or directly between the floating diffusion node 108 and the storage node 106.

[0057] In some embodiments, the doped isolation region 303 may extend under at least a portion of the first isolation structure 114. In additional embodiments, the doped isolation region 303 may be disposed directly between a portion of the first vertical transfer gate 116c and the storage node 106 and / or between a portion of the second vertical transfer gate 116d and the storage node 106. In other embodiments, the doped isolation region 303 may be spaced apart from the first vertical transfer gate 116c and / or the second vertical transfer gate 116d by a lateral distance.

[0058] In some embodiments, the doped isolation region 303 formed with a second doping type dopant has a higher doping concentration than the doped well 302. The doped isolation region 303 formed with a second doping type dopant may have a doping concentration between about 5×10 15 cm -3 and about 5×10 18 cm -3 Since the doped well 302 formed with a second doping type dopant has a doping concentration between about 5×10 15 cm -3 and about 5×10 18cm -3 The doping concentration between them, so the doped isolation region 303 can improve the QE, AR, and / or SE of the BSIGS image sensor 100 by improving the electrical isolation (e.g., via p-n junction isolation) between the storage node 106 and the floating diffusion node 108 and / or between the second doped regions 112.

[0059] Figure 3 It is also shown that an integrated chip (IC) 304 is disposed above the first semiconductor substrate 102, the first ILD structure 122, and the first interconnect structure 124. The IC 304 includes a third semiconductor substrate 306. The third semiconductor substrate 306 can include any type of semiconductor body (e.g., single crystal silicon / CMOS bulk, SiGe, SOI, etc.). A plurality of semiconductor devices 308a to 308b (e.g., p-channel MOSFETs, n-channel MOSFETs, etc.) are disposed on the third semiconductor substrate 306. In some embodiments, the semiconductor devices 308a to 308b are image processing devices configured to process the signals output by the storage node 106.

[0060] A fourth ILD structure 310 is disposed between the third semiconductor substrate 306 and the first ILD structure 122. In some embodiments, the fourth ILD structure 310 includes one or more stacked ILD layers, and the one or more stacked ILD layers can respectively include a low-k dielectric material (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO 2 )) or the like. A second interconnect structure 312 (e.g., a copper interconnect) is disposed in the fourth ILD structure 310. The second interconnect structure 312 includes a plurality of conductive features (e.g., metal lines, metal vias, metal contacts, bonding pads, etc.). In additional embodiments, the plurality of conductive features can include, for example, Cu, Al, W, Au, some other conductive material, or a combination of the foregoing. It should be understood that in some embodiments, one or more conductive features (e.g., substrate vias) can be disposed in the third semiconductor substrate 306 to provide an electrical connection between the second interconnect structure 312 and one or more I / O structures.

[0061] The fourth ILD structure 310 is joined to the third ILD structure 210. The first interconnect structure 124 may include a plurality of first conductive bonding pads 124d. The second interconnect structure 312 may include a plurality of second conductive bonding pads 312a. In some embodiments, the first conductive bonding pads 124d are respectively joined to the second conductive bonding pads 312a. In additional embodiments, the first conductive bonding pads 124d are respectively electrically coupled to the second conductive bonding pads 312a, thereby providing electrical connections between features (such as AB gates, vertical transfer gates, reset gates, source follower gates, source / drain regions, floating diffusion nodes, etc.) disposed on a first semiconductor substrate to a plurality of semiconductor devices 308a to 308b disposed on a third semiconductor substrate 306.

[0062] Figure 4 shows Figure 1 A cross-sectional view of some other embodiments of the BSIGS image sensor 100.

[0063] As Figure 4 shown, a third doped region 402 is disposed in the first semiconductor substrate 102. The third doped region is a region of the first semiconductor substrate 102 having a second doping type. The third doped region 402 is disposed between the photodetector 104 and the front side 102f of the first semiconductor substrate 102.

[0064] A plurality of fourth doped regions 404 are disposed in the first semiconductor substrate 102. For ease of illustration, only one of the fourth doped regions 404 is labeled. The fourth doped regions 404 are regions of the first semiconductor substrate 102 having a second doping type. The fourth doped regions 404 may extend from the front side 102f of the first semiconductor substrate 102 into the first semiconductor substrate 102. The first of the fourth doped regions 404 may extend into the first semiconductor substrate 102 between the photodetector 104 and the storage node 106. The second of the fourth doped regions 404 may extend into the first semiconductor substrate 102 on the opposite side of the photodetector 104 in a manner similar to the first of the fourth doped regions 404. The third of the fourth doped regions 404 may extend into the first semiconductor substrate 102 on the opposite side of the storage node 106 in a manner similar to the first of the fourth doped regions 404. In some embodiments, the third of the fourth doped regions 404 is directly disposed beneath a portion of the first isolation structure 114. In additional embodiments, a first doped region 110 may be disposed in the second of the fourth doped regions 404.

[0065] In some embodiments, the bottom side of the fourth doped region 404 is disposed between the back side 102b of the first semiconductor substrate 102 and both the storage node 106 and the photodetector 104. In additional embodiments, the fourth doped region 404 is spaced apart from the back side 102b of the first semiconductor substrate 102. The fourth doped region 404 may have different widths. For example, a first one of the fourth doped regions 404 may have a third width, and a second (and / or third) one of the fourth doped regions 404 may have a fourth width different from the third width. In still other embodiments, the second isolation structure 126 is at least partially disposed in the fourth doped region 404.

[0066] The doped isolation region 303 may be disposed between the reflective structure 128b (the second portion of the reflective structure 128) and the reflective structure 128c (the third portion of the reflective structure 128). In some embodiments, the bottom side of the doped isolation region 303 may be disposed between the front side 102f of the first semiconductor substrate 102 and the uppermost surface of the reflective structure 128b (the second portion of the reflective structure 128) and / or between the front side 102f and the uppermost surface of the reflective structure 128c (the third portion of the reflective structure 128). In other embodiments, the uppermost surface of the reflective structure 128b (the second portion of the reflective structure 128) and / or the uppermost surface of the reflective structure 128c (the third portion of the reflective structure 128) is disposed between the upper side and the bottom side of the doped isolation region 303. In still other additional embodiments, the uppermost surface of the reflective structure 128b (the second portion of the reflective structure 128) and / or the uppermost surface of the reflective structure 128c (the third portion of the reflective structure 128) is disposed between the front side 102f of the first semiconductor substrate 102 and the upper side of the doped isolation region 303. In additional embodiments, a portion of the first vertical transfer gate 116c is disposed between the second isolation structure 126a (the first portion of the second isolation structure 126) and the doped isolation region 303. In additional embodiments, a portion of the second vertical transfer gate 116d is disposed between the second isolation structure 126b (the second portion of the second isolation structure 126) and the doped isolation region 303.

[0067] In some embodiments, the dielectric structure 130 may include a first dielectric layer 130a and a second dielectric layer 130b. The first dielectric layer 130a is disposed between the second dielectric layer 130b and the first semiconductor substrate 102. The first dielectric layer 130a may have a substantially flat bottom surface. The reflective structure 128a (the first portion of the reflective structure 128) may be embedded in the first dielectric layer 130a. In additional embodiments, the reflective structure 128a (the first portion of the reflective structure 128) has a substantially flat bottom surface that is coplanar with the bottom surface of the first dielectric layer 130a. In still other embodiments, the first dielectric layer 130a may include, for example, an oxide (e.g., SiO 2 ), a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y ), a high-k dielectric material (e.g., HfO 2 ), ZrO 2 or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing.

[0068] The second dielectric layer 130b separates the reflective structure 128a (the first portion of the reflective structure 128) from the filter 202. The second dielectric layer 130b may have a substantially flat bottom surface. In some embodiments, the second dielectric layer 130b may include, for example, an oxide (e.g., SiO 2 ), a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y ), a high-k dielectric material (e.g., HfO 2 ), ZrO 2 or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing. In additional embodiments, the second dielectric layer 130b may contact the bottom surface of the first dielectric layer 130a and the bottom surface of the reflective structure 128a (the first portion of the reflective structure 128). In still other embodiments, the first dielectric layer 130a and the second dielectric layer 130b may include the same dielectric material. In other embodiments, the first dielectric layer 130a and the second dielectric layer 130b may include different dielectric materials.

[0069] Figures 5 to 20 A series of cross-sectional views showing some embodiments of the BSIGS image sensor 100 for forming Figure 4 .

[0070] As Figure 5As shown, a first isolation structure 114 is formed in the first semiconductor substrate 102. In some embodiments, the first isolation structure 114 may be formed by selectively etching the first semiconductor substrate 102 to form a trench on the first semiconductor substrate 102, and then filling the trench with a dielectric material. In other embodiments, the first semiconductor substrate 102 is selectively etched by forming a mask layer (e.g., a positive / negative photoresist) (not shown) on the front side 102f of the first semiconductor substrate 102, and then exposing the first semiconductor substrate 102 to an etchant (e.g., a wet / dry etchant) to remove unmasked portions of the first semiconductor substrate 102. Subsequently, in some embodiments, the mask layer is stripped. In yet other embodiments, the dielectric material may include an oxide (e.g., SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), carbides (eg, SiC), or the like. It should be appreciated that in some embodiments, before forming the first isolation structure 114, the first semiconductor substrate 102 may be doped (eg, via ion implantation) with a second doping type (eg, p-type / n-type).

[0071] like Figure 6 As shown, a photodetector 104 is formed in a first semiconductor substrate 102. The photodetector 104 includes a region of the first semiconductor substrate 102 having a first doping type (e.g., n-type / p-type) opposite to a second doping type. In some embodiments, the photodetector 104 may be formed by a first implantation process (e.g., via ion implantation) that selectively implants a first doping type dopant (e.g., n-type dopant) into the first semiconductor substrate 102 using a first mask layer (not shown) on a front side 102f of the first semiconductor substrate 102. Subsequently, in some embodiments, the first mask layer is stripped.

[0072] Figure 6 102. It is also shown that a storage node 106 is formed in the first semiconductor substrate 102. The storage node 106 is a region of the first semiconductor substrate 102 having a first doping type. In some embodiments, the storage node 106 is deeper in the first semiconductor substrate 102 than the photodetector 104 (e.g., spaced farther from the front side 102f). In some embodiments, the storage node 106 can be formed by a second implantation process that utilizes a second mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant the first doping type dopant into the first semiconductor substrate 102. Subsequently, in some embodiments, the second mask layer is stripped. In other embodiments, the storage node 106 and the photodetector 104 can be formed by the same selective implantation process (e.g., utilizing the same mask layer and / or the same ion implantation process).

[0073] As shown Figure 7 in FIG. 1, a doped well 302 is formed in the first semiconductor substrate 102. The doped well 302 is a region of the first semiconductor substrate 102 having a second doping type. In some embodiments, the doped well 302 is formed directly above the storage node 106. In other embodiments, the doped well 302 may be formed by a first implantation process that uses a first mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant a second doping type dopant (e.g., a p-type dopant) into the first semiconductor substrate 102. Subsequently, in some embodiments, the first mask layer is stripped.

[0074] Figure 7 FIG. 1 also shows that a doped isolation region 303 is formed in the first semiconductor substrate 102. The doped isolation region 303 is a region of the first semiconductor having a second doping type. In some embodiments, the doped isolation region 303 formed with the second dopant has a higher doping concentration than the doped well 302 also formed with the second dopant. In other embodiments, the doped isolation region 303 may be formed in the doped well 302. It should be understood that the doped isolation region 303 may be formed before or after the doped well 302.

[0075] In some embodiments, the process for forming the doped isolation region 303 includes forming a second mask layer on the front side 102f of the first semiconductor substrate 102. Thereafter, a second implantation process is performed with the second mask layer in place to implant a second doping type dopant into the unmasked portion of the first semiconductor substrate 102, thereby forming the doped isolation region 303. Subsequently, in some embodiments, the second mask layer is stripped.

[0076] In some embodiments, the second implantation process implants a second doping type dopant into the first semiconductor substrate 102 such that the doped isolation region 303 has a doping concentration of the second doping type dopant between about 5×10 15 cm -3 and about 5×10 18 cm -3 . It should be understood that in some embodiments, the second mask layer is not formed, but the first mask layer may be used to mask the first semiconductor substrate 102 during the second implantation process. In other embodiments, the second mask layer may be formed on the first mask layer and the first semiconductor substrate 102, and both the first mask layer and the second mask layer may be stripped after the second implantation process.

[0077] Figure 7It is also shown that a plurality of fourth doped regions 404 are formed in the first semiconductor substrate 102. The fourth doped regions 404 are regions of the first semiconductor substrate 102 having a second doping type. In some embodiments, the fourth doped regions 404 may be formed by a third implantation process that uses a third mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to selectively implant a second doping type dopant into the first semiconductor substrate 102. Subsequently, in some embodiments, the third mask layer is stripped. It should be understood that the fourth doped regions 404 may be formed before or after the formation of the doped wells 302, or may be formed before or after the formation of the doped isolation regions 303.

[0078] As Figure 8 shown, a plurality of openings 802a to 802b are formed in the first semiconductor substrate 102. For example, a first opening 802a and a second opening 802b are formed in the first semiconductor substrate 102 and are spaced apart from each other. The first opening 802a and the second opening 802b may be formed on opposite sides of the doped isolation region 303. The openings 802a to 802b are formed to extend from the front side 102f of the first semiconductor substrate 102 into the first semiconductor substrate 102. In some embodiments, the openings 802a to 802b are formed with sloped sidewalls. The openings 802a to 802b may be formed with a bottom surface disposed between the storage node 106 and the bottom surface of the first isolation structure 114. In additional embodiments, the process for forming the openings 802a to 802b includes forming a mask layer (not shown) on the front side 102f of the first semiconductor substrate 102. Thereafter, the first semiconductor substrate 102 is exposed to an etchant to remove the unmasked portions of the first semiconductor substrate 102, thereby forming the openings 802a to 802b. Subsequently, in some embodiments, the mask layer is stripped.

[0079] As Figure 9 shown, a gate dielectric layer 902 is formed on the front side 102f of the first semiconductor substrate 102 and lines the openings 802a to 802b. In some embodiments, the process for forming the gate dielectric layer 902 includes depositing or growing a gate dielectric layer 902 on the first semiconductor substrate 102. The gate dielectric layer 902 may be deposited or grown by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing. In additional embodiments, the gate dielectric layer 902 may include, for example, an oxide (such as SiO 2) high-k dielectric materials (such as HfO 2 ZrO 2 or some other dielectric material having a dielectric constant greater than about 3.9) or the like.

[0080] Figure 9 Also shown in is that a gate electrode layer 904 is formed on the gate dielectric layer 902. In some embodiments, the process for forming the gate electrode layer 904 includes depositing the gate electrode layer 904 on the gate dielectric layer 902. The gate electrode layer 904 can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the foregoing. In additional embodiments, the gate electrode layer 904 can include, for example, polysilicon (such as doped / undoped polysilicon), metal (such as W, Al, Ti, Mo, or the like), or the like.

[0081] As Figure 10 shown, a plurality of gates 116 are formed on the front side 102f of the first semiconductor substrate 102. For example, a first gate 116a, a second gate 116b, a first vertical transfer gate 116c, and a second vertical transfer gate 116d are formed on / within the first semiconductor substrate 102 and are spaced apart from each other. In some embodiments, the process for forming the plurality of gates 116 includes forming a mask layer (not shown) on the gate electrode layer 904 (see, for example, Figure 9 ). Thereafter, the gate electrode layer 904 and the gate dielectric layer 902 are exposed to an etchant. The etchant removes the unmasked portions of the gate electrode layer 904 to form a plurality of gate electrodes 120 on the gate dielectric layer 902 and removes the unmasked portions of the gate dielectric layer 902 to form a plurality of gate dielectric layers 118. Subsequently, the mask layer can be stripped. It should be understood that one or more etchants and / or mask layers can be used to form the plurality of gates 116.

[0082] As Figure 11 shown, a plurality of sidewall spacers 206 are formed above the first semiconductor substrate 102 and along the sidewalls of the plurality of gates 116. In some embodiments, the sidewall spacers 206 can be formed by depositing a spacer layer (not shown) above the first semiconductor substrate 102 and above the plurality of gates 116. In additional embodiments, the spacer layer can be deposited by PVD, CVD, ALD, sputtering, or the like. Subsequently, the spacer layer is etched to remove the spacer layer from the horizontal surfaces, leaving the spacer layer extending along opposite sides of the plurality of gates 116 as the sidewall spacers 206. In some embodiments, the spacer layer can include, for example, nitride (such as SiN), oxynitride (such as SiO X N Y) or the like. It should be understood that in some embodiments, lightly doped source / drain regions may be formed in the first semiconductor substrate 102 before forming the sidewall spacers 206.

[0083] Figure 11 Also shown is that a third doped region 402 is formed in the first semiconductor substrate 102. In some embodiments, the third doped region 402 has a second doping type. In additional embodiments, the third doped region 402 may be at least partially formed in the photodetector 104. In still other embodiments, the process for forming the third doped region 402 includes forming a mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 and above the plurality of gates 116. Thereafter, with the mask layer in place, an implantation process is performed to selectively implant dopants of the second doping type into the first semiconductor substrate 102. Subsequently, in some embodiments, the mask layer is stripped.

[0084] As Figure 12 shown, a floating diffusion node 108, a first doped region 110, and a second doped region 112 are formed in the first semiconductor substrate 102. The floating diffusion node 108 is a region of the first semiconductor substrate 102 having a first doping type. In some embodiments, the first doped region 110 has the first doping type. In additional embodiments, the second doped region 112 has the first doping type. The floating diffusion node 108 and the second doped region 112 may be formed in the doped well 302. In additional embodiments, the floating diffusion node 108 and the second doped region 112 are formed between the first vertical transfer gate 116c and the second vertical transfer gate 116d. In still other embodiments, the first doped region 110 may be formed in one of the fourth doped regions 404.

[0085] In some embodiments, the process for forming the floating diffusion node 108, the first doped region 110, and the second doped region 112 includes forming a mask layer (not shown) on the front side 102f of the first semiconductor substrate 102 to cover the plurality of gates 116. Thereafter, with the mask layer in place, an implantation process is performed to selectively implant dopants of the first doping type into the first semiconductor substrate 102. It should be understood that in some embodiments, multiple implantation processes are performed to form the floating diffusion node 108, the first doped region 110, and the second doped region 112.

[0086] As Figure 13As shown, a second ILD structure 208 is formed above the front side 102f of the first semiconductor substrate 102 and above the plurality of gates 116. In some embodiments, the second ILD structure 208 may be formed with a substantially flat upper surface. In additional embodiments, the process for forming the second ILD structure 208 includes depositing an ILD layer on the first semiconductor substrate 102 such that the ILD layer covers the plurality of gates 116. The ILD layer may be deposited by CVD, PVD, sputtering, or some other deposition process. Thereafter, a planarization process (e.g., chemical-mechanical polishing (CMP)) may be performed on the ILD layer.

[0087] Figure 13 Also shown is that a plurality of conductive contact structures 124a are formed extending through the second ILD structure 208. The conductive contact structures 124a may be formed to extend to the plurality of gate electrodes 120 and / or the first semiconductor substrate 102 (e.g., floating diffusion node 108, first doped region 110, second doped region 112, etc.). In some embodiments, the process for forming the conductive contact structures 124a includes forming a plurality of conductive contact structure openings in the second ILD structure 208 that extend to the plurality of gates 116 and / or the first semiconductor substrate 102. The conductive contact structure openings may be formed by a selective etching process that uses a mask layer (not shown) on the second ILD structure 208 to selectively expose the second ILD structure 208 to an etchant and remove the unmasked portions of the second ILD structure 208. Subsequently, in some embodiments, the mask layer is stripped.

[0088] Subsequently, a conductive material (e.g., W) is deposited on the second ILD structure 208 such that the conductive material fills the conductive contact structure openings. Subsequently, a planarization process (e.g., CMP) is performed on the conductive material, thereby forming the conductive contact structures 124a. In some embodiments, the conductive material may be deposited by CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the foregoing.

[0089] As Figure 14As shown, a third ILD structure 210, a plurality of vias 124b, a plurality of conductive lines 124c, and a plurality of first conductive bonding pads 124d are formed over the second ILD structure 208 and the conductive contact structure 124a. The third ILD structure 210 may be formed with a substantially flat upper surface. In some embodiments, the process for forming the third ILD structure 210 includes depositing a plurality of ILD layers stacked on top of each other over the second ILD structure 208 and the conductive contact structure 124a. The ILD layers may be deposited by CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In additional embodiments, a planarization process (e.g., CMP) may be performed on one or more of the plurality of ILD layers.

[0090] In some embodiments, the process for forming the conductive lines 124c, the vias 124b, and the first conductive bonding pads 124d includes forming a first ILD layer over the second ILD structure 208 and the conductive contact structure 124a. The first ILD layer is selectively etched to form a first set of conductive line openings (not shown) corresponding to the first set of conductive lines 124c. A conductive material (e.g., Cu) is deposited on the first ILD layer and in the first set of conductive line openings. A planarization process (e.g., CMP) is performed on the conductive material to form the first set of conductive lines 124c.

[0091] Thereafter, a second ILD layer is formed over the first set of conductive lines and the first ILD layer. The second ILD layer is selectively etched to form a first set of via openings (not shown) corresponding to the first set of vias 124b. A conductive material (e.g., Cu) is deposited on the second ILD layer and in the first set of via openings. A planarization process (e.g., CMP) is performed on the conductive material to form the first set of vias 124b. This process (e.g., alternately forming conductive lines and vias) is repeated until the conductive lines 124c and the vias 124b are formed. It should be understood that in some embodiments, the conductive lines 124c and the vias 124b may be formed by one or more dual damascene processes.

[0092] Thereafter, a third ILD layer is formed over the conductive lines 124c, the first ILD layer, the vias 124b, and the second ILD layer. The third ILD layer is selectively etched to form a plurality of bonding pad openings (not shown) on the third ILD layer. A conductive material (e.g., Cu, Au, etc.) is deposited on the third ILD layer and in the bonding pad openings. A planarization process (e.g., CMP) is performed on the conductive material to form the first conductive bonding pads 124d. In still other embodiments, after forming the first conductive bonding pads 124d, the formation of the first ILD structure 122 is completed.

[0093] As Figure 15As shown, an integrated chip (IC) 304 is bonded to a first semiconductor substrate 102. In some embodiments, the IC 304 includes: a third semiconductor substrate 306; a plurality of semiconductor devices 308a to semiconductor device 308b; a fourth ILD structure 310; and a second interconnect structure 312 including a plurality of second conductive bonding pads 312a. In additional embodiments, the process for bonding the IC 304 to the first semiconductor substrate 102 includes placing the IC 304 such that the second conductive bonding pads 312a are substantially aligned with and face the first conductive bonding pads 124d, respectively. Thereafter, the second conductive bonding pads 312a are bonded to the first conductive bonding pads 124d, respectively (e.g., via a hybrid bonding process, a direct bonding process, etc.). It should be understood that in some embodiments, the fourth ILD structure 310 is bonded to the third ILD structure 210.

[0094] As Figure 16 shown, a second isolation structure 126 is formed in the first semiconductor substrate 102. The second isolation structure 126 is formed to extend from the backside 102b of the first semiconductor substrate 102 into the first semiconductor substrate 102. A second isolation structure 126a, which is a first part of the second isolation structure 126, may be formed to extend into the first semiconductor substrate 102 and extend between the memory node 106 and the photodetector 104. A second isolation structure 126b, which is a second part of the second isolation structure 126, may be formed to extend into the first semiconductor substrate 102 and may be formed on the opposite side of the memory node 106 as the second isolation structure 126a (the first part of the second isolation structure 126). In some embodiments, the second isolation structure 126a (the first part of the second isolation structure 126) may be formed in one of the fourth doped regions 404, and the second isolation structure 126b (the second part of the second isolation structure 126) may be formed in the other of the fourth doped regions 404.

[0095] In some embodiments, the process for forming the second isolation structure 126 includes selectively etching the first semiconductor substrate 102 to form an isolation structure opening on the first semiconductor substrate 102, the isolation structure opening extending from the backside 102b of the first semiconductor substrate 102 into the first semiconductor substrate 102. Thereafter, the isolation structure opening is filled with a dielectric material (e.g., via CVD, PVD, ALD, thermal oxidation, sputtering, etc.). In additional embodiments, the first semiconductor substrate 102 is selectively etched by: forming a mask layer (not shown) on the backside 102b of the first semiconductor substrate 102 and then exposing the first semiconductor substrate 102 to an etchant configured to remove the unmasked portion of the first semiconductor substrate 102. In additional embodiments, the dielectric material may include an oxide (e.g., SiO2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), carbides (such as SiC) or the like. In still other embodiments, a planarization process (such as CMP) may be performed on the dielectric material and the first semiconductor substrate 102 to form a substantially planar surface. It should be understood that in some embodiments, the first semiconductor substrate 102 may be thinned (such as by grinding, CMP or the like) before (or after) forming the second isolation structure 126.

[0096] As Figure 17 shown, a first dielectric layer 130a is formed on the back side 102b of the first semiconductor substrate 102 and the second isolation structure 126. In some embodiments, the first dielectric layer 130a may be formed by CVD, PVD, ALD, sputtering or the like. Subsequently, in some embodiments, a planarization process (such as CMP) may be performed on the first dielectric layer 130a to planarize the upper surface of the first dielectric layer 130a.

[0097] As Figure 18 shown, a reflective structure 128 is formed on the back side 102b of the first semiconductor substrate 102. In some embodiments, the reflective structure 128 is formed to extend from the back side 102b into the first semiconductor substrate 102. For example, a reflective structure 128a, which is the first part of the reflective structure 128, may be formed in the first dielectric layer 130a, a reflective structure 128b, which is the second part of the reflective structure 128, may be formed in the second isolation structure 126a (the first part of the second isolation structure 126), and a reflective structure 128c, which is the third part of the reflective structure 128, may be formed in the second isolation structure 126b (the second part of the second isolation structure 126).

[0098] In some embodiments, the process for forming the reflective structure 128 includes forming a first opening (not shown) corresponding to the reflective structure 128a (the first part of the reflective structure 128) in the first dielectric layer 130a. The first opening may be formed by a first selective etching process that uses a first mask layer (not shown) on the first dielectric layer 130a to selectively expose the first dielectric layer 130a to a first etchant that removes the unmasked portion of the first dielectric layer 130a. Subsequently, in some embodiments, the first mask layer is stripped.

[0099] Thereafter, a plurality of second openings extending into the second isolation structure are formed. The second openings respectively correspond to the reflection structure 128b (the second part of the reflection structure 128) and the reflection structure 128c (the third part of the reflection structure 128). The second openings can be formed by a second selective etching process that uses a second mask layer (not shown) on the first dielectric layer 130a to selectively expose the first dielectric layer 130a and the second isolation structure 126 to a second etchant that removes the unmasked portions of the first dielectric layer 130a and the second isolation structure 126. Then, a conductive material (such as W, Al, Cu, etc.) is deposited on the first dielectric layer 130a, in the first opening, and in the second opening. A planarization process (such as CMP) is performed on the conductive material to form the reflection structure 128. Subsequently, in some embodiments, the second mask layer is stripped. It should be understood that in some embodiments, the second mask layer can be formed on the first mask layer and the first dielectric layer 130a, and after depositing the conductive material, the first mask layer and the second mask layer can be stripped.

[0100] As Figure 19 shown, a second dielectric layer 130b is formed on the first dielectric layer 130a and the reflection structure 128. The second dielectric layer 130b can be formed by CVD, PVD, ALD, sputtering, or the like in some embodiments. Subsequently, in some embodiments, a planarization process (such as CMP) can be performed on the second dielectric layer 130b to planarize the upper surface of the second dielectric layer 130b. In some embodiments, after forming the second dielectric layer 130b, the formation of the dielectric structure 130 is completed. In additional embodiments, the dielectric structure 130 can be a BSI antireflection structure configured to reduce the amount of reflection of the first semiconductor substrate 102 for incident radiation. In other embodiments, the dielectric structure 130 can be different from the BSI antireflection structure. In such embodiments, it should be understood that a BSI antireflection layer (such as via CVD, PVD, ALD, sputtering, etc.) can be formed before (or after) forming the dielectric structure 130.

[0101] As Figure 20 shown, a filter 202 is formed on the dielectric structure 130. In some embodiments, the filter 202 is formed on the second dielectric layer 130b. In some embodiments, the process for forming the filter 202 includes depositing a light filtering material (such as via CVD, PVD, ALD, sputtering, spin coating, etc.) onto the dielectric structure 130. The light filtering material is a material that allows radiation (such as light) within a specific wavelength range to pass through while blocking light outside the specified range of wavelengths. Subsequently, in some embodiments, a planarization process (such as CMP) can be performed on the filter 202 to planarize the upper surface of the filter 202.

[0102] Figure 20 It is also shown that a microlens 204 is formed on the filter 202. In some embodiments, the microlens 204 can be formed by depositing a microlens material on the filter 202 (e.g., via CVD, PVD, ALD, sputtering, spin coating, etc.). A microlens template (not shown) having an arcuate upper surface is patterned on the microlens material. In some embodiments, the microlens template may include a photoresist material, and the photoresist material is exposed, developed, and baked by using a distributed exposure dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curved portion and less light is exposed at the top of the curved portion) to form a circular shape. Then, the microlens 204 is formed by selectively etching the microlens material according to the microlens template. In additional embodiments, after the microlens 204 is formed, the formation of the BSIGS image sensor 100 is completed.

[0103] Figure 21 FIG. 2100 is a flowchart showing some embodiments of a method for forming a backside illuminated global shutter (BSIGS) image sensor 100. Although Figure 21 the flowchart 2100 is shown and described herein as a series of actions or events, it should be understood that the shown order of these actions or events should not be construed in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events in addition to those shown and / or described herein. Moreover, not all of the illustrated actions are required to implement one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0104] At operation 2102, a photodetector and a storage node are formed in a first semiconductor substrate, wherein the first semiconductor substrate includes a front side and a back side opposite the front side. Figures 5 to 6 A series of cross-sectional views corresponding to operation 2102 are shown.

[0105] At operation 2104, a plurality of gates are formed on the front side of the semiconductor substrate, wherein the plurality of gates includes a first vertical transfer gate and a second vertical transfer gate extending from the front side into the semiconductor substrate. Figures 7 to 11 A series of cross-sectional views corresponding to operation 2104 are shown. In some embodiments, a doped isolation region may be formed in the first semiconductor substrate before the plurality of gates are formed. Figure 7 A cross-sectional view showing some embodiments for forming a doped isolation region is shown.

[0106] At operation 2106, a floating diffusion node, a first doped region, and a second doped region are formed in the first semiconductor substrate. Figure 12A cross-sectional view showing some embodiments corresponding to operation 2106.

[0107] At operation 2108, an interlayer dielectric (ILD) structure is formed on the front side of the first semiconductor substrate and above the plurality of gates. Figures 13 to 14 A series of cross-sectional views showing some embodiments corresponding to operation 2108.

[0108] At operation 2110, a second semiconductor substrate is bonded to the first semiconductor substrate, wherein the first semiconductor substrate is separated from the second semiconductor substrate by the ILD structure. Figure 15 A cross-sectional view showing some embodiments corresponding to operation 2110.

[0109] At operation 2112, an isolation structure is formed in the first semiconductor substrate, which extends from the back side of the first semiconductor substrate into the first semiconductor substrate. Figure 16 A cross-sectional view showing some embodiments corresponding to operation 2112.

[0110] At operation 2114, a reflective structure is formed on the back side of the first semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposite sides of the storage node. Figures 17 to 19 A series of cross-sectional views showing some embodiments corresponding to operation 2114. In some embodiments, a filter and / or a microlens are formed on the back side of the first semiconductor substrate. Figure 20 A cross-sectional view showing some embodiments for forming a filter and / or a microlens.

[0111] In some embodiments, the present disclosure provides an image sensor. The image sensor includes: a photodetector disposed in a semiconductor substrate; an interlayer dielectric (ILD) structure disposed on a first side of the semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; a first isolation structure disposed in the semiconductor substrate and located between the photodetector and the storage node, wherein the first isolation structure extends from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate, and wherein the first isolation structure is spaced apart from the first side by a second distance less than the first distance.

[0112] In some embodiments, the image sensor further includes: a metal structure disposed on the second side, wherein a first portion of the metal structure is disposed between opposite sides of the storage node.

[0113] In some embodiments, at least a portion of the metal structure is offset from the photodetector in a lateral direction.

[0114] In some embodiments, the opposite sides of the storage node are disposed between opposite sidewalls of the metal structure.

[0115] In some embodiments, a second portion of the metal structure is disposed in the first isolation structure and extends from the second side into the semiconductor substrate.

[0116] In some embodiments, the second portion of the metal structure is spaced from the first side by a third distance greater than the first distance.

[0117] In some embodiments, the image sensor further includes: a microlens disposed on the second side, wherein the metal structure is disposed between the microlens and the semiconductor substrate.

[0118] In some embodiments, the image sensor further includes: a dielectric structure disposed between the microlens and the semiconductor substrate, wherein the metal structure is disposed in the dielectric structure.

[0119] In some embodiments, the image sensor further includes: a first vertical transfer gate configured to selectively form a first conductive channel between the photodetector and the storage node, wherein the first vertical transfer gate extends from the first side into the semiconductor substrate, and wherein a bottommost surface of the first vertical transfer gate is spaced from the first side by a fourth distance greater than the second distance.

[0120] In some embodiments, the image sensor further includes: a second vertical transfer gate spaced from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and the floating diffusion node, wherein the second vertical transfer gate extends from the first side into the semiconductor substrate, and wherein a bottommost surface of the second vertical transfer gate is spaced from the first side by a fifth distance greater than the second distance.

[0121] In some embodiments, the image sensor further includes: a second isolation structure disposed in the semiconductor substrate and separated from the first isolation structure by the storage node, wherein the second isolation structure extends from the second side into the semiconductor substrate, and wherein both the first vertical transfer gate and the second vertical transfer gate are at least partially disposed between the first isolation structure and the second isolation structure.

[0122] In some embodiments, the second isolation structure is spaced from the first side by a sixth distance less than the first distance and the fourth distance.

[0123] In some embodiments, the image sensor further includes: a doped isolation region disposed in the semiconductor substrate and between the first vertical transfer gate and the second vertical transfer gate, wherein the doped isolation region is disposed between the storage node and the floating diffusion node, and wherein the doped isolation region has a doping type opposite to that of the floating diffusion node.

[0124] In some embodiments, the present disclosure provides an image sensor. The image sensor includes: a photodetector disposed in a semiconductor substrate, wherein the photodetector is spaced apart from a first side of the semiconductor substrate by a first distance; an interlayer dielectric (ILD) structure disposed on the first side of the semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a second distance greater than the first distance; and a first vertical transfer gate disposed on the first side and configured to selectively form a first conductive channel between the photodetector and the storage node, wherein a first portion of the first vertical transfer gate extends from the first side into the semiconductor substrate by a third distance, and wherein the third distance is greater than the first distance and less than the second distance.

[0125] In some embodiments, the image sensor further includes: a doped isolation region disposed in the semiconductor substrate, wherein the doped isolation region is disposed between the storage node and at least a second portion of the first vertical transfer gate, and wherein the doped isolation region has a doping type opposite to that of the storage node.

[0126] In some embodiments, the image sensor further includes: a reflective structure disposed on a second side of the semiconductor substrate opposite to the first side, wherein opposite sides of the storage node are disposed between opposite sidewalls of the reflective structure.

[0127] In some embodiments, the image sensor further includes: a first isolation structure extending from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate, wherein the first isolation structure extends into the semiconductor substrate and is located between the storage node and the photodetector, and wherein the first portion of the first vertical transfer gate and the photodetector are disposed on opposite sides of the first isolation structure.

[0128] In some embodiments, the image sensor further includes: a second vertical transfer gate spaced apart from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and the floating diffusion node, wherein a portion of the second vertical transfer gate extends from the first side into the semiconductor substrate by a fourth distance, and wherein the fourth distance is greater than the first distance and less than the second distance.

[0129] In some embodiments, the first isolation structure laterally surrounds the storage node; the first portion of the first vertical transfer gate and the portion of the second vertical transfer gate are both disposed within the inner perimeter of the first isolation structure; and the floating diffusion node and the photodetector are both disposed outside the inner perimeter of the first isolation structure.

[0130] In some embodiments, the present disclosure provides a method for forming an image sensor, including: forming a photodetector in a semiconductor substrate; forming a storage node in the semiconductor substrate and spaced apart from the photodetector; forming a first vertical transfer gate and a second vertical transfer gate on a first side of the semiconductor substrate, wherein a portion of the first vertical transfer gate and a portion of the second vertical transfer gate extend from the first side into the semiconductor substrate; forming an interlayer dielectric (ILD) structure on the first side and above the first vertical transfer gate and the second vertical transfer gate; forming an isolation structure in the semiconductor substrate, wherein the isolation structure extends from a second side of the semiconductor substrate opposite the first side into the first semiconductor substrate; and forming a reflective structure on the second side of the semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposite sides of the storage node.

[0131] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: a photodetector disposed in a semiconductor substrate; an interlayer dielectric structure disposed on a first side of the semiconductor substrate; a storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; a first isolation structure disposed in the semiconductor substrate and located between the photodetector and the storage node, wherein the first isolation structure extends from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate, and wherein the first isolation structure is spaced apart from the first side by a second distance less than the first distance; and a doped isolation region disposed in the semiconductor substrate and extending between the storage node and the first side on one side of the first isolation structure, wherein the doped isolation region is spaced apart from the first side, and wherein the doped isolation region has a doping type opposite to that of the storage node.

2. The image sensor according to claim 1, further comprising: a metal structure disposed on the second side, wherein a first portion of the metal structure is disposed between opposite sides of the storage node.

3. The image sensor according to claim 2, wherein at least a portion of the metal structure is offset from the photodetector in a lateral direction.

4. The image sensor according to claim 2, wherein the opposite sides of the storage node are disposed between opposite sidewalls of the metal structure.

5. The image sensor according to claim 2, wherein a second portion of the metal structure is disposed in the first isolation structure and extends from the second side into the semiconductor substrate.

6. The image sensor according to claim 5, wherein the second portion of the metal structure is spaced apart from the first side by a third distance greater than the first distance.

7. The image sensor according to claim 2, further comprising: a microlens disposed on the second side, wherein the metal structure is disposed between the microlens and the semiconductor substrate.

8. The image sensor according to claim 7, further comprising: a dielectric structure disposed between the microlens and the semiconductor substrate, wherein the metal structure is disposed in the dielectric structure.

9. The image sensor according to claim 1, further comprising: a first vertical transfer gate configured to selectively form a first conductive channel between the photodetector and the storage node, wherein the first vertical transfer gate extends from the first side into the semiconductor substrate, and wherein a bottommost surface of the first vertical transfer gate is spaced apart from the first side by a fourth distance greater than the second distance.

10. The image sensor according to claim 9, further comprising: a floating diffusion node disposed in the semiconductor substrate and spaced apart from the photodetector and the storage node; and A second vertical transfer gate, spaced apart from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and the floating diffusion node, wherein the second vertical transfer gate extends from the first side into the semiconductor substrate, and wherein a bottommost surface of the second vertical transfer gate is spaced apart from the first side by a fifth distance greater than the second distance.

11. The image sensor according to claim 10, further comprising: A second isolation structure disposed in the semiconductor substrate and separated from the first isolation structure by the storage node, wherein the second isolation structure extends from the second side into the semiconductor substrate, and wherein both the first vertical transfer gate and the second vertical transfer gate are at least partially disposed between the first isolation structure and the second isolation structure.

12. The image sensor according to claim 11, wherein the second isolation structure is spaced apart from the first side by a sixth distance, the sixth distance being less than the first distance and the fourth distance.

13. The image sensor according to claim 12, wherein the doped isolation region is located between the first vertical transfer gate and the second vertical transfer gate, wherein the doped isolation region is disposed between the storage node and the floating diffusion node, and wherein the doped isolation region has a doping type opposite to that of the floating diffusion node.

14. A method for forming an image sensor, comprising: Forming a photodetector in a semiconductor substrate; Forming a storage node in the semiconductor substrate and spaced apart from the photodetector; Forming a doped isolation region in the semiconductor substrate, wherein the doped isolation region extends between the storage node and a first side of the semiconductor substrate, wherein the doped isolation region is spaced apart from the first side, and wherein the doped isolation region has a doping type opposite to that of the storage node; Forming a first vertical transfer gate and a second vertical transfer gate on the first side, wherein a portion of the first vertical transfer gate and a portion of the second vertical transfer gate extend from the first side into the semiconductor substrate, and wherein the doped isolation region extends between the first vertical transfer gate and the second vertical transfer gate; forming an interlayer dielectric structure on the first side and above the first vertical transfer gate and the second vertical transfer gate; Forming an isolation structure in the semiconductor substrate, wherein the isolation structure extends from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate; and Forming a reflective structure on the second side of the semiconductor substrate, wherein at least a portion of the reflective structure is disposed between opposite sides of the storage node.

15. An image sensor, comprising: A photodetector disposed in a semiconductor substrate; An interlayer dielectric structure disposed on a first side of the semiconductor substrate; A storage node disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; A first vertical transfer gate extending from the first side into the semiconductor substrate, wherein the first vertical transfer gate is configured to selectively form a first conductive channel between the photodetector and the storage node; A first isolation structure disposed in the semiconductor substrate and between the photodetector and the storage node, wherein the first isolation structure extends from a second side of the semiconductor substrate opposite the first side into the semiconductor substrate, and wherein the first isolation structure is spaced from the first side by a second distance less than the first distance; A doped isolation region disposed in the semiconductor substrate and extending between the storage node and the first side on one side of the first vertical transfer gate, wherein the doped isolation region is spaced from the first side, and wherein the doped isolation region has a doping type opposite to that of the storage node; And A metal structure disposed on the second side, wherein a first portion of the metal structure is disposed between opposite sides of the storage node.

16. The image sensor according to claim 15, wherein at least a portion of the metal structure is offset laterally from the photodetector.

17. The image sensor according to claim 15, wherein the opposite sides of the storage node are disposed between opposite sidewalls of the metal structure.

18. The image sensor according to claim 15, wherein a second portion of the metal structure is disposed in the first isolation structure and extends from the second side into the semiconductor substrate.

19. The image sensor according to claim 18, wherein the second portion of the metal structure is spaced from the first side by a third distance greater than the first distance.

20. The image sensor according to claim 15, further comprising: A microlens disposed on the second side, wherein the metal structure is disposed between the microlens and the semiconductor substrate.

21. The image sensor according to claim 20, further comprising: A dielectric structure disposed between the microlens and the semiconductor substrate, wherein the metal structure is disposed in the dielectric structure.

22. The image sensor according to claim 15, wherein a bottommost surface of the first vertical transfer gate is spaced from the first side by a fourth distance greater than the second distance.

23. The image sensor according to claim 22, further comprising: A floating diffusion node disposed in the semiconductor substrate and spaced from the photodetector and the storage node; And A second vertical transfer gate spaced from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and the floating diffusion node, wherein the second vertical transfer gate extends from the first side into the semiconductor substrate, and wherein a bottommost surface of the second vertical transfer gate is spaced from the first side by a fifth distance greater than the second distance.

24. The image sensor according to claim 23, further comprising: A second isolation structure, disposed in the semiconductor substrate and separated from the first isolation structure by the storage node, wherein the second isolation structure extends from the second side into the semiconductor substrate, and wherein the first vertical transfer gate and the second vertical transfer gate are both at least partially disposed between the first isolation structure and the second isolation structure.

25. The image sensor according to claim 24, wherein the second isolation structure is spaced apart from the first side by a sixth distance, the sixth distance being less than the first distance and the fourth distance.

26. The image sensor according to claim 25, wherein the doped isolation region is located between the first vertical transfer gate and the second vertical transfer gate, wherein the doped isolation region is disposed between the storage node and the floating diffusion node, and wherein the doped isolation region has a doping type opposite to that of the floating diffusion node.

27. An image sensor, comprising: a photodetector, disposed in a semiconductor substrate; an interlayer dielectric structure, disposed on a first side of the semiconductor substrate; a storage node, disposed in the semiconductor substrate and spaced apart from the photodetector; an isolation structure, disposed in the semiconductor substrate and laterally surrounding the storage node, wherein the isolation structure extends from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate, wherein a first portion of the isolation structure laterally spaces the photodetector from the storage node; a first vertical transfer gate, disposed on the first side, wherein a portion of the first vertical transfer gate extends vertically into the semiconductor substrate, wherein the portion of the first vertical transfer gate is disposed between the first portion of the isolation structure and a second portion of the isolation structure relative to the first portion, and wherein the first vertical transfer gate is configured to selectively form a first conductive channel between the photodetector and the storage node; a second vertical transfer gate, disposed on the first side and spaced apart from the first vertical transfer gate, wherein a portion of the second vertical transfer gate extends vertically into the semiconductor substrate, wherein the portion of the second vertical transfer gate is disposed between the first portion of the isolation structure and the second portion, and wherein the second vertical transfer gate is configured to selectively form a second conductive channel between the storage node and a floating diffusion node disposed in the semiconductor substrate and spaced apart from the photodetector and the storage node; and a doped isolation region, disposed in the semiconductor substrate and extending between the first vertical transfer gate and the second vertical transfer gate between the storage node and the first side, wherein the doped isolation region is spaced apart from the first side, and wherein the doped isolation region has a doping type opposite to that of the storage node.

28. An image sensor, comprising: a photodetector, disposed in a semiconductor substrate; an interlayer dielectric structure, disposed on a first side of the semiconductor substrate; A storage node, disposed in the semiconductor substrate and spaced apart from the photodetector, wherein the storage node is spaced apart from the first side by a first distance; A first vertical transfer gate, extending from the first side into the semiconductor substrate, wherein the first vertical transfer gate is configured to selectively form a first conductive channel between the photodetector and the storage node; An isolation structure, disposed in the semiconductor substrate and located between the photodetector and the storage node, wherein the isolation structure extends from a second side of the semiconductor substrate opposite to the first side into the semiconductor substrate, wherein the isolation structure is spaced apart from the first side by a second distance less than the first distance, and wherein a bottommost surface of the first vertical transfer gate is spaced apart from the first side by a third distance greater than the second distance; and A doped isolation region, disposed in the semiconductor substrate and extending between the storage node and the first side on one side of the first vertical transfer gate, wherein the doped isolation region is spaced apart from the first side, and wherein the doped isolation region has a doping type opposite to that of the storage node.

29. The image sensor according to claim 28, wherein the doped isolation region is disposed between the storage node and at least a portion of the first vertical transfer gate, and wherein the doped isolation region has a doping type opposite to that of a floating diffusion node disposed in the semiconductor substrate and spaced apart from the photodetector and the storage node.

30. The image sensor according to claim 28, further comprising: A reflective structure, disposed on the second side of the semiconductor substrate, wherein opposite sides of the storage node are disposed between opposite sidewalls of the reflective structure.

31. The image sensor according to claim 28, wherein a portion of the first vertical transfer gate extends into the semiconductor substrate from the first side by a fourth distance, and wherein the fourth distance is less than or equal to the first distance.

32. The image sensor according to claim 31, further comprising: A second vertical transfer gate, spaced apart from the first vertical transfer gate and configured to selectively form a second conductive channel between the storage node and the floating diffusion node, wherein a portion of the second vertical transfer gate extends into the semiconductor substrate from the first side by a fifth distance, wherein the fifth distance is less than or equal to the first distance.

33. The image sensor according to claim 32, wherein: the isolation structure laterally surrounds the storage node; the portion of the first vertical transfer gate and the portion of the second vertical transfer gate are both disposed within an inner perimeter of the isolation structure; and the floating diffusion node and the photodetector are both located outside the inner perimeter of the isolation structure.

Images