Semiconductor device and method of manufacturing a semiconductor device

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device may include a channel pattern stacked on a substrate and a gate electrode stacked on the substrate. The channel pattern includes a semiconductor pattern. The gate electrode extends to intersect the channel pattern. The gate electrode may include a dielectric layer, a first work function adjustment pattern, and a second work function adjustment pattern. The dielectric layer may surround the semiconductor pattern, the first work function adjustment pattern may surround the dielectric layer, and the second work function adjustment pattern may surround the first work function adjustment pattern. The first work function adjustment pattern may be formed of a material containing aluminum, and each corresponding first work function adjustment pattern in the first work function adjustment pattern contacts a corresponding second work function adjustment pattern in the second work function adjustment pattern that surrounds the corresponding first work function adjustment pattern in the first work function adjustment pattern.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0063033 filed on May 29, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and in particular, to a semiconductor device including a gate-all-around transistor and a method for manufacturing the semiconductor device. Background Art

[0003] Semiconductor devices are considered important components in the electronics industry due to their small size, multifunctionality and / or low cost. Semiconductor devices are classified into memory devices for storing data, logic devices for processing data, and hybrid devices including both memory and logic elements. In order to meet the growing demand for electronic devices with high speed and / or low energy consumption, it is necessary to realize semiconductor devices with high reliability, high performance and / or multifunctionality. In order to meet these technical requirements, the complexity and / or integration density of semiconductor devices are being improved. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics and a method of manufacturing the semiconductor device.

[0005] According to an embodiment of the inventive concept, a method for manufacturing a semiconductor device may include the following steps: forming an active pattern on a substrate, the active pattern including sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; forming an interlayer insulating layer on the substrate to cover the active pattern and define a gate region in which a gate electrode intersecting the active pattern will be formed; removing the sacrificial pattern; sequentially depositing a dielectric layer, a first work function adjustment pattern, and a second work function adjustment pattern, the dielectric layer, the first work function adjustment pattern, and the second work function adjustment pattern sequentially surrounding a surface of the active pattern exposed in the gate region; and then filling the gate region with a semiconductor material. The steps of forming the first work function adjustment pattern and the second work function adjustment pattern can be performed in situ.

[0006] According to an embodiment of the inventive concept, a method for manufacturing a semiconductor device may include the following steps: forming an active pattern on a substrate, the active pattern including alternating and repetitive stacking of sacrificial patterns and semiconductor patterns; forming a sacrificial gate pattern to intersect the active pattern; forming gate spacers at both sides of the sacrificial gate structure pattern; removing each of the sacrificial patterns and the sacrificial gate patterns between the gate spacers to form an empty space; and forming a gate structure in the empty space. Forming the gate structure includes sequentially depositing a dielectric layer, a first work function adjustment pattern, and a second work function adjustment pattern on an outer peripheral surface of the semiconductor pattern exposed in the empty space, and the first work function adjustment pattern may contact the second work function adjustment pattern.

[0007] According to an embodiment of the inventive concept, a method for manufacturing a semiconductor device may include the following steps: forming a first active pattern and a second active pattern on a substrate, each of the first active pattern and the second active pattern including a sacrificial pattern and a semiconductor pattern alternately and repeatedly stacked; forming a sacrificial gate pattern to intersect the first active pattern and the second active pattern; forming gate spacers on opposite side surfaces of the sacrificial gate pattern; removing each of the sacrificial patterns and the sacrificial gate pattern between the gate spacers to form an empty space, forming a first work function adjustment pattern surrounding the semiconductor pattern of the first active pattern in the empty space; forming a second work function adjustment pattern surrounding the semiconductor pattern of the second active pattern in the empty space; and forming a third work function adjustment pattern surrounding the semiconductor pattern of the first active pattern and the second active pattern in the empty space. The steps of forming the second work function adjustment pattern and forming the third work function adjustment pattern may be performed continuously in the same process chamber.

[0008] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; a channel pattern stacked on the substrate, the channel pattern including a semiconductor pattern; and a gate structure located on the substrate, the gate structure extending to intersect the channel pattern. The gate structure may include a dielectric layer, a first work function adjustment pattern, and a second work function adjustment pattern. The dielectric layers may respectively surround the semiconductor patterns. The first work function adjustment patterns may respectively surround the dielectric layers, and the second work function adjustment patterns may respectively surround the first work function adjustment patterns. The first work function adjustment patterns may be formed of a material including aluminum, and each corresponding first work function adjustment pattern among the first work function adjustment patterns may contact a corresponding one of the second work function adjustment patterns that surrounds the corresponding first work function adjustment pattern among the first work function adjustment patterns.

[0009] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; a first active structure and a second active structure located on the substrate, each of the first active structure and the second active structure being spaced apart from each other, each of the first active structure and the second active structure including a semiconductor pattern stacked on the substrate; a first gate structure intersecting the first active structure; and a second gate structure intersecting the second active structure. The first gate structure may include a first dielectric layer surrounding the semiconductor pattern of the first active structure, a first work function adjustment pattern surrounding the first dielectric layer, and a second work function adjustment pattern surrounding the first work function adjustment pattern. The second gate structure may include a second dielectric layer surrounding the semiconductor pattern of the second active structure and a third work function adjustment pattern surrounding the second dielectric layer. The oxygen (O) content in the first work function adjustment pattern may be in a range of 0% to 30%, and the first work function adjustment pattern may be in direct contact with the second work function adjustment pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0011] Figure 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 1B It is along Figure 1A A cross-sectional view taken along line AA'.

[0013] Figure 1C It is along Figure 1A Cross-sectional view taken along line BB'.

[0014] Figure 2A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0015] Figure 2B It is along Figure 2A Cross-sectional view taken along line C-C'.

[0016] Figure 2C It is along Figure 2A A cross-sectional view taken along line D-D'.

[0017] Figures 3A to 11A is a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0018] Figures 3B to 11B are respectively along Figures 3A to 11A A cross-sectional view taken along line AA'.

[0019] Figures 3C to 11C are respectively along Figures 3A to 11ACross-sectional view taken along line BB'.

[0020] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials utilized in certain example embodiments and are intended to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structural characteristics or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values ​​or performances encompassed by the example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0021] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0022] Figure 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 1B It is along Figure 1A A cross-sectional view taken along line AA'. Figure 1C It is along Figure 1A Cross-sectional view taken along line BB'.

[0023] Reference Figures 1A to 1C A substrate 100 including a first region RG1 and a second region RG2 may be provided. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon (Si) wafer or a germanium (Ge) wafer. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) wafer. The first region RG1 and the second region RG2 of the substrate 100 may be arranged side by side in a first direction D1. The first region RG1 and the second region RG2 of the substrate 100 may be regions on which the first transistor TR1 and the second transistor TR2 are respectively provided.

[0024] Hereinafter, the first direction D1 and the second direction D2 may be defined to be parallel to the top surface of the substrate 100 and perpendicular to each other, and the third direction D3 may be defined to be perpendicular to the top surface of the substrate 100 .

[0025] In an embodiment, the first region RG1 and the second region RG2 of the substrate 100 may be memory cell regions in which a plurality of memory cells for storing data are formed. For example, memory cell transistors constituting a plurality of SRAM cells may be provided in the memory cell region of the substrate 100. The first transistor TR1 and the second transistor TR2 may be some of the memory cell transistors.

[0026] In some embodiments, the first region RG1 and the second region RG2 of the substrate 100 may be logic cell regions in which logic transistors constituting a logic circuit of the semiconductor device are disposed. For example, logic transistors may be disposed in the logic cell region of the substrate 100. The first transistor TR1 and the second transistor TR2 may be some of the logic transistors. However, the inventive concept is not limited to these examples.

[0027] The first transistor TR1 and the second transistor TR2 in the first region RG1 and the second region RG2 may have the same conductivity type. For example, the first transistor TR1 and the second transistor TR2 in the first region RG1 and the second region RG2 may be NMOSFETs. As another example, the first transistor TR1 and the second transistor TR2 in the first region RG1 and the second region RG2 may be PMOSFETs. In some embodiments, the first transistor TR1 and the second transistor TR2 may have different conductivity types. For example, the first transistor TR1 in the first region RG1 may be an NMOSFET, while the second transistor TR2 in the second region RG2 may be a PMOSFET.

[0028] The base active pattern 102 may be disposed on the substrate 100. The base active pattern 102 may protrude from the substrate 100 in the third direction D3. The base active pattern 102 may extend along the first direction D1. Figure 1A and Figure 1C As shown in , a plurality of base active patterns 102 may be provided, and the plurality of base active patterns 102 may be arranged along the second direction D2.

[0029] A device insulating layer ST may be disposed on the substrate 100 and disposed on both sides of each base active pattern 102. The device insulating layer ST may extend in the first direction D1. The device insulating layer ST may fill the spaces between the base active patterns 102. The device insulating layer ST may expose the upper sidewalls of the base active patterns 102. For example, the top surface of the device insulating layer ST may be located at a lower level than the top surface of the base active pattern 102. The device insulating layer ST may be formed of or include oxide, nitride, or oxynitride.

[0030] The active structure AS may be disposed on the base active pattern 102. When viewed in a plan view, the active structure AS may overlap the base active pattern 102. Each active structure AS may be a linear structure extending in the first direction D1. For example, the active structure AS may extend along the top surface of the base active pattern 102 and in the first direction D1.

[0031] Each active structure AS may include a channel pattern CH and a source / drain pattern SD. The channel pattern CH may be interposed between a pair of source / drain patterns SD. The channel pattern CH and the source / drain pattern SD may be arranged along the top surface of the base active pattern 102 and in a first direction D1. The channel pattern CH of the first region RG1 may include a plurality of vertically stacked first semiconductor patterns NS1. The channel pattern CH of the second region RG2 may include a plurality of vertically stacked second semiconductor patterns NS2.

[0032] The first semiconductor patterns NS1 may be spaced apart from one another in the third direction D3. The bottommost of the first semiconductor patterns NS1 may be spaced apart from the base active pattern 102 in the third direction D3. The spacing distance between the first semiconductor patterns NS1 in the third direction D3 may be in a range of 1 nm to 15 nm. Each of the source / drain patterns SD may be in direct contact with a sidewall of the first semiconductor pattern NS1. In other words, the first semiconductor pattern NS1 may be in contact with a pair of adjacent source / drain patterns SD. Figure 1B and Figure 1C An example is shown in which the number of first semiconductor patterns NS1 of the channel patterns CH of the first region RG1 is three, but the inventive concept is not limited to this example. The first semiconductor patterns NS1 may have the same thickness as each other or different thicknesses from each other. The first semiconductor pattern NS1 may be formed of or include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). If necessary, the first semiconductor pattern NS1 may be doped with impurities. For example, when the first transistor TR1 is an NMOSFET, the impurity may be boron (B). When the first transistor TR1 is a PMOSFET, the impurity may be phosphorus (P).

[0033] The second semiconductor pattern NS2 may be configured to have substantially the same features as the first semiconductor pattern NS1 described above. In the case where the first and second transistors TR1 and TR2 have different conductivity types from each other, the second semiconductor pattern NS2 may be doped with impurities different from those in the first semiconductor pattern NS1.

[0034] The first semiconductor pattern NS1 and the second semiconductor pattern NS2 disposed at the same level may be formed of the same semiconductor layer. The first semiconductor pattern NS1 and the second semiconductor pattern NS2 disposed at the same level may have substantially the same thickness. The first semiconductor pattern NS1 and the second semiconductor pattern NS2 disposed at the same level may be formed of or include substantially the same semiconductor material.

[0035] The source / drain pattern SD may be an epitaxial pattern formed using the first and second semiconductor patterns NS1 and NS2 and the base active pattern 102 as a seed layer. For example, when the first and second transistors TR1 and TR2 are NMOSFETs, the source / drain pattern SD may include a semiconductor material that applies tensile stress to the channel pattern CH. As an example, the source / drain pattern SD may be formed of or include a semiconductor material having a smaller lattice constant than that of the semiconductor material of the channel pattern CH. In some embodiments, the source / drain pattern SD may include the same semiconductor material as that of the channel pattern CH. When the first and second transistors TR1 and TR2 are PMOSFETs, the source / drain pattern SD may include a semiconductor material that applies compressive stress to the channel pattern CH. As an example, the source / drain pattern SD may be formed of or include a semiconductor material having a larger lattice constant than that of the semiconductor material of the channel pattern CH.

[0036] The source / drain pattern SD may further include impurities. The impurities may be used to improve the electrical characteristics of the first transistor TR1 and the second transistor TR2 including the source / drain pattern SD. If the first transistor TR1 and the second transistor TR2 are NMOSFETs, the impurities may be phosphorus (P). If the first transistor TR1 and the second transistor TR2 are PMOSFETs, the impurities may be boron (B).

[0037] The first gate structure GS1 and the second gate structure GS2 may be disposed on the active structure AS. The first gate structure GS1 and the second gate structure GS2 may be disposed to intersect the channel patterns CH of the first region RG1 and the second region RG2, respectively, and may extend in the second direction D2. The first gate structure GS1 and the second gate structure GS2 may be spaced apart from each other in the first direction D1. When viewed in a plan view, the channel pattern CH of the first region RG1 may overlap with the first gate structure GS1, and the channel pattern CH of the second region RG2 may overlap with the second gate structure GS2. Source / drain patterns SD may be disposed on both sides of the first gate structure GS1 and on both sides of the second gate structure GS2.

[0038] The first gate structure GS1 and the second gate structure GS2 may include a first work function adjustment pattern WF1 and a second work function adjustment pattern WF2. The first gate structure GS1 and the second gate structure GS2 may include a gate electrode GE.

[0039] Each of the first gate structure GS1 and the second gate structure GS2 may have a first portion P1 and a second portion P2. The first portion P1 may be disposed in a space between first semiconductor patterns NS1 adjacent to each other in the vertical direction and in a space between second semiconductor patterns NS2 adjacent to each other in the vertical direction. In other words, the first portion P1 may be a portion interposed between first semiconductor patterns NS1 adjacent to each other in the vertical direction and a portion interposed between second semiconductor patterns NS2 adjacent to each other in the vertical direction. The second portion P2 may be disposed in a space above the topmost semiconductor patterns NS1 and NS2. The space above the topmost semiconductor patterns NS1 and NS2 may be a space surrounded by a pair of gate spacers GSP and by the topmost semiconductor patterns NS1 and NS2, the pair of gate spacers GSP being described below. In other words, the second portion P2 may be a portion located above the topmost semiconductor patterns NS1 and NS2 and interposed between the pair of gate spacers GSP.

[0040] In the first portion P1, each of the first work function adjustment patterns WF1 may cover a surface of a corresponding one of the first semiconductor patterns NS1. Figure 1C As shown in , the first work function adjustment pattern WF1 may surround the outer peripheral surface of the first semiconductor pattern NS1, or may surround the outer peripheral surface of the second semiconductor pattern NS2. Here, the outer peripheral surfaces of the semiconductor patterns NS1 and NS2 may refer to the side surfaces of the semiconductor patterns NS1 and NS2 exposed in the second direction D2 and the top and bottom surfaces of the semiconductor patterns NS1 and NS2 exposed in the third direction D3. In other words, each of the first transistor TR1 and the second transistor TR2 may be a surround-gate field-effect transistor. The first work function adjustment pattern WF1 may include a metal compound having a relatively low work function. As an example, the first work function adjustment pattern WF1 may be doped with aluminum (Al) or a metal compound containing aluminum. In embodiments, the first work function adjustment pattern WF1 may be formed of or include titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or tantalum aluminum nitride (TaAlN). Here, the content of oxygen (O) in the first work function adjustment pattern WF1 may be in the range of 0% to 30%.

[0041] In the first portion P1, the first work function adjustment pattern WF1 and the second work function adjustment pattern WF2 may be sequentially stacked on the surfaces of the semiconductor patterns NS1 and NS2. Figure 1CAs shown in , the first work function adjustment pattern WF1 may surround the outer peripheral surface of the semiconductor patterns NS1 and NS2, and the second work function adjustment pattern WF2 may surround the outer peripheral surface of the first work function adjustment pattern WF1. The second work function adjustment pattern WF2 may be in direct contact with the first work function adjustment pattern WF1. For example, an intermediate layer such as an oxide layer or a nitride layer may not be interposed between the sequentially stacked first work function adjustment pattern WF1 and the second work function adjustment pattern WF2. The second work function adjustment pattern WF2 may include a metal compound having a relatively high work function. As an example, the second work function adjustment pattern WF2 may be formed of or include titanium nitride (TiN), titanium oxynitride (TiON), or tantalum nitride (TaN). In some embodiments, the second work function adjustment pattern WF2 may have a multilayer structure including a titanium oxynitride (TiON) layer and a tantalum nitride (TaN) layer. In the case where the second work function adjustment pattern WF2 includes titanium oxynitride (TiON), the content of oxygen (O) in the second work function adjustment pattern WF2 may be in the range of 30% to 60%.

[0042] The second portion P2 of the first and second gate structures GS1 and GS2 may include a first and second work function adjustment pattern WF1 and WF2 that are sequentially stacked.

[0043] The gate electrode GE in the first portion P1 may fill the space between the first semiconductor pattern NS1 and the space between the second semiconductor pattern NS2. Furthermore, the gate electrode GE in the second portion P2 may be disposed on the first work function adjustment pattern WF1 and the second work function adjustment pattern WF2. The gate electrode GE may have a lower resistance than the first work function adjustment pattern WF1 and the second work function adjustment pattern WF2. For example, the gate electrode GE may be formed of or include at least one of a low-resistance metal such as aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta).

[0044] A pair of gate spacers GSP may be provided on opposite side surfaces of each of the first gate structure GS1 and the second gate structure GS2. The gate spacers GSP may extend along the first gate structure GS1 and the second gate structure GS2 or extend in the second direction D2. The top surface of the gate spacer GSP may be higher than the top surface of the gate electrode GE. The first work function adjustment pattern WF1 and the second work function adjustment pattern WF2 (i.e., the second portion P2) on the channel pattern CH may extend along the inner sidewalls of the gate spacer GSP or extend in the third direction D3. The gate spacer GSP may include at least one of a silicon nitride carbon (SiCN) layer, a silicon oxynitride carbon (SiCON) layer, and a silicon nitride (SiN) layer, or may have a single-layer structure or a multi-layer structure.

[0045] The gate cap pattern CP may be disposed on the first gate structure GS1 and the second gate structure GS2. The gate cap pattern CP may extend along the first gate structure GS1 and the second gate structure GS2 or extend in the second direction D2. The top surface of the gate cap pattern CP may be coplanar with the top surface of the gate spacer GSP. The gate cap pattern CP may be formed of or include at least one of silicon oxynitride (SiON), silicon carbon nitride (SiCN), and silicon nitride (SiN).

[0046] The spacer pattern 110 can be arranged between the source / drain pattern SD and the first gate structure GS1 and between the source / drain pattern SD and the second gate structure GS2. The spacer pattern 110 can be arranged on the side surface of each of the first gate structure GS1 and the second gate structure GS2, and can be spaced apart from each other in the third direction D3. In other words, the spacer pattern 110 and the first semiconductor pattern NS1 and the spacer pattern 110 and the second semiconductor pattern NS2 can be stacked alternately and repeatedly in the third direction D3. Each spacer pattern 110 can be arranged between two adjacent ones of the first semiconductor pattern NS1 and between two adjacent ones of the second semiconductor pattern NS2, or can be arranged between the bottommost semiconductor pattern NS1 and NS2 of the semiconductor patterns NS1 and NS2 and the base active pattern 102. The source / drain pattern SD may contact the semiconductor patterns NS1 and NS2 and may be spaced apart from the first gate structure GS1 and the second gate structure GS2, with a spacer pattern 110 interposed between the source / drain pattern SD and the first gate structure GS1 and between the source / drain pattern SD and the second gate structure GS2. The spacer pattern 110 may electrically disconnect the first gate structure GS1 and the second gate structure GS2 from the source / drain pattern SD. The spacer pattern 110 may be formed of, or may include, silicon nitride (SiN).

[0047] A gate dielectric layer GI (or dielectric layer) may be interposed between the first semiconductor pattern NS1 and the first gate structure GS1, and between the second semiconductor pattern NS2 and the second gate structure GS2. Each gate dielectric layer GI may partially and conformally fill the space between the first semiconductor patterns NS1 or the space between the second semiconductor patterns NS2. The gate dielectric layer GI may be formed of or include at least one high-k dielectric material having a higher dielectric constant than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), lanthanum oxide (LAO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), lithium oxide (LiO), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO) and lead zinc niobate (PbZnNbO).

[0048] Here, the space between the gate dielectric layers GI disposed around adjacent first semiconductor patterns NS1 and the space between the gate dielectric layers GI disposed around adjacent second semiconductor patterns NS2 may be less than or equal to 10 nm. In other words, the space disposed between adjacent first semiconductor patterns NS1 and adjacent second semiconductor patterns NS2 and filled with the first and second work function adjustment patterns WF1 and WF2 and the gate electrode GE may have a thickness of less than or equal to 10 nm. In an embodiment, the space disposed between adjacent first semiconductor patterns NS1 and adjacent second semiconductor patterns NS2 may be in a range of 1 nm to 10 nm.

[0049] In the first transistor TR1 and the second transistor TR2, the threshold voltage of the first transistor TR1 may be smaller than the threshold voltage of the second transistor TR2. For example, the first work function adjustment pattern WF1 of the first transistor TR1 and the first work function adjustment pattern WF2 of the second transistor TR2 may be formed of or include different materials from each other.

[0050] The first work function adjustment pattern WF1 of the first transistor TR1 may include a metal compound having a relatively low work function. As an example, the first work function adjustment pattern WF1 of the first transistor TR1 may be a metal compound doped with or containing aluminum (Al). In an embodiment, the first work function adjustment pattern WF1 of the first transistor TR1 may be formed of or include titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or tantalum aluminum nitride (TaAlN). By varying the doping concentration of aluminum (Al) used as a dopant in the first work function adjustment pattern WF1 of the first transistor TR1, the work function of the first work function adjustment pattern WF1 of the first transistor TR1 may be adjusted.

[0051] Compared to the first work function adjustment pattern WF1 of the first transistor TR1, the first work function adjustment pattern WF1 of the second transistor TR2 may include a metal compound having a high work function. As an example, the first work function adjustment pattern WF1 of the second transistor TR2 may be formed of or include titanium nitride (TiN), titanium oxynitride (TiON), or tantalum nitride (TaN). The first work function adjustment pattern WF1 of the second transistor TR2 may be substantially free of impurities (e.g., aluminum (Al), etc.).

[0052] In an embodiment, the first transistor TR1 and the second transistor TR2 may be transistors of different conductivity types. For example, the first transistor TR1 may be an NMOSFET, and the second transistor TR2 may be a PMOSFET. Here, the first work function adjustment pattern WF1 of the first transistor TR1 may include a material having a low work function (e.g., titanium aluminum carbide (TiAlC)), and the first work function adjustment pattern WF1 of the second transistor TR2 may include a material having a high work function (e.g., titanium oxynitride (TiON) or a multilayer structure of titanium oxynitride (TiON) and tantalum nitride (TiN), etc.). However, the inventive concept is not limited to this example, and the first transistor TR1 and the second transistor TR2 may be transistors having different threshold voltages but the same conductivity type.

[0053] In some embodiments, an intermediate layer, such as an oxide layer or a nitride layer, may not be interposed between the sequentially stacked first and second work work adjustment patterns WF1 and WF2. If an intermediate layer containing an oxide or nitride is formed between the first and second work work adjustment patterns WF1 and WF2, the resistance between the first and second work work adjustment patterns WF1 and WF2 may increase. Furthermore, dopants (i.e., aluminum (Al)) in the first work work adjustment pattern WF1 may diffuse into the intermediate layer, or the dopants in the first work work adjustment pattern WF1 may be oxidized, resulting in an increase in the work function of the first work work adjustment pattern WF1. However, according to embodiments of the inventive concept, no intermediate layer may be formed between the first and second work work adjustment patterns WF1 and WF2, thereby improving the electrical characteristics of the semiconductor device. This subject matter will be described in more detail in conjunction with a method for manufacturing a semiconductor device.

[0054] The space between the first semiconductor patterns NS1 may be substantially the same as the space between the second semiconductor patterns NS2. The thickness of the first work function adjustment pattern WF1 in the first region RG1 may be substantially the same as the thickness of the first work function adjustment pattern WF1 in the second region RG2. In this case, by forming the first work function adjustment pattern WF1 of the first transistor TR1 and the first work function adjustment pattern WF1 of the second transistor TR2 using different materials, the first transistor TR1 and the second transistor TR2 may be formed to have different threshold voltages. In an embodiment, the first work function adjustment patterns WF1 disposed in the first region RG1 and the second region RG2, respectively, may have different work functions.

[0055] In some embodiments, the first work function adjustment pattern WF1 may be formed to have different thicknesses in the first and second regions RG1 and RG2 , respectively, which may result in a difference between the threshold voltages of the first and second transistors TR1 and TR2 . Figure 2A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 2B It is along Figure 2A The cross-sectional view taken along the line C-C' is Figure 2C It is along Figure 2A The cross-sectional view taken along the D-D' line. Figures 2A to 2CAs shown in , the thickness of the first work function adjustment pattern WF1′ in the first region RG1 may be thicker than the thickness of the first work function adjustment pattern WF1 in the second region RG2. Here, in the case where the thickness of the first work function adjustment pattern WF1′ in the first region RG1 is thick enough, the first work function adjustment pattern WF1′ may fill the space between the first semiconductor patterns NS1. Therefore, in the first region RG1, the second work function adjustment pattern WF2 and the gate electrode GE may not extend to the space between the first semiconductor patterns NS1, and may be formed to surround the channel pattern CH and the first work function adjustment pattern WF1′. The first work function adjustment pattern WF1 in the first region RG1 and the second region RG2 may include the same material. As described above, in the case where the first work function adjustment pattern WF1′ and the second work function adjustment pattern WF2 in the first region RG1 and the second region RG2 are formed to have different thicknesses, a difference may be able to occur between the threshold voltage of the first transistor TR1 and the threshold voltage of the second transistor TR2. The following description will refer to Figures 1A to 1C The embodiment shown in FIG.

[0056] The interlayer insulating layer 120 may be disposed on the entire top surface of the substrate 100. The interlayer insulating layer 120 may cover the device insulating layer ST, the first and second gate structures GS1 and GS2, and the source / drain pattern SD. The top surface of the interlayer insulating layer 120 may be substantially coplanar with the top surface of the gate capping pattern CP. The interlayer insulating layer 120 may be formed of or include silicon oxide (SiO) or silicon oxynitride (SiON).

[0057] Although not shown, a contact portion (not shown) penetrating the interlayer insulating layer 120 may be provided and connected to the source / drain pattern SD or the gate structures GS1 and GS2. The contact portion may be formed of or include at least one of metal materials such as tungsten (W), titanium (Ti), and tantalum (Ta).

[0058] Figures 3A to 11A is a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Figures 3B to 11B are respectively along Figures 3A to 11A A cross-sectional view taken along line AA'. Figures 3C to 11C are respectively along Figures 3A to 11A For ease of description, the cross-sectional view taken along the BB' line can be omitted. Figures 3A to 11A Some of the components in.

[0059] Reference Figures 3A to 3C , sacrificial layers 150 and semiconductor layers 152 may be alternately and repeatedly stacked on the substrate 100. Figure 3B and Figure 3C , the stacked semiconductor layer 152 is shown as including three layers stacked, but the inventive concept is not limited to this example. The sacrificial layer 150 and the semiconductor layer 152 can be formed by an epitaxial growth process using the substrate 100 as a seed layer. The sacrificial layer 150 and the semiconductor layer 152 can be conformally grown from the entire top surface of the substrate 100. Each of the sacrificial layer 150 and the semiconductor layer 152 can have a thickness in the third direction D3. The sacrificial layer 150 and the semiconductor layer 152 can be formed to have the same thickness as each other or to have different thicknesses from each other. The thickness of each sacrificial layer 150 can be about The thickness of each semiconductor layer 152 may be in the range of about 100 nm. The sacrificial layer 150 may include silicon germanium (SiGe) or germanium (Ge) having an etching selectivity with respect to the semiconductor layer 152, and the semiconductor layer 152 may include silicon (Si).

[0060] If necessary, the semiconductor layer 152 may be doped with impurities. For example, when the first transistor TR1 and the second transistor TR2 are formed as NMOSFETs, the impurities may be boron (B). When the first transistor TR1 and the second transistor TR2 are formed as PMOSFETs, the impurities may be phosphorus (P). If the first transistor TR1 and the second transistor TR2 are formed to have different conductivity types, the semiconductor layer 152 in the first region RG1 and the second region RG2 may be doped with different impurities.

[0061] A preliminary active pattern PAP and a base active pattern 102 may be formed on a substrate 100. Forming the preliminary active pattern PAP and the base active pattern 102 may include sequentially patterning the sacrificial layer 150, the semiconductor layer 152, and the upper portion of the substrate 100 to form trenches T defining the preliminary active pattern PAP and the base active pattern 102. The trenches T may have a linear shape extending in a first direction D1 and may be spaced apart from each other in a second direction D2. The preliminary active patterns PAP may be disposed on the base active pattern 102, respectively. The preliminary active pattern PAP may be formed to have a linear shape or a stripe shape extending in the first direction D1.

[0062] A device insulating layer ST may be formed to fill the trench T. The formation of the device insulating layer ST may include forming an insulating layer on the entire top surface of the substrate 100 and recessing the insulating layer to completely expose the preliminary active pattern PAP. Therefore, the top surface of the device insulating layer ST may be lower than the top surface of the base active pattern 102.

[0063] Reference Figures 4A to 4C, a sacrificial gate structure SGS may be formed to intersect the initial active pattern PAP. The sacrificial gate structure SGS may extend in the second direction D2 and intersect the base active pattern 102 and the device insulating layer ST. The sacrificial gate structure SGS may include a sacrificial gate pattern 162 and a gate mask pattern 164 sequentially stacked on the substrate 100. The formation of the sacrificial gate pattern 162 and the gate mask pattern 164 may include sequentially forming a sacrificial gate layer and a gate mask layer on the substrate 100 and sequentially patterning the sacrificial gate layer and the gate mask layer. The sacrificial gate layer may be formed of or include polysilicon. The gate mask layer may be formed of or include silicon nitride (SiN) or silicon oxynitride (SiON). The sacrificial gate structure SGS may have a linear shape extending in the second direction D2. The sacrificial gate structure SGS may cover side surfaces of the preliminary active pattern PAP facing away from each other in the second direction D2 and may cover a top surface of the preliminary active pattern PAP and a top surface of the device insulating layer ST.

[0064] The sacrificial gate structure SGS may further include gate spacers GSP. A pair of gate spacers GSP may be formed on opposite sides of each sacrificial gate structure SGS. The gate spacers GSP may be formed using silicon nitride carbon (SiCN), silicon oxynitride carbon (SiCON), or silicon nitride (SiN). Formation of the gate spacers GSP may include forming a spacer layer using a deposition process (e.g., a CVD or ALD process) and performing an anisotropic etching process on the spacer layer.

[0065] Reference Figures 5A to 5C The preliminary active pattern PAP may be patterned to form a channel pattern CH. The preliminary active pattern PAP may be patterned using the gate mask pattern 164 and the gate spacers GSP as an etching mask. Therefore, the base active pattern 102 may be partially exposed by the gate mask pattern 164 and the gate spacers GSP.

[0066] Specifically, the sacrificial layer 150 of the preliminary active pattern PAP may be patterned to form a sacrificial pattern 156. The semiconductor layer 152 of the preliminary active pattern PAP may be patterned to form a first semiconductor pattern NS1 and a second semiconductor pattern NS2. The first semiconductor pattern NS1 may constitute a channel pattern CH of the first region RG1, and the second semiconductor pattern NS2 may constitute a channel pattern CH of the second region RG2.

[0067] After the patterning process, the exposed portion of the sacrificial pattern 156 may be horizontally removed to form the recessed region 112. The formation of the recessed region 112 may include performing an etching process using an etching source having an etching selectivity with respect to the sacrificial pattern 156.

[0068] A spacer pattern 110 may be formed to fill the recessed region 112. The spacer patterns 110 may be vertically spaced apart from each other, with the first semiconductor pattern NS1 and the second semiconductor pattern NS2 interposed therebetween. Specifically, an insulating layer may be conformally formed on the entire top surface of the substrate 100. The insulating layer may fill the recessed region 112. Thereafter, the insulating layer may be etched so that the spacer pattern 110 remains only partially in the recessed region 112.

[0069] Source / drain patterns SD may be formed at both sides of each channel pattern CH. Specifically, a selective epitaxial process may be performed in which the first and second semiconductor patterns NS1 and NS2 and the base active pattern 102 are used as seed layers to form the source / drain patterns SD. The channel pattern CH and the source / drain patterns SD may be connected to each other.

[0070] In one embodiment, the source / drain pattern SD may be formed of the same semiconductor material as that of the channel pattern CH (e.g., silicon (Si)). During or after the selective epitaxial growth process, the source / drain pattern SD may be doped with n-type impurities. Alternatively, the source / drain pattern SD may be formed of silicon germanium (SiGe), which has a larger lattice constant than silicon (Si). In another embodiment, during or after the selective epitaxial growth process, p-type impurities may be doped into the source / drain pattern SD.

[0071] Reference Figures 6A to 6C , an interlayer insulating layer 120 may be formed on the entire top surface of the substrate 100. Thereafter, a process for planarizing the interlayer insulating layer 120 may be performed to expose the top surface of the sacrificial gate pattern 162. The planarization process may include an etch-back process and / or a chemical mechanical polishing (CMP) process. When planarizing the interlayer insulating layer 120, the gate mask pattern 164 may be removed together with the interlayer insulating layer 120. The interlayer insulating layer 120 may be formed using silicon oxide (SiO) or silicon oxynitride (SiON).

[0072] The sacrificial gate pattern 162 exposed by the planarization process may be selectively removed. Due to the removal of the sacrificial gate pattern 162, first and second trenches TC1 and TC2 may be formed in the first and second regions RG1 and RG2 of the substrate 100, respectively. The first and second trenches TC1 and TC2 may be empty regions defined by the gate spacers GSP. The first and second trenches TC1 and TC2 may expose the channel pattern CH. The first and second trenches TC1 and TC2 may expose the sacrificial pattern 156. When viewed in plan, the first and second trenches TC1 and TC2 may have a linear shape extending in the second direction D2 and may expose the top surface of the device insulating layer ST.

[0073] The exposed sacrificial pattern 156 can be selectively removed. When the sacrificial pattern 156 includes silicon germanium (SiGe) and the first and second semiconductor patterns NS1 and NS2 include silicon (Si), a selective etching process can be performed using an etching solution containing peracetic acid. Here, the source / drain pattern SD can be protected by the spacer pattern 110 and the interlayer insulating layer 120. Due to the selective removal of the sacrificial pattern 156, first and second spaces SP1 and SP2 (for example, the first and second spaces SP1 and SP2 can be referred to as empty spaces) can be formed in the first and second regions RG1 and RG2. The first space SP1 can be a space between vertically adjacent first semiconductor patterns NS1 and between vertically adjacent second semiconductor patterns NS2. The second space SP2 can be a space surrounded by a pair of gate spacers GSP and the uppermost first semiconductor pattern NS1 of the first semiconductor pattern NS1, or can be a space surrounded by the uppermost second semiconductor pattern NS2 of the pair of gate spacers GSP and the second semiconductor pattern NS2. The first and second spaces SP1 and SP2 may be connected to the first and second trenches TC1 and TC2 and may expose the first and second semiconductor patterns NS1 and NS2 .

[0074] Reference 7A to 7C, a gate dielectric layer GI may be formed on the first semiconductor pattern NS1 and the second semiconductor pattern NS2 exposed by the first trench TC1 and the second trench TC2. The gate dielectric layer GI may be formed to conformally cover the inner surfaces of the first trench TC1 and the second trench TC2. Each gate dielectric layer GI may partially fill the first space SP1 of the first trench TC1 and the second trench TC2. Each gate dielectric layer GI may partially fill the second space SP2 of the first trench TC1 and the second trench TC2. The gate dielectric layer GI may directly cover the spacer pattern 110 and the first semiconductor pattern NS1 and the second semiconductor pattern NS2. The gate dielectric layer GI may be formed using a high-k dielectric material having a higher dielectric constant than silicon oxide (SiO).

[0075] Although not shown, before forming the gate dielectric layer GI, an oxidation process using plasma may be performed on the first semiconductor pattern NS1 and the second semiconductor pattern NS2 exposed by the first trench TC1 and the second trench TC2. As a result of this process, an interface layer (not shown) may be grown from the exposed surfaces of the first semiconductor pattern NS1 and the second semiconductor pattern NS2. The formation of the interface layer (not shown) may include a thermal oxidation process and / or a chemical oxidation process. The oxidation process may be performed using a plasma of at least one of oxygen, ozone, and steam. The interface layer (not shown) may be formed of silicon oxide (SiO). The interface layer (not shown) may directly surround the exposed surfaces of the first semiconductor pattern NS1 and the second semiconductor pattern NS2.

[0076] Reference Figures 8A to 8C A first work function adjustment layer WL1 may be conformally deposited in the first trench TC1 and the second trench TC2. The first work function adjustment layer WL1 may be formed by a deposition process (e.g., ALD, CVD, or PVD process). The first work function adjustment layer WL1 may conformally cover the gate dielectric layer GI. The first work function adjustment layer WL1 may be formed to surround the first semiconductor pattern NS1 and the second semiconductor pattern NS2. The first work function adjustment layer WL1 may include a material having a relatively low work function. For example, the first work function adjustment layer WL1 may include titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or tantalum aluminum nitride (TaAlN).

[0077] In some embodiments, after forming the first work function adjustment layer WL1, the first work function adjustment layer WL1 may be additionally deposited in the first region RG1. Figures 9A to 9CAs shown in , a mask pattern MP may be formed in the second region RG2. The mask pattern MP may be formed to expose the first region RG1. A deposition process may be additionally performed on the first work function adjustment layer WL1′ exposed in the first region RG1. Therefore, the first work function adjustment layer WL1′ in the first region RG1 may be formed to be thicker than the first work function adjustment layer WL1 in the second region RG2. In some embodiments, the first work function adjustment layer WL1′ may be formed to have a thick thickness in the first region RG1 and the second region RG2, a mask pattern MP may be formed in the first region RG1, and an upper portion of the first work function adjustment layer WL1 in the second region RG2 may be removed. In this case, a reference pattern may be manufactured. Figures 2A to 2C A semiconductor device is described.

[0078] In some embodiments, the first work function adjustment layer WL1 in the first region RG1 and the second region RG2 may be formed to include different materials. For example, after forming the first work function adjustment layer WL1, a mask pattern MP may be formed in the second region RG2. The first work function adjustment layer WL1 exposed in the first region RG1 may be removed. Thereafter, a deposition process may be performed to form a layer in the first region RG1 that is formed of a material different from that of the first work function adjustment layer WL1 in the second region RG2. In this case, the first transistor TR1 and the second transistor TR2 formed in the first region RG1 and the second region RG2, respectively, may be of different types.

[0079] The following description will refer to Figures 8A to 8C The embodiment shown in FIG.

[0080] Reference 10A to 10C A second work function adjustment layer WL2 may be formed in the first trench TC1 and the second trench TC2. The second work function adjustment layer WL2 may be conformally deposited in the first trench TC1 and the second trench TC2. The second work function adjustment layer WL2 may be formed by a deposition process (e.g., ALD, CVD, or PVD). The second work function adjustment layer WL2 may conformally cover the first work function adjustment layer WL1. The second work function adjustment layer WL2 may include a material having a relatively high work function. For example, the second work function adjustment layer WL2 may include titanium nitride (TiN), titanium oxynitride (TiON), or tantalum nitride (TaN).

[0081] The first process S1 for forming the first work function adjustment layer WL1 and the second process S2 for forming the second work function adjustment layer WL2 can be performed in situ. In other words, the first process S1 and the second process S2 can be performed continuously in the same process chamber. Here, the expression "continuously performed" can mean that the multiple processes can be performed under the same process conditions (e.g., process time, process temperature, and gas atmosphere in the process chamber). In addition, the first process S1 and the second process S2 can be performed in a vacuum atmosphere (e.g., a vacuum environment) or an oxygen-free atmosphere (e.g., an oxygen-free environment).

[0082] Typically, in order to improve efficiency in a large-scale production system, the first process S1 for forming the first work function adjustment layer WL1 and the second process S2 for forming the second work function adjustment layer WL2 may be performed separately in different chambers. For example, the first process S1 for forming the first work function adjustment layer WL1 may be performed in the first chamber, and the second process S2 for forming the second work function adjustment layer WL2 may be performed in the second chamber. In this case, when the semiconductor device under manufacture is transported from the first chamber to the second chamber, the first work function adjustment layer WL1 may be exposed to oxygen. In this case, as shown in FIG. Figures 11A to 11C As shown in FIG, the exposed surface of the first work function adjustment layer WL1 is oxidized, forming an oxide layer OL on the first work function adjustment layer WL1. If the first work function adjustment layer WL1 includes a material highly reactive toward oxygen (e.g., aluminum (Al)), the formation of the oxide layer OL is accelerated. Consequently, the oxide layer OL forms on a portion of the first work function adjustment layer WL1. In this case, the thickness of the first work function adjustment layer WL1 may be reduced, or the material constituting the first work function adjustment layer WL1 may diffuse into the oxide layer OL, causing the work function of the first work function adjustment layer WL1 to increase. This can make it difficult to control the threshold voltages of transistors TR1 and TR2.

[0083] Furthermore, if an additional layer, such as an oxide layer OL, is formed on the first work function adjustment layer WL1, the first and second work function adjustment layers WL1 and WL2, which are formed sequentially, will not contact each other. In other words, the oxide layer OL will be interposed between the first and second work function adjustment layers WL1 and WL2. In this case, the resistance between the first and second work function adjustment layers WL1 and WL2 will increase, and the electrical characteristics of the semiconductor device may deteriorate.

[0084] In embodiments, the first process S1 and the second process S2 may be performed in an in-situ manner. The chamber for such an in-situ manner may be in a vacuum atmosphere (e.g., a vacuum environment) or an oxygen-free atmosphere (e.g., an oxygen-free environment). Thus, exposure of the first work function adjustment layer WL1 to external oxygen may be limited and / or prevented, and thus, an additional layer, such as an oxide layer OL, may not be formed on the first work function adjustment layer WL1. Here, the content of oxygen (O) included in the first work function adjustment layer WL1 may be substantially zero, or may be in a range of 0% to 30%. The content of aluminum (Al) in the first work function adjustment layer WL1 before the formation of the second work function adjustment layer WL2 may be substantially equal to the content of aluminum (Al) in the first work function adjustment layer WL1 after the formation of the second work function adjustment layer WL2. The threshold voltages of the transistors TR1 and TR2 may be easily adjusted without losing the first work function adjusting layer WL1, and since the first and second work function adjusting layers WL1 and WL2 are in direct contact with each other, degradation of electrical characteristics of the semiconductor device may be limited and / or prevented.

[0085] In some embodiments, a first process S1 for forming the first work function adjustment layer WL1 can be performed in a first chamber, and a second process S2 for forming the second work function adjustment layer WL2 can be performed in a second chamber. First, an oxide layer OL can be formed on the first work function adjustment layer WL1. Thereafter, the semiconductor device under fabrication can be transported to the second chamber, and a process for removing the oxide layer OL can be performed in the second chamber before forming the second work function adjustment layer WL2. Thus, the second work function adjustment layer WL2 can be formed on the first work function adjustment layer WL1, so that the second work function adjustment layer WL2 is in direct contact with the first work function adjustment layer WL1.

[0086] Return to reference Figures 1A to 1C The gate dielectric layer GI, the first work function adjustment layer WL1, and the second work function adjustment layer WL2 may each be partially removed. Specifically, the portion of the gate dielectric layer GI disposed on the interlayer insulating layer 120, the portion of the first work function adjustment layer WL1 disposed on the interlayer insulating layer 120, and the portion of the second work function adjustment layer WL2 disposed on the interlayer insulating layer 120 may be removed. At this time, the upper portion of the gate dielectric layer GI disposed in the first and second trenches TC1 and TC2, the upper portion of the first work function adjustment layer WL1 disposed in the first and second trenches TC1 and TC2, and the upper portion of the second work function adjustment layer WL2 disposed in the first and second trenches TC1 and TC2 may be recessed. As a result of the recessing process, the first and second work function adjustment layers WL1 and WL2 may form first and second work function adjustment patterns WF1 and WF2, respectively.

[0087] A gate electrode GE may be formed in the first trench TC1 and the second trench TC2. The gate electrode GE may be formed on the second work function adjustment pattern WF2. The gate electrode GE may fill the remaining portions of the first trench TC1 and the second trench TC2. The gate electrode GE may be formed using a low-resistance metal. For example, a conductive material may be formed to fill the first trench TC1 and the second trench TC2 and cover the interlayer insulating layer 120, and then a planarization process may be performed to expose the top surface of the interlayer insulating layer 120.

[0088] The upper portion of the gate electrode GE may be recessed to form a recessed region between the gate spacers GSP. A gate capping pattern CP may be formed in the recessed region. Formation of the gate capping pattern CP may include forming the gate capping pattern on the interlayer insulating layer 120 to fill the recessed region, and then planarizing the gate capping pattern to expose the interlayer insulating layer 120. The gate capping pattern CP may be formed using silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

[0089] The gate dielectric layer GI, the first and second work function adjustment patterns WF1 and WF2, the gate electrode GE, the gate cap pattern CP, and the gate spacers GSP may constitute gate structures GS1 and GS2. The first and second semiconductor patterns NS1 and NS2 may constitute a channel pattern CH. The source / drain patterns SD may be spaced apart from each other in a first direction D1 with the channel pattern CH interposed therebetween, and each of the source / drain patterns SD may be in contact with the channel pattern CH. The channel pattern CH and the source / drain pattern SD may constitute an active structure AS disposed on the base active pattern 102. The active structure AS and the gate structures GS1 and GS2 may constitute a gate-all-around field-effect transistor.

[0090] Although not shown, an upper insulating layer (not shown) may be formed on the interlayer insulating layer 120. Contacts may be formed through the upper insulating layer and the interlayer insulating layer 120, and the contacts may be electrically connected to the source / drain patterns SD or the gate structures GS1 and GS2. Interconnections (not shown) may be formed on the upper insulating layer and may be coupled to the contacts. The contacts and the interconnections may be formed of a conductive material.

[0091] A semiconductor device can be manufactured by the above-described method.

[0092] In a method for manufacturing a semiconductor device according to an embodiment of the inventive concept, exposure of the first work function adjustment layer to external oxygen can be limited and / or prevented. Therefore, additional layers, such as an oxide layer, may not be formed on the first work function adjustment layer. Therefore, the threshold voltage of the transistor can be easily adjusted without damaging the first work function adjustment layer. Furthermore, since the first and second work function adjustment layers are formed in direct contact with each other, degradation of the electrical characteristics of the semiconductor device can be limited and / or prevented.

[0093] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: substrate; a channel pattern stacked on the substrate, the channel pattern comprising a semiconductor pattern; as well as A gate structure is located on the substrate, and the gate structure extends to intersect with the channel pattern. The gate structure includes a dielectric layer, a first work function adjustment pattern, and a second work function adjustment pattern, wherein the dielectric layer surrounds the semiconductor pattern, the first work function adjustment pattern surrounds the dielectric layer, and the second work function adjustment pattern surrounds the first work function adjustment pattern, the first work function adjustment pattern is formed of a material containing aluminum, and each corresponding first work function adjustment pattern among the first work function adjustment patterns directly contacts a corresponding second work function adjustment pattern among the second work function adjustment patterns that surrounds the corresponding first work function adjustment pattern among the first work function adjustment patterns, so that each of the plurality of discrete second work function adjustment patterns among the second work function adjustment patterns surrounds the top surface, side surface, and bottom surface of a corresponding discrete first work function adjustment pattern among the plurality of discrete first work function adjustment patterns among the first work function adjustment patterns. The semiconductor device does not include an oxide layer or a nitride layer between the first work function adjustment pattern and the second work function adjustment pattern adjacent to each other.

2. The semiconductor device according to claim 1, wherein The first work function adjustment pattern has a lower work function than that of the second work function adjustment pattern.

3. The semiconductor device according to claim 1, wherein The first work function adjustment pattern includes titanium aluminum carbide, and The second work function adjustment pattern includes titanium nitride.

4. The semiconductor device according to claim 3, wherein The content of oxygen in the first work function adjustment pattern is in the range of 0% to 30%. The semiconductor device according to claim 1 , wherein The space between the semiconductor patterns is in the range of 1 nm to 15 nm.

6. The semiconductor device according to claim 1, further comprising: Source / drain patterns are located on the substrate, the source / drain patterns are spaced apart from each other and the gate structure is located between the source / drain patterns, The channel pattern and the source / drain pattern are connected to each other.

7. The semiconductor device according to claim 6, further comprising: spacer patterns on the substrate, the spacer patterns being located below each of the semiconductor patterns and spaced apart from each other with the gate structure located between the spacer patterns, Each of the spacer patterns is interposed between each of the source / drain patterns and the gate structure.

8. The semiconductor device according to claim 1, wherein The semiconductor patterns of the channel pattern are stacked on each other in a vertical direction over the substrate and are spaced apart from each other, The corresponding first work function adjustment pattern in the first work function adjustment patterns and the corresponding second work function adjustment pattern in the second work function adjustment patterns surround the same dielectric layer in the dielectric layer and the same semiconductor pattern in the semiconductor pattern, and Both the corresponding first work function adjustment pattern of the first work function adjustment patterns and the corresponding second work function adjustment pattern of the second work function adjustment patterns extend between two adjacent semiconductor patterns stacked on each other in a vertical direction among the semiconductor patterns of the channel pattern.

9. The semiconductor device according to claim 1, wherein The semiconductor patterns of the channel pattern are stacked on each other in a vertical direction over the substrate and are spaced apart from each other, The gate structure includes a conductive layer including a conductive material different from a material of the first work function adjustment pattern and a material of the second work function adjustment pattern, and A portion of the conductive layer fills a space between two adjacent semiconductor patterns stacked on each other in a vertical direction among the semiconductor patterns of the channel pattern.

10. A semiconductor device, comprising: substrate; a first active structure and a second active structure located on the substrate and spaced apart from each other, each of the first active structure and the second active structure including a semiconductor pattern stacked on the substrate; a first gate structure intersecting the first active structure, the first gate structure comprising a first dielectric layer surrounding the semiconductor pattern of the first active structure, a first work function adjustment pattern surrounding the first dielectric layer, and a second work function adjustment pattern surrounding the first work function adjustment pattern, the first work function adjustment pattern being formed of a material including aluminum, each of a plurality of discrete second work function adjustment patterns among the second work function adjustment patterns surrounding a corresponding discrete first work function adjustment pattern among the plurality of discrete first work function adjustment patterns among the first work function adjustment patterns by surrounding the top surface, the side surface, and the bottom surface of the corresponding discrete first work function adjustment pattern; as well as a second gate structure intersecting the second active structure, the second gate structure comprising a second dielectric layer surrounding the semiconductor pattern of the second active structure and a third work function adjustment pattern surrounding the second dielectric layer; The oxygen content in the first work function adjustment pattern is in the range of 0% to 30%, and The first work function adjustment pattern is in direct contact with the second work function adjustment pattern, wherein The work function of the first work function adjustment pattern is lower than the work function of the second work function adjustment pattern. The semiconductor device according to claim 10 , wherein: The first work function adjustment pattern includes titanium aluminum carbide, and The second work function adjustment pattern includes titanium nitride.

12. The semiconductor device according to claim 10, wherein The third work function adjustment pattern includes titanium oxynitride or a multi-layer structure including titanium oxynitride and titanium nitride.

13. The semiconductor device according to claim 12, wherein The content of oxygen in the third work function adjustment pattern is in the range of 30% to 60%.

14. The semiconductor device according to claim 10, wherein The space between the semiconductor patterns of the first active structure is in the range of 1 nm to 10 nm, and The space between the semiconductor patterns of the second active structure is in the range of 1 nm to 10 nm.

15. The semiconductor device according to claim 10, wherein The first active structure and the first gate structure constitute a first n-type transistor, and The second active structure and the second gate structure constitute a p-type second transistor.

16. The semiconductor device according to claim 10, further comprising: Source / drain patterns are located on the substrate, the source / drain patterns are spaced apart from each other, and the first gate structure or the second gate structure is located between the source / drain patterns. Each of the semiconductor patterns of the first active structure and the source / drain patterns are connected to each other, and each of the semiconductor patterns of the second active structure and the source / drain patterns are connected to each other.

17. A method for manufacturing a semiconductor device, the method comprising the steps of: forming an active pattern on a substrate, the active pattern comprising sacrificial patterns and semiconductor patterns that are alternately and repeatedly stacked; forming a sacrificial gate pattern to intersect the active pattern; forming gate spacers at both sides of the sacrificial gate pattern; removing each of the sacrificial patterns and removing the sacrificial gate patterns between the gate spacers to form an empty space; as well as A gate structure is formed in the empty space, The gate structure forming step includes sequentially depositing a dielectric layer, a first work function adjustment pattern, and a second work function adjustment pattern on the peripheral surface of the semiconductor pattern exposed in the empty space, and The first work function adjustment pattern is formed of a material including aluminum, the first work function adjustment pattern surrounds the dielectric layer, and the second work function adjustment pattern surrounds the first work function adjustment pattern. The first work function adjustment pattern is in contact with the second work function adjustment pattern.

18. The method according to claim 17, wherein Deposition of the first work function adjustment pattern and the second work function adjustment pattern is performed in an in-situ manner.

19. The method according to claim 18, wherein The in-situ deposition of the first work function adjustment pattern and the second work function adjustment pattern is performed in a vacuum atmosphere.

20. The method according to claim 17, further comprising: Before stacking the second work function adjustment pattern, the oxide layer formed on the first work function adjustment pattern is removed.

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