Phase change memory

Abstract

The present disclosure relates to a method for manufacturing a phase-change memory and a phase-change memory device. The method includes forming a first insulating layer in a cavity, the cavity being positioned vertically aligned with a phase-change material strip, and anisotropically etching a portion of the first insulating layer located at the bottom of the cavity; and a phase-change memory device including the first insulating layer, the first insulating layer being positioned adjacent to a sidewall of the cavity positioned vertically aligned with the phase-change material strip.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices and, more particularly, to phase change memory. Background Art

[0002] Memory is generally arranged in an array, comprising word lines and bit lines. A memory cell containing binary information is located at each intersection of a word line and a bit line.

[0003] In phase-change memory, each memory cell includes a strip of phase-change material with its lower portion in contact with a resistive element. Phase-change materials are materials that can transition from a crystalline phase to an amorphous phase, and vice versa. This transition is caused by a temperature increase in the underlying resistive element through which current is conducted. The difference in resistance between the material's amorphous and crystalline phases is used to define two memory states, 0 and 1.

[0004] In the example of a phase-change memory, the memory cells are controlled, for example, by select transistors that conduct or not conduct the current used to heat the resistive element. Memory cells belonging to the same bit line are interconnected by a conductor covering the phase-change material, and memory cells belonging to the same word line are interconnected by a terminal of a transistor common to all transistors of the same word line.

[0005] For example, binary information of a memory cell of a phase change memory is accessed or read by measuring the resistance between a bit line and a word line of the memory cell. Summary of the Invention

[0006] Various embodiments disclosed herein overcome the shortcomings of known phase change memories.

[0007] An embodiment provides a method of manufacturing a phase change memory, the method comprising: forming a first insulating layer in a cavity, the cavity being positioned vertically aligned with a phase change material strip; and anisotropically etching a portion of the first insulating layer at a bottom of the cavity.

[0008] Embodiments provide a phase change memory device comprising a first insulating layer abutting sidewalls of a cavity positioned in vertical alignment with a strip of phase change material.

[0009] According to an embodiment, each strip of phase change material is covered by a conductive strip.

[0010] According to an embodiment, the cavity is formed in the second insulating layer and reaches the upper surface of the conductive strip.

[0011] According to an embodiment, the method includes the following steps: forming a selection transistor inside and on top of a silicon layer; forming a first via and a second via for contacting the transistor through a third insulating layer; vertically forming a resistive element in line with the first via; forming phase change material strips; forming conductive strips on these phase change material strips; forming a second insulating layer; and forming the cavity in the second insulating layer.

[0012] According to an embodiment, at least one cavity comprises a secondary cavity, at least a portion of one wall of the secondary cavity being made of a phase change material.

[0013] According to an embodiment, a portion of one wall of at least one secondary cavity is formed by a resistive element.

[0014] According to an embodiment, the at least one secondary cavity is filled by the first insulating layer.

[0015] According to an embodiment, the cavity is filled with a conductive material to form a contact.

[0016] According to an embodiment, at least some of the contacts are conductive vias.

[0017] According to an embodiment, at least some of the contacts are conductive strips.

[0018] According to an embodiment, the thickness of the first insulating layer is greater than the thickness of the conductive tape.

[0019] According to an embodiment, the thickness of the first insulating layer is in a range from about 2 nm to about 5 nm.

[0020] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A Including along Figure 1B A cross-sectional view of plane AA, and Figure 1B Including along Figure 1A BB, thereby illustrating the results of the exemplary steps of the method for manufacturing a phase change memory.

[0022] Figure 2A Including along Figure 2B A cross-sectional view of plane AA, and Figure 2B Including along Figure 2A BB, thereby illustrating the result of another step of the embodiment of the phase change memory manufacturing method.

[0023] Figure 3A Including along Figure 3B A cross-sectional view of plane AA, and Figure 3B Including along Figure 3ABB, thereby illustrating the result of another step of the embodiment of the phase change memory manufacturing method.

[0024] Figure 4A Including along Figure 4B A cross-sectional view of plane AA, and Figure 4B Including along Figure 4A BB, thereby illustrating the result of another step of the embodiment of the phase change memory manufacturing method.

[0025] Figure 5A Including along Figure 5B A cross-sectional view of plane AA, and Figure 5B Including along Figure 5A BB, thereby illustrating the result of another step of the embodiment of the phase change memory manufacturing method. DETAILED DESCRIPTION

[0026] In different drawings, the same elements have been designated with the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be designated with the same reference numerals and may have the same structure, dimensions and material properties.

[0027] For the sake of clarity, those steps and elements useful for understanding the described embodiments have been shown and described in detail. In particular, other electronic components contained in the memory have not been described in detail.

[0028] Throughout this disclosure, the term “connected” is used to designate a direct electrical connection between circuit elements with no intervening elements other than conductors, while the term “coupled” is used to designate an electrical connection between circuit elements that may be direct or via one or more other elements.

[0029] In the following description, unless otherwise stated, when reference is made to terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or relative positions (such as terms "above", "below", "upper", "lower", etc.), or to terms defining directions (such as terms "horizontal", "vertical", etc.), reference is made to the orientation of the accompanying drawings.

[0030] The terms "about," "approximately," "substantially," and "approximately" are used herein to designate a tolerance of plus or minus 10% or plus or minus 5% or the value in question.

[0031] Figure 1A 、 1B , 2A, 2B, 3A, 3B, 4A, 4B, 5A and 5B show results of consecutive steps of an embodiment of a phase change memory manufacturing method.

[0032] Figure 1A Including along Figure 1B A cross-sectional view of plane AA, and Figure 1B Including along Figure 1A The cross-sectional view of plane BB of FIG. 1 illustrates the result of the embodiment steps of the phase change memory manufacturing method. More specifically, Figure 1A is a cross-sectional view in the direction of the bit line, and Figure 1B is a cross-sectional view in the direction of the word line. Figure 1A and 1B Two memory cells 2 are shown in each case.

[0033] The memory device includes a layer 14. For example, the layer 14 is a substrate made of a semiconductor material such as silicon. The layer 14 is, for example, part of a solid substrate. The layer 14 can also be a silicon layer covering an insulating layer in a so-called SOI (Silicon-On-Insulator) structure.

[0034] Layer 14 is covered by an insulating layer 15. Select transistor 16 is formed inside and on top of layer 14. Figure 1A The select transistor 16 is shown with its gate located in layer 15. The transistors 16 of the different bit lines are connected by insulating trenches 18 extending through layer 14 (in the Figure 1B ) are separated from each other.

[0035] Contacts (or vias) 20 and 22 traverse insulating layer 15 to contact and electrically couple to the source and drain regions of select transistor 16 .

[0036] Layer 15 is covered by an insulating layer 24, which can include a variety of insulator types. Resistive elements 26 extend in layer 24 between contacts 20 and strips or layers 28 of phase change material. Each strip 28 is covered by a strip or layer 30 of conductive material having a horizontal dimension substantially equal to that of strip 28. Resistive elements 26, strips 28, and strips 30 of the same bit line are, for example, etched together.

[0037] In this example, the resistive element has an L-shaped profile. More specifically, Figure 1A and 1B In the embodiment shown, the resistor element 26 is shown in cross-sectional view ( Figure 1A In other words, in one embodiment, each resistor element 26 includes a first direction (eg, Figure 1A and a first portion extending in a second direction transverse to the first direction (e.g., Figure 1B A second portion extending in the vertical direction (in the vertical direction).

[0038] Each bit line includes a strip 28 that is common to all bit lines and contacts the resistive elements 26 of all bit lines. Similarly, each bit line includes a strip 30 of conductive material covering strip 28. Strips 28 and 30 of different bit lines are laterally insulated from each other by insulator regions 31.

[0039] For example, the contact 22 contacts a source or drain region shared by two adjacent transistors 16 of the same bit line. The contacts 22 of the same word line are interconnected, for example, by a conductive strip.

[0040] Thus, to store a value in a memory cell, a voltage is applied between layer 30 of the bit line associated with the memory cell and contact 20 of the word line while turning on select transistor 16 located between contact 22 of the memory cell and contact 20 of the word line.

[0041] Figure 2A Including along Figure 2B A cross-sectional view of plane AA, and Figure 2B Including along Figure 2A BB, thereby illustrating the result of another step of the embodiment of the phase change memory manufacturing method.

[0042] During this step, a layer 40 is formed on the upper surface of the insulating layer 31 and on the upper surface of the strip of conductive material 30. The layer 40 is an insulating layer, for example made of silicon oxide or silicon nitride.

[0043] A cavity or opening 42 is formed in insulating layer 40. Thus, cavity 42 is formed after forming phase change material strip 28. The cavity is, for example, a cylindrical cavity. The cavity will enable conductive contacts to be made to the bit lines, such as by forming conductive vias. The cavity extends from the upper surface of layer 40 to the level of the upper surface of strip 30. Each bit line will include multiple contacts. Figure 2A and 2B Each view of FIG. 4 shows two cavities 42 , which will each enable the formation of a conductive via. Thus, the two terminals of the phase change memory cell will be the contact 20 and the contact to be formed in the cavity 42 .

[0044] Cavity 42 is positioned in vertical alignment with strip 30. Cavity 42 is positioned opposite strip 30, but not opposite insulating layer 31. However, the cavity may shift, for example, when the etch mask is not properly aligned or formed.

[0045] In one embodiment, the etch is a selective etch of the material of insulating layer 40 over the material of strips 30. For example, the etch etches the material of layer 40 at least five times faster than the material of strips 31.

[0046] The duration of etching the cavities 42 is chosen to ensure that all cavities reach the strips 30 , ie that the strips 30 form the bottom of the cavities 42 .

[0047] When the cavity is offset, the risk is that the etching will continue long enough to reach layer 31 and possibly layer 24 .

[0048] exist Figure 2B In the example of FIG, cavity 42 on the left side of the drawing is offset relative to strip 30 and therefore secondary cavities or openings 44 are formed in layers 31 and 24. Thus, cavity 42 includes secondary cavities 44.

[0049] More generally, there may be a plurality of offset cavities 42, and therefore a plurality of secondary cavities 44. For example, all cavities may be offset due to an offset of the etch mask.

[0050] During etching, the strips 30 and the resistive element 28 are thus exposed. At least a portion of the walls of the secondary cavity 44 are formed by the side walls of the strips 30 and 28 and by the side walls of the resistive element 26.

[0051] The contact can be formed by directly filling the cavity with conductive material. However, the secondary cavity 44 will then also be filled with conductive material. There may then be a direct electrical connection between the strip 30 and one of the resistive elements, i.e., a connection via the conductive material, rather than via the phase-change material strip 28. Such a connection would interfere with the storage of data in the corresponding memory cell. However, in the case where the secondary cavity 44 does not reach the resistive element 26, it may reach the phase-change material strip 28. The connection may then heat the phase-change material during the data storage step, which may modify the state of the strip 28 and, in particular, its resistance at the level of the memory cell. This resistance difference may cause interference with the reading of the stored data.

[0052] Furthermore, it may not be possible to determine whether a cavity 44 exists in the memory before the contact is made.

[0053] exist Figure 2B In the example shown, the horizontal dimension of the cavity, and therefore the contact, is substantially equal to the horizontal dimension of the strip 30. It may be possible to choose to form smaller contacts (e.g., conductive vias) to allow for greater margin for misalignment. However, reducing the contact size may not be possible or may result in manufacturing problems, such as increased manufacturing costs.

[0054] As a variant, cavity 42 can have the shape of a trench to allow the formation of a conductive strip. For example, a conductive strip will make it possible to connect all the memory cells of a word line or bit line together. In the case of a cavity having a trench shape or other shape, the steps described below are the same.

[0055] As a variation, the cavities may have different shapes. For example, at least some of cavities 42 may have a shape that allows for the formation of conductive vias. Further, at least some of cavities 42 may have a shape that allows for the formation of conductive strips. At least some other cavities may have other shapes.

[0056] Figure 3A Including along Figure 3B A cross-sectional view of plane AA, and Figure 3B Including along Figure 3A BB, thereby illustrating the result of another step of an embodiment of the method for manufacturing a phase change memory.

[0057] During this step, an insulating layer 50 is formed on the Figure 2B Layer 50 is deposited or formed, for example, conformally on the structure, i.e., it covers all surfaces accessible from the top surface of the structure. In particular, layer 50 extends over the top surface of layer 40, over the walls and bottom of cavity 42, and over the walls and bottom of secondary cavity 44. Thus, layer 50 extends over the exposed portions of strips 30 and 28, as well as over the exposed portions of resistive element 26.

[0058] It is possible that the layer 50 may completely fill the secondary cavity 44 .

[0059] The layer 50 has a thickness in the range of about 2 nm to about 5 nm, for example. Figure 3B In the plan view shown in , the secondary cavity 44 may completely fill the cavity having a horizontal dimension in the range of about 4 nm to about 10 nm.

[0060] In one embodiment, the thickness of layer 50 is greater than the thickness of tape 30 .

[0061] Figure 4A Including along Figure 4B A cross-sectional view of plane AA, and Figure 4B Including along Figure 4A BB, thereby illustrating the result of another step of an embodiment of the method for manufacturing a phase change memory.

[0062] During this step, an etch is performed, for example selective to the material of layer 50 above the material of strips 30 .

[0063] For example, the method etches the material of layer 50 at least five times faster than it etches the material of layer 30 .

[0064] In one embodiment, the etching is anisotropic, i.e., an etching process that etches in the vertical direction. Thus, the horizontal portion of layer 50 located at the bottom of cavities 42 and 44 is etched. In addition, the horizontal portion of layer 50 located on the upper surface of layer 30 is etched. Thus, after etching, layer 50 is present on the sidewalls of cavities 42 and 44.

[0065] Thus, the portion of the strip 30 forming the bottom of the cavity is exposed. It will thus be possible to make an electrical connection with the upper surface of the strip 30.

[0066] Vertical portions of layer 50 (i.e., portion 60 located on the wall of cavity 42 and portion 62 located on the wall of cavity 44) are not etched. In particular, portion 62 located on the sidewalls of strips 30 and 28 and on the sidewalls of the resistive element are not etched. Thus, the sidewalls of strips 30 and 28 and the sidewalls of resistive element 26 are not exposed.

[0067] The etch may remove the upper portion of horizontal portion 62 that covers the sidewalls of cavity 44. For example, a portion of the sidewall of strip 30 may be exposed. In one embodiment, the thickness of layer 50 is greater than the thickness of strip 30. Therefore, when the etch removes a thickness of layer 50 material substantially equal to the thickness of layer 30, portion 62 is not etched along the entire height of strip 30. Therefore, there is no risk of etching that exposes a portion of the sidewalls of strip 28 and / or conductive element 26.

[0068] Similarly, if cavity 44 is completely filled with insulating layer 50 , the etch may remove the upper portion of insulating layer 50 located in cavity 44 , but not enough to reach strap 28 .

[0069] Figure 5A Including along Figure 5B A cross-sectional view of plane AA, and Figure 5B Including along Figure 5A BB, thereby illustrating the result of another step of the embodiment of the phase change memory manufacturing method.

[0070] During this step, cavity 42, and possibly cavity 44 (if not already filled with insulating layer 50), is filled with a conductive material (e.g., copper) to form contact 70. In the example shown, contact 70 is a conductive via, but could also be a conductive strip or other conductive element. Thus, there is an electrical connection between contact 70 and ribbon 30. However, there is no electrical contact between contact 70 and ribbon 28 or resistive element 26.

[0071] As a variant, the horizontal dimension of the contacts 70 could be greater than the horizontal dimension of the strips 30. It is thus possible for the cavities 44 to be formed on the side walls of both strips 28 and 30. The aforementioned method steps apply in the same way.

[0072] An advantage of the aforementioned embodiments is that they enable phase change memories to be obtained that include contacts that do not form a short circuit and are not directly electrically connected to the phase change material 28 or the resistive element 26 .

[0073] Another advantage of the described embodiments is that they enable short-circuit-free contacts 70 to be obtained even when the contacts are deflected.

[0074] Another advantage of the described embodiments is that they can have lower restrictions on the size of the contacts 70. Indeed, the described embodiments can include contacts 70 having horizontal dimensions that are larger than the dimensions of the strips 28 of phase change material.

[0075] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0076] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the disclosure.Accordingly, the foregoing description is by way of example only and is not intended to be limiting.

[0077] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing a phase change memory, comprising: forming a transistor on a substrate; forming a first insulating layer on the transistor; forming a conductive via extending through the first insulating layer; forming a second insulating layer on the first insulating layer; forming a resistive element on the conductive via, the resistive element extending through the second insulating layer; forming a phase change material layer on the resistor element; forming a conductive layer on the phase change material layer; forming a third insulating layer on the conductive layer; forming a cavity in the third insulating layer, wherein the cavity vertically covers the phase change material layer; as well as forming a fourth insulating layer on the sidewalls and bottom surface of the cavity, The forming of the cavity comprises: forming a secondary cavity having a sidewall, wherein a portion of the sidewall of the secondary cavity is formed by the phase change material layer, and A portion of the side wall of the secondary cavity is formed by the resistive element.

2. The method according to claim 1, wherein Forming the fourth insulating layer includes forming the fourth insulating layer on the sidewalls of the cavity and the base of the cavity.

3. The method according to claim 2, further comprising: A portion of the fourth insulating layer located on the substrate in the cavity is removed.

4. The method according to claim 1, wherein Forming the cavity includes exposing a surface of the conductive layer by removing a portion of the third insulating layer.

5. The method according to claim 4, wherein Forming the cavity includes exposing a surface of the first insulating layer by removing a portion of the second insulating layer.

6. The method according to claim 1, wherein Forming the fourth insulating layer includes forming the fourth insulating layer on the sidewall of the secondary cavity.

7. The method according to claim 1, further comprising: A conductive contact is formed in the cavity.

8. The method according to claim 7, wherein: The conductive contact is a conductive via.

9. The method according to claim 7, wherein: The conductive contacts are conductive strips.

10. The method according to claim 1, wherein The thickness of the fourth insulating layer is greater than that of the conductive layer.

11. The method according to claim 1, wherein The thickness of the fourth insulating layer is in a range from 2 nanometers to 5 nanometers.

12. A phase change memory comprising: substrate; a transistor on the substrate; a first insulating layer on the transistor; a conductive via extending through the first insulating layer; a second insulating layer on the first insulating layer; a resistive element, on the conductive via, the resistive element extending through the second insulating layer; a phase change material layer on the resistive element; a conductive layer on the phase change material layer; a third insulating layer on the conductive layer; an opening in the third insulating layer, the opening vertically covering the phase change material layer; as well as a fourth insulating layer on the sidewalls and bottom surface of the opening, wherein the opening comprises: a first portion having a first base formed by the conductive layer and a first sidewall formed by the third insulating layer, and The second portion has a second base formed by the first insulating layer and a second sidewall formed by the resistor, the phase-change material layer and the conductive layer.

13. The phase change memory according to claim 12, wherein: The fourth insulating layer is on the first sidewall and the second sidewall.

14. The phase change memory according to claim 13, further comprising: A conductive contact is provided in the opening.

15. A device comprising: substrate; as well as a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells comprising: a transistor on the substrate; a first insulating layer on the transistor; a conductive via electrically coupled to the transistor and extending through the first insulating layer; a second insulating layer on the first insulating layer; Bit lines, including: a resistive element on the conductive via and extending through the second insulating layer; a strip of phase change material on the resistive element; and a conductive material strip on the phase change material strip; a third insulating layer on the conductive material strip; a conductive contact on the strip of conductive material and extending through the third insulating layer; and a fourth insulating layer, the conductive contact being separated from the third insulating layer by the fourth insulating layer, wherein a portion of the conductive contact is positioned to the side of the resistive element, the phase change material strip, and the conductive material strip, and wherein the portion of the conductive contact is separated from the resistive element, the phase change material strip, and the conductive material strip by the fourth insulating layer.

16. The apparatus according to claim 15, wherein The resistor element includes a first portion extending in a first direction and a second portion extending in a second direction transverse to the first direction.

17. A method for manufacturing a phase change memory, comprising: forming a first insulating layer (24) on the substrate; forming a resistive element (26) extending through the first insulating layer; forming a phase change material strip (28) on the first insulating layer, the phase change material strip being formed on the resistive element; forming a conductive material strip (30) on the phase change material strip; forming a second insulating layer (40) on the conductive material strip; forming a cavity in the second insulating layer (40) and the first insulating layer (24), wherein a portion of the cavity vertically overlies the phase change material strip; as well as A third insulating layer (50) is formed in the cavity and on the sidewalls of the phase change material strip, the sidewalls of the resistive element, and the sidewalls of the conductive material strip.

18. The method according to claim 17, further comprising: forming a transistor on the substrate (14); forming a fourth insulating layer (15) on the transistor; A conductive via (20) is formed extending through the fourth insulating layer, the first insulating layer (24) being on the fourth insulating layer (15).

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