Three-dimensional memory device

Abstract

A three-dimensional memory device is provided, comprising: a first memory cell array including first memory cells vertically stacked on a first memory cell array region on a top surface of a substrate; a second memory cell array including second memory cells vertically stacked on a second memory cell array region on a top surface; a plurality of first word lines connected to the first memory cells and including a subset of the plurality of first word lines and the remaining first word lines; a plurality of second word lines connected to the second memory cells and including a subset of the plurality of second word lines and the remaining second word lines; and a line decoder including a plurality of merged transmission transistors, each of the plurality of merged transmission transistors being commonly connected to a corresponding first word line in the subset of the plurality of first word lines and a corresponding second word line in the subset of the plurality of second word lines, wherein the line decoder is disposed in a region between the first memory cell array region and the second memory cell array region.

Description

[0001] Priority is claimed to Korean Patent Application No. 10-2019-0065472, filed on June 3, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to memory devices, and more specifically, to three-dimensional memory devices. Background Technology

[0003] Memory devices are used to store data and are generally classified as volatile memory devices that lose data when there is no power or non-volatile memory devices that retain data when there is no power. An example of a non-volatile memory device is a flash memory device commonly found in cellular phones, digital cameras, portable digital assistants (PDAs), mobile computing devices, fixed computing devices, and other devices.

[0004] Three-dimensional (3D) memory devices have been developed to meet the conflicting demands for higher memory capacity and miniaturization in non-volatile memory devices. A 3D memory device comprises multiple memory cells or arrays of memory cells vertically stacked on a substrate. However, as the number of stacked memory cells increases, the number of transistors required to control those cells increases dramatically. Consequently, the space required to arrange the transistors in a 3D memory device increases, thus increasing the overall size of the device. This makes it difficult to avoid exceeding the critical size limits of memory packages that include 3D memory devices. Summary of the Invention

[0005] The inventive concept provides a three-dimensional memory device with reduced size through the connection structure between transistors and memory cells, as well as the arrangement structure of transistors.

[0006] An embodiment of the inventive concept provides a memory device comprising: a substrate including a top surface; a first memory cell array including first memory cells vertically stacked on a first memory cell array region on the top surface of the substrate; a second memory cell array including second memory cells vertically stacked on a second memory cell array region on the top surface of the substrate; a plurality of first word lines connected to the first memory cells, the plurality of first word lines including a subset of the plurality of first word lines and the remaining first word lines; a plurality of second word lines connected to the second memory cells, the plurality of second word lines including a subset of the plurality of second word lines and the remaining second word lines; and a line decoder including a plurality of merging transmission transistors, each of the plurality of merging transmission transistors being commonly connected to a corresponding first word line in the subset of the plurality of first word lines and a corresponding second word line in the subset of the plurality of second word lines, and the line decoder being disposed in a line decoder region on the top surface of the substrate between the first memory cell array region and the second memory cell array region.

[0007] Embodiments of the inventive concept also provide a memory device, the memory device comprising: a substrate having a top surface; a first memory cell array including a first memory stack, the first memory stack including first memory cells vertically stacked on a first memory cell array region on the top surface of the substrate; a second memory cell array including a second memory stack, the second memory stack including second memory cells vertically stacked on a second memory cell array region on the top surface of the substrate; a plurality of first word lines connected to the first memory cells, the plurality of first word lines including a subset of the plurality of first word lines and the remaining first word lines; and a plurality of second word lines connected to the second memory cells. The plurality of second word lines includes a subset of the plurality of second word lines and the remaining second word lines; a plurality of first merged transmission transistors are arranged in the region between the first memory cell array region and the second memory cell array region, each of the plurality of first merged transmission transistors being commonly connected to a corresponding first word line in the subset of the plurality of first word lines and a corresponding second word line in the subset of the plurality of second word lines; a plurality of first transmission transistors are arranged adjacent to the first memory cell array region and respectively connected to the remaining first word lines; and a plurality of second transmission transistors are arranged adjacent to the second memory cell array region and respectively connected to the remaining second word lines.

[0008] Embodiments of the inventive concept also provide a memory device, the memory device comprising: a substrate including a top surface; a first memory cell array including memory cells vertically stacked on a first memory cell array region on the top surface of the substrate; a second memory cell array including memory cells vertically stacked on a second memory cell array region on the top surface of the substrate; a plurality of first word lines and a plurality of first select lines connected to the first memory cell array, the plurality of first word lines including a subset of the plurality of first word lines and the remaining first word lines, the plurality of first select lines including a subset of the plurality of first select lines and the remaining first select lines; and a plurality of second word lines and a plurality of second select lines connected to the second memory cell array, the plurality of second word lines including the plurality of second word lines. The plurality of second selection lines include a subset of the plurality of second selection lines and the remaining second selection lines; and a line decoder, including a plurality of first merging transmission transistors and a plurality of second merging transmission transistors, each of the plurality of first merging transmission transistors being commonly connected to a corresponding first word line in the subset of the plurality of first word lines and a corresponding second word line in the subset of the plurality of second word lines, each of the plurality of second merging transmission transistors being commonly connected to a corresponding first selection line in the subset of the plurality of first selection lines and a corresponding second selection line in the subset of the plurality of second selection lines, the line decoder being disposed in a line decoder region between a first memory cell array region and a second memory cell array region. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a schematic configuration of a memory device MD according to an embodiment of the inventive concept;

[0011] Figure 2 This is a schematic block diagram of a memory cell array of a memory device according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 This is a circuit diagram illustrating another example of a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept;

[0013] Figure 4 It is a layout diagram used to describe the arrangement of components included in a memory device according to an exemplary embodiment of the inventive concept;

[0014] Figure 5 This is a schematic cross-sectional view of a memory device according to an exemplary embodiment of the inventive concept;

[0015] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a diagram illustrating the combined transmission transistor and the connection structure of the transmission transistor to the word line according to an exemplary embodiment of the inventive concept;

[0016] Figure 7A and Figure 7B It shows along Figure 5 A diagram showing the plane of lines AA′ and BB′;

[0017] Figure 7C It is a graph showing the trend of the resistance value of the character line;

[0018] Figure 7D It is a graph showing the trend of the resistance values ​​of the connecting lines to the word lines;

[0019] Figure 8 This is a table illustrating the conditions for connecting word lines to the merged transmission transistor according to an example embodiment of the inventive concept;

[0020] Figure 9A and Figure 9B This is a diagram illustrating a plurality of combined transmission transistors and a connection structure of the plurality of transmission transistors to word lines according to an exemplary embodiment of the inventive concept.

[0021] Figure 10A , Figure 10B and Figure 10C This is a diagram illustrating a plurality of combined transmission transistors and a connection structure of the plurality of transmission transistors to word lines according to an exemplary embodiment of the inventive concept.

[0022] Figure 11 It is a layout diagram for describing the arrangement of a line decoder included in a memory device according to an example embodiment of the inventive concept;

[0023] Figure 12 These are diagrams illustrating an example embodiment of a memory device according to the inventive concept; and

[0024] Figure 13 This is a diagram illustrating a computing system device including a memory system according to an example embodiment of the inventive concept. Detailed Implementation

[0025] As is customary in the field of inventive conception, embodiments can be described and illustrated in blocks that perform one or more functions as described. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and may optionally be driven by firmware and / or software. For example, the circuitry may be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Without departing from the scope of the inventive conception, each block of an embodiment may be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of the inventive conception, the blocks of an embodiment may be physically combined into more complex blocks.

[0026] Figure 1 This is a block diagram illustrating a schematic configuration of a memory device MD according to an embodiment of the inventive concept.

[0027] Reference Figure 1 The memory device MD may include a memory cell array 1, a row decoder 2, a transfer transistor (TR) unit 3, a page buffer 4, a column decoder 5, and control circuitry 6. Hereinafter, it is assumed that the memory device MD is a non-volatile memory device, wherein the memory cell array 1 may be a non-volatile memory including flash memory, magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), etc. Hereinafter, it will be assumed that the memory device MD is a three-dimensional flash memory device. However, the assumptions here are merely examples, and the inventive concept is not limited thereto. The memory cell array 1 includes a plurality of memory blocks BLK1 to BLKn (where n is an integer greater than or equal to 3), and each of the memory blocks BLK1 to BLKn may include a plurality of memory cells arranged in three dimensions and a plurality of word lines WL and a plurality of bit lines BL electrically connected to the memory cells, respectively.

[0028] The line decoder 2 and the transmission TR unit 3 can select any one of the memory blocks BLK1 to BLKn by decoding the externally supplied address ADDR and selecting any one of the word lines WL of the memory block. The line decoder 2 and the transmission TR unit 3 can be connected together to the memory blocks BLK1 to BLKn, and can provide drive signals (serial select signal SS, ground select signal GS, and word line signal WS) generated by the voltage generation circuit (not shown) to the word line WL and select lines (ground select line GSL and serial select line SSL) of the memory block selected according to the block select signal BS.

[0029] Transmission TR unit 3 can be connected to memory cell array 1 via word line WL and select lines SSL and GSL. Transmission TR unit 3 can be controlled by block select signal BS provided from row decoder 2. Transmission TR unit 3 can send word line signal WS and select signals SS and GS to the word line WL and select lines SSL and GSL of the selected memory block.

[0030] The memory cell array 1 may include three-dimensional flash memory cells. Programming voltage, read voltage, pass voltage, and verification voltage generated by a voltage generator (not shown) may be provided to the word line WL as word line signals WS. For example, the programming voltage may be a relatively high voltage compared to the read voltage, pass voltage, and verification voltage, and the transfer TR cell 3 may include a transfer transistor capable of withstanding high voltages.

[0031] The transmission TR unit 3 according to an embodiment of the inventive concept may further include a plurality of merging transmission transistors 10. The merging transmission transistors 10 may be connected to two different word lines to merge these two different word lines. The memory cell array 1 may be divided into multiple memory cell arrays. For example, the memory cell array 1 may be divided into a first memory cell array and a second memory cell array. Although the first memory cell array and the second memory cell array are structurally separate from each other, the first memory cell array and the second memory cell array can operate as a single memory cell array 1 during memory operation. For example, the merging transmission transistors 10 may be connected to some of the multiple word lines of the first memory cell array and some of the multiple word lines of the second memory cell array. Furthermore, according to an exemplary embodiment, the merging transmission transistors 10 may be connected to two different select lines and merge these two different select lines. For example, the merging transmission transistors 10 may be connected to some of the multiple select lines of the first memory cell array and some of the multiple select lines of the second memory cell array. Through the merging transmission transistors 10, the first memory cell array and the second memory cell array can be simultaneously electrically connected to each other. Detailed examples of the merging transmission transistors 10 will be described later.

[0032] In this way, the space used to set up the transmission TR unit 3 can be minimized by reducing the number of transmission transistors including the combined transmission transistor 10 in the example embodiment of the inventive concept. As a result, the size of the memory device MD can be reduced.

[0033] Page buffer 4 can be connected to memory cell array 1 via bit line BL and read information stored in memory cells. Page buffer 4 can be connected to a bit line selected according to the address decoded by column decoder 5. Page buffer 4 can temporarily store data to be stored in memory cells or detect data stored in memory cells depending on the operating mode. For example, page buffer 4 can operate as a write driver circuit in programming mode and as a sense amplifier circuit in read mode. Page buffer 4 can receive power (e.g., voltage or current) from control circuit 6 and supply power to the selected bit line.

[0034] Column decoder 5 provides a data transfer path between page buffer 4 and an external device (e.g., a memory controller). Column decoder 5 can select any bit line by decoding an externally input address. Column decoder 5 is commonly connected to memory blocks BLK1 to BLKn and can provide data information to the bit lines of the memory block selected according to the block select signal BS.

[0035] Control circuit 6 controls the overall operation of the memory device MD. Control circuit 6 can receive control signals and external voltages, and operate according to the received control signals. Control circuit 6 may include a voltage generator for generating the voltages required for internal operations (e.g., programming voltage, read voltage, erase voltage, etc.) using an external voltage. Control circuit 6 can control programming, read, and erase operations in response to control signals.

[0036] although Figure 1 The illustrated embodiment shows the line decoder 2 and the transmission TR unit 3 arranged separately; however, the illustrated embodiment is merely an example, and the inventive concept is not limited thereto. For example, the line decoder 2 may be configured to include the transmission TR unit 3. Therefore, the transmission TR unit 3 may also be arranged in the region where the line decoder 2 is disposed. Hereinafter, the arrangement of the combined transmission transistor 10 will be described based on the region where the line decoder 2 and the transmission TR unit 3 are arranged together. However, the described arrangement is only for ease of explanation, and it is clear that the arrangement of the combined transmission transistor 10 according to the embodiments of the inventive concept can be applied to various configurations of the line decoder 2.

[0037] Figure 2 This is a schematic block diagram of a memory cell array of a memory device according to an exemplary embodiment of the inventive concept.

[0038] Reference Figure 2 The memory cell array 1 may include a plurality of memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include an electrode structure comprising word lines stacked along a third direction D3 on a plane extending along a first horizontal direction D1 and a second horizontal direction D2. Here, the word lines of the electrode structure may be combined with a plurality of vertical semiconductor pillars and constitute a three-dimensionally arranged memory cell. Furthermore, each of the memory blocks BLK1 to BLKn may include bit lines electrically connected to the memory cell. Each of the memory blocks BLK1 to BLKn may include at least one memory stack. In one embodiment, Figure 1 The merged transfer transistor 10 can be connected to a specific word line within a memory stack. Furthermore, when each of the memory blocks BLK1 to BLKn comprises multiple memory stacks, Figure 1 The merged transfer transistor 10 can be connected to a specific word line in each memory stack. A detailed embodiment of this will be described later.

[0039] Figure 3 This is a circuit diagram illustrating another example of a memory block BLKn included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0040] Reference Figure 3 Memory cell array (e.g., Figure 1 The memory cell array 1) can be a vertical NAND flash memory cell array and may include multiple memory blocks. Figure 3 This example illustrates eight word lines WL1 to WL8 configured within a memory block BLKn. The memory block BLKn may include multiple NAND cell strings NS11 to NS33, multiple word lines WL1 to WL8, multiple bit lines BL1 to BL3, multiple ground select lines GSL1 to GSL3, multiple string select lines (or cell string select lines) SSL1 to SSL3, and a common-source line CSL. The number of NAND cell strings, word lines, bit lines, ground select lines, and cell string select lines can vary.

[0041] NAND cell strings NS11, NS21, and NS31 are positioned between the first bit line BL1 and the common source line CSL; NAND cell strings NS12, NS22, and NS32 are positioned between the second bit line BL2 and the common source line CSL; and NAND cell strings NS13, NS23, and NS33 are positioned between the third bit line BL3 and the common source line CSL. Each NAND cell string (e.g., NS11) may include a series-connected cell string select transistor (or string select transistor) SST, multiple memory cells MC1 to MC8, and a ground select transistor GST.

[0042] Strings of NAND cells connected to a single bit line form a column. For example, NAND cell strings NS11, NS21, and NS31 connected to the first bit line BL1 can form the first column, NAND cell strings NS12, NS22, and NS32 connected to the second bit line BL2 can form the second column, and NAND cell strings NS13, NS23, and NS33 connected to the third bit line BL3 can form the third column.

[0043] NAND cell strings connected to a single cell string select line form a row. For example, NAND cell strings NS11, NS12, and NS13 connected to the first cell string select line SSL1 form the first row, and NAND cell strings NS21, NS22, and NS23 connected to the second cell string select line SSL2 form the second row. NAND cell strings NS31, NS32, and NS33 connected to the third cell string select line SSL3 form the third row.

[0044] The cell string select transistor SST is connected to the corresponding string select line SSL1, SSL2, or SSL3. Memory cells MC1 to MC8 are connected to the corresponding word lines WL1 to WL8, respectively. The ground select transistor GST is connected to the corresponding ground select line GSL1, GSL2, or GSL3. The cell string select transistor SST is connected to the corresponding bit line BL1, BL2, or BL3, and the ground select transistor GST is connected to the common source line CSL.

[0045] Word lines at the same height on the third-direction D3 (e.g., WL1) are interconnected, while cell string select lines SSL1 to SSL3 are separate, as are ground select lines GSL1 to GSL3. For example, when programming a memory cell connected to the first word line WL1 and belonging to NAND cell strings NS11, NS12, and NS13, the first word line WL1 and the first cell string select line SSL1 are selected. Ground select lines GSL1 to GSL3 may be interconnected.

[0046] Figure 4 It is a layout diagram used to describe the arrangement of components included in a memory device 100 according to an example embodiment of the inventive concept.

[0047] Reference Figure 4The memory device 100 can be implemented on a semiconductor chip, and the semiconductor chip may include memory cell array regions CA1_R and CA2_R, row decoder regions RD1_R, RD2_R and RD3_R, and peripheral circuit region PERI_R. The memory cell array, as a vertically stacked structure, can be arranged in the memory cell array regions CA1_R and CA2_R. The row decoder regions RD1_R, RD2_R and RD3_R are adjacent to the memory cell array regions CA1_R and CA2_R in a first horizontal direction D1, and the row decoder can be arranged in the row decoder regions RD1_R, RD2_R and RD3_R. The peripheral circuit region PERI_R is adjacent to the memory cell array regions CA1_R and CA2_R and the row decoder regions RD1_R, RD2_R and RD3_R in a second horizontal direction D2, and page buffers and data input / output circuitry can be arranged in the peripheral circuit region PERI_R.

[0048] The memory cell arrays arranged in memory cell array regions CA1_R and CA2_R are spaced apart from each other at a specific distance, but the memory cell arrays can be controlled as a single memory cell array for memory operations by a row decoder and peripheral circuitry.

[0049] According to the example embodiment, the first line decoder region RD1_R may include a transmission TR unit, which includes the above-described combination. Figure 1 The described merge transfer transistor M_TR. The first row decoder region RD1_R can be the region located between the first memory cell array region CA1_R and the second memory cell array region CA2_R. The merge transfer transistor M_TR can be connected via connecting lines CLa and CLb to any one of the multiple word lines of the first memory cell array disposed in the first memory cell array region CA1_R and any one of the multiple word lines of the second memory cell array disposed in the second memory cell array region CA2_R. The first row decoder region RD1_R may include multiple merge transfer transistors M_TR, so that some word lines of the first memory cell array and some word lines of the second memory cell array can be merged by the merge transfer transistors M_TR. Furthermore, in the first row decoder region RD1_R, multiple first transfer transistors connected to other word lines of the first memory cell array and multiple second transfer transistors connected to other word lines of the second memory cell array can also be arranged.

[0050] According to another example embodiment, in the first row decoder region RD1_R, the first and second transmission transistors are not separately arranged; only the combined transmission transistor M_TR is arranged. Therefore, among the multiple word lines in the first memory cell array and the multiple word lines in the second memory cell array, word lines of the same height on the third direction D3 can be combined with each other.

[0051] According to another example embodiment, the merged transmission transistor M_TR can be connected to any one of the multiple select lines of the first memory cell array and any one of the multiple select lines of the second memory cell array via connection lines CLa and CLb. For example, the merged transmission transistor M_TR can be connected to the cell string select line of the first memory cell array and the cell string select line of the second memory cell array. Furthermore, the merged transmission transistor M_TR can be connected to the ground select line of the first memory cell array and the ground select line of the second memory cell array. The first row decoder region RD1_R may include the merged transmission transistor M_TR, thus some select lines of the first memory cell array and some select lines of the second memory cell array can be merged via the merged transmission transistor M_TR.

[0052] According to another example embodiment, the merged transmission transistor M_TR can be connected to the dummy word lines of the first memory cell array and the second memory cell array via connection lines CLa and CLb.

[0053] Thus, the memory device 100 according to an example embodiment of the inventive concept may include a merged transmission transistor M_TR capable of merging word lines, cell string select lines, ground select lines, and dummy word lines of memory cell arrays arranged in adjacent memory cell array regions CA1_R and CA2_R. In the following, embodiments of merging word lines using the merged transmission transistor M_TR will be described, but the inventive concept is not limited thereto. It is clear that the inventive concept can also be applied to structures in which select lines (cell string select lines or ground select lines) or dummy word lines are merged.

[0054] pass Figure 4 The combined transfer transistor M_TR can reduce the overall chip size by reducing the number of transfer transistors required.

[0055] Figure 5 This is a schematic cross-sectional view of a memory device 100 according to an exemplary embodiment of the inventive concept.

[0056] Reference Figure 4 and Figure 5The substrate Sub may include a first memory cell array region CA1_R and a first row decoder region RD1_R. The substrate Sub may include any of a material with semiconductor properties (e.g., a silicon wafer) and a semiconductor or conductor covered by an insulating material (e.g., glass). For example, the substrate Sub may include a silicon wafer.

[0057] Multiple transmit transistors PT and multiple merge transmit transistors M_PT can be arranged in the first row decoder region RD1_R. A first memory cell array, including a cell array structure, can be disposed on the first memory cell array region CA1_R of the substrate Sub. The cell array structure may include an electrode structure ST, a vertical semiconductor pillar VP penetrating the electrode structure ST, a data storage layer DS disposed between the electrode structure ST and the vertical semiconductor pillar VP, and a bit line BL extending across the electrode structure ST and connected to the vertical semiconductor pillar VP. Refer to the following for more detailed description. Figure 7A and Figure 7B The data storage layer DS may include a tunnel insulation layer (TIL), a charge storage layer (CIL), and a barrier insulation layer (BIL).

[0058] More specifically, the electrode structure ST may extend along a first horizontal direction D1 and may include a plurality of electrodes and insulating layers vertically and alternately stacked on a substrate Sub. The electrodes of the electrode structure ST may include a cell string select line SSL, a ground select line GSL, and word lines WL1 to WLm stacked along a third horizontal direction D3.

[0059] In some embodiments, to achieve the electrical connection of the word lines WL1 to WLm and the select lines GSL and SSL of the electrode structure ST to the transmission transistor PT and the merging transmission transistor M_PT of the first row decoder region RD1_R, the electrode structure ST may have a stepped structure descending from the first memory cell array region CA1_R toward the first row decoder region RD1_R. In other words, the height of the electrode structure ST may decrease in the direction from the first memory cell array region CA1_R to the first row decoder region RD1_R, and the lengths of the word lines WL1 to WLm and the select lines GSL and SSL may decrease as the distance from the substrate Sub increases.

[0060] In some embodiments, the vertical semiconductor pillar VP can penetrate the electrode structure ST and be electrically connected to the substrate Sub. In other words, the vertical semiconductor pillar VP can extend along a third direction D3 perpendicular to the top surface of the substrate Sub. The vertical semiconductor pillar VP comprises a semiconductor material (e.g., silicon) and can be used as a reference above. Figure 3 The description includes the ground selection transistor GST, the cell string selection transistor SST, and the channels of memory cells MC1 to MC8.

[0061] Vertical semiconductor pillars (VPs) can be formed by anisotropically etching vertically stacked films to create holes through which the VPs pass, and by depositing semiconductor films in the holes. Since the VPs are formed in holes penetrating the vertically stacked films, they can have a width (or diameter) that increases in the upward direction (i.e., the third direction D3). The following will refer to… Figures 7A to 7D A detailed description of the width (or diameter) of the vertical semiconductor pillar VP is given, and a detailed description of the connection structure of the merged transfer transistor M_TR based on the structural characteristics of the vertical semiconductor pillar VP will be given below with reference to FIG9.

[0062] Bit line BL may extend across electrode structure ST along a second horizontal direction D2. Bit line BL may be electrically connected to vertical semiconductor pillar VP via bit line contact plugs BPLG and conductive pads (or conductive pads) D. Contact plugs PLG may be connected to word lines WL1 to WLm and select lines GSL and SSL, respectively, wherein the lengths of contact plugs PLG may be different from each other. Connection lines CL may be connected to contact plugs PLG. Connection lines CL may be connected to the merged transmission transistor M_PT or transmission transistor PT of the first line decoder region RD1_R, respectively. Although not shown, connection lines CL may include connection lines extending along the first horizontal direction D1 to connect to the merged transmission transistor M_PT or transmission transistor PT. Vertical semiconductor pillar VP may have a U-shaped shape and may be filled with insulating material. In another embodiment, vertical semiconductor pillar VP may have a cylindrical column shape. Vertical semiconductor pillar VP may include conductive pads D for electrical connection with bit line BL.

[0063] The electrode structure ST can form a memory stack structure, and although in Figure 5 Not shown, but at least one electrode structure ST can be stacked on the electrode structure ST to form a multi-memory stack structure. Hereinafter, a merged transfer transistor M_PT merging word lines of a memory cell array, each having a memory stack structure, will be described. However, this is merely an example, and the inventive concept is not limited thereto. The merged transfer transistor M_PT can merge word lines of a memory cell array having a multi-memory stack structure for each memory stack. A detailed description of this is given below.

[0064] An electrode structure ST' having a shape symmetrical to the electrode structure ST on the third direction D3 can be disposed in the second memory cell array region CA2_R. Since the structure of the electrode structure ST' of the second memory cell array disposed in the second memory cell array region CA2_R is the same as the structure of the electrode structure ST of the first memory cell array, its detailed description will be omitted. The following will refer to... Figure 5The structure of the memory device 200 shown is used to illustrate an example of the connection and arrangement of the combined transmission transistor M_PT.

[0065] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a diagram illustrating the connection structure of the combined transmission transistor M_TR and transmission transistors PT1 to PT4 to the word line according to an exemplary embodiment of the inventive concept.

[0066] Reference Figure 4 and Figure 6A The combined transmission transistor M_PT and transmission transistors PT1 to PT4 can be arranged in the first row decoder region RD1_R. The combined transmission transistor M_TR can be connected to the z-word line WLz_CA1 of the first memory cell array disposed in the first memory cell array region CA1_R and the z-word line WLz_CA2 of the second memory cell array disposed in the second memory cell array region CA2_R. According to an embodiment, the height of the z-word line WLz_CA1 of the first memory cell array on the third direction D3 can be the same as the height of the z-word line WLz_CA2 of the second memory cell array on the third direction D3.

[0067] The first transmission transistor PT1 can be connected to the x-word line WLx_CA1 of the first memory cell array, and the second transmission transistor PT2 can be connected to the y-word line WLy_CA1 of the first memory cell array. The first transmission transistor PT1 and the second transmission transistor PT2 can be located in a region relatively close to the first memory cell array region CA1_R, based on the region where the merged transmission transistor M_PT is disposed.

[0068] The third transmission transistor PT3 can be connected to the y-word line WLy_CA2 of the second memory cell array, and the fourth transmission transistor PT4 can be connected to the x-word line WLx_CA1 of the first memory cell array. The third transmission transistor PT3 and the fourth transmission transistor PT4 can be located in a region relatively close to the second memory cell array region CA2_R, based on the region where the merged transmission transistor M_PT is located.

[0069] The combined transmission transistors M_PT and PT1 to PT4 can be connected to the word lines WLx_CA1 to WLz_CA1 of the first memory cell array and the word lines WLx_CA2 to WLz_CA2 of the second memory cell array via connection lines CLx_CA1 to CLz_CA1 and CLx_CA2 to CLz_CA2, respectively.

[0070] According to the example embodiment, the gate width Wa and gate length La of the combined transmission transistor M_PT can be the same as the gate width Wb and gate length Lb of the transmission transistors PT1 to PT4. Therefore, the combined transmission transistor M_PT can have the same signal gain or drive performance as the transmission transistors PT1 to PT4.

[0071] although Figure 6A The diagram shows four transmission transistors PT1 to PT4 and one merged transmission transistor M_PT arranged along a line on the first horizontal direction D1 in the first row decoder region RD1_R. However, this is merely an example, and the inventive concept is not limited thereto. More merged transmission transistors M_PT can be arranged on the first horizontal direction D1, and fewer or more transmission transistors PT can also be arranged.

[0072] Reference Figure 6B The gate width Wa' of the combined transmission transistor M_PT can be greater than the gate width Wb of the transmission transistors PT1 to PT4, and the gate length La of the combined transmission transistor M_PT can be the same as the gate length Lb of the transmission transistors PT1 to PT4. Therefore, the combined transmission transistor M_PT can have a higher signal gain or driving performance than the transmission transistors PT1 to PT4.

[0073] Reference Figure 6C The gate length La' of the combined transmission transistor M_PT can be smaller than the gate length Lb of the transmission transistors PT1 to PT4, and the gate width Wa of the combined transmission transistor M_PT can be the same as the gate width Wb of the transmission transistors PT1 to PT4. Therefore, the combined transmission transistor M_PT can have a higher signal gain or driving performance than the transmission transistors PT1 to PT4.

[0074] Reference Figure 6D The gate width Wa' and gate length La' of the combined transmission transistor M_PT can be different from the gate width Wb and gate length Lb of the transmission transistors PT1 to PT4, respectively. Therefore, the combined transmission transistor M_PT can have a higher signal gain or driving performance than the transmission transistors PT1 to PT4.

[0075] Figure 7A and Figure 7B They are respectively showing along Figure 5 A plan view showing lines AA′ and BB′. Figure 7C It is a graph showing the trend of the resistance value of the word lines. Figure 7D It is a graph showing the trend of the resistance value of the connection line connected to the word line.

[0076] Reference Figure 5, Figure 7A and Figure 7B The vertical semiconductor pillar VP can penetrate the first word line WL1 and the m-th word line WLm. The width W1 of the vertical semiconductor pillar VP penetrating the first word line WL1 can be smaller than the width W2 of the vertical semiconductor pillar VP penetrating the m-th word line WLm. Therefore, since the remaining area of ​​the first word line WL1 (excluding the area penetrated by the vertical semiconductor pillar VP) is larger than the remaining area of ​​the m-th word line WLm (excluding the area penetrated by the vertical semiconductor pillar VP), the resistance value of the m-th word line WLm can be greater than the resistance value of the first word line WL1.

[0077] Reference Figure 7C Due to the structural characteristics of the vertical semiconductor pillars VP, which become increasingly narrow in the downward direction, the resistance value of the word lines can increase from the first word line WL1 to the m-th word line WLm. In other words, the upper word lines can exhibit higher resistance values. Considering the trend of word line resistance values, it can be as follows... Figure 7D The resistance value of the connecting wire is shown in the figure.

[0078] Reference Figure 7D The resistance value of the connecting wire to the upper character line can be less than the resistance value of the connecting wire to the lower character line. In other words, a character line with a high resistance value can be connected to a connecting wire with a low resistance value. By connecting the connecting wires and character lines as described above, the total resistance of the lines can be adjusted evenly.

[0079] based on Figure 7C and Figure 7D The graph shows the word lines that will be connected to the merged transmission transistor. The following will refer to... Figure 8 Provide a detailed description.

[0080] Figure 8 This is a table illustrating the conditions for connecting word lines to a merged transmission transistor according to an exemplary embodiment of the inventive concept. In the following, as... Figure 8 In the diagram, "M" represents the number of word lines merged (or the number of merged transmission transistors), and "N" represents the number of word lines (e.g., Figure 5 The number of character lines in the text is m), "K" represents a reference value, and "j" represents any integer. For ease of explanation, we will assume that "K" is 2.

[0081] Reference Figure 8 The word line to be connected to the merged transmission transistor (hereinafter referred to as the target word line) can be determined primarily based on the resistance value of the word line. For example, when "M" is equal to or less than "N / 2", the target word line WL M_PTj The resistance value can be set to be equal to or greater than the "N / 2" word line WL. N / 2 The condition for the resistance value. The "N / 2" word line WL N / 2The resistance value can correspond to the conditions used to determine the target word line. In other words, based on Figure 5 The structure of the memory device 200, target word line WL M_PTj It can be set at the "N / 2" word line WL N / 2 Any of the word lines above.

[0082] In another example, when “M” exceeds “N / 2”, it has a word line WL that is equal to or greater than the “N / 2”th word line. N / 2 The number of target word lines A1 can be set to satisfy a resistance value greater than that of word line WL with a resistance value less than the "N / 2"th word line. N / 2 The resistance value is the target word line number A2 condition.

[0083] Next, the target word line can be determined based on the resistance value of the connecting line. For example, when "M" is equal to or less than "N / 2", the connecting line CL... M_PTj (Hereinafter referred to as the target connector) (For example, Figure 6A The resistance value of half (i.e., R / 2) of the connection lines used to merge the transmission transistor M_PT (including the z-th connection lines CLz_CA1 and CLz_CA2) can satisfy being less than or equal to that of connection line CL. N / 2 (For example, when) Figure 6A The y-th word line WLy_CA1 is the "N / 2"th word line WL N / 2 At that time, the connecting line CL N / K The condition corresponding to the resistance value of the connecting line CLy_CA1 connected to the y-th word line WLy_CA1 is that the connecting line CLy_CA1... M_PTj Extend to connect to the target word line WL M_PTj CL connecting line N / 2 Extend to connect to the "N / 2" word line WL N / 2 Extend to connect to the "N / 2" word line WL N / 2 CL connection line N / 2 The resistance value can correspond to the standard used to determine the target word line.

[0084] In another example, when “M” exceeds “N / 2”, half of the corresponding resistance value (i.e., R / 2) is less than or equal to the connection line CL. N / 2 The target connection line CL with resistance value M_PTj The quantity B1 satisfies the requirement of being greater than half of the corresponding resistance value and greater than the connection wire CL. N / 2 The target connection line CL with resistance value M_PTj The condition for quantity B2, connecting line CL N / 2 Extend to the line WL of the “N / 2”th word N / 2 connect.

[0085] However, the above reference Figure 8 The conditions described for connecting word lines to merged transmission transistors are merely examples and are not limited thereto. Various embodiments can be applied to memory devices depending on the memory stacking structure of the memory device (or the form of vertical semiconductor pillars included in the memory stack).

[0086] Figure 9A and Figure 9B This is a diagram illustrating a plurality of merged transmission transistors and a connection structure of the plurality of transmission transistors to word lines according to an exemplary embodiment of the inventive concept.

[0087] Reference Figure 9A A first memory cell array, including first word lines WL1 to twelfth word lines WL12, may be disposed in a first memory cell array region CA1_R, and a second memory cell array, including first word lines WL1 to twelfth word lines WL12, may be disposed in a second memory cell array region CA2_R. For example, both the first and second memory cell arrays may have a structure including a memory stack. (See reference...) Figure 7A and Figure 7B As described, regarding the first word line WL1 to the twelfth word line WL12, the twelfth word line WL12 may be farther from the substrate in the vertical direction (i.e., the third direction D3) than the first word line WL1. The upper word line may exhibit a larger resistance value. For example, the second word line WL2 is farther from the substrate in the vertical direction than the first word line WL1, and the resistance value of the second word line WL2 is greater than the resistance value of the first word line WL1.

[0088] The first merged transfer transistors M_PT1 to the fourth merged transfer transistor M_PT4, and the first to sixteenth transfer transistors PT11 to PT18 and PT21 to PT28 can be arranged in the first row decoder region RD1_R between the first memory cell array region CA1_R and the second memory cell array region CA2_R. The first transfer transistors PT11 to the fourth transfer transistor PT14, which are arranged closest to the first memory cell array region CA1_R, can be connected to the first word lines WL1 to the fourth word lines WL4 via connection lines CL_11 to CL_14, respectively. The fifth transfer transistors PT15 to the eighth transfer transistor PT18, which are arranged second closest to the first memory cell array region CA1_R, can be connected to the fifth word lines WL5 to the eighth word lines WL8 via connection lines CL_15 to CL_18, respectively.

[0089] The ninth to twelfth transmission transistors PT21 to PT24, which are located closest to the second memory cell array region CA2_R, can be connected to the first word lines WL1 to the fourth word lines WL4 via connection lines CL_21 to CL_24, respectively. The thirteenth to sixteenth transmission transistors PT25 to PT28, which are located second closest to the second memory cell array region CA2_R, can be connected to the fifth word lines WL5 to the eighth word lines WL8 via connection lines CL_25 to CL_28, respectively.

[0090] The first merged transfer transistors M_PT1 to the fourth merged transfer transistors M_PT4 can be arranged between the region where the first transfer transistors PT11 to the eighth transfer transistors PT18 are arranged and the region where the ninth transfer transistors PT21 to the sixteenth transfer transistors PT28 are arranged. The first merged transfer transistors M_PT1 to the fourth merged transfer transistors M_PT4 can be connected to the ninth word line WL9 to the twelfth word line WL12 of each of the first memory cell array and the second memory cell array via connection lines CL_M1 to CL_M4, respectively. In other words, in a memory stack, the first merged transfer transistors M_PT1 to the fourth merged transfer transistors M_PT4 can be connected to the upper word line of the first memory cell array and the second memory cell array, and the first to sixteenth transfer transistors PT11 to PT18 and PT21 to PT28 can be connected to the lower word line of the first memory cell array or the second memory cell array.

[0091] Word lines WL9 to WL12 of the first memory cell array connected to the first merged transfer transistor M_PT1 to the fourth merged transfer transistor M_PT4 can be referred to as the first word line group WL_G1, and word lines WL9 to WL12 of the second memory cell array connected to the first merged transfer transistor M_PT1 to the fourth merged transfer transistor M_PT4 can be referred to as the second word line group WL_G2. Word lines WL9 to WL12 included in the first word line group WL_G1 can be merged with word lines WL9 to WL12 included in the second word line group WL_G2, respectively.

[0092] The first character line group WL_G1 and the second character line group WL_G2 may include character lines WL9 to WL12 arranged continuously in the vertical direction. Furthermore, the first character line group WL_G1 and the second character line group WL_G2 may satisfy… Figure 8 The target word line condition is based on the resistance value of the word line. However, this is only an example, and the first word line group WL_G1 and the second word line group WL_G2 can be included in the condition that satisfies... Figure 8 The target character line conditions are met while the character lines are irregularly arranged.

[0093] Furthermore, the horizontally extending connection lines CL_M1 to CL_M4 connecting the first merged transmission transistors M_PT1 to M_PT4 to the ninth word line WL9 to the twelfth word line WL12 can have a symmetrical structure. For example, the length of the connection line CL_M1 extending towards the first memory cell array in the first horizontal direction D1 can be the same as the length of the connection line CL_M1 extending towards the second memory cell array in the first horizontal direction D1. Connection lines CL_M1 to CL_M4 can satisfy... Figure 8 The target connection line condition based on the resistance value of the connection line.

[0094] Reference Figure 9B ,and Figure 9A In contrast, the first merged transfer transistors M_PT1 to the fourth merged transfer transistor M_PT4 may include gates with extended widths to ensure higher gain or drive performance than the other transfer transistors PT11 to PT18 and PT21 to PT28. Furthermore, refer to... Figure 6C and Figure 6D The described embodiments can be applied to the first combined transmission transistor M_PT1 through the fourth combined transmission transistor M_PT4.

[0095] because Figure 9A and Figure 9B The embodiments shown are merely examples, and the inventive concept is not limited thereto; furthermore, combining a transmission transistor and a transmission transistor can satisfy various requirements. Figure 8 The conditions are arranged in various ways.

[0096] Figures 10A to 10C This is a diagram illustrating a plurality of merged transmission transistors and a connection structure of the plurality of transmission transistors to word lines according to an exemplary embodiment of the inventive concept.

[0097] Reference Figure 10A A first memory cell array, including first word lines WL1 to twelfth word lines WL12, can be disposed in a first memory cell array region CA1_R, and a second memory cell array, including first word lines WL1 to twelfth word lines WL12, can be disposed in a second memory cell array region CA2_R. (The above has been referred to...) Figure 9A Details of the first and second memory cell arrays are described, therefore identical descriptions will be omitted.

[0098] The first merged transmission transistors M_PT1 to the eighth merged transmission transistor M_PT8, as well as the first to eighth transmission transistors PT11 to PT14 and PT21 to PT24, can be arranged in the first row decoder region RD1_R' between the first memory cell array region CA1_R and the second memory cell array region CA2_R. The first transmission transistors PT11 to the fourth transmission transistor PT14, which are arranged closest to the first memory cell array region CA1_R, can be connected to the first word lines WL1 to the fourth word lines WL4 via connection lines CL_11 to CL_14, respectively. The fifth transmission transistors PT21 to the eighth transmission transistor PT24, which are arranged closest to the second memory cell array region CA2_R, can be connected to the first word lines WL1 to the fourth word lines WL4 via connection lines CL_21 to CL_24, respectively.

[0099] The first merged transfer transistors M_PT1 to the eighth merged transfer transistors M_PT8 can be arranged between the region where the first transfer transistors PT11 to the fourth transfer transistors PT14 are arranged and the region where the fifth transfer transistors PT21 to the eighth transfer transistors PT24 are arranged. The first merged transfer transistors M_PT1 to the eighth merged transfer transistors M_PT8 can be connected to the fifth word line WL5 to the twelfth word line WL12 of each of the first memory cell array and the second memory cell array via connection lines CL_M1 to CL_M8, respectively. In other words, in a memory stack, the first merged transfer transistors M_PT1 to the eighth merged transfer transistors M_PT8 can be connected to the upper word line of the first memory cell array and the second memory cell array, and the first transfer transistors PT11 to PT14 and PT21 to PT24 can be connected to the lower word line of the first memory cell array or the second memory cell array.

[0100] Word lines WL5 to WL12 of the first memory cell array connected to the first merged transfer transistors M_PT1 to the eighth merged transfer transistors M_PT8 can be referred to as the first word line group WL_G1', and word lines WL5 to WL12 of the second memory cell array connected to the first merged transfer transistors M_PT1 to the eighth merged transfer transistors M_PT8 can be referred to as the second word line group WL_G2'. Word lines WL5 to WL12 included in the first word line group WL_G1' can be merged with word lines WL5 to WL12 included in the second word line group WL_G2', respectively.

[0101] The first character line group WL_G1' and the second character line group WL_G2' may include character lines WL5 to WL12 arranged continuously in the vertical direction. Furthermore, the first character line group WL_G1' and the second character line group WL_G2' may satisfy... Figure 8The target word line condition is based on the resistance value of the word line. However, this is only an example, and the first word line group WL_G1' and the second word line group WL_G2' can be included in the condition that satisfies... Figure 8 The target character line condition is an irregularly arranged character line.

[0102] Furthermore, the connection lines CL_M1 to CL_M8 extending horizontally to connect the first merged transmission transistors M_PT1 to the eighth merged transmission transistor M_PT8 to the fifth word line WL5 to the twelfth word line WL12 can have an asymmetrical structure. For example, the length of the connection line CL_M1 extending towards the first memory cell array in the first horizontal direction D1 can be different from the length of the connection line CL_M1 extending towards the second memory cell array in the first horizontal direction D1. Connection lines CL_M1 to CL_M8 can satisfy... Figure 8 The target connection line condition based on the resistance value of the connection line.

[0103] Reference Figure 10B ,and Figure 10A In contrast, the first merged transfer transistors M_PT1 to the eighth merged transfer transistor M_PT8 may include gates with extended widths to ensure higher gain or drive performance than the other transfer transistors PT11 to PT14 and PT21 to PT24. Furthermore, refer to... Figure 6C and Figure 6D The described embodiments can be applied to the first combined transmission transistor M_PT1 through the eighth combined transmission transistor M_PT8.

[0104] Reference Figure 10C ,and Figure 10B In contrast, some combined transfer transistors M_PT1 to M_PT4 may include gates with extended widths to ensure higher gain or drive performance than other transfer transistors PT11 to PT14 and PT21 to PT24. Furthermore, refer to... Figure 6C and Figure 6D The described embodiments can be applied to some of the combined transfer transistors M_PT1 to M_PT4. The remaining combined transfer transistors M_PT5 to M_PT8 may have the same gain or drive performance as the other transfer transistors PT11 to PT14 and PT21 to PT24.

[0105] because Figures 10A to 10C The embodiments shown are merely examples, and the inventive concept is not limited thereto; furthermore, combining a transmission transistor and a transmission transistor can satisfy various requirements. Figure 8 The conditions are arranged in various ways.

[0106] Figure 11 This is a layout diagram used to describe the arrangement of a line decoder included in a memory device 200 according to an example embodiment of the inventive concept.

[0107] Reference Figure 11 The memory device 200 can be implemented on a semiconductor chip, which may include memory cell array regions CA1_R to CA4_R, row decoder regions RD1_R to RD6_R, page buffer regions PB1_R to PB4_R, and peripheral circuit region PERI_R. The row decoder regions RD1_R to RD6_R are adjacent to the memory cell array regions CA1_R to CA4_R in a second horizontal direction D2, and the row decoders can be arranged within the row decoder regions RD1_R to RD6_R. The page buffer regions PB1_R to PB4_R are arranged adjacent to the memory cell array regions CA1_R to CA4_R in a first horizontal direction D1. Multiple page buffers can be disposed within the page buffer regions PB1_R to PB4_R.

[0108] The memory cell array regions CA1_R to CA4_R, the row decoder regions RD1_R to RD6_R, and the page buffer regions PB1_R to PB4_R can be arranged parallel to each other in a direction parallel to the top surface of the substrate. Components including data input / output circuitry can be located in the peripheral circuitry region PERI_R.

[0109] In an example embodiment applying the inventive concept, multiple merged transmission transistors M_TR can be arranged in a first row decoder region RD1_R between a first memory cell array region CA1_R and a second memory cell array region CA2_R. Furthermore, in an example embodiment applying the inventive concept, the merged transmission transistors M_TR can be arranged in a fourth row decoder region RD4_R between a third memory cell array region CA3_R and a fourth memory cell array region CA4_R.

[0110] Figure 12 This is a diagram illustrating an example embodiment of a memory device 300 according to an inventive concept.

[0111] Reference Figure 12 The memory device 300 may include a first memory cell array, a second memory cell array, a first combined transmission transistor group M_TR_G1, and a second combined transmission transistor group M_TR_G2. The first memory cell array is disposed in the first memory cell array region CA1_R, the second memory cell array is disposed in the second memory cell array region CA2_R, and the first combined transmission transistor group M_TR_G1 and the second combined transmission transistor group M_TR_G2 are arranged in the first row decoder region RD1_R.

[0112] The first memory cell array may include a first electrode structure ST11 and a second electrode structure ST12 as a multi-memory stack structure. The second memory cell array may include a third electrode structure ST21 and a fourth electrode structure ST22 as a multi-memory stack structure. Each of the first electrode structures ST11 to the fourth electrode structure ST22 may include at least one vertical semiconductor pillar VP11 to VP22. A first merged transfer transistor group M_TR_G1 may be connected to a first word line group WL_G11 including the upper word line of the word lines of the first electrode structure ST11 and a third word line group WL_G21 including the upper word line of the word lines of the third electrode structure ST21. A second merged transfer transistor group M_TR_G2 may be connected to a second word line group WL_G12 including the upper word line of the word lines of the second electrode structure ST12 and a fourth word line group WL_G22 including the upper word line of the word lines of the fourth electrode structure ST22.

[0113] In the memory stack corresponding to the first electrode structure ST11 and the third electrode structure ST21, the first word line group WL_G11 and the third word line group WL_G21 can satisfy... Figure 8 The conditions shown in the diagram. Furthermore, in the memory stack corresponding to the second electrode structure ST12 and the fourth electrode structure ST22, the second word line group WL_G12 and the fourth word line group WL_G22 can satisfy... Figure 8 The conditions are shown in the diagram.

[0114] The second word line group WL_G12 can be positioned on the third direction D3 at a predetermined distance from the first word line group WL_G11, and the fourth word line group WL_G22 can be positioned on the third direction D3 at a predetermined distance from the third word line group WL_G21.

[0115] Including but not limited to Figure 12 In the embodiment shown, the first memory cell array and the second memory cell array may further include electrode structures corresponding to more memory stacks, and the merged transmission transistor group connected to the word line may also be arranged in the first row decoder region RD1_R to interact with... Figure 8 The conditions shown in the figure correspond.

[0116] Figure 13 This is a diagram illustrating a computing system device 1000 including a memory system 1010 according to an example embodiment of the inventive concept.

[0117] Reference Figure 13The computing system device 1000 may include a CPU 1030, a user interface 1050, and a memory system 1010 including a memory controller 1012 and a memory device 1011, wherein the CPU 1030, the user interface 1050, and the memory system 1010 are electrically connected to a bus 1060.

[0118] The memory device 1011 may include a combined transmission transistor applied in an example embodiment of the inventive concept. Therefore, the size of the memory device 1011 can be reduced, thereby reducing the size of the memory system 1010.

[0119] The computing system device 1000 may also include RAM 1040 and a power supply 1020. For example, when the computing system device 1000 is a mobile device, a battery for supplying the operating voltage of the computing system 1010 and a modem such as a baseband chipset may be provided separately. Furthermore, it will be apparent to those skilled in the art that the computing system device 1000 may also include an application chipset, a camera image processor (CIS), mobile DRAM, etc., and therefore a detailed description thereof will be omitted.

[0120] The memory controller 1012 and the memory device 1011 can be configured, for example, as a solid-state drive / solid-state disk (SSD) that uses non-volatile memory to store data.

[0121] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A memory device, the memory device comprising: The substrate, including the top surface; The first memory cell array includes a plurality of first memory cells stacked vertically on a first memory cell array region on the top surface of the substrate; The second memory cell array includes a plurality of second memory cells stacked vertically on a second memory cell array region on the top surface of the substrate; Multiple first word lines are connected to the multiple first memory cells, the multiple first word lines including a subset of the multiple first word lines and the remaining first word lines; Multiple second word lines are connected to the multiple second memory cells, the multiple second word lines including a subset of the multiple second word lines and the remaining second word lines; and A line decoder includes a plurality of merged transmission transistors, each of which is commonly connected to a corresponding first word line in a subset of the plurality of first word lines and a corresponding second word line in a subset of the plurality of second word lines, and the line decoder is disposed in a line decoder region on the top surface of the substrate between a first memory cell array region and a second memory cell array region.

2. The memory device according to claim 1, wherein, The corresponding first character line in the subset of the plurality of first character lines and the corresponding second character line in the subset of the plurality of second character lines extend horizontally at the same height above the top surface of the substrate.

3. The memory device according to claim 1, wherein, The line decoder also includes: Multiple first transmission transistors are respectively connected to the remaining first word lines; and Multiple second transmission transistors are connected to the remaining second word lines, respectively.

4. The memory device according to claim 3, wherein, The line decoder region includes: A first region, adjacent to a first memory cell array region, wherein the plurality of first transmission transistors are arranged; A second region, adjacent to the second memory cell array region, wherein the plurality of second transmission transistors are arranged; and The third region, located between the first and second regions, contains the plurality of combined transmission transistors.

5. The memory device according to claim 3, wherein, The gain of each of the plurality of combined transmission transistors is greater than the gain of each of the plurality of first transmission transistors and the gain of each of the plurality of second transmission transistors.

6. The memory device according to claim 3, wherein, At least one of the gate width and gate length of each of the plurality of merged transmission transistors is different from at least one of the gate width and gate length of each of the plurality of first transmission transistors and at least one of the gate width and gate length of each of the plurality of second transmission transistors.

7. The memory device according to claim 1, wherein, A subset of the plurality of first word lines includes at least one group of first word lines, each of the at least one group of first word lines comprising word lines continuously arranged in a vertical direction and connected to the plurality of merged transmission transistors; and The subset of the plurality of second word lines includes at least one group of second word lines, each of the at least one group of second word lines including word lines that are arranged continuously in the vertical direction and connected to the plurality of merged transmission transistors.

8. The memory device according to claim 1, wherein, Any one of the plurality of merged transmission transistors is connected to a first connection line and a second connection line. The first connection line extends horizontally toward the first memory cell array to connect to a corresponding first word line in a subset of the plurality of first word lines. The second connection line extends horizontally toward the second memory cell array to connect to a corresponding second word line in a subset of the plurality of second word lines. The length of the first connecting line is equal to the length of the second connecting line.

9. The memory device according to claim 1, further comprising: The first connecting line and the second connecting line extending in the horizontal direction Each of the plurality of merged transmission transistors is connected to a corresponding first connection line in the first connection line and a corresponding second connection line in the second connection line. The corresponding first connection line extends toward the first memory cell array to connect to a corresponding first word line in a subset of the plurality of first word lines, and the corresponding second connection line extends toward the second memory cell array to connect to a corresponding second word line in a subset of the plurality of second word lines. The length of a corresponding first connecting line in the first connecting line is different from the length of a corresponding second connecting line in the second connecting line.

10. The memory device according to claim 1, wherein, The line decoder is electrically connected to both the first memory cell array and the second memory cell array simultaneously via the multiple merged transmission transistors.

11. A memory device, the memory device comprising: The substrate has a top surface; A first memory cell array includes a first memory stack, the first memory stack including a plurality of first memory cells vertically stacked on a first memory cell array region on the top surface of a substrate; The second memory cell array includes a second memory stack, the second memory stack including a plurality of second memory cells stacked vertically on a second memory cell array region on the top surface of the substrate; Multiple first word lines are connected to the multiple first memory cells, the multiple first word lines including a subset of the multiple first word lines and the remaining first word lines; Multiple second word lines are connected to the multiple second memory cells, the multiple second word lines including a subset of the multiple second word lines and the remaining second word lines; A plurality of first merged transmission transistors are arranged in the region between a first memory cell array region and a second memory cell array region, each of the plurality of first merged transmission transistors being commonly connected to a corresponding first word line in a subset of the plurality of first word lines and a corresponding second word line in a subset of the plurality of second word lines; Multiple first transmission transistors are arranged adjacent to the first memory cell array region and are respectively connected to the remaining first word lines; and Multiple second transmission transistors are arranged adjacent to the second memory cell array region and are respectively connected to the remaining second word lines.

12. The memory device according to claim 11, wherein, The plurality of first character lines are stacked vertically, and the plurality of second character lines are stacked vertically. Among them, the resistance values ​​of the first word lines and the second word lines to which the plurality of first merged transmission transistors are respectively connected are equal to or greater than the resistance value of the reference word line located in the middle of the vertical stack of the plurality of first word lines or the middle of the vertical stack of the plurality of second word lines.

13. The memory device according to claim 11, wherein, The plurality of first character lines are stacked vertically, and the plurality of second character lines are stacked vertically. Wherein, the number of word lines with resistance values ​​equal to or greater than the reference value in the subsets of the plurality of first word lines and the subsets of the plurality of second word lines is greater than the number of word lines with resistance values ​​less than the reference value in the subsets of the plurality of first word lines and the subsets of the plurality of second word lines, and The reference value corresponds to the resistance value of a reference word line located in the middle of the vertical stack of the plurality of first word lines or in the middle of the vertical stack of the plurality of second word lines.

14. The memory device according to claim 11, wherein, The word lines that are connected to the plurality of first word lines and the plurality of second word lines respectively by the plurality of first merged transmission transistors include: an upper word line that is continuously arranged vertically from the first reference word line among the plurality of first word lines, and an upper word line that is continuously arranged vertically from the second reference word line among the plurality of second word lines.

15. The memory device according to claim 11, wherein, The plurality of first character lines are stacked vertically, and the plurality of second character lines are stacked vertically. The plurality of first merged transmission transistors are connected to a subset of the plurality of first word lines via a first connection line, and to a subset of the plurality of second word lines via a second connection line. The resistance value of each of the first and second connecting lines is less than or equal to the resistance value of the connecting line connected to the reference word line, and the reference word line is located in the middle of the vertical stack of the plurality of first word lines or the middle of the vertical stack of the plurality of second word lines.

16. The memory device according to claim 11, wherein, The number of connecting lines in the first and second connecting lines with resistance values ​​equal to or less than the reference value is greater than the number of connecting lines in the first and second connecting lines with resistance values ​​greater than the reference value, and The reference value is twice the resistance value of the connection line connected to the reference word line.

17. The memory device according to claim 11, wherein, The first memory cell array further includes a third memory stack, the third memory stack including a plurality of third memory cells vertically stacked on the first memory stack; the second memory cell array further includes a fourth memory stack, the fourth memory stack including a plurality of fourth memory cells vertically stacked on the second memory stack; the memory device further includes: Multiple third word lines are connected to the multiple third memory cells, the multiple third word lines including a subset of the multiple third word lines and the remaining third word lines; Multiple fourth word lines are connected to the multiple fourth memory cells, the multiple fourth word lines including a subset of the multiple fourth word lines and the remaining fourth word lines; A plurality of second combined transmission transistors are arranged in the region between the first memory cell array region and the second memory cell array region, each of the plurality of second combined transmission transistors being commonly connected to a corresponding third word line in a subset of the plurality of third word lines and a corresponding fourth word line in a subset of the plurality of fourth word lines; Multiple third transmission transistors are arranged adjacent to the first memory cell array region and respectively connected to the remaining third word lines; and Multiple fourth transmission transistors are arranged adjacent to the second memory cell array region and are respectively connected to the remaining fourth word lines.

18. The memory device according to claim 17, wherein, The word lines connected by the plurality of second merge transmission transistors to the subsets of the plurality of third word lines and the subsets of the plurality of fourth word lines are vertically spaced by a certain distance from the word lines connected by the plurality of first merge transmission transistors to the subsets of the plurality of first word lines and the subsets of the plurality of second word lines.

19. A memory device, the memory device comprising: The substrate, including the top surface; The first memory cell array includes a plurality of memory cells stacked vertically on a first memory cell array region on the top surface of the substrate; The second memory cell array includes a plurality of memory cells stacked vertically on a second memory cell array region on the top surface of the substrate; Multiple first word lines and multiple first select lines are connected to a first memory cell array. The multiple first word lines include a subset of the multiple first word lines and the remaining first word lines. The multiple first select lines include a subset of the multiple first select lines and the remaining first select lines. Multiple second word lines and multiple second select lines are connected to a second memory cell array. The multiple second word lines include a subset of the multiple second word lines and the remaining second word lines. The multiple second select lines include a subset of the multiple second select lines and the remaining second select lines. and A line decoder includes a plurality of first combined transmission transistors and a plurality of second combined transmission transistors. Each of the plurality of first combined transmission transistors is commonly connected to a corresponding first word line in a subset of the plurality of first word lines and a corresponding second word line in a subset of the plurality of second word lines. Each of the plurality of second combined transmission transistors is commonly connected to a corresponding first select line in a subset of the plurality of first select lines and a corresponding second select line in a subset of the plurality of second select lines. The row decoder is located in the row decoder region between the first memory cell array region and the second memory cell array region.

20. The memory device according to claim 19, wherein, Both the subset of the plurality of first character lines and the subset of the plurality of second character lines include at least one dummy character line.

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