Microprocessor and synchronization method of its processing core

Abstract

The present invention discloses a microprocessor and a synchronization method for a processing core thereof. The microprocessor includes multiple processing cores and a control unit. The control unit receives a synchronization request from a processing core, wherein the processing core is one of the multiple processing cores, and the synchronization request includes a synchronization type and a synchronization range, wherein the synchronization range refers to all the processing cores to be synchronized. The control unit determines whether all other processing cores in the synchronization range have sent synchronization requests of the synchronization type.

Description

Technical Field

[0001] The present invention relates to a microprocessor, and in particular to a microprocessor with multiple processing cores and a synchronization method of the processing cores. Background Art

[0002] As integrated circuit technology advances, the number of processing cores that can be included in a microprocessor is increasing. Multiple processing cores in the microprocessor need to communicate with each other to meet various requirements, such as power management (e.g., entering C-state), cache management, or debugging. In existing multi-processing core microprocessors, there are many synchronization methods for making multiple processing cores in the microprocessor operate synchronously.

[0003] However, as the number of processing cores of microprocessors increases, and different processing cores often use different resources (such as CPU cache L2, clock, or power), it is very time-consuming and unnecessary to synchronize all processing cores at the same time. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a synchronization method for a microprocessor and a processing core thereof.

[0005] A microprocessor according to an embodiment of the present invention includes a plurality of processing cores and a control unit. The control unit receives a synchronization request from a processing core, wherein the processing core is one of the plurality of processing cores, and the synchronization request includes a synchronization type and a synchronization range, wherein the synchronization range refers to all the processing cores to be synchronized; the control unit determines whether all other processing cores within the synchronization range have sent synchronization requests of the synchronization type.

[0006] A synchronization method according to an embodiment of the present invention is applicable to a microprocessor having multiple processing cores, and the synchronization method includes: receiving a synchronization request from a processing core, wherein the processing core is one of the multiple processing cores, and the synchronization request includes a synchronization type and a synchronization range, wherein the synchronization range refers to all processing cores to be synchronized; and determining whether all other processing cores within the synchronization range have sent synchronization requests of the synchronization type.

[0007] Through the synchronization method of the microprocessor and the processing core thereof proposed by the present invention, only the processing cores within the synchronization range can be synchronized, thereby reducing the time used for synchronization and improving the synchronization efficiency between the processing cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic diagram of a microprocessor 100 according to an embodiment of the present disclosure.

[0009] Figure 2 A structural diagram of a synchronization request according to an embodiment of the present disclosure.

[0010] Figure 3 FIG. 3 is an operation flow 300 of a control unit of a microprocessor 100 according to an embodiment of the present disclosure.

[0011]

Explanation of symbols

[0012] 100: Microprocessor

[0013] 102A, 102B, 102C, 102D: Core

[0014] 102E, 102F, 102G, 102H: Core

[0015] 102J, 102K, 102L, 102M: Core

[0016] 102N, 102P, 102Q, 102R: Core

[0017] 104A, 104B: Non-core units

[0018] 106A, 106B: Control unit

[0019] 108, 108': register

[0020] 108A, 108B, 108C, 108D: Synchronous request

[0021] 108E, 108F, 108G, 108H: Synchronous request

[0022] 110A, 110B: Inter-crystal bus unit

[0023] 112A, 112B, 112C, 112D: Core group

[0024] 114A, 114B: Crystal

[0025] 118, 118': register

[0026] 118J, 118K, 118L, 118M: Synchronous request

[0027] 118N, 118P, 118Q, 118R: Synchronous request

[0028] S301, S303, S305, S307, S309, S311, S313: Steps DETAILED DESCRIPTION

[0029] The present invention is described with reference to the accompanying drawings, in which the same reference numerals throughout the drawings indicate similar or identical elements. The above-mentioned figures are not depicted according to the actual scale, and they only provide an explanation of the present invention. Some forms of the invention are described below as references for illustrated exemplary applications. This means that many special details, relationships and methods are described to provide a complete understanding of this invention. In any case, a person with general knowledge of the relevant field will recognize that this invention can still be implemented without one or more special details or by other methods. In other examples, well-known structures or operations are not listed in detail to avoid confusion with this invention. The present invention is not limited by the order of the actions or events described, such as some actions may occur in different orders or simultaneously under other actions or events. In addition, not all described actions or events need to be performed in the same method as the existing invention.

[0030] Figure 1 FIG. 1 is a schematic diagram of a microprocessor 100 according to an embodiment of the present disclosure. Figure 1 As shown, microprocessor 100 includes a node 114A and a node 114B. Node 114A includes a core cluster 112A, a core cluster 112B, a non-core unit 104A, and an inter-node bus unit 110A. Node 114B includes a core cluster 112C, a core cluster 112D, a non-core unit 104B, and an inter-node bus unit 110B. Core cluster 112A includes processing core 102A, processing core 102B, processing core 102C, and processing core 102D, and core cluster 112B includes processing core 102E, processing core 102F, processing core 102G, and processing core 102H. Each processing core in core clusters 112A and 112B is coupled to non-core unit 104A. Core group 112C includes processing core 102J, processing core 102K, processing core 102L, and processing core 102M, and core group 112D includes processing core 102N, processing core 102P, processing core 102Q, and processing core 102R. Each processing core in core groups 112C and 112D is coupled to non-core unit 104B. Non-core unit 104A includes a control unit 106A, and control unit 106A includes a register 108 and a shadow register 118'. Non-core unit 104B includes a control unit 106B, and control unit 106B includes a register 118 and a shadow register 108'.

[0031] The processing cores 102A, 102B, 102C, 102D, 102E, 102F, 102G, and 102H in the crystal 114A may each send a synchronization request to the control unit 106A of the non-core unit 104A. The control unit 106A stores each synchronization request (e.g., synchronization request 108A-108H) corresponding to each processing core (e.g., processing cores 102A-102H) in the register 108. Specifically, synchronization request 108A represents a synchronization request from processing core 102A, synchronization request 108B represents a synchronization request from processing core 102B, synchronization request 108C represents a synchronization request from processing core 102C, synchronization request 108D represents a synchronization request from processing core 102D, synchronization request 108E represents a synchronization request from processing core 102E, synchronization request 108F represents a synchronization request from processing core 102F, synchronization request 108G represents a synchronization request from processing core 102G, and synchronization request 108H represents a synchronization request from processing core 102H. Similarly, the processing cores 102J, 102K, 102L, 102M, 102N, 102P, 102Q, and 102R in the crystal 114B can respectively provide their own synchronization requests to the control unit 106B of the non-core unit 104B, and the control unit 106B respectively stores the synchronization requests corresponding to each processing core (for example, the processing cores 102J-102R) in the register 118.

[0032] The control unit 106A can directly obtain the synchronization requests of the cores 102A-102H (in this application, unless otherwise specified, the core refers to the processing core, the same below) in the crystal 114A, and can obtain the synchronization requests of the cores 102J-102R in the crystal 114B through the inter-crystal bus units 110A and 110B, and store them in the shadow register 118'. In other words, the control unit 106A maps all the data in the register 118 in the control unit 106B to its own shadow register 118'. Similarly, the control unit 106B can obtain the synchronization requests of the cores 102A-102H in the crystal 114A through the inter-crystal bus units 110B and 110A, and store them in the shadow register 108'. In other words, the control unit 106B maps all the data in the register 108 in the control unit 106A to its own shadow register 108'. Therefore, the control units 106A and 106B can obtain the synchronization requests of all cores, and thus can know the current synchronization requests of all cores.

[0033] Figure 2FIG. 1 is a structural diagram of a synchronization request according to an embodiment of the present disclosure. As can be seen from the above, when a processing core (eg, processing core 102A) of the microprocessor 100 needs to synchronize with other processing cores, the processing core first generates a synchronization request (eg: Figure 1 The core 102A generates a synchronization request 108A). The synchronization request is as follows Figure 2 As shown in FIG. 1 , the synchronization request includes a synchronization bit field, a synchronization type field, a synchronization value field, and a synchronization range field. Each field will be described below.

[0034] The synchronization bit field of the synchronization request is used to indicate whether synchronization with other processing cores is required. In one embodiment, the synchronization bit field of the synchronization request is set to 1 to indicate that a processing core generating the synchronization request needs to be synchronized with other processing cores. The synchronization bit field of the synchronization request is set to 0 to indicate that the above-mentioned processing core has completed synchronization with the above-mentioned other processing cores. In another embodiment, the synchronization bit field is 0 to indicate that synchronization is required, and the synchronization bit field is set to 1 to indicate that synchronization is completed.

[0035] Figure 2 The synchronization type field in is used to store the synchronization type. The synchronization type may include situation synchronization, sleep synchronization, etc. In one embodiment, the synchronization type field is 0 to indicate situation synchronization. Sometimes, when it is necessary to dump the debugging information of multiple processing cores of the microprocessor 100, it is necessary to enable multiple processing cores to start executing the same code at the same time, that is, multiple processing cores execute the same code synchronously, which is a synchronization situation. In one embodiment, the synchronization type field is 1 to indicate sleep synchronization, sleep is the sleep state C-state, and sleep synchronization refers to the sleep state C-state synchronization. In another embodiment, the synchronization type field is 1 to indicate situation synchronization, and the synchronization type field is 0 to indicate sleep synchronization.

[0036] Figure 2The synchronization value in indicates the synchronization situation or the sleep state. The following will take the situation synchronization with the synchronization type field being 0 and the sleep synchronization with the synchronization type field being 1 as examples for description. When the synchronization type is situation synchronization (i.e., the synchronization type field is 0), the synchronization value indicates the synchronization situation, and each synchronization value indicates a synchronization situation. The synchronization value field may include multiple bits to indicate a variety of different synchronization situations. For example: the synchronization value field includes 2 bits to indicate 4 different synchronization situations, the synchronization value field includes 4 bits to indicate 16 different synchronization situations... and so on. For example, in the process of dumping the debugging information of multiple processing cores of the microprocessor 100, each processing core needs to send multiple synchronization requests to perform multiple situation synchronizations. Each processing core needs to set a different synchronization value (for example, synchronization value 0, 1, 2... and so on) in each synchronization request to indicate various different synchronization situations in the process of dumping the debugging information. For example, a synchronization condition 0 with a synchronization value of 0 indicates that the processing core is ready to execute the code for storing the debugging information in the memory; a synchronization condition 1 with a synchronization value of 1 indicates that the processing core has stored the debugging information in the memory; a synchronization condition 2 with a synchronization value of 2 indicates that the processing core has completed the dumping of the debugging information... and so on. After each processing core sends a synchronization request, it will stop executing the subsequent code to be executed. When the control unit determines that all processing cores in the multiple processing cores have sent a synchronization request, and the synchronization values ​​in the synchronization request are the same (for example, all processing cores have sent a synchronization request with a synchronization value of 0), the control unit notifies each processing core in the multiple processing cores to start to continue to execute the code to be executed at the same time. When each processing core continues to execute the code, if it needs to synchronize the situation again, it will repeat the aforementioned synchronization process (which will not be described here) until the dumping operation of the debugging information is completed.

[0037] When the synchronization type is sleep synchronization (i.e., the synchronization type field value is 1), the synchronization value corresponds to a sleep state (i.e., C-state, such as C1, C2, etc.). In one embodiment, the synchronization value can be one of 1-6, corresponding to one of the six sleep states (C1-C6). The larger the synchronization value, the deeper the sleep depth of the processing core. Figure 1For example, when the core 102A is in the sleep state of C1 or C2, its core clock must be turned off, so the non-core unit 104A turns off the core clock output to the core 102A. When the core 102A is in the sleep state of C3, in addition to the core clock, its core power must also be turned off, so the non-core unit 104A turns off the core clock and core power output to the core 102A. When the core 102A is in the sleep state of C4, the core clock, core power, and part of the power of its cache must be turned off, so the non-core unit 104A turns off the core clock, core power, and part of the power of the cache output to the core 102A. When the core 102A is in the sleep state of C5, the core clock, core power, and all the power of the cache must be turned off, so the non-core unit 104A turns off the core clock, core power, and all the power of the cache output to the core 102A. The above sleep states can be freely set according to design requirements and are not limited to the present invention.

[0038] Figure 2 The synchronization range field in is used to store the synchronization range. The synchronization range refers to the entirety of the processing cores to be synchronized. When the processing core sends a synchronization request, a synchronization range can be set, and the control unit only performs synchronization operations on the processing cores within the synchronization range, thereby saving time for synchronization. The synchronization range includes a first range, a second range, and a third range, wherein the third range includes at least one second range, and the second range includes at least one first range, wherein the second range is one of the at least one second range, and the first range is one of the at least one first range. Figure 1 Taking the microprocessor 100 as an example, the first range is all the processing cores 102A-102D in the core group 112A, which is 4 processing cores in total. The second range is all the processing cores 102A-102H in the crystal 114A, which is 8 processing cores in total. The third range is all the processing cores 102A-102R in the microprocessor 100, which is 16 processing cores in total. Figure 1In the embodiment shown, only three synchronization ranges (first range, second range and third range) are included, and the number of processing cores in the latter range is twice the number of processing cores in the former range (the number of processing cores in the second range is twice the number of processing cores in the first range, and the number of processing cores in the third range is twice the number of processing cores in the second range). However, the present invention is not limited to this. When more levels are included, the microprocessor 100 will include more synchronization ranges, such as 4 synchronization ranges or 5 synchronization ranges; when fewer levels are included, the microprocessor 100 will include fewer synchronization ranges, such as 2 synchronization ranges or only 1 synchronization range. In addition, the number of processing cores in adjacent synchronization ranges may not be a multiple relationship. For example, in one embodiment, the first range (for example, core group 112A) includes 3 processing cores, the second range (for example, crystal 114A) includes 5 processing cores, and the third range (for example, microprocessor 100) includes 8 processing cores.

[0039] In addition, in a specific implementation, the above-mentioned synchronization range can use 2 bits to represent 3 synchronization ranges, the 0th bit scope_cluster is used to indicate whether it is the second range, and the 1st bit scope_node is used to indicate whether it is the third range. The values ​​of the 0th bit scope_cluster and the 1st bit scope_node are both 0 (that is, neither the second range nor the third range), indicating the first range, that is, 00 (binary number) indicates the first range; the value of the 0th bit scope_cluster is 1 and the value of the 1st bit scope_node is 0, indicating the second range, that is, 01 (binary number) indicates the second range; the value of the 1st bit scope_node is 1, indicating the third range (the value of the 0th bit scope_cluster can be 0 or 1), that is, 10 (binary number) or 11 (binary number) indicates the third range.

[0040] In another embodiment, the value of the synchronization range field is 0 (decimal number) to indicate the first range, the value of the synchronization range field is 1 (decimal number) to indicate the second range, the value of the synchronization range field is 2 (decimal number) to indicate the third range, and the value of the synchronization range field is 3 (decimal number) to indicate the fourth range. In another embodiment, the synchronization range field includes multiple bits, each bit is used to indicate a range, and 3 bits can be used to indicate 3 ranges, the 0th bit is used to indicate whether it is the first range, the 1st bit is used to indicate whether it is the second range, and the 2nd bit is used to indicate whether it is the third range; for example, 001 (binary number) indicates the first range, 01X (binary number) indicates the second range (X indicates that the bit value can be 0 or 1, the same below), and 1XX (binary number) indicates the third range.

[0041] Figure 3FIG. 3 is an operation flow 300 of a control unit of a microprocessor 100 according to an embodiment of the present disclosure. Figure 3 As shown, the control unit receives a synchronization request from a processing core coupled thereto (S301), wherein the synchronization request includes a synchronization range; the control unit determines whether all other processing cores within the synchronization range have sent synchronization requests of the same synchronization type (S303); if all other processing cores within the synchronization range have sent synchronization requests of the same synchronization type, the control unit determines what the synchronization type of the synchronization request is (S305); and then the control unit performs corresponding processing for different synchronization types.

[0042] The following will be matched Figure 1 , Figure 2 and Figure 3 , to respectively illustrate the process of the execution unit executing the processing flow 300 when the synchronization type of the synchronization request is sleep synchronization or situation synchronization. In the first embodiment, the execution unit executes the process of the processing flow 300 when the synchronization request is sleep synchronization. In the second embodiment, the execution unit executes the process of the processing flow 300 when the synchronization request is situation synchronization.

[0043] [First embodiment]

[0044] The control unit executes step S301. In step S301, the control unit receives a synchronization request from a processing core. In detail, the microprocessor 100 has multiple processing cores (described above in conjunction with Figure 1 The relationship between multiple processing cores is described, which will not be repeated here). When each processing core needs to synchronize with other processing cores, it needs to send a synchronization request to the control unit of the non-core unit coupled to it. For example, Figure 1 As shown, when the processing core 102A needs to synchronize with the processing cores 102B-102H, the processing core 102A sends a synchronization request to the control unit 106A of the non-core unit 104A. The control unit 106A receives and processes the synchronization request 108A from any processing core coupled thereto, wherein the synchronization request 108A includes the following: Figure 2 The fields such as the synchronization bit, synchronization type, synchronization value and synchronization range are shown. In this embodiment, it is assumed that the value of the synchronization bit field of the synchronization request 108A is 1 (indicating a request for synchronization), the value of the synchronization type field is 1 (indicating sleep synchronization), the value of the synchronization value field is 3 (indicating entering sleep state C3), and the value of the synchronization range field is 01 (a binary number, indicating the second range. As mentioned above, the 1 on the left is the value of scope_node, and the 0 on the right is the value of scope_cluster). The synchronization request 108A will continue to be used as an example in the following steps of this embodiment.

[0045] Then, step S303 is executed. In step S303, the control unit determines whether all other processing cores within the synchronization range have sent synchronization requests of the same synchronization type. That is, the control unit determines whether all other processing cores within the synchronization range have sent synchronization requests and the synchronization type is sleep synchronization. If the judgment result is "no", the control unit completes this execution; otherwise, the control unit executes step S305. As described in the above embodiment, since the synchronization range in the synchronization request 108A is the second range, the control unit 106A will determine whether other processing cores within the second range (such as Figure 1 As shown, whether the other processing cores in the second range include processing cores 102B, 102C, 102D, 102E, 102F, 102G and 102H) have all sent synchronization requests and the synchronization type is sleep synchronization. If the synchronization bit field (such as Figure 2 If the values ​​of the SyncType field are both 1 and the SyncType field values ​​are both 1, the judgment result is "yes", otherwise the judgment result is "no". If the judgment result is "no", the control unit 106A completes this execution; if the judgment result is "yes", the control unit 106A executes step S305.

[0046] In step S305, the control unit determines what the synchronization type of the synchronization request is. Based on the above embodiment, the value of the synchronization type field in the synchronization request 108A is 1, so the control unit 106A determines that its synchronization type is "sleep synchronization". Then, the control unit 106A executes step S307.

[0047] In step S307, the control unit determines whether all the processing cores it manages are within the synchronization range. Specifically, after receiving the synchronization request, the control unit obtains the synchronization range from the synchronization request. Then, the control unit determines whether all the processing cores coupled to it are within the synchronization range. If the judgment result is "no", the control unit completes the execution; otherwise, step S309 is executed. As described in the above embodiment, the synchronization range included in the synchronization request 108A is the second range. Figure 1 As shown, the processing cores 102A-102H managed by the control unit 106A are all within the second range, so the judgment result is “yes.” Then, the control unit 106A executes step S309.

[0048] In step S309, the control unit selects the minimum synchronization value among the synchronization values ​​of all the processing cores within the synchronization range. As described in the above embodiment, since the synchronization range is the second range, and the processing core 102A is in the sleep state C3 (synchronization value 3), the processing core 102B is in the sleep state C5 (synchronization value 5), the processing core 102C is in the sleep state C4 (synchronization value 4), the processing core 102D is in the sleep state C2 (synchronization value 2), the processing core 102E is in the sleep state C3 (synchronization value 3), the processing core 102F is in the sleep state C2 (synchronization value 2), the processing core 102G is in the sleep state C4 (synchronization value 4), and the processing core 102H is in the sleep state C2 (synchronization value 2), the control unit 106A will select the sleep state C2 corresponding to the lowest synchronization value 2 as its own sleep state, so that at least the core clock (clock frequency), core power (operating voltage), and cache size requirements of the cores 102D, 102F, and 102H when they are in the sleep state C2 can be met.

[0049] In some embodiments, the control unit 106A executes a program code b to select the minimum synchronization value among the synchronization values ​​of all processing cores within the synchronization range, and uses the sleep state corresponding to the minimum synchronization value as the sleep state executed by itself. The program code b is as follows:

[0050] lowerA_B=min(syn_cond,syn_cond_B);

[0051] lowerA_C=min(syn_cond,syn_cond_C);

[0052] lowerA_D=min(syn_cond,syn_cond_D);

[0053] lowerA_E=(scope_node|scop_cluster)? min(syn_cond,syn_cond_E):MAX_CSTATE;

[0054] lowerA_F=(scope_node|scop_cluster)? min(syn_cond, syn_cond_F):MAX_CSTATE;

[0055] lowerA_G=(scope_node|scop_cluster)? min(syn_cond, syn_cond_G):MAX_CSTATE;

[0056] lowerA_H=(scope_node|scop_cluster)?min(syn_cond,syn_cond_H):MAX_CSTATE;

[0057] lowerA_J=(scope_node)?min(syn_cond,syn_cond_J):MAX_CSTATE;

[0058] lowerA_K=(scope_node)?min(syn_cond,syn_cond_K):MAX_CSTATE;

[0059] lowerA_L=(scope_node)?min(syn_cond,syn_cond_L):MAX_CSTATE;

[0060] lowerA_M=(scope_node)?min(syn_cond,syn_cond_M):MAX_CSTATE;

[0061] lowerA_N=(scope_node)?min(syn_cond,syn_cond_N):MAX_CSTATE;

[0062] lowerA_P=(scope_node)?min(syn_cond,syn_cond_P):MAX_CSTATE;

[0063] lowerA_Q=(scope_node)?min(syn_cond,syn_cond_Q):MAX_CSTATE;

[0064] lowerA_R=(scope_node)?min(syn_cond,syn_cond_R):MAX_CSTATE;

[0065] lowest_CSTATE=min(lowerA_B,lowerA_C,lowerA_D,lowerA_E,lowerA_F,lowerA_G,lowerA_H,lowerA_J,lowerA_K,lowerA_L,lowerA_M,lowerA_N,lowerA_P,lowerA_Q,lowerA_R);

[0066] As shown in the above program code b, since the synchronization range is the second range, the control unit 106A refers to the synchronization values ​​in the synchronization requests 108A, 108B, 108C, 108D, 108E, 108F, 108G, and 108H in the register 108. "lowerA_B" is a lower synchronization value selected from the synchronization requests 108A (synchronization value is 3, and the corresponding sleep state is C3) and 108B (synchronization value is 5, and the corresponding sleep state is C5), so the value of "lowerA_B" is 3, and the corresponding sleep state is C3. Similarly, "lowerA_C" is a lower synchronization value selected from the synchronization requests 108A (synchronization value is 3, and the corresponding sleep state is C3) and 108C (synchronization value is 4, and the corresponding sleep state is C4), so the value of "lowerA_C" is 3, and the corresponding sleep state is C3. "lowerA_D" selects a lower synchronization value from the synchronization requests 108A (synchronization value is 3, the corresponding sleep state is C3) and 108D (synchronization value is 2, the corresponding sleep state is C2), so the value of "lowerA_D" is 2, and its corresponding sleep state is C2. Since the synchronization range is the second range, the scope_node value is 0, and the scope_cluster value is 1, so "scope_node|scope_cluster" is equal to 1. Among them, "scope_node|scope_cluster" means that scope_node and scope_cluster perform a bitwise OR operation, the same below. In the above program code b, "lowerA_E" selects a smaller synchronization value from the synchronization requests 108A (synchronization value is 3, the corresponding sleep state is C3) and 108E (synchronization value is 3, the corresponding sleep state is C3), so the value of "lowerA_E" is 3, and its corresponding sleep state is C3. "lowerA_F" is a smaller synchronization value selected from the synchronization request 108A (synchronization value is 3, the corresponding sleep state is C3) and 108F (synchronization value is 2, the corresponding sleep state is C2), so the value of "lowerA_F" is 2, and its corresponding sleep state is C2. "lowerA_G" is a smaller synchronization value selected from the synchronization request 108A (synchronization value is 3, the corresponding sleep state is C3) and 108G (synchronization value is 4, the corresponding sleep state is C4), so the value of "lowerA_G" is 3, and its corresponding sleep state is C3. "lowerA_H" is a smaller synchronization value selected from the synchronization request 108A (synchronization value is 3, the corresponding sleep state is C3) and 108H (synchronization value is 2, the corresponding sleep state is C2), so the value of "lowerA_H" is 2, and its corresponding sleep state is C2.

[0067] Since the synchronization scope is the second scope, the scope_node value is 0. In the above program code b, "lowerA_J", "lowerA_K", "lowerA_L", "lowerA_M", "lowerA_N", "lowerA_P", "lowerA_Q", and "lowerA_R" are all set to "MAX_CSTATE" (i.e., the maximum synchronization value 6). “lowest_CSTATE” indicates that the control unit 106A selects the smallest one from “lowerA_B” (3), “lowerA_C” (3), “lowerA_D” (2), “lowerA_E” (3), “lowerA_F” (2), “lowerA_G” (3), “lowerA_H” (2), “lowerA_J” (6), “lowerA_K” (6), “lowerA_L” (6), “lowerA_M” (6), “lowerA_N” (6), “lowerA_P” (6), “lowerA_Q” (6), and “lowerA_R” (6), that is, “lowest_CSTATE” is 2. Then, the control unit 106A executes step S311.

[0068] In step S311, the control unit uses the sleep state corresponding to the minimum synchronization value as the sleep state of the non-core unit. As described in the above embodiment, after using program b to obtain the minimum synchronization value 2, the control unit 106A selects the sleep state C2 corresponding to the minimum synchronization value 2 as the sleep state of the non-core unit 104A, so that at least the core clock (clock frequency), core power (operating voltage), and cache size requirements when the core 102D is in the sleep state C2 can be met.

[0069] In the above embodiment, the process of describing the processing flow 300 is performed by taking the synchronization range as the second range as an example. Those skilled in the art can deduce that when the synchronization range is the first range or the third range, the control unit executes the process of the processing flow 300, which will not be described in detail here.

[0070] In another embodiment, in step S307, when the synchronization range included in the synchronization request 108A is the first range, Figure 1 As shown, the processing cores 102E-102H managed by the control unit 106A are not within the first range, so the judgment result is "no" and the control unit 106A will complete the execution.

[0071] In another embodiment, in step S309, as shown in the program code b above, when the synchronization scope is the third scope (represented by the binary number "10", as mentioned above, the 1 on the left is the value of scope_node, and the 0 on the right is the value of scope_cluster), the control unit 106A simultaneously refers to the synchronization values ​​in the synchronization requests 108A-108H in the register 108 and the synchronization values ​​in the synchronization requests 118J-118R of the shadow register 118'.

[0072] When the synchronization range is the first range or the third range, the operation principle of the control unit 106A executing the program code b is the same as when the synchronization range is the second range, and will not be repeated here.

[0073] The above embodiment is described by taking the case where the core 102A in the crystal 114A sends a synchronization request as an example, so the control unit 106A of the non-core unit 104A executes the above program code b. When the core 102J in the crystal 114B sends a synchronization request, the control unit 106B of the non-core unit 104B executes the above program code b. Although the codes in the above program code are modified accordingly, the operating principle is still the same.

[0074] [Second embodiment]

[0075] The following describes the process of the control unit executing the processing flow 300 when the synchronization request is situation synchronization.

[0076] First, the control unit executes step S301. In step S301, the control unit receives a synchronization request from the processing core. In this embodiment, we still assume that the control unit 106A receives the synchronization request 108A from the processing core 102A. Different from the first embodiment, in this embodiment, we assume that the value of the synchronization type field of the synchronization request 108A is 0 (indicating situation synchronization) and the value of the synchronization value field is 1 (indicating entering synchronization situation 1). The other operations in step S301 of this embodiment are the same as step S301 of the first embodiment, and will not be repeated here.

[0077] Then, step S303 is executed. In step S303, the control unit determines whether all other processing cores within the synchronization range have sent synchronization requests of the same synchronization type. Specifically, the control unit will determine whether all other processing cores within the synchronization range have sent synchronization requests, the synchronization type is situation synchronization, and the synchronization value is the same. If the judgment result is "no", the control unit completes this execution; otherwise, the control unit executes step S305. As described in the above embodiment, since the synchronization range in the synchronization request 108A is the second range, the control unit 106A will determine whether other processing cores (such as Figure 1As shown, whether the other processing cores in the second range include processing cores 102B, 102C, 102D, 102E, 102F, 102G and 102H) have all sent synchronization requests, the synchronization type is situation synchronization and the synchronization value is the same. If the values ​​of the synchronization bit fields in the synchronization requests 108B, 108C, 108D, 108E, 108F, 108G and 108H are all 1, and the values ​​of the synchronization type fields are all 0, the control unit 106A executes the following program code a to determine whether the other processing cores in the synchronization range have all sent synchronization requests with the same synchronization value:

[0078] syncA_B=(syn_cond==syn_cond_B);

[0079] syncA_C=(syn_cond==syn_cond_C);

[0080] syncA_D=(syn_cond==syn_cond_D);

[0081] syncA_E=(scope_node|scope_cluster)? (syn_cond==syn_cond_E):1;

[0082] syncA_F=(scope_node|scope_cluster)? (syn_cond==syn_cond_F):1;

[0083] syncA_G=(scope_node|scope_cluster)? (syn_cond==syn_cond_G):1;

[0084] syncA_H=(scope_node|scope_cluster)? (syn_cond==syn_cond_H):1;

[0085] syncA_J=(scope_node)? (syn_cond==syn_cond_J):1;

[0086] syncA_K=(scope_node)? (syn_cond==syn_cond_K):1;

[0087] syncA_L=(scope_node)? (syn_cond==syn_cond_L):1;

[0088] syncA_M=(scope_node)? (syn_cond==syn_cond_M):1;

[0089] syncA_N=(scope_node)?(syn_cond==syn_cond_N):1;

[0090] syncA_P=(scope_node)?(syn_cond==syn_cond_P):1;

[0091] syncA_Q=(scope_node)?(syn_cond==syn_cond_Q):1;

[0092] syncA_R=(scope_node)?(syn_cond==syn_cond_R):1;

[0093] synced=syncA_B&syncA_C&syncA_D&syncA_E&syncA_F&syncA_G&syncA_H&syncA_J&syncA_K&syncA_L&syncA_M&syncA_N&syncA_P&syncA_Q&syncA_R;

[0094] Since the synchronization range of the synchronization request 108A is the second range, the control unit 106A compares the synchronization values ​​in the synchronization requests 108B, 108C, 108D, 108E, 108F, 108G, and 108H in the register 108 with the synchronization value in the synchronization request 108A, but does not compare with the synchronization values ​​in the synchronization requests 118J-118R in the shadow register 118'. As shown in the above program code a, when the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_B in the synchronization request 108B, "syncA_B" is equal to 1. When the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_C in the synchronization request 108C, "syncA_C" is equal to 1. When the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_D in the synchronization request 108D, "syncA_D" is equal to 1. Since when the synchronization scope is the second scope, the scope_node value is 0 and the scope_cluster value is 1, "scope_node|scope_cluster" is equal to 1. As shown in the above program code a, when the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_E in the synchronization request 108E, "syncA_E" will be equal to 1. When the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_F in the synchronization request 108F, "syncA_F" will be equal to 1. When the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_G in the synchronization request 108G, "syncA_G" will be equal to 1. When the synchronization value syn_cond in the synchronization request 108A is equal to the synchronization value syn_cond_H in the synchronization request 108H, "syncA_H" will be equal to 1.

[0095] Similarly, since the synchronization range is the second range, the control unit 106A directly sets the values ​​of "syncA_J", "syncA_K", "syncA_L", "syncA_M", "syncA_N", "syncA_P", "syncA_Q", and "syncA_R" in the above program code a to 1. "synced" in the above program code a performs a bitwise AND operation on the values ​​of "syncA_B", "syncA_C", "syncA_D", "syncA_E", "syncA_F", "syncA_G", "syncA_H", "syncA_J", "syncA_K", "syncA_L", "syncA_M", "syncA_N", "syncA_P", "syncA_Q", and "syncA_R". When the value of "synced" is 1, it means that all other processing cores in the synchronization range (i.e., the second range) have sent synchronization requests of the same synchronization type. When the value of "synced" is 0, it means that at least one of the other processing cores in the synchronization range has not sent a synchronization request of the same synchronization type.

[0096] In step S303, when the control unit determines that all other processing cores within the synchronization range have sent synchronization requests, the synchronization type is situation synchronization, and the synchronization values ​​are the same, step S305 is executed.

[0097] In step S305, the control unit determines what the synchronization type of the synchronization request is. As described in the above embodiment, the value of the synchronization type field in the synchronization request 108A is 0, so the control unit 106A determines that the synchronization type of the synchronization request 108A is "situation synchronization". Then, the control unit 106A executes step S313.

[0098] In step S313, the control unit wakes up all processing cores within the synchronization range. Specifically, the control unit first sets the value of the synchronization bit field of the synchronization request stored in the temporary register of all processing cores within the synchronization range to 0, and then wakes up all processing cores within the synchronization range (for example, turns on the clock signal to the processing core 102A). As described in the above embodiment, since the synchronization range is the second range, the control unit 106A will set the value of the synchronization bit field of the synchronization request 108A-108H to 0, and then wake up the processing cores 102A-102H.

[0099] In the above embodiment, the process of describing the processing flow 300 is performed by taking the synchronization range as the second range as an example. Those skilled in the art can deduce that when the synchronization range is the first range or the third range, the control unit executes the process of the processing flow 300, which will not be described in detail here.

[0100] In the synchronization method of the microprocessor and its processing core proposed in the present invention, the status of other processing cores within the synchronization range is judged through program code, so only the processing cores within the synchronization range can be synchronized, thereby reducing the time used for synchronization and improving the synchronization efficiency between processing cores.

[0101] Although the embodiments of the present invention are described above, it should be understood that what is presented above is only an example and not a limitation. Many changes to the above exemplary embodiments can be implemented without violating the spirit and scope of the invention according to this embodiment. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. Rather, the scope of the present invention should be defined by the claims and their equivalents. Although the above invention has been illustrated and described by one or more related executions, equivalent changes and modifications will be thought of by others who are familiar with this field based on the above specifications and drawings. In addition, although a particular feature of the present invention has been demonstrated by one of the related multiple executions, the above feature may be combined with one or more other features so that there may be a need and help for any known or special application.

[0102] The professional terms used in this specification are only for the purpose of describing specific embodiments and are not intended to be used as limitations of the present invention. Unless the context clearly indicates otherwise, the singular form, one, this and the above-mentioned meanings as used herein also include plural forms. Furthermore, the words "include", "comprise", "have", "have", or their variations are either used as detailed descriptions or as claims. The above-mentioned words mean to include, and to some extent are equivalent to the word "include". Unless there are different definitions, all the words used in this article (including technical or scientific terms) can be generally understood by those skilled in the art. We should be more aware that the above-mentioned words, such as those defined in commonly used dictionaries, should be interpreted as the same meaning in the context of the relevant technology. Unless explicitly defined in this article, the above-mentioned words will not be interpreted as idealized or overly formal.

Claims

1. A microprocessor, comprising: Multiple processing cores; as well as A control unit is used to receive a synchronization request from a processing core, wherein the processing core is one of the multiple processing cores, and the synchronization request includes a synchronization type and a synchronization range, wherein the synchronization range refers to all the processing cores to be synchronized; the control unit determines whether all other processing cores within the synchronization range have sent synchronization requests of the synchronization type, Wherein, when the synchronization type is situation synchronization, the synchronization request also includes a synchronization value, and the synchronization value includes multiple bits, which are used to represent multiple different situation synchronizations; when each processing core within the synchronization range has sent the synchronization request, the execution of the subsequent code to be executed will be stopped, and when all other processing cores within the synchronization range have sent a synchronization request with the synchronization type being situation synchronization, and the synchronization value in the synchronization request of all other processing cores within the synchronization range is the same as the synchronization value, it means that all other processing cores within the synchronization range have sent a synchronization request of the synchronization type, and the control unit notifies each processing core among the multiple processing cores to start to continue to execute the code to be executed at the same time; When the synchronization type is sleep synchronization, when all other processing cores in the synchronization range have sent a synchronization request of the sleep synchronization type, it means that all other processing cores in the synchronization range have sent a synchronization request of the synchronization type. Among them, when all other processing cores within the synchronization range have sent synchronization requests with the synchronization type being sleep synchronization, the control unit selects the minimum synchronization value among the synchronization values ​​of all processing cores within the synchronization range, and uses the sleep state corresponding to the minimum synchronization value as the sleep state of the non-core unit.

2. The microprocessor according to claim 1, wherein: The synchronization range includes 2 bits, the 0th bit of the synchronization range indicates whether it is the second range, and the 1st bit of the synchronization range indicates whether it is the third range.

3. The microprocessor according to claim 2, wherein: The 0th bit and the 1st bit of the synchronization range are both 0, indicating that it is the first range; the 0th bit of the synchronization range is 1 and the 2nd bit is 0, indicating that it is the second range; and the 1st bit of the synchronization range is 1, indicating that it is the third range.

4. The microprocessor according to claim 1, wherein: The synchronization range includes a first range, a second range and a third range, wherein the third range includes at least one second range, the second range includes at least one first range, wherein the second range is one of the at least one second range, and the first range is one of the at least one first range.

5. The microprocessor according to claim 4, wherein: The number of processing cores in the second range is twice the number of processing cores in the first range, and the number of processing cores in the third range is twice the number of processing cores in the second range.

6. The microprocessor according to claim 4, wherein: The first range is all processing cores in the core group, the second range is all processing cores in the crystal, and the third range is all processing cores in the microprocessor.

7. The microprocessor according to claim 1, wherein: When all other processing cores in the synchronization range send synchronization requests of the synchronization type being situation synchronization, and the synchronization values ​​in the synchronization requests of all other processing cores in the synchronization range are the same as the synchronization value, the control unit wakes up all processing cores in the synchronization range.

8. The microprocessor according to claim 7, wherein: The control unit determines whether the synchronization value of the processing core is equal to the synchronization value of each of the other processing cores within the synchronization range to obtain multiple judgment results. When the multiple judgment results are all "equal", it means that the synchronization value in the synchronization request of all other processing cores within the synchronization range is the same as the synchronization value.

9. The microprocessor of claim 4, wherein: When the synchronization type is sleep synchronization, the synchronization range is the second range or the third range.

10. The microprocessor of claim 9, wherein: The control unit selects a lower synchronization value from the synchronization value of the processing core and the synchronization value of each processing core in all other processing cores within the synchronization range to obtain multiple lower synchronization values, wherein the minimum synchronization value is the minimum value of the multiple lower synchronization values.

11. The microprocessor of claim 9, wherein: The synchronization request also includes a synchronization value, which corresponds to a sleep state. The larger the synchronization value is, the deeper the sleep depth of the processing core is.

12. A synchronization method, applicable to a microprocessor having multiple processing cores, the synchronization method comprising: receiving a synchronization request from a processing core, wherein the processing core is one of the plurality of processing cores, the synchronization request including a synchronization type and a synchronization range, wherein the synchronization range refers to all processing cores to be synchronized; and Determine whether all other processing cores within the synchronization range have sent synchronization requests of the synchronization type. Wherein, when the synchronization type is situation synchronization, the synchronization request also includes a synchronization value, and the synchronization value includes multiple bits, which are used to represent multiple different situation synchronizations; when each processing core within the synchronization range has sent the synchronization request, the execution of the subsequent code to be executed will be stopped, and when all other processing cores within the synchronization range have sent a synchronization request with the synchronization type being situation synchronization, and the synchronization value in the synchronization request of all other processing cores within the synchronization range is the same as the synchronization value, it means that all other processing cores within the synchronization range have sent a synchronization request of the synchronization type, and the control unit notifies each processing core among the multiple processing cores to start to continue to execute the code to be executed at the same time; When the synchronization type is sleep synchronization; when all other processing cores within the synchronization range have sent a synchronization request with the synchronization type being sleep synchronization, it means that all other processing cores within the synchronization range have sent a synchronization request of the synchronization type, Among them, when all other processing cores within the synchronization range have sent synchronization requests with the synchronization type being sleep synchronization, the control unit selects the minimum synchronization value among the synchronization values ​​of all processing cores within the synchronization range, and uses the sleep state corresponding to the minimum synchronization value as the sleep state of the non-core unit.

13. The synchronization method according to claim 12, wherein: The synchronization range includes 2 bits, the 0th bit of the synchronization range indicates whether it is the second range, and the 1st bit of the synchronization range indicates whether it is the third range.

14. The synchronization method according to claim 13, wherein: The 0th bit and the 1st bit of the synchronization range are both 0, indicating that it is the first range; the 0th bit of the synchronization range is 1 and the 2nd bit is 0, indicating that it is the second range; and the 1st bit of the synchronization range is 1, indicating that it is the third range.

15. The synchronization method according to claim 12, wherein: The synchronization range includes a first range, a second range and a third range, wherein the third range includes at least one second range, the second range includes at least one first range, wherein the second range is one of the at least one second range, and the first range is one of the at least one first range.

16. The synchronization method according to claim 15, wherein: The number of processing cores in the second range is twice the number of processing cores in the first range, and the number of processing cores in the third range is twice the number of processing cores in the second range.

17. The synchronization method according to claim 15, wherein: The first range is all processing cores in the core group, the second range is all processing cores in the crystal, and the third range is all processing cores in the microprocessor.

18. The synchronization method according to claim 12, further comprising: When all other processing cores in the synchronization range send synchronization requests of the synchronization type being situation synchronization, and the synchronization values ​​in the synchronization requests of all other processing cores in the synchronization range are the same as the synchronization value, the control unit wakes up all processing cores in the synchronization range.

19. The synchronization method according to claim 18, further comprising: The control unit determines whether the synchronization value of the processing core is equal to the synchronization value of each of the other processing cores within the synchronization range to obtain multiple judgment results. When the multiple judgment results are all "equal", it means that the synchronization value in the synchronization request of all other processing cores within the synchronization range is the same as the synchronization value.

20. The synchronization method according to claim 15, wherein: When the synchronization type is sleep synchronization, the synchronization range is the second range or the third range.

21. The synchronization method according to claim 20, further comprising: The control unit selects a lower synchronization value from the synchronization value of the processing core and the synchronization value of each processing core in all other processing cores within the synchronization range to obtain multiple lower synchronization values, wherein the minimum synchronization value is the minimum value of the multiple lower synchronization values.

22. The synchronization method according to claim 20, wherein: The synchronization request also includes a synchronization value, which corresponds to a sleep state. The larger the synchronization value is, the deeper the sleep depth of the processing core is.

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