Memory device

Abstract

A memory device is provided, the memory device comprising: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of word lines extending along a first direction and stacked along a second direction substantially perpendicular to the first direction; and a plurality of transfer transistors disposed in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is disposed between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, and wherein the plurality of signal lines and a common source line are arranged at the same horizontal level.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0066996, filed on June 5, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a memory device, and more specifically, to a non-volatile memory device having a cell overperiphery (COP) structure. Background Technology

[0003] As information and communication devices become more multifunctional, there is a need for highly integrated memory devices with large capacities. Due to the reduction in the size of memory cells to increase the integration of memory devices, the operating circuitry and / or wiring structure of memory devices has become complex. Therefore, techniques are being developed for designing highly integrated memory devices with excellent electrical characteristics. In particular, to increase the integration of memory devices, the number of word lines stacked on the substrate in the vertical direction can be increased. However, in this case, the number of transmission transistors connected to the word lines increases, thus increasing the chip size. Summary of the Invention

[0004] According to an exemplary embodiment of the inventive concept, a memory device is provided, the memory device comprising: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of word lines extending along a first direction and stacked along a second direction substantially perpendicular to the first direction; and a plurality of transmission transistors disposed in the first semiconductor layer, wherein a first transmission transistor of the plurality of transmission transistors is disposed between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, wherein the plurality of signal lines and a common source line are arranged at the same horizontal level.

[0005] According to an exemplary embodiment of the inventive concept, a memory device is provided, the memory device comprising: a memory cell array including a plurality of word lines stacked in a vertical direction; and a plurality of vertical transmission transistors, wherein a first vertical transmission transistor of the plurality of vertical transmission transistors includes a first vertical channel extending in a vertical direction between a first drive signal line and the first word line of the plurality of word lines, wherein the first vertical channel is disposed near an end of the first word line, and wherein the first drive signal line and the common source line are arranged in the same layer.

[0006] According to an exemplary embodiment of the inventive concept, a memory device is provided, the memory device including a first semiconductor layer, the first semiconductor layer including: a memory cell array including a plurality of word lines stacked in a vertical direction; and a plurality of transfer transistors, a first transfer transistor of the plurality of transfer transistors being connected to a drive signal line, wherein the drive signal line is connected to a gate disposed on the same layer as a ground select line. Attached Figure Description

[0007] The above and other features of the inventive concept will be more clearly understood by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

[0009] Figure 2 The structure of a memory device according to an exemplary embodiment of the inventive concept is shown;

[0010] Figure 3 An array of memory cells is shown according to an exemplary embodiment of the inventive concept;

[0011] Figure 4 An equivalent circuit of a memory block according to an exemplary embodiment of the inventive concept is shown;

[0012] Figure 5 A line decoder and a transmission transistor circuit according to an exemplary embodiment of the inventive concept are shown;

[0013] Figure 6 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of a memory device with a transmission transistor circuit;

[0014] Figure 7 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of a memory device with a transmission transistor circuit;

[0015] Figure 8 A line decoder and a transmission transistor circuit according to an exemplary embodiment of the inventive concept are shown;

[0016] Figure 9 This illustrates exemplary embodiments according to the inventive concept, including... Figure 8 A cross-sectional view of a memory device with a transmission transistor circuit;

[0017] Figure 10 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A top view of a memory device with a transmission transistor circuit;

[0018] Figure 11 It is an exemplary embodiment based on the inventive concept. Figure 10 A sectional view taken by line XI-XI';

[0019] Figure 12 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of a memory device with a transmission transistor circuit;

[0020] Figure 13 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of a memory device with a transmission transistor circuit;

[0021] Figure 14 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A top view of a memory device with a transmission transistor circuit;

[0022] Figure 15 It is an exemplary embodiment based on the inventive concept. Figure 14 A cross-sectional view taken by line XV-XV';

[0023] Figure 16 It is an exemplary embodiment based on the inventive concept. Figure 14 A sectional view taken by line XVI-XVI';

[0024] Figure 17 This illustrates the voltage applied to the word line drive signal line via memory operation according to an exemplary embodiment of the inventive concept;

[0025] Figure 18 A line decoder and a transmission transistor circuit according to an exemplary embodiment of the inventive concept are shown;

[0026] Figure 19 This illustrates exemplary embodiments according to the inventive concept, including... Figure 18 A cross-sectional view of a memory device with a transmission transistor circuit;

[0027] Figure 20 , Figure 21 and Figure 22 These are perspective views showing exemplary embodiments of a memory device according to the inventive concept.

[0028] Figure 23 The top surface of a memory device according to a comparative example and the top surface of a memory device according to an exemplary embodiment of the inventive concept are shown.

[0029] Figure 24 yes Figure 23 Enlarged views of the first and second regions;

[0030] Figure 25 This is a top view showing a first surface of a first semiconductor layer included in a memory device according to an exemplary embodiment of the inventive concept;

[0031] Figure 26 and Figure 27 A memory device according to an exemplary embodiment of the inventive concept is shown;

[0032] Figure 28 The structure of a memory device according to an exemplary embodiment of the inventive concept is shown;

[0033] Figure 29 This illustrates exemplary embodiments based on the inventive concept. Figure 28 A cross-sectional view of a memory device; and

[0034] Figure 30 This is a block diagram illustrating an example of a memory device applied to a solid-state drive (SSD) system according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0035] In the following description, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals may refer to the same elements.

[0036] Figure 1 This is a block diagram illustrating a memory device 10 according to an exemplary embodiment of the inventive concept.

[0037] Reference Figure 1 The memory device 10 may include a memory cell array 100 and peripheral circuitry 200. The peripheral circuitry 200 may include a transfer transistor circuit 210, a row decoder 220, control logic 230, and a page buffer 240. The peripheral circuitry 200 may also include a voltage generator, data input and output circuitry, input and output interfaces, column logic, a pre-decoder, a temperature sensor, a command decoder, or an address decoder. In an exemplary embodiment of the inventive concept, the memory device 10 may be a non-volatile memory device. Hereinafter, "memory device" may be referred to as a non-volatile memory device.

[0038] In one exemplary embodiment of the inventive concept, the memory cell array 100, the transmission transistor circuit 210, and the line decoder 220 may be arranged on the upper semiconductor layer (e.g., Figure 2 In L1), control logic 230 and page buffer 240 can be arranged in the lower semiconductor layer (e.g., Figure 2In L2). However, the inventive concept is not limited thereto. In another exemplary embodiment of the inventive concept, the memory cell array 100 and the transmission transistor circuit 210 may be arranged in the upper semiconductor layer, and the row decoder 220, control logic 230, and page buffer 240 may be arranged in the lower semiconductor layer. In another exemplary embodiment of the inventive concept, some circuitry of the circuitry constructing the row decoder 220 may be arranged together with the memory cell array 100 and the transmission transistor circuit 210 in the upper semiconductor layer, and other circuitry of the control logic 230, page buffer 240, and the circuitry constructing the row decoder 220 may be arranged in the lower semiconductor layer.

[0039] In an exemplary embodiment of the inventive concept, the transmission transistor circuit 210 may include a plurality of vertical transmission transistors (e.g., Figure 6 (TR1 to TRs). For example, multiple vertical transmission transistors can be arranged in the upper semiconductor layer. In an exemplary embodiment of the inventive concept, the transmission transistor circuit 210 may include multiple vertical transmission transistors (e.g., TR1 to TRs). Figure 22 TR1 to TRm) and multiple common transmission transistors (e.g., Figure 22 (TRn). For example, multiple vertical transmission transistors can be arranged in the upper semiconductor layer, and multiple ordinary transmission transistors can be arranged in the lower semiconductor layer. In this case, the first part of the transmission transistor circuit 210 can be arranged on the upper semiconductor layer, and the second part of the transmission transistor circuit 210 can be arranged on the lower semiconductor layer.

[0040] The memory cell array 100 can be connected to the page buffer 240 via the bit line BL, and can be connected to the transmission transistor circuit 210 via the word line WL, the serial select line SSL, and the ground select line GSL. Furthermore, the transmission transistor circuit 210 can be connected to the row decoder 220 via the block select signal line BS, the serial select line drive signal line SS, the word line drive signal line SI, and the ground select line drive signal line GS. The serial select line drive signal line SS, the word line drive signal line SI, and the ground select line drive signal line GS can be referred to as "drive signal lines".

[0041] Furthermore, the memory cell array 100 may include a plurality of memory cells, and the memory cells may be, for example, flash memory cells. In the following, exemplary embodiments of the inventive concept will be described in detail with reference to an example where the plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto. In some exemplary embodiments of the inventive concept, the plurality of memory cells may be resistive memory cells (such as resistive random access memory (ReRAM), phase-change RAM (PRAM), or magnetic RAM (MRAM)).

[0042] In an exemplary embodiment of the inventive concept, the memory cell array 100 may include a three-dimensional memory cell array, which may include a plurality of NAND strings, and each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. (Refer to...) Figure 3 and Figure 4 This construction is described. The construction of a three-dimensional memory array is described by reference to the following patent documents, all of which are incorporated herein by reference: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Publication No. 2011 / 0233648. However, the inventive concept is not limited thereto. In some exemplary embodiments of the inventive concept, the memory cell array 100 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0043] Control logic 230 can generate various control signals for programming data into, reading data from, or erasing data stored in memory cell array 100 based on command CMD, address ADDR, and control signal CTRL. For example, control logic 230 can output row address X-ADDR to row decoder 220 and column address Y-ADDR to page buffer 240. Therefore, control logic 230 can control various operations in memory device 10.

[0044] In response to row address X-ADDR, row decoder 220 can output a block select signal for selecting one of a plurality of memory blocks to block select signal line BS. Furthermore, in response to row address X-ADDR, row decoder 220 outputs a word line drive signal for selecting one of the word lines WL of the selected memory block to word line drive signal line SI, a serial select line drive signal for selecting one of the serial select lines SSL to serial select line drive signal line SS, and a ground select line drive signal for selecting one of the ground select lines GSL to ground select line drive signal line GS. In response to column address Y-ADDR, page buffer 240 can select a subset of bit lines BL. For example, page buffer 240 operates as a write driver or a sense amplifier depending on the operating mode.

[0045] As the number of memory cell levels arranged in the memory cell array 100 increases, in other words, as the number of word lines WL stacked vertically increases, the number of vertical transmission transistors used to drive the word lines WL increases. Therefore, the area occupied by the transmission transistor circuit 210 increases. On the other hand, as the number of word lines WL stacked vertically increases, the area of ​​the memory cell array 100 decreases. When the memory device 10 is implemented using a cell-on-periphery (COP) structure, when the area of ​​the memory cell array 100 decreases, the area of ​​the peripheral circuitry arranged below the memory cell array 100 also decreases, so the entire peripheral circuitry 200 may not need to be arranged below the memory cell array 100.

[0046] According to this embodiment of the inventive concept, the transmission transistor circuit 210 can be arranged in the stepped region of the word line WL (e.g., Figure 6 In other words, the transfer transistor circuit 210 may be located in the region where the word line WL has a stepped shape. In an exemplary embodiment of the inventive concept, the transfer transistor circuit 210 may include a plurality of vertical transfer transistors arranged in the stepped region of the word line WL. Therefore, since the region where the transfer transistor circuit 210 is arranged overlaps with the stepped region of the word line WL, the chip size of the memory device 10 can be prevented from increasing even if the number of vertical transfer transistors increases with the increase of the number of stacked word lines WL.

[0047] Figure 2 The structure of a memory device 10 according to an exemplary embodiment of the inventive concept is shown.

[0048] Reference Figure 1 and Figure 2 The memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 along a vertical direction VD. For example, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 along a vertical direction VD.

[0049] In an exemplary embodiment of the inventive concept, the memory cell array 100, the transmission transistor circuit 210, and the row decoder 220 can be formed in a first semiconductor layer L1, and the control logic 230 and the page buffer 240 can be formed in a second semiconductor layer L2. Therefore, the memory device 10 can have a structure in which the memory cell array 100 is arranged on a portion of the peripheral circuitry; in other words, the memory device 10 can have a COP structure. In the COP structure, the horizontal area can be reduced, and the integration density of the memory device 10 can be increased.

[0050] In an exemplary embodiment of the inventive concept, the second semiconductor layer L2 may include a substrate. Circuitry including control logic 230 and page buffer 240 can be formed in the second semiconductor layer L2 by forming semiconductor devices such as transistors on the substrate and by patterning for wiring the semiconductor devices. After forming the circuitry in the second semiconductor layer L2, a first semiconductor layer L1 including a memory cell array 100, a transmission transistor circuit 210, and a row decoder 220 can be formed, and patterns for electrically connecting bit lines BL of the memory cell array 100 to the circuitry formed in the second semiconductor layer L2 or patterns for electrically connecting the row decoder 220 to the circuitry formed in the second semiconductor layer L2 can be formed.

[0051] Figure 3 A memory cell array 100 according to an exemplary embodiment of the inventive concept is shown.

[0052] Reference Figure 3 The memory cell array 100 may include multiple memory blocks BLK1 to BLKi (“i” can be a positive integer). Each of the multiple memory blocks BLK1 to BLKi may have a three-dimensional structure (or a vertical structure). For example, each of the multiple memory blocks BLK1 to BLKi may include multiple NAND strings extending along the vertical direction VD. In this case, the multiple NAND strings may be spaced apart from each other along a first horizontal direction HD1 and a second horizontal direction HD2. This can be achieved by a line decoder (…). Figure 1 The row decoder 220 can select multiple memory blocks BLK1 to BLKi. For example, the row decoder 220 can select the memory block corresponding to the block address from the multiple memory blocks BLK1 to BLKi.

[0053] Figure 4 An equivalent circuit of a memory block BLK according to an exemplary embodiment of the inventive concept is shown. For example, the memory block BLK may correspond to... Figure 3 One of the multiple memory blocks BLK1 to BLKi.

[0054] Reference Figure 4 The memory block BLK may include: multiple NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33; multiple word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8; multiple bit lines BL1, BL2, and BL3; multiple ground select lines GSL1, GSL2, and GSL3; multiple string select lines SSL1, SSL2, and SSL3; and a common-source line CSL. Here, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines can vary according to exemplary embodiments of the inventive concept.

[0055] NAND strings NS11, NS21, and NS31 are positioned between the first bit line BL1 and the common source line CSL; NAND strings NS12, NS22, and NS32 are positioned between the second bit line BL2 and the common source line CSL; and NAND strings NS13, NS23, and NS33 are positioned between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MCs, and a ground select transistor GST connected in series with each other.

[0056] The serial select transistor SST is connected to the corresponding serial select lines SSL1 to SSL3. Multiple memory cells MCs are connected to their corresponding word lines WL1 to WL8. The ground select transistor GST is connected to its corresponding ground select lines GSL1 to GSL3. The serial select transistor SST is connected to its corresponding bit lines BL1 to BL3, and the ground select transistor GST is connected to the common source line CSL.

[0057] In this embodiment of the inventive concept, word lines of the same height (e.g., WL1) are connected together, string select lines SSL1 to SSL3 are separate from each other, and ground select lines GSL1 to GSL3 are separate from each other. Figure 4 The diagram illustrates string select lines SSL1 through SSL3 sharing word lines of the same height. However, the inventive concept is not limited to this. For example, two string select lines can share word lines of the same height. In another example, four string select lines can share word lines of the same height.

[0058] Figure 5 The diagram illustrates a line decoder 220a and a transmission transistor circuit 210a according to an exemplary embodiment of the inventive concept.

[0059] Reference Figure 5 The memory block BLKa can correspond to Figure 3 The memory block BLK1 to BLKi is used, and "a" can be a positive integer. The line decoder 220a can be... Figure 1 In the example of line decoder 220, the transmission transistor circuit 210a can be Figure 1 An example of the transmission transistor circuit 210. Therefore, the above refers to... Figures 1 to 4 The detailed description can be applied to the current embodiment.

[0060] The line decoder 220a may include a block decoder 221 and a drive signal line decoder 222a. The transmission transistor circuit 210a may include multiple vertical transmission transistors TRs, TR1 to TRm, and TRg, where "m" can be a positive integer. The transmission transistor circuit 210a may be located within a memory block ( Figure 3In each of BLK1 to BLKi, and the block decoder 221 and the drive signal line decoder 222a can be jointly configured to the memory block ( Figure 3 (BLK1 to BLKi).

[0061] The block decoder 221 can be connected to the transmission transistor circuit 210a via the block select signal line BS. For example, the block select signal line BS can be connected to the gates of multiple vertical transmission transistors TRs, TR1 to TRm, and TRg. For example, when the block select signal provided via the block select signal line BS is activated, the multiple vertical transmission transistors TRs, TR1 to TRm, and TRg are turned on. Therefore, the memory block BLKa can be selected.

[0062] The drive signal line decoder 222a can be connected to the transmission transistor circuit 210a via the serial select line drive signal line SS, the word line drive signal lines SI1 to SIm, and the ground select line drive signal line GS. For example, the serial select line drive signal line SS, the word line drive signal lines SI1 to SIm, and the ground select line drive signal line GS can be connected to the sources of multiple vertical transmission transistors TRs, TR1 to TRm, and TRg, respectively.

[0063] The transmission transistor circuit 210a can be connected to the memory block BLKa via the ground select line GSL, multiple word lines WL1 to WLm, and the serial select line SSL. Vertical transmission transistors TR1 to TRm can connect the multiple word lines WL1 to WLm to their respective word line drive signal lines SI1 to SIm. Vertical transmission transistor TRs can connect the serial select line SSL to its corresponding serial select line drive signal line SS. Vertical transmission transistor TRg can connect the ground select line GSL to its corresponding ground select line drive signal line GS. The drains of vertical transmission transistors TRs, TR1 to TRm, and TRg can be connected to the memory block BLKa. For example, when the block select signal is activated, vertical transmission transistors TRs, TR1 to TRm, and TRg can provide drive signals via the serial select line drive signal line SS, word line drive signal lines SI1 to SIm, and ground select line drive signal line GS to the serial select line SSL, the multiple word lines WL1 to WLm, and the ground select line GSL, respectively.

[0064] In an exemplary embodiment of the present invention, the vertical transmission transistors TRs and TR1 to TRm can be implemented using vertical transmission transistors. In this specification, a "vertical transmission transistor" can be a transistor comprising a vertical channel. For example, the vertical transmission transistors TRs and TR1 to TRm can be arranged in a stepped region of a word line (e.g., Figure 6In an exemplary embodiment of the inventive concept, the vertical transmission transistor TRg can be implemented by a common transmission transistor. In the present specification, a "common transmission transistor" can be a transistor including a horizontal channel. For example, the vertical transmission transistor TRg can be arranged in the decoder region (e.g., Figure 23 In DAa), this will refer to Figures 6 to 8 Describe in detail.

[0065] Figure 6 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of a memory device 10a with a transmission transistor circuit.

[0066] Reference Figure 6 The memory device 10a may include a memory cell array 100a, a plurality of vertical transmission transistors TR1 to TRm and TRs, and a plurality of drive signal lines SI1 to SIm and SS. For example, the memory device 10a may correspond to Figure 2 A portion of the first semiconductor layer L1, and page buffers or control logic may be arranged along the vertical direction VD below the memory cell array 100a, multiple vertical transmission transistors TR1 to TRm and TRs, and multiple drive signal lines SI1 to SIm and SS.

[0067] Memory cell array 100a can be arranged in cell region CA and can include multiple word lines WL1 to WLm. The multiple word lines WL1 to WLm can be stacked along the vertical direction VD and can extend along the first horizontal direction HD1. The multiple word lines WL1 to WLm can be electrically insulated by multiple insulating layers. One end of each of the multiple word lines WL1 to WLm along the first horizontal direction HD1 can be implemented in a stepped shape. In the present specification, the stepped shape is located in stepped region SA.

[0068] Furthermore, the memory cell array 100a may also include a common-source line CSL disposed below the plurality of word lines WL1 to WLm. In an exemplary embodiment of the inventive concept, the common-source line CSL and the plurality of drive signal lines SI1 to SIm and SS may be arranged at the same horizontal level. For example, the common-source line CSL and the plurality of drive signal lines SI1 to SIm and SS may be arranged at the same horizontal level along a first horizontal direction HD1. In an exemplary embodiment of the inventive concept, the common-source line CSL and the plurality of drive signal lines SI1 to SIm and SS may be implemented by a metal layer MT. For example, the common-source line CSL may be implemented by a metal plate or conductive plate of the metal layer MT.

[0069] Furthermore, the memory cell array 100a may also include a vertical channel structure VP. The vertical channel structure VP may extend along a vertical direction VD and may pass through multiple word lines WL1 to WLm and multiple insulating layers. The vertical channel structure VP may be referred to as a vertical pillar. In an exemplary embodiment of the inventive concept, the vertical channel structure VP may have a first width W1 along a first horizontal direction HD1. For example, multiple vertical channel structures VP may be formed in a ring. In this case, the first width W1 may correspond to a first channel aperture size. However, the inventive concept is not limited thereto. The vertical channel structure VP may be in the form of an elliptical pillar or a rectangular pillar. Multiple vertical channel structures VP may be spaced apart from each other along the first horizontal direction HD1 and the second horizontal direction HD2.

[0070] In one exemplary embodiment of the inventive concept, the vertical channel structure VP may include a charge storage layer CS, a channel layer CL, and an inner layer I. The channel layer CL may include a first type (e.g., p-type) silicon material and may serve as the channel region. The inner layer I may include an insulating material such as silicon oxide or an air gap. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunneling insulating layer"), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure.

[0071] Drains or drain contacts (DRs) are disposed on multiple vertical channel structures (VPs). For example, the drains or drain contacts (DRs) may comprise silicon material doped with a second type (e.g., n-type) impurity. Bit lines (BLs) may be disposed above the drain contacts (DRs) and may be connected to the drain contacts (DRs) via bit line contacts (BLCs).

[0072] Furthermore, the memory cell array 100a may also include a ground select line GSL between multiple word lines WL1 to WLm and the common source line CSL, and a serial select line SSL disposed above the multiple word lines WL1 to WLm. Figure 6 The diagram shows a memory device 10a including a single string select line SSL. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the memory device 10a may include two string select lines stacked along the vertical direction VD (e.g., Figure 12 (SSLu and SSLd).

[0073] Multiple vertical transmission transistors TR1 to TRm and TRs can be arranged in the stepped region SA of multiple word lines WL1 to WLm. The multiple vertical transmission transistors TR1 to TRm can be connected between their respective word lines and corresponding word line drive signal lines. For example, the first vertical transmission transistor TR1 can be connected between the first word line WL1 and the first word line drive signal line SI1, the second vertical transmission transistor TR2 can be connected between the second word line WL2 and the second word line drive signal line SI2, and the m-th vertical transmission transistor TRm can be connected between the m-th word line WLm and the m-th word line drive signal line SIm. Vertical transmission transistors TRs can be connected between the serial select line SSL and the serial select line drive signal line SS.

[0074] Each of the plurality of vertical transmission transistors TR1 to TRm and TRs may include a vertical channel VC extending along the vertical direction VD. For example, the vertical channel VC of the first vertical transmission transistor TR1 may extend vertically from the first word line drive signal line SI1. The vertical channel VC may have a second width W2 at the same level that is greater than the first width W1, and the width of the vertical channel VC located between the gate GT and the first word line WL1 may be larger than the width of the vertical channel VC located below the gate GT. Therefore, the breakdown problem associated with the plurality of vertical transmission transistors TR1 to TRm and TRs can be solved. For example, the second width W2 may be approximately not less than twice the first width W1. However, the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, the first width W1 and the second width W2 may vary. In an exemplary embodiment of the inventive concept, the heights of the plurality of vertical channels VC along the vertical direction VD may be equal to each other as a first height H1. In an exemplary embodiment of the inventive concept, the top surface level of the plurality of vertical channels VC may be lower than the bottom surface level of the first word line WL1. In an exemplary embodiment of the inventive concept, the top surface level of the plurality of vertical channels VC can be disposed between the bottom surface level of the first word line WL1 and the gate GT.

[0075] In an exemplary embodiment of the inventive concept, the vertical channel VC can be formed using the same process as the vertical channel structure VP to have the same structure as the vertical channel structure VP. Therefore, the vertical channel VC may also include a charge storage layer CS, a channel layer CL, and an inner layer I. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the vertical channel VC may include only the channel layer CL and the inner layer I.

[0076] Furthermore, the vertical channels VC included in the plurality of vertical transmission transistors TR1 to TRm and TRs can be commonly connected to the gate GT. In the current embodiment, the gate GT, which is commonly connected to the plurality of vertical transmission transistors TR1 to TRm and TRs, can be arranged at the same level as the ground select line GSL. In some embodiments of the inventive concept, the vertical channels VC included in the plurality of vertical transmission transistors TR1 to TRm and TRs can be connected to different gates GT, and the lengths of the different gates GT in the vertical direction VD can be different from each other. Therefore, the driving capabilities of the plurality of vertical transmission transistors TR1 to TRm and TRs can be different from each other.

[0077] In some embodiments of the inventive concept, the length of the gate GT in the vertical direction VD may be equal to the length of the ground select line GSL in the vertical direction VD. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the length of the gate GT in the vertical direction VD may be equal to the length of each of the word lines WL1 to WLm in the vertical direction VD. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the length of the gate GT in the vertical direction VD may be equal to the length of the string select line SSL in the vertical direction VD. However, the inventive concept is not limited thereto.

[0078] Multiple contacts CP1 to CPm and CPs can be respectively arranged on multiple vertical transmission transistors TR1 to TRm and TRs. The multiple vertical transmission transistors TR1 to TRm can be connected to corresponding word lines WL1 to WLm via corresponding contacts CP1 to CPm, and the vertical transmission transistor TRs can be connected to the string select line SSL via contact CPs. In an exemplary embodiment of the inventive concept, the heights of the multiple contacts CP1 to CPm and CPs in the vertical direction VD can be equal to each other, forming a second height H2. For example, the top surface level of the multiple contacts CP1 to CPm and CPs can be equal to the top surface level of the string select line SSL.

[0079] In one exemplary embodiment of the inventive concept, the line decoder 220a may be adjacent to the plurality of vertical transmission transistors TR1 to TRm and TRs along a first horizontal direction HD1 or a second horizontal direction HD2. However, the inventive concept is not limited thereto. At least one of the block decoder 221 and the drive signal line decoder 222a may be arranged below the plurality of vertical transmission transistors TR1 to TRm and TRs along a vertical direction VD.

[0080] Figure 7 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of the memory device 10b with a transmission transistor circuit.

[0081] Reference Figure 7 The memory device 10b may include a first semiconductor layer L1 and a second semiconductor layer L2, and may correspond to Figure 6 A variation of the memory device 10a shown. The second semiconductor layer L2 may include a substrate SUB, a first lower insulating layer IL21, and a second lower insulating layer IL22. For example, Figure 1 The control logic 230 or page buffer 240 can be arranged in the second semiconductor layer L2.

[0082] The substrate SUB can be a semiconductor substrate comprising semiconductor materials such as single-crystal silicon or single-crystal germanium (Ge), and can be fabricated from a silicon wafer. The first lower insulating layer IL21 and the second lower insulating layer IL22 can be formed from an insulating material such as silicon oxide using a chemical vapor deposition (CVD) process or a spin-coating process. Multiple semiconductor devices, including transistor TR, can be formed on the substrate SUB included in the second semiconductor layer L2. The transistor TR can be electrically connected via a contact CP21 formed in the second lower insulating layer IL22, the contact CP21 passing through the first lower insulating layer IL21.

[0083] The first semiconductor layer L1 can be stacked on the second semiconductor layer L2. For example, Figure 5 The transmission transistor circuit 210a and the memory block BLKa can be arranged in the first semiconductor layer L1. The first semiconductor layer L1 may include a base layer BP and an upper insulating layer IL1. In an exemplary embodiment of the inventive concept, the base layer BP can be formed from polycrystalline silicon by a sputtering process, a CVD process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process.

[0084] In an exemplary embodiment of the inventive concept, the base layer BP can be formed by forming an amorphous silicon layer on the second lower insulating layer IL22 and transforming the amorphous silicon layer into a monocrystalline silicon layer by performing heat treatment on the amorphous silicon layer or irradiating the amorphous silicon layer with a laser beam. Therefore, defects in the base layer BP can be removed. In an exemplary embodiment of the inventive concept, the base layer BP can be formed by a wafer bonding process. In this case, the base layer BP can be formed on the second lower insulating layer IL22 by attaching a monocrystalline silicon wafer to the second lower insulating layer IL22 and partially removing or planarizing the top of the monocrystalline silicon wafer.

[0085] The first word line drive signal line SI1 can be disposed on the base layer BP and can extend along the second horizontal direction HD2. The first word line drive signal line SI1 can be electrically connected to the transistor TR included in the second semiconductor layer L2 via contacts CP11, CP21, and CP12 and metal patterns MP11 and MP21. For example, the transistor TR formed in the second semiconductor layer L2 can be configured with… Figure 5The circuit corresponding to the drive signal line decoder 222a.

[0086] Figure 8 The diagram illustrates a line decoder 220a' and a transmission transistor circuit 210a' according to an exemplary embodiment of the inventive concept.

[0087] Reference Figure 8 The memory block BLKa' can correspond to Figure 3 One of the memory blocks BLK1 to BLKi. With Figure 5 Compared to the memory block BLKa, the memory block BLKa' may further include first dummy word lines to fourth dummy word lines DWL1, DWL2, DWL3, and DWL4. The first dummy word line DWL1 and the second dummy word line DWL2 may be arranged between the ground select line GSL and the first word line WL1, and the third dummy word line DWL3 and the fourth dummy word line DWL4 may be arranged between the m-th word line WLm and the string select line SSL. In some embodiments of the inventive concept, the memory block BLKa' may include at least one of the first dummy word lines DWL1 to the fourth dummy word line DWL4. According to exemplary embodiments of the inventive concept, the number of dummy word lines included in the memory block BLKa' may vary.

[0088] Line decoder 220a' can correspond to Figure 5 A variant of the line decoder 220a, the transmission transistor circuit 210a' can correspond to Figure 5 A variation of the transmission transistor circuit 210. With Figure 5 Compared to the transmission transistor circuit 210, the transmission transistor circuit 210a' may further include vertical transmission transistors TRd1, TRd2, TRd3, and TRd4. The vertical transmission transistors TRd1 to TRd4 can respectively connect the dummy word lines DWL1 to DWL4 to the corresponding dummy word line drive signal lines DSI1, DSI2, DSI3, and DSI4.

[0089] Figure 9 This is an illustrative representation of an exemplary embodiment according to the inventive concept, including... Figure 8 A cross-sectional view of a memory device 10a' with a transmission transistor circuit.

[0090] Reference Figure 9The memory device 10a' may include: a memory cell array 100a', a plurality of vertical transfer transistors TR1 to TRm, TRs and TRd1 to TRd4, word line drive signal lines SI1 to SIm, a serial select line drive signal line SS, and dummy word line drive signal lines DSI1 to DSI4. The plurality of vertical transfer transistors TR1 to TRm, TRs and TRd1 to TRd4 may be connected to the same gate GT. The length of the contact CPd arranged above the dummy word line drive signal lines DSI1 to DSI4 in the vertical direction VD may be equal to the length of the contacts CP1, CP2 and CPm arranged above the word line drive signal lines SI1 to SIm in the vertical direction VD. The memory device 10a' corresponds to... Figure 6 A variation of the memory device 10a. See above. Figure 6 and Figure 7 The description applies to the current embodiment.

[0091] Figure 10 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A top view of a memory device 10c with a transmission transistor circuit. Figure 11 It is an exemplary embodiment based on the inventive concept. Figure 10 The sectional view taken by line XI-XI'.

[0092] Reference Figure 10 and Figure 11 Multiple drive signal lines SI1, SI2, SI3, and SI4, as well as SS1, SS2, SS3, and SS4, and the common source line CSL can be arranged at the same horizontal level. For example, multiple drive signal lines SI1 to SI4, SS1 to SS4, and the common source line CSL can be formed using the same process. In an exemplary embodiment of the inventive concept, the multiple drive signal lines SI1 to SI4 and SS1 to SS4 extend along a second horizontal direction HD2 and can be spaced apart from each other along a first horizontal direction HD1. In an exemplary embodiment of the inventive concept, the common source line CSL extends along the second horizontal direction HD2 and can be implemented using a metal plate. The multiple drive signal lines SI1 to SI4 and SS1 to SS4 can also be implemented using a metal plate.

[0093] The first word lines WL1 to the fourth word lines WL4 can be formed in a stepped shape within the stepped region SA. The first word line WL1 can be arranged above the gate GT along the vertical direction VD and can include a tungsten region W and a nitride region NT. Here, the tungsten region W can include, for example, a conductive material such as, but not limited to, W. The contact CP1 can pass through the tungsten region W of the first word line WL1. Furthermore, the nitride region NT can include an insulating material such as, but not limited to, nitrides. The second word lines WL2 to the fourth word lines WL4 can be sequentially stacked above the first word line WL1 along the vertical direction VD. The first word line WL1 can be connected to the vertical channel VC1 via the contact CP1, and the vertical channel VC1 can be connected to the first word line drive signal line SI1. The third word line WL3 can be connected to the vertical channel VC2 via the contact CP3, and the vertical channel VC2 can be connected to the third word line drive signal line SI3. The third word line WL3 can also include a tungsten region W, with the contact CP3 passing through the tungsten region W. The first word line WL1 to the fourth word line WL4 can extend along the first horizontal direction HD1, and the word lines arranged at the same horizontal level can be separated by the word line cutting area WLC.

[0094] The first serial select line SSLu1, the second serial select line SSLu2, the third serial select line SSLu3, and the fourth serial select line SSLu4 can be arranged at the same horizontal level and can be separated by the serial select line cutting area SSLC. The first serial select line SSLu1 can be connected to the vertical channel VC3 via contact CPs1, and the vertical channel VC3 can be connected to the serial select line drive signal line SS1. The second serial select line SSLu2 can be connected to the vertical channel VC4 via contact CPs2, and the vertical channel VC4 can be connected to the serial select line drive signal line SS2. The first serial select line SSLu1 and the second serial select line SSLu2 may include tungsten W.

[0095] Figure 12 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of a memory device 10d with a transmission transistor circuit.

[0096] Reference Figure 12 The memory device 10d may include a memory cell array 100a, a transmission transistor circuit 210a, and a block decoder 221a, and the block decoder 221a may be arranged below the transmission transistor circuit 210a along the vertical direction VD. The memory device 10d corresponds to... Figure 11 This is a variation of the memory device 10c, and the previously given description of the memory device 10c is omitted.

[0097] The gate GT, commonly connected to the vertical channel VC, can be connected to the block decoder 221a via wiring including contacts CP13, CP14, CP22, and CP23, and metal patterns MP12, MP21, and MP22. In other words, the block select signal BS output from the block decoder 221a can be provided to the gate GT via wiring including contacts CP13, CP14, CP22, and CP23, and metal patterns MP12, MP21, and MP22. In this case, the block select signal BS can turn on the transistor connected to the gate GT. The metal patterns MP21 and MP22, contacts CP22 and CP23, and the block decoder 221a can be arranged in... Figure 2 In the second semiconductor layer L2.

[0098] Figure 13 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A cross-sectional view of the memory device 10e with a transmission transistor circuit.

[0099] Reference Figure 13 The memory device 10e may include a memory cell array 100a, a transmission transistor circuit 210a, a block decoder 221b, and peripheral circuitry 200a, wherein the peripheral circuitry 200a may be arranged below the transmission transistor circuit 210a along the vertical direction VD. In this case, the block decoder 221b may be adjacent to the peripheral circuitry 200a along the first horizontal direction HD1. However, the inventive concept is not limited thereto. The block decoder 221b may be adjacent to the peripheral circuitry 200a along the second horizontal direction HD2. The memory device 10e corresponds to Figure 11 This is a variation of the memory device 10c, and the previously given description of the memory device 10c is omitted.

[0100] The gate GT, commonly connected to the vertical channel VC, can be connected to the block decoder 221b via wiring including contacts CP13, CP14, CP22, and CP23, and metal patterns MP12, MP21, and MP22. In other words, the block selection signal BS output from the block decoder 221b can be provided to the gate GT via wiring including contacts CP13, CP14, CP22, and CP23, and metal patterns MP12, MP21, and MP22. For example, metal patterns MP21 and MP22, contacts CP22 and CP23, the block decoder 221b, and peripheral circuitry 200a can be arranged in... Figure 2 In the second semiconductor layer L2.

[0101] Figure 14 This illustrates exemplary embodiments according to the inventive concept, including... Figure 5 A top view of the memory device 10f with a transmission transistor circuit.

[0102] Reference Figure 14 Multiple drive signal lines SI1 to SI4 and SS1 to SS4, as well as the common source line CSL, can be arranged at the same horizontal level. For example, the multiple drive signal lines SI1 to SI4 and SS1 to SS4 extend along a second horizontal direction HD2 and can be spaced apart from each other along a first horizontal direction HD1. The gate GT can be arranged above the multiple drive signal lines SI1 to SI4 and SS1 to SS4 along the vertical direction VD and can extend along the first horizontal direction HD1. The first word lines WL1 to the fourth word lines WL4 can be sequentially stacked above the gate GT along the vertical direction VD.

[0103] Figure 15 It is an exemplary embodiment based on the inventive concept. Figure 14 A sectional view taken from line XV-XV'.

[0104] Reference Figure 15 Contacts CP11 can be arranged on multiple drive signal lines SI1 to SI4 and SS1 to SS4 respectively, and the multiple drive signal lines SI1 to SI4 and SS1 to SS4 can be electrically connected to the metal pattern MP11 through contacts CP11 respectively. In this case, the drive signal line decoder 222 can be arranged below the multiple drive signal lines SI1 to SI4 and SS1 to SS4 along the vertical direction VD. The drive signal line decoder 222 can be arranged on... Figure 2 In the second semiconductor layer L2.

[0105] Figure 16 It is an exemplary embodiment based on the inventive concept. Figure 14 A sectional view taken by line XVI-XVI'.

[0106] Reference Figure 16 The word line drive signal line SI1 can be connected to the drive signal line decoder 222 via wiring including contacts CP11, CP12', CP15, and CP16 and metal patterns MP11, MP13, and MP14. In other words, the drive signal line decoder 222 can provide word line drive signals to the first word line drive signal line SI1 via wiring including contacts CP11, CP12', CP15, and CP16 and metal patterns MP11, MP13, and MP14. For example, the word line drive signal can have... Figure 17 The voltage levels shown.

[0107] Figure 17 The diagram illustrates the voltage applied to the word line drive signal line via memory operation according to an exemplary embodiment of the inventive concept.

[0108] Reference Figure 17The selected word line drive signal line SIa corresponds to the drive signal line connected to the selected word line WLsel, and the unselected word line drive signal line SIb may correspond to the drive signal line connected to the unselected word line WLunsel. During programming operations, a programming voltage Vpgm (e.g., about 20V) may be applied to the selected word line drive signal line SIa, and a pass voltage Vpass (e.g., about 9V) may be applied to the unselected word line drive signal line SIb. In an exemplary embodiment of the inventive concept, the programming voltage Vpgm may be about 10V to about 25V, and the pass voltage Vpass may be about 5V to about 15V. During read operations, a read voltage Vr (e.g., about 0V) may be applied to the selected word line drive signal line SIa, and a read pass voltage Vread (e.g., about 6V) may be applied to the unselected word line drive signal line SIb. In an exemplary embodiment of the inventive concept, the read voltage Vr may be about -1V to about 10V, and the read pass voltage Vread may be about 4V to about 10V. During the erase operation, an erase voltage Ver (e.g., about 0V) is applied to both the selected word line drive signal line SIa and the unselected word line drive signal line SIb. In an exemplary embodiment of the inventive concept, the erase voltage Ver can be about -2V to about 3V.

[0109] Figure 18 The diagram illustrates a line decoder 220b and a transmission transistor circuit 210b according to an exemplary embodiment of the inventive concept.

[0110] Reference Figure 18 The memory block BLKb can correspond to Figure 3 The memory block BLK1 to BLKi is used, and "b" can be a positive integer. The line decoder 220b can correspond to... Figure 5 A variant of the line decoder 220a, and the transmission transistor circuit 210b can correspond to Figure 5 A variation of the transmission transistor circuit 210a. Therefore, the previously referenced Figures 1 to 8 The given description applies to the present embodiment. The line decoder 220b may include a block decoder 221 and a drive signal line decoder 222b. The transmission transistor circuit 210b may include a plurality of vertical transmission transistors TRs, TR1 to TRm, TRg, and TRgd.

[0111] The drive signal line decoder 222b can be connected to the transmission transistor circuit 210b via the serial select line drive signal line SS, word line drive signal lines SI1 to SIm, ground select line drive signal line GS, and gate-induced drain-leakage (GIDL) gate drive signal line GDS. For example, the serial select line drive signal line SS, word line drive signal lines SI1 to SIm, ground select line drive signal line GS, and GIDL gate drive signal line GDS can be connected to multiple vertical transmission transistors TRs, TR1 to TRm, TRg, and TRgd, respectively.

[0112] The transmission transistor circuit 210b can be connected to the memory block BLKb via the ground select line GSL, multiple word lines WL1 to WLm, the serial select line SSL, and the GIDL gate line GIDL. The vertical transmission transistor TRgd can be connected to the GIDL gate drive signal line GDS corresponding to the GIDL gate line GIDL. For example, when the block select signal is activated, the multiple vertical transmission transistors TRs, TR1 to TRm, TRg, and TRgd can provide drive signals provided by the serial select line drive signal line SS, word line drive signal lines SI1 to SIm, ground select line drive signal line GS, and GIDL gate drive signal line GDS to the serial select line SSL, multiple word lines WL1 to WLm, ground select line GSL, and GIDL gate line GIDL, respectively.

[0113] In an exemplary embodiment of the inventive concept, a plurality of vertical transmission transistors TRs, TR1 to TRm, and TRg can be implemented using vertical transmission transistors. For example, the plurality of vertical transmission transistors TRs, TR1 to TRm, and TRg can be arranged in the stepped region of the word line (e.g., Figure 6 In an exemplary embodiment of the inventive concept, the vertical transmission transistor TRgd can be implemented by a common transmission transistor. For example, the vertical transmission transistor TRgd can be arranged in the decoder region (e.g., Figure 23 In DAa), this will refer to Figure 19 Describe in detail.

[0114] Figure 19 This illustrates exemplary embodiments according to the inventive concept, including... Figure 18 A cross-sectional view of a memory device 10g with a transmission transistor circuit.

[0115] Reference Figure 19 The memory device 10g may include: a memory cell array 100b, multiple vertical transmission transistors TR1 to TRm, TRs and TRg, and multiple drive signal lines SI1 to SIm, SS and GS. The memory device 10g corresponds to... Figure 6 This is a variation of the memory device 10a, and the previously given description of the memory device 10a is omitted.

[0116] The memory cell array 100b can be arranged in the cell region CA and can include a serial select line SSL, multiple word lines WL1 to WLm, a ground select line GSL, a gate line GIDL GIDL, and a common source line CSL. The serial select line SSL, multiple word lines WL1 to WLm, ground select line GSL, and gate line GIDL GIDL can be stacked along the vertical direction VD and can extend along the first horizontal direction HD1. The serial select line SSL, multiple word lines WL1 to WLm, ground select line GSL, and gate line GIDL GIDL can be electrically insulated by multiple insulating layers.

[0117] Multiple vertical transmission transistors TR1 to TRm, TRs, and TRg can be arranged in the stepped regions SA of multiple word lines WL1 to WLm. Vertical transmission transistor TRg can be connected between the ground select line GSL and the ground select line drive signal line GS. The vertical channels VC included in the multiple vertical transmission transistors TR1 to TRm, TRs, and TRg can be commonly connected to the gate GT. In the current embodiment, the gate GT, which is commonly connected to the vertical channels VC included in the multiple vertical transmission transistors TR1 to TRm, TRs, and TRg, can be arranged at the same level as the GIDL gate line GIDL.

[0118] Multiple contacts CP1 to CPm, CPs, and CPg can be respectively arranged on multiple vertical transmission transistors TR1 to TRm, TRs, and TRg. The multiple vertical transmission transistors TR1 to TRm can be connected to corresponding word lines WL1 to WLm via corresponding contacts CP1 to CPm, vertical transmission transistor TRs can be connected to the serial select line SSL via contact CPs, and vertical transmission transistor TRg can be connected to the ground select line GSL via contact CPg. In an exemplary embodiment of the inventive concept, the heights of the multiple contacts CP1 to CPm, CPs, and CPg in the vertical direction VD can be equal to each other, forming a second height H2'.

[0119] In an exemplary embodiment of the inventive concept, the line decoder 220b may be adjacent to a plurality of vertical transmission transistors TR1 to TRm, TRs, and TRg along a first horizontal direction HD1 or a second horizontal direction HD2. However, the inventive concept is not limited thereto. At least one of the block decoder 221 and the drive signal line decoder 222b of the line decoder 220b may be arranged below the plurality of vertical transmission transistors TR1 to TRm, TRs, and TRg along a vertical direction VD.

[0120] Figure 20 This is a perspective view showing a memory device 10h according to an exemplary embodiment of the inventive concept.

[0121] Reference Figure 20 The memory device 10h may include a plurality of metal lines MT arranged parallel to each other along a first horizontal direction HD1 and extending along a second horizontal direction HD2. The plurality of metal lines MT may include a common source line CSL and an m-th word line drive signal line SIm arranged at the same horizontal level. For example, the common source line CSL may be formed of a metal plate, and the m-th word line drive signal line SIm may be formed in a line shape.

[0122] Memory cell array (e.g., Figure 1 The 100) can be arranged above the common source line CSL. For example, the ground select line GSL, multiple word lines WL1 to WLm, the lower serial select line SSLd, and the upper serial select line SSLu can be stacked vertically above the common source line CSL. The upper serial select line SSLu can include a first to a fourth upper serial select line arranged at the same horizontal level (e.g., Figure 10 (SSLu1 to SSLu4). Multiple vertical channel structures VP extend along the vertical direction VD and can pass through the ground select line GSL, multiple word lines WL1 to WLm, the lower string select line SSLd, and the upper string select line SSLu.

[0123] Drain contacts DR are disposed on multiple vertical channel structures VP, and bit line contacts BLC can be disposed on the drain contacts DR. The drain contacts DR can be implemented by studs. Bit lines BL, spaced apart from each other along a first horizontal direction HD1 and extending along a second horizontal direction HD2, are disposed on the bit line contacts BLC. In some embodiments of the inventive concept, the memory device 10h may not include the bit line contacts BLC, and the bit lines BL may be disposed above the drain contacts DR.

[0124] Transmission transistor circuit (e.g., Figure 1 The 210) can be positioned above the m-word drive signal line SIm. For example, the gate GTm can be positioned above the m-word drive signal line SIm, and the vertical channel VC extending along the vertical direction VD can pass through the gate GTm. The gate GTm and the vertical channel VC can form a vertical transmission transistor TRm. A contact CPm extending along the vertical direction VD can be formed above the vertical channel VC, and the contact CPm can electrically connect the m-word line WLm to the vertical channel VC.

[0125] Furthermore, contacts CP11 and CP11' extending along the vertical direction VD can be arranged above the m-word drive signal line SIm, and a metal pattern MP11 extending along the second horizontal direction HD2 can be arranged above contact CP11'. For example, contact CP11' can be arranged at the same level as the bit line contact BLC. For example, the metal pattern MP11 can be arranged at the same level as the bit line BL. In some embodiments of the inventive concept, the memory device 10d may not include contact CP11', and the metal pattern MP11 may be arranged above contact CP11.

[0126] Figure 21 This is a perspective view showing a memory device 10i according to an exemplary embodiment of the inventive concept.

[0127] Reference Figure 21 The memory device 10i may include a plurality of metal lines MT arranged parallel to each other along a first horizontal direction HD1 and extending along a second horizontal direction HD2. The plurality of metal lines MT may include a common-source line CSL and first word line drive signal lines SI1 to m-th word line drive signal lines SIm arranged at the same horizontal level. For example, the common-source line CSL may be formed of a metal plate. Figure 20 Compared to the memory device 10h, the memory device 10i according to the current embodiment may further include a first word line drive signal line SI1 to a (m-1)th word line drive signal line SIm-1. Therefore, the previously referenced Figure 20 The given description applies to the current embodiment and is omitted.

[0128] Multiple vertical channels VC and multiple gates GT1 to GTm can be arranged above the first word line drive signal line SI1 to the m-th word line drive signal line SIm. The multiple gates GT1 to GTm can extend along a first horizontal direction HD1 and can be spaced apart from each other along a second horizontal direction HD2.

[0129] In exemplary embodiments of the inventive concept, the lengths of the plurality of gates GT1 to GTm in the first horizontal direction HD1 may be different from each other. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the lengths of the plurality of gates GT1 to GTm in the first horizontal direction HD1 may be equal to each other. In exemplary embodiments of the inventive concept, the plurality of gates GT1 to GTm may be arranged at the same level as the ground select line GSL. However, the inventive concept is not limited thereto. In some embodiments of the inventive concept, the plurality of gates GT1 to GTm may be arranged at the same level as the GIDL gate line.

[0130] Furthermore, multiple contacts CP1 to CPm extending along the vertical direction VD can be respectively arranged above multiple vertical channels VC, and the lengths of the multiple contacts CP1 to CPm in the vertical direction VD can be equal to each other. For example, the vertical channel VC and gate GT1 arranged above the first word line drive signal line SI1 can constitute the first vertical transmission transistor TR1. The contact CP1 arranged above the first vertical transmission transistor TR1 can be electrically connected to the first word line WL1. Furthermore, the vertical channel VC and gate GTm-1 arranged above the (m-1)th word line drive signal line SIm-1 can constitute the (m-1)th vertical transmission transistor TRm-1. The contact CPm-1 arranged above the (m-1)th vertical transmission transistor TRm-1 can be electrically connected to the (m-1)th word line WLm-1.

[0131] On the other hand, the gate GT1 can be disposed above the first word line drive signal lines SI1 to SIm, and among the contacts CP1 to CPm disposed above the vertical channel VC formed through the gate GT1, only contact CP1 can be electrically connected to the first word line WL1, while the other contacts CP2 to CPm can be not electrically connected to the first word line WL1. For example, the other contacts CP2 to CPm can be connected to the nitride region of the first word line WL1 (e.g., Figure 11 (NT), thereby preventing other contacts CP2 to CPm from being electrically connected to the first word line WL1. Contact CP1 can be connected to the tungsten region of the first word line WL1 (e.g., NT), thus preventing other contacts CP2 to CPm from being electrically connected to the first word line WL1. Figure 11 (W), thereby allowing contact CP1 to be electrically connected to the first word line WL1.

[0132] Furthermore, the gate GTm-1 can be disposed above the (m-1)th word line drive signal line SIm-1 and the mth word line drive signal line SIm. Of the contacts CPm-1 and CPm disposed above the vertical channel VC formed through the gate GTm-1, only contact CPm-1 can be electrically connected to the (m-1)th word line WLm-1, while the other contact CPm can be not electrically connected to the (m-1)th word line WLm-1. For example, the other contact CPm can be connected to the nitride region of the (m-1)th word line WLm-1 (e.g., Figure 11 The NT of the (m-1)th word line WLm-1 is connected to prevent another contact CPm from being electrically connected to the (m-1)th word line WLm-1. Contact CPm-1 can be connected to the tungsten region of the (m-1)th word line WLm-1 (e.g., Figure 11 The W), thereby allowing the contact CPm-1 to be electrically connected to the (m-1) word line WLm-1.

[0133] Furthermore, the multiple metal lines MT may also include a metal line SI0, and the metal line SI0 may have the same structure as the first word line drive signal lines SI1 to the m-th word line drive signal lines SIm. This is used to receive block selection signals (e.g., Figure 8 The contact CPb for receiving the block selection signal BS can be arranged on the gate GT1. The contact for receiving the block selection signal BS can also be arranged on other gates GT2 to GTm.

[0134] Figure 22 This is a perspective view showing a memory device 10j according to an exemplary embodiment of the inventive concept.

[0135] Reference Figure 22 The memory device 10j corresponds to Figure 21 A variation of the memory device 10i, and compared to the memory device 10i, the memory device 10j may further include at least one general-purpose transmission transistor TRn arranged vertically below multiple metal lines MT. For example, the multiple metal lines MT, vertical transmission transistors TR1 to TRm, contacts CP1 to CPm, contacts CP11, CP11' and CPb, metal pattern MP11, ground select line GSL, multiple word lines WL1 to WLm, lower string select line SSLd, upper string select line SSLu, and vertical channel structure VP may be arranged in the first semiconductor layer (e.g., Figure 2 In L1). A common transfer transistor TRn can be arranged in the second semiconductor layer (e.g., L1). Figure 2 In L2).

[0136] In an exemplary embodiment of the inventive concept, the memory device 10j may include an active region 101, a gate insulating layer 102, and a gate electrode layer GTp, and the active region 101, the gate insulating layer 102, and the gate electrode layer GTp can form a conventional transfer transistor TRn. The gate electrode layer GTp may extend along a first horizontal direction HD1. Contacts CP24 and CP25 extending along a vertical direction VD may be disposed on the active region 101. For example, contacts CP24 and CP25 may correspond to source contacts and drain contacts, respectively. A metal pattern MP24 extending along a second horizontal direction HD2 may be disposed on the contact CP24, and a metal pattern MP25 extending along the first horizontal direction HD1 may be disposed on the contact CP25. For example, the metal pattern MP24 may be disposed above the metal pattern MP25 along the vertical direction VD. However, the inventive concept is not limited thereto.

[0137] According to the current embodiment, the memory device 10j may include a hybrid transfer transistor circuit comprising vertical transfer transistors TR1 to TRm and a general transfer transistor TRn. For example, the general transfer transistor TRn may be connected to the ground select line GSL. However, the inventive concept is not limited thereto.

[0138] Figure 23 The top surface of memory device 20 according to a comparative example and the top surface of memory device 30 according to an exemplary embodiment of the inventive concept are shown. Figure 24 yes Figure 23 Enlarged views of the first region 21 and the second region 31.

[0139] Reference Figure 23 and Figure 24 The memory device 20 may include a first cell region CAa and a second cell region CAb, a first transmission transistor circuit region PAa and a second transmission transistor circuit region PAb, a first decoder region DAa' and a second decoder region DAb', and a pad region PAD. The memory device 20 may have a first chip size CS1 on a second horizontal direction HD2.

[0140] A first memory cell array is arranged in a first cell region CAa, and a second memory cell array may be arranged in a second cell region CAb. In a first transmission transistor circuit region PAa, multiple transmission transistors connected to gate lines may be arranged; in other words, serial select lines, ground select lines, and word lines included in the first memory cell array may be arranged. In a second transmission transistor circuit region PAb, multiple transmission transistors connected to gate lines may be arranged; in other words, serial select lines, ground select lines, and word lines included in the second memory cell array may be arranged. In a first decoder region DAa', a row decoder and transmission transistors connected to the first memory cell array may be arranged. In a second decoder region DAb', a row decoder and transmission transistors connected to the second memory cell array may be arranged.

[0141] For example, the first region 21 may include a portion of the first unit region CAa and the first decoder region DAa'. The portion of the first unit region CAa may include a vertical channel structure disposed therein (e.g., Figure 6 The first decoder region DAa' may include a cell region CA and a step region SA of word lines. The first decoder region DAa' may include a region in which transmission transistor circuitry is arranged and a region in which line decoders are arranged. In this case, the transmission transistor circuitry may include ordinary transmission transistors (in other words, planar transmission transistors). As mentioned above, the ratio of the region in which transmission transistor circuitry is arranged to the first decoder region DAa' is very high. Therefore, the first chip size CS1 of the memory device 20 will be very large.

[0142] On the other hand, the memory device 30 according to an exemplary embodiment of the inventive concept may include a first cell region CAa and a second cell region CAb, a first decoder region DAa and a second decoder region DAb, and a pad region PAD. The memory device 30 may have a second chip size CS2 on a second horizontal direction HD2. A first memory cell array may be arranged in the first cell region CAa, and a second memory cell array may be arranged in the second cell region CAb. A row decoder connected to the first memory cell array may be arranged in the first decoder region DAa, and a row decoder connected to the second memory cell array may be arranged in the second decoder region DAb.

[0143] According to the current embodiment, compared to memory device 20, memory device 30 does not include the first transmission transistor circuit region PAa and the second transmission transistor circuit region PAb. Furthermore, the lengths of the first decoder region DAa and the second decoder region DAb in the second horizontal direction HD2 can be less than the lengths of the first decoder region DAa' and the second decoder region DAb' in the second horizontal direction HD2. Therefore, the second chip size CS2 can be smaller than the first chip size CS1.

[0144] For example, the second region 31 may include a portion of the first unit region CAa and the first decoder region DAa. A portion of the first unit region CAa may include a vertical channel structure disposed therein (e.g., Figure 6 The first decoder region DAa may include the cell region CA of the VP and the step region SA of the word line. The first decoder region DAa may include the line decoder (e.g., VP) in which the line decoder is arranged. Figure 1 The region of 220). In an exemplary embodiment of the inventive concept, the transmission transistor can be implemented by a vertical transmission transistor, and the vertical transmission transistor can be arranged in the stepped region SA of the word line. Therefore, the transmission transistor circuit (e.g., Figure 1 The region 210 can be included in the first unit region CAa. Therefore, the length of the first decoder region DAa in the second horizontal direction HD2 can be less than the length of the first decoder region DAa' in the second horizontal direction.

[0145] Figure 25 This is a top view showing the first surface of the first semiconductor layer 300 included in an exemplary embodiment of a memory device according to the inventive concept.

[0146] Reference Figure 25The first semiconductor layer 300 may include multiple drive signal lines SI1 to SI4 and SS1 to SS4, as well as a common source line CSL, arranged at the same horizontal level. For example, the multiple drive signal lines SI1 to SI4 and SS1 to SS4 extend along a second horizontal direction HD2 and may be spaced apart from each other along a first horizontal direction HD1. A gate GT is arranged above the multiple drive signal lines SI1 to SI4 and SS1 to SS4 along a vertical direction VD and may extend along the first horizontal direction HD1. First word lines WL1 to fourth word lines WL4 may be sequentially stacked above the gate GT along the vertical direction VD. In an exemplary embodiment of the inventive concept, in the first semiconductor layer 300, a substrate may be arranged on a second surface facing the first surface. Therefore, the multiple drive signal lines SI1 to SI4 and SS1 to SS4, as well as the common source line CSL, may be arranged on the substrate.

[0147] Figure 26 and Figure 27 A memory device 40 according to an exemplary embodiment of the inventive concept is shown. For example, Figure 26 The first semiconductor layer 300 shows along Figure 25 The cross-section taken from line XXVI-XXVI' Figure 27 The first semiconductor layer 300 shows along Figure 25 The cross section taken from line XXVII-XXVII'.

[0148] Reference Figure 26 and Figure 27 The first semiconductor layer 300 can be bonded to the second semiconductor layer 400, for example, via Cu-to-Cu (C2C) wafer bonding. In this case, multiple bonding pads PD1a and PD1b can be formed on the first surface of the first semiconductor layer 300, and multiple bonding pads PD2a and PD2b can be formed on the first surface of the second semiconductor layer 400. Therefore, Figure 25 The first semiconductor layer 300 is flipped so that the first surface of the first semiconductor layer 300 can be bonded to the first surface of the second semiconductor layer 400. In an exemplary embodiment, an input / output (I / O) pad formation process and a back lap process can be sequentially performed on the second surface of the first semiconductor layer 300.

[0149] The gate GT can be connected to the transistor 440 via wiring including contacts 310, metal pattern 330, and bonding pad PD1a contained in the first semiconductor layer 300, and bonding pad PD2a, contacts 410 and 430, and metal pattern 420 contained in the second semiconductor layer 400. Furthermore, the word line drive signal line SI1 can be connected to the transistor 480 via wiring including contacts 320 and bonding pad PD1b contained in the first semiconductor layer 300, and bonding pad PD2b, contacts 450 and 470, and metal pattern 460 contained in the second semiconductor layer 400.

[0150] Figure 28 The structure of a memory device 50 according to an exemplary embodiment of the inventive concept is shown.

[0151] Reference Figure 1 and Figure 28 The memory device 50 may include a first semiconductor layer L1' and a second semiconductor layer L2', and the second semiconductor layer L2' may be stacked on the first semiconductor layer L1' along the vertical direction VD. For example, the first semiconductor layer L1' and the second semiconductor layer L2' may be bonded by wafer bonding, and the second semiconductor layer L2' may be disposed above the first semiconductor layer L1' along the vertical direction VD.

[0152] In an exemplary embodiment of the inventive concept, the memory cell array 100, the transmission transistor circuit 210, and the row decoder 220 can be formed in a first semiconductor layer L1', and the control logic 230 and the page buffer 240 can be formed in a second semiconductor layer L2'. Therefore, the memory device 50 can have a structure in which the memory cell array 100 is arranged below a portion of the peripheral circuitry; in other words, it has a peripheral over cell (POC) structure. In the POC structure, the horizontal area can be reduced, and the integration density of the memory device 50 can be increased.

[0153] In an exemplary embodiment of the inventive concept, each of the first semiconductor layer L1' and the second semiconductor layer L2' may include a substrate, and after the memory cell array 100, the transmission transistor circuit 210 and the row decoder 220 are formed in the first semiconductor layer L1' and the circuit including the control logic 230 and the page buffer 240 is formed in the second semiconductor layer L2', the first semiconductor layer L1' and the second semiconductor layer L2' may be combined by C2C wafer bonding.

[0154] Figure 29 This illustrates exemplary embodiments based on the inventive concept. Figure 28 A cross-sectional view of the memory device 50.

[0155] Reference Figure 29 The first semiconductor layer L1' may include a first substrate SUB1, multiple drive signal lines SI1 to SI4 and SS1 to SS4, a common source line CSL, a gate GT, a ground select line GSL, word lines WL1 to WLm, a lower string select line SSLd, and an upper string select line SSLu. Furthermore, the first semiconductor layer L1' may also include multiple vertical channels 510, multiple contacts 520, and multiple bonding pads PD1 respectively connected to the multiple contacts 520. Additionally, the first semiconductor layer L1' may also include multiple vertical channel structures 530. The second semiconductor layer L2' may include a second substrate SUB2, a transistor TR, metal layers 540 and 550, contacts 560, and multiple bonding pads PD2.

[0156] Figure 30 This is a block diagram illustrating an example of a memory device applied to a solid-state drive (SSD) system according to an exemplary embodiment of the inventive concept.

[0157] Reference Figure 30 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 transmits and receives the SIG signal to and from the host 1100 via a signal connector, and receives power PWR via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 can be configured using reference... Figures 1 to 29 The above embodiments are implemented. Memory devices 1230, 1240 and 1250 can be connected to SSD controller 1210 via channels Ch2, Ch2, ..., Chn.

[0158] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A memory device, the memory device comprising: A memory cell array is disposed in a first semiconductor layer, the memory cell array including multiple word lines extending along a first direction and stacked along a second direction perpendicular to the first direction; as well as Multiple transmission transistors are disposed in a first semiconductor layer, wherein a first transmission transistor of the multiple transmission transistors is disposed between a first signal line of the multiple signal lines and a first word line of the multiple word lines. The multiple signal lines and the common source electrode are arranged at the same horizontal level, and Among them, the memory device is a non-volatile memory device. The memory device further includes a gate extending along a first direction between the plurality of signal lines and the plurality of word lines, wherein the first transmission transistor includes a channel extending from the first signal line along a second direction through the gate. The memory cell array further includes multiple channel structures that extend from the common source line along a second direction and pass through the ground selection line. Among the plurality of channel structures, the first channel structure has a first width in the region between the ground select line and the first word line, and the channel of the first transmission transistor has a second width in the region between the gate and the first word line, the second width being larger than the first width.

2. The memory device according to claim 1, wherein, The first transmission transistor is a vertical transmission transistor, and Each of the plurality of transmission transistors includes a vertical channel, wherein the top of the plurality of vertical channels is below the first word line.

3. The memory device according to claim 2, wherein, The width of the channel between the gate and the first word line is greater than the width of the channel below the gate.

4. The memory device according to claim 3, wherein, The tops of the plurality of vertical channels are at the same level as each other, and The second width is at least twice the width of the first width.

5. The memory device according to claim 1, wherein, The plurality of transmission transistors are formed in the region where the plurality of word lines form a stepped shape.

6. The memory device of claim 1, further comprising a second semiconductor layer, wherein, A first semiconductor layer is stacked on a second semiconductor layer along a second direction. The second semiconductor layer includes a second transistor, which is electrically connected to a first transmission transistor. The second transistor is included in the line decoder.

7. The memory device according to claim 1, wherein, The gate is connected to at least one of the plurality of transmission transistors, wherein the gate and the ground select line are arranged at the same level.

8. The memory device according to claim 1, wherein, The plurality of transfer transistors are connected together to the gate line, and The plurality of transmission transistors are provided with the same block selection signal.

9. A memory device, the memory device comprising: A memory cell array comprising multiple word lines stacked vertically; as well as A plurality of vertical transmission transistors, wherein a first vertical transmission transistor of the plurality of vertical transmission transistors includes a first vertical channel extending in a vertical direction between a first drive signal line and a first word line of the plurality of word lines, wherein the first vertical channel is disposed near the end of the first word line, and In this configuration, the first driving signal line and the common source electrode line are arranged in the same layer. The memory device further includes a gate disposed between the first drive signal line and the first word line, wherein the first vertical channel of the first vertical transmission transistor extends vertically from the first drive signal line through the gate. The memory cell array further includes multiple channel structures that extend vertically from the common source line through the ground selection line, and... Among them, the first channel structure of the plurality of channel structures has a first width in the region between the ground select line and the first word line, and the first vertical channel of the first vertical transmission transistor has a second width in the region between the gate and the first word line, the second width being larger than the first width.

10. The memory device according to claim 9, wherein, A first driving signal line is disposed on the substrate of the first semiconductor layer and extends horizontally. The first driving signal line is connected to a transistor included in the second semiconductor layer. The first drive signal line is connected to the transistor in the second semiconductor layer through a contact and a metal pattern in the first semiconductor layer.

11. The memory device according to claim 9, wherein, The plurality of vertical transmission transistors includes a second vertical transmission transistor, which includes a second vertical channel extending in a vertical direction between the second drive signal line and a second word line among the plurality of word lines, the second vertical channel being disposed near the end of the second word line.

12. The memory device according to claim 11, wherein, The end of the second word line is closer to the cell region of the memory cell array than the end of the first word line. The first vertical channel and the second vertical channel have the same height in the vertical direction, and The top surface of the first vertical channel and the top surface of the second vertical channel are located below the bottom surface of the first character line.

13. The memory device according to claim 9, wherein, The first letter line includes tungsten and nitride regions, and The tungsten region is connected to the contact element, and the contact element is connected to the first word line through the tungsten region.

14. The memory device of claim 9, further comprising: The ground select line is positioned between the common source line and the first word line, wherein the gate and ground select lines are positioned at the same horizontal level. The memory cell array and the plurality of vertical transmission transistors are disposed in the first semiconductor layer, and at least a portion of the line decoder is disposed in the second semiconductor layer below the first semiconductor layer.

15. The memory device according to claim 9, wherein, A first word line connected to a first drive signal line is provided with a programming voltage, and a second word line connected to a second drive signal line is provided with a pass voltage. The programming voltage is 10V to 25V, and the pass voltage is 5V to 15V.

16. The memory device according to claim 9, wherein, A first word line connected to a first drive signal line is provided with a read voltage, and a second word line connected to a second drive signal line is provided with a read pass voltage. The reading voltage ranges from -1V to 10V, and the reading pass voltage ranges from 4V to 10V.

17. The memory device according to claim 9, wherein, The first word line connected to the first drive signal line is provided with an erase voltage, and The erase voltage is -2V to 3V.

18. A memory device, the memory device comprising: A first semiconductor layer includes: a memory cell array including multiple word lines stacked vertically; a plurality of transfer transistors, a first transfer transistor of the plurality of transfer transistors being connected to a drive signal line; and a gate disposed on the same layer as a ground select line; and The second semiconductor layer includes a first transistor connected to a contact, the contact being connected to a second bonding pad, and the second bonding pad being connected to the first bonding pad. The first transmission transistor is connected to the gate, the gate is connected to the contact, and the contact is connected to the first bonding pad. The multiple word lines have a stepped shape in the region where the first transmission transistor is placed. The first transmission transistor includes a channel extending vertically from the drive signal line through the gate, and the first transmission transistor is disposed between the drive signal line and a first word line among the plurality of word lines. The memory cell array further includes multiple channel structures that extend vertically from the common source line through the ground selection line, and... Among the plurality of channel structures, the first channel structure has a first width in the region between the ground select line and the first word line, and the channel of the first transmission transistor has a second width in the region between the gate and the first word line, the second width being larger than the first width.

19. The memory device according to claim 18, wherein, The second semiconductor layer is bonded to the first semiconductor layer, and The second semiconductor layer includes a transistor connected to a gate in the first semiconductor layer.

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