Semiconductor package

Abstract

The present invention provides a semiconductor package comprising: a semiconductor chip; an interposer layer on the semiconductor chip; and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer layer. The interposer layer includes an interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulating from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers the upper surface of the interposer substrate and at least a portion of the sidewalls of the upper pad. At least a portion of the upper surface of the upper pad is not covered by the molding layer.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority to Korean Patent Application No. 10-2019-0067575, filed with the Korean Intellectual Property Office on June 7, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to semiconductor packages, and more specifically, to semiconductor packages having improved heat dissipation properties. Background Technology

[0004] Generally, packaging processes are performed on semiconductor chips formed by executing various semiconductor processes on wafers. Recently, various types of semiconductor chips are packaged in a single package, and these chips are electrically interconnected to operate as a single system. However, excessive heat is generated during the operation of semiconductor chips. Semiconductor packages may degrade due to excessive heat. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor package includes: a first semiconductor chip; a first interposer layer on the first semiconductor chip, the first interposer layer including a first interposer substrate and a first heat dissipation pattern, the first heat dissipation pattern passing through the first interposer substrate and electrically insulating the first semiconductor chip; and a molding layer covering at least a portion of the first semiconductor chip and at least a portion of the first interposer layer. The first heat dissipation pattern may include a first through electrode passing through the first interposer substrate and a first upper pad on the upper surface of the first interposer substrate and connected to the first through electrode. The molding layer may cover at least a portion of the sidewalls of the first upper pad and at least a portion of the upper surface of the first interposer substrate. At least a portion of the upper surface of the first upper pad may not be covered by the molding layer.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a first interposer on the first semiconductor chip, the first interposer including a first interposer substrate and a first heat dissipation pattern through the first interposer substrate; and a second interposer on the second semiconductor chip, the second interposer including a second interposer substrate and a second heat dissipation pattern through the second interposer substrate.

[0007] According to an exemplary embodiment of the present invention, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a third semiconductor chip on the first semiconductor chip; a first interposer on the first semiconductor chip, the first interposer including a first interposer substrate and a plurality of first heat dissipation patterns electrically insulated from the first semiconductor chip; a second interposer on the second semiconductor chip, the second interposer including a second interposer substrate and a plurality of second heat dissipation patterns electrically insulated from the second semiconductor chip; a third interposer on the third semiconductor chip, the third interposer including a third interposer substrate and a plurality of third heat dissipation patterns electrically insulated from the third semiconductor chip; and a molding layer covering at least a portion of the first semiconductor chip, at least a portion of the first interposer, at least a portion of the second semiconductor chip, at least a portion of the second interposer, at least a portion of the third semiconductor chip, and at least a portion of the third interposer. Each of the plurality of first heat dissipation patterns may include a first through electrode passing through the first interposer substrate and a first upper pad on the upper surface of the first interposer substrate and connected to the first through electrode. Each of the plurality of second heat dissipation patterns may include a second through electrode passing through the second interposer substrate and a second upper pad on the upper surface of the second interposer substrate and connected to the second through electrode. Each of the plurality of third heat dissipation patterns may include a third through electrode passing through the third interposer substrate and a third upper pad on the upper surface of the third interposer substrate and connected to the third through electrode. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view illustrating an exemplary embodiment of the intermediary layer according to the concept of the present invention.

[0009] Figure 2A and Figure 2B These are examples illustrating some exemplary embodiments based on the concepts of the present invention. Figure 1 A plan view showing the arrangement of heat dissipation patterns in the intermediate layer.

[0010] Figure 3 This is a cross-sectional view illustrating an exemplary embodiment of the intermediary layer according to the concept of the present invention.

[0011] Figure 4 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the concept of the present invention.

[0012] Figure 5 yes Figure 4 An enlarged cross-sectional view of a portion of the semiconductor package shown.

[0013] Figure 6This illustrates an exemplary embodiment of the concept according to the present invention. Figure 4 The flowchart shows a method for molding a semiconductor package.

[0014] Figure 7A and Figure 7B This illustrates some exemplary embodiments of the formation according to the concept of the present invention. Figure 4 A cross-sectional view of the method for molding the semiconductor package shown.

[0015] Figure 8 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the concept of the present invention.

[0016] Figure 9 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the concept of the present invention.

[0017] Figure 10A , Figure 10B and Figure 10C These are examples illustrating some exemplary embodiments based on the concepts of the present invention. Figure 9 Plan view of the first and second interposers of the semiconductor package shown.

[0018] Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor package according to the concept of the present invention.

[0019] Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor package according to the concept of the present invention.

[0020] Figure 21A and Figure 21B This illustrates an exemplary embodiment of manufacturing according to the concept of the present invention. Figure 9 A cross-sectional view of the method for producing the semiconductor package shown.

[0021] Figure 22A , Figure 22B , Figure 22C and Figure 22D This illustrates an exemplary embodiment of manufacturing according to the concept of the present invention. Figure 17 A cross-sectional view of the method for producing the semiconductor package shown.

[0022] [Explanation of Symbols]

[0023] 100, 100a: Intermediate layer

[0024] 110: Intermediate substrate

[0025] 120, 120a: Heat dissipation patterns

[0026] 121: Through electrode

[0027] 122: Upper connecting pad

[0028] 123: Lower pad

[0029] 124: Upper Covering Layer

[0030] 125: Lower overlay

[0031] 200, 200a, 200b, 200c, 200d, 200e, 200g, 200f, 300, 300a, 300b, 300c, 300d: Semiconductor packages

[0032] 210: Packaging substrate

[0033] 211, 215: Upper substrate pads

[0034] 213: Lower substrate pad

[0035] 220: First Semiconductor Chip

[0036] 220a: First surface of the first semiconductor chip

[0037] 220b: The second surface of the first semiconductor chip

[0038] 221: First chip pad

[0039] 223: Connecting part

[0040] 225, 237: Bottom filling material layer

[0041] 227: Through Silicon Via (TSV)

[0042] 230: Second semiconductor chip

[0043] 230a: First surface of the second semiconductor chip

[0044] 230b: Second surface of the second semiconductor chip

[0045] 231: Second chip pad

[0046] 233: Adhesive layer

[0047] 235: Inter-chip connectors

[0048] 240: First thermal interface material

[0049] 241: Second thermal interface material

[0050] 243: Third thermal interface material

[0051] 250: First Intermediary Layer

[0052] 250a: First Sub-Intermediate Layer

[0053] 250b: Second Sub-intermediary Layer

[0054] 251: First interposer substrate

[0055] 251a: First sub-intermediate substrate

[0056] 251b: Second sub-intermediate substrate

[0057] 253: First heat dissipation pattern

[0058] 253a: First sub-heat dissipation pattern

[0059] 253b: Second sub-heat dissipation pattern

[0060] 260: Second Intermediary Layer

[0061] 261: Second Intermediate Layer Substrate

[0062] 263: Second heat dissipation pattern

[0063] 270: Molding layer

[0064] 271: Molding materials

[0065] 280, 281: Conductive wires

[0066] 285: Heat sink

[0067] 287: TIM

[0068] 290: External connection terminal

[0069] 400: Redistributed Structure

[0070] 411: First insulating layer

[0071] 413: Second insulating layer

[0072] 420: Redistribution Pattern

[0073] 2531: First penetrating electrode

[0074] 2532: First upper connecting pad

[0075] 2533: First connecting pad

[0076] CA: Carrier

[0077] MF: Molded film

[0078] S110, S120, S130: Steps

[0079] X, Y, Z: Direction Detailed Implementation

[0080] Various exemplary embodiments will now be described more fully below with reference to the accompanying drawings. Throughout this application, the same reference numerals may refer to the same elements.

[0081] Figure 1 This is a cross-sectional view illustrating an exemplary embodiment of the intermediary layer according to the concept of the present invention.

[0082] Reference Figure 1 The interposer 100 may include an interposer substrate 110 and a heat dissipation pattern 120.

[0083] Intermediate substrate 110 may comprise an organic material. For example, intermediate substrate 110 may be formed from prepreg, a material in which resin is infiltrated into glass fibers or carbon fibers and cured to stage B (the semi-cured state of the resin). In some embodiments, intermediate substrate 110 may be a silicon wafer comprising silicon (e.g., monocrystalline silicon, polycrystalline silicon, or amorphous silicon). In some embodiments, intermediate substrate 110 may comprise ceramic. Intermediate substrate 110 may have a plate shape and may have an upper surface and a lower surface opposite each other.

[0084] The heat dissipation pattern 120 can extend through the interposer substrate 110. That is, the heat dissipation pattern 120 can extend from the upper surface of the interposer substrate 110 to the lower surface of the interposer substrate 110. When the interposer 100 is attached to an object that requires heat dissipation, the heat dissipation pattern 120 can serve as a path for releasing heat to the outside. For example, when the interposer 100 is attached to an object that requires heat dissipation, since the bottom of the heat dissipation pattern 120 contacts the object and the top of the heat dissipation pattern 120 is exposed to the outside, heat generated from the object can be released to the outside through the heat dissipation pattern 120.

[0085] The heat dissipation pattern 120 may include a material with high thermal conductivity. For example, the heat dissipation pattern 120 may include a material with a thermal conductivity of 10 W / mK or higher. For example, the heat dissipation pattern 120 may include at least one of copper (Cu), nickel (Ni), gold (Au), tungsten (W), and aluminum (Al).

[0086] The heat dissipation pattern 120 may include a through electrode 121 penetrating the interposer substrate 110, an upper pad 122 on the upper surface of the interposer substrate 110, and a lower pad 123 on the lower surface of the interposer substrate 110. The top end of the through electrode 121 may be connected to the upper pad 122. The bottom end of the through electrode 121 may be connected to the lower pad 123. The upper pad 122 and the lower pad 123 may be thermally coupled through the through electrode 121. When the interposer 100 is attached to an object requiring heat dissipation, at least a portion of the upper pad 122 may be exposed to the outside, and the lower pad 123 may contact the object.

[0087] In some exemplary embodiments, the width of the through electrode 121 in the horizontal direction (i.e., the X or Y direction) may be between 50 μm and 500 μm. The height of the through electrode 121 in the vertical direction (i.e., the Z direction) may be between 50 μm and 300 μm.

[0088] In some exemplary embodiments, the width of the upper pad 122 in the horizontal direction may be greater than the width of the through electrode 121 in the horizontal direction. In other words, in an XY plane having X and Y directions, the planar area of ​​the upper pad 122 may be greater than the planar area of ​​the through electrode 121. In this case, since the surface area of ​​the upper pad 122 exposed to the outside is increased, heat transfer from the upper pad 122 to the outside can be improved.

[0089] In some exemplary embodiments, the width of the upper pad 122 in the horizontal direction may be at least 10 μm larger than the width of the through electrode 121 in the horizontal direction. For example, the difference between the width of the upper pad 122 and the width of the through electrode 121 may be between 10 μm and 70 μm.

[0090] In some exemplary embodiments, the distance between adjacent upper pads 122 in the horizontal direction may be between 10 μm and 100 μm.

[0091] In some exemplary embodiments, the height of the upper pad 122 in the vertical direction may be between 5 μm and 50 μm.

[0092] like Figure 1 As shown, one upper pad 122 may be connected to one through electrode 121. However, in some embodiments, one upper pad 122 may be connected to multiple through electrodes 121. For example, the upper pad 122 may have a plate shape covering at least a portion of the upper surface of the interposer substrate 110 and connected to the multiple through electrodes 121.

[0093] In some exemplary embodiments, the width of the lower pad 123 in the horizontal direction may be greater than the width of the through electrode 121 in the horizontal direction. That is, in the XY plane, the planar area of ​​the lower pad 123 may be greater than the planar area of ​​the through electrode 121. In this case, since the contact area of ​​the lower pad 123 with the object that needs to dissipate heat is increased, the heat transfer between the object and the lower pad 123 can be improved.

[0094] In some exemplary embodiments, the width of the lower pad 123 in the horizontal direction may be at least 10 μm larger than the width of the through electrode 121 in the horizontal direction. For example, the difference between the width of the lower pad 123 and the width of the through electrode 121 may be between 10 μm and 70 μm.

[0095] In some exemplary embodiments, the distance between adjacent lower pads 123 in the horizontal direction may be between 10 μm and 100 μm.

[0096] In some exemplary embodiments, the height of the lower pad 123 in the vertical direction may be between 5 μm and 50 μm.

[0097] like Figure 1 As shown, a lower pad 123 may be connected to a through electrode 121. However, in some exemplary embodiments, a lower pad 123 may be connected to multiple through electrodes 121. For example, the lower pad 123 may have a plate shape covering at least a portion of the lower surface of the interposer substrate 110 and connected to the multiple through electrodes 121.

[0098] Figure 2A and Figure 2B These are examples illustrating some exemplary embodiments based on the concepts of the present invention. Figure 1 A plan view showing the arrangement of heat dissipation patterns in the intermediate layer.

[0099] exist Figure 2A The image shows a first arrangement of the heat dissipation pattern 120. Figure 2B The image shows a second arrangement of heat dissipation patterns 120. A first arrangement of heat dissipation patterns 120 may represent a case where the number or density of heat dissipation patterns 120 is relatively large, and a second arrangement of heat dissipation patterns 120 may represent a case where the number or density of heat dissipation patterns 120 is relatively small. Here, the arrangement of heat dissipation patterns 120 may refer to the number, density, or array form of the heat dissipation patterns 120.

[0100] Since the heat dissipation properties of the interlayer 100 change depending on the number or density of the heat dissipation pattern 120, the arrangement of the heat dissipation pattern 120 can be changed according to the object that needs to dissipate heat.

[0101] For example, when the interposer 100 is used to dissipate heat from the semiconductor chip, the arrangement of the heat dissipation pattern 120 can be varied depending on the type of semiconductor chip. For example, when the amount of heat generated by the semiconductor chip is relatively large or when the semiconductor chip needs to dissipate heat quickly in situations where the semiconductor chip is susceptible to heat, the number or density of the heat dissipation pattern 120 can be increased.

[0102] Furthermore, the arrangement of the heat dissipation patterns 120 can vary between different regions of the interposer layer 100. For example, the number or density of heat dissipation patterns 120 in the first region of the interposer layer 100 can be greater than the number or density of heat dissipation patterns 120 in the second region of the interposer layer 100. For example, when the first region of the interposer layer 100 corresponds to a central region in the semiconductor chip where the amount of heat generated is relatively large and the second region of the interposer layer 100 corresponds to a peripheral region in the semiconductor chip where the amount of heat generated is relatively small, the number or density of heat dissipation patterns 120 in the first region of the interposer layer 100 can be greater than the number or density of heat dissipation patterns 120 in the second region of the interposer layer 100.

[0103] Figure 3 This is a cross-sectional view illustrating an exemplary embodiment of the intermediary layer according to the concept of the present invention. In addition to further including an upper cover layer and a lower cover layer, Figure 3 The intermediary layer shown can be connected with Figure 1 The intermediate layer 100 shown is the same as or substantially similar to the intermediate layer 100 shown.

[0104] Reference Figure 3 The heat dissipation pattern 120a of the interlayer 100a may include an upper cover layer 124 on the upper pad 122 and a lower cover layer 125 on the lower pad 123.

[0105] The upper capping layer 124 may cover the upper pad 122 on the upper surface of the interposer substrate 110. The upper capping layer 124 may serve as an oxide barrier layer to prevent oxidation of the upper pad 122. The upper capping layer 124 may, for example, contain nickel (Ni) and / or gold (Au). For example, the upper capping layer 124 may be formed by a plating process.

[0106] The lower capping layer 125 may cover the lower pad 123 on the lower surface of the interposer substrate 110. The lower capping layer 125 may serve as an oxide barrier layer to prevent oxidation of the lower pad 123. The lower capping layer 125 may, for example, contain nickel (Ni) and / or gold (Au). For example, the lower capping layer 125 may be formed by a plating process.

[0107] Figure 4 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the concept of the present invention. Figure 5 yes Figure 4 An enlarged cross-sectional view of a portion of the semiconductor package shown.

[0108] Reference Figure 4 and Figure 5 The semiconductor package 200 may include a package substrate 210, a first semiconductor chip 220, a first interposer 250, and a molding layer 270.

[0109] The packaging substrate 210 may be, for example, a printed circuit board. The packaging substrate 210 may include a substrate base made of at least one of phenolic resin, epoxy resin, and polyimide. The packaging substrate 210 may include an upper substrate pad 215 and a lower substrate pad 213 respectively on the upper and lower surfaces of the substrate base. The upper substrate pad 215 and the lower substrate pad 213 may, for example, comprise copper (Cu), nickel (Ni), and / or aluminum (Al). Internal wiring may be disposed in the substrate base to connect the upper substrate pad 215 and the lower substrate pad 213.

[0110] External connection terminal 290 may be attached to the lower surface of package substrate 210. For example, external connection terminal 290 may be attached to lower substrate pad 213. External connection terminal 290 may be, for example, a solder ball or a bump. External connection terminal 290 may electrically connect semiconductor package 200 to an external device.

[0111] A first semiconductor chip 220 may be mounted on a packaging substrate 210. The first semiconductor chip 220 may include a semiconductor substrate having opposing active and non-active surfaces, and a semiconductor device layer on the active surface of the semiconductor substrate. The first semiconductor chip 220 may have opposing first surfaces 220a and second surfaces 220b. A first chip pad 221 may be disposed on the first surface 220a of the first semiconductor chip 220. The first chip pad 221 may be electrically connected to the semiconductor device layer via a wiring structure.

[0112] The first semiconductor chip 220 may be a memory chip, such as a volatile memory chip and / or a non-volatile memory chip. Volatile memory chips may include, for example, dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero-capacitor RAM (ZRAM), or twin-transistor RAM (TTRAM). Non-volatile memory chips may include, for example, flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM, or insulator resistive switching memory.

[0113] The first semiconductor chip 220 may be a non-memory chip. For example, the first semiconductor chip 220 may be a logic chip, such as an artificial intelligence semiconductor chip, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a system on a chip, but the concept of the present invention is not limited thereto.

[0114] The first semiconductor chip 220 can be mounted on the packaging substrate 210, such that the first surface 220a of the first semiconductor chip 220, on which the first chip pad 221 is disposed, faces upward. The first chip pad 221 can be arranged along one side of the first semiconductor chip 220. The first chip pad 221 can be electrically connected to the upper substrate pad 215 of the packaging substrate 210 via a conductive wire 280. The first chip pad 221 can be used as a terminal for transmitting input / output data signals of the first semiconductor chip 220, or as a terminal for providing power and / or grounding to the first semiconductor chip 220.

[0115] A first interposer 250 may be stacked on a first surface 220a of a first semiconductor chip 220. The first interposer 250 may include a first interposer substrate 251 and a first heat dissipation pattern 253. The first heat dissipation pattern 253 may include a first through-electrode 2531, a first upper pad 2532, and a first lower pad 2533. The first interposer 250 may include a reference... Figures 1 to 3 The aforementioned intermediary layer 100 or intermediary layer 100a.

[0116] The first heat dissipation pattern 253 can be used as a heat transfer path to release heat from the first semiconductor chip 220 to the outside. For example, the bottom of the first heat dissipation pattern 253 may contact the first surface 220a of the first semiconductor chip 220, and the top of the first heat dissipation pattern 253 may be exposed to the outside. In this case, heat from the first semiconductor chip 220 can be dissipated to the outside through the first heat dissipation pattern 253. The first heat dissipation pattern 253 may be electrically insulated from the first semiconductor chip 220. The first heat dissipation pattern 253 of the first interposer 250 may be spaced apart from and electrically insulated from the first chip pad 221 of the first semiconductor chip 220.

[0117] In some exemplary embodiments, a first thermal interface material (TIM) 240 may be sandwiched between the first interposer 250 and the first semiconductor chip 220. The first thermal interface material 240 can physically fix the first interposer 250 to the first semiconductor chip 220 and can enhance the thermal coupling between the first heat dissipation pattern 253 of the first interposer 250 and the first semiconductor chip 220. For example, the first thermal interface material 240 may be formed of an insulating material (e.g., an insulating material capable of maintaining electrical insulation).

[0118] The first interposer 250 may be stacked on the first semiconductor chip 220 without overlapping the first chip pads 221 of the first semiconductor chip 220. For example, in the case where a plurality of first chip pads 221 are disposed adjacent to the side edges of the first surface 220a of the first semiconductor chip 220, the first interposer 250 may be spaced apart from the side edges of the first surface 220a of the first semiconductor chip 220 by a required distance (or, alternatively, a predetermined distance) so as not to cover the plurality of first chip pads 221.

[0119] The molding layer 270 can cover at least a portion of the first semiconductor chip 220 and at least a portion of the first interposer layer 250. Therefore, the molding layer 270 can protect the first semiconductor chip 220 and the first interposer layer 250 from the influence of the external environment.

[0120] A molding layer 270 can be formed by injecting an appropriate amount of molding material around the first semiconductor chip 220 and curing the molding material. The molding layer 270 may be part of the appearance of the semiconductor package 200. In some exemplary embodiments, the molding material used to form the molding layer 270 may include an epoxy molding resin or a polyimide molding resin. For example, the molding layer 270 may contain an epoxy molding compound (EMC).

[0121] like Figure 5As shown, the molding layer 270 may cover a portion of the first interposer substrate 251 and the first upper contact pad 2532, and may expose another portion of the first upper contact pad 2532 to the outside. For example, the molding layer 270 may cover a portion of the sidewall of the first upper contact pad 2532, and may expose the upper surface of the first upper contact pad 2532. In this case, the molding layer 270 may protect said portion of the sidewall of the first upper contact pad 2532.

[0122] A first thermal interface material 240 may be sandwiched between the lower surface of the first interposer substrate 251 and the first semiconductor chip 220. The first thermal interface material 240 may fill the space between the lower surface of the first interposer substrate 251 and the first semiconductor chip 220, and may cover the first lower pad 2533 on the lower surface of the first interposer substrate 251. For example, the first thermal interface material 240 may fill the space between adjacent first lower pads 2533, and may cover at least a portion of the first lower pads 2533. Although not specifically shown, according to some exemplary embodiments, the first thermal interface material 240 may further cover the lower surface of the first lower pad 2533 facing the first surface 220a of the first semiconductor chip 220.

[0123] In some exemplary embodiments, the thermal properties of the semiconductor package 200 can be improved by using a first interposer 250 attached to the first semiconductor chip 220 to release the heat generated from the first semiconductor chip 220.

[0124] Figure 6 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 4 The flowchart shows a method for molding a semiconductor package. Figure 7A and Figure 7B This illustrates some exemplary embodiments of the formation according to the concept of the present invention. Figure 4 A cross-sectional view of the method for molding the semiconductor package shown.

[0125] Reference Figure 4 , Figure 6 , Figure 7A and Figure 7B In order to form the molding layer 270 of the semiconductor package 200, the steps of positioning the molding film MF on the first interposer 250, forming the molding layer 270 by injecting and curing the molding material 271, and removing the molding film MF can be performed sequentially.

[0126] For example, in step S110, where the molding film MF is positioned on the first interposer 250, the molding film MF may cover (contact) a portion of the surface of the first upper pad 2532, and may not cover (not contact) at least a portion of the sidewalls of the first upper pad 2532. The molding film MF may be spaced from the upper surface of the first interposer substrate 251 by a desired distance (or, alternatively, a predetermined distance) to form a space between the upper surface of the first interposer substrate 251 and the molding film MF.

[0127] In step S120, which forms the molding layer 270 by injection molding and curing the molding material 271, the molding material 271 can be provided under the molding film MF, and the molding material 271 can be formed to cover the first semiconductor chip 220 and the first interposer substrate 251. The molding material 271 can fill the space between the molding film MF and the first interposer substrate 251. At this time, the molding material 271 may not cover the portion of the first upper pad 2532 covered (in contact) by the molding film MF. When a certain pressure and heat are applied to the molding material 271 to cure the molding material 271, the molding layer 270 can be formed to cover at least a portion of the first upper pad 2532.

[0128] For example, such as Figure 7A As shown, the molding layer 270 can be formed using the molding film MF via a transfer molding method. In some exemplary embodiments, such as Figure 7B As shown, the molding layer 270 can be formed by using the compression molding method of the molding film MF.

[0129] After the molding layer 270 is formed, the molding film MF can be removed (S130). The molding film MF can be, for example, a release film. Since the molding film MF is removed, a portion of the first upper pad 2532 can be covered by the molding layer 270, while another portion of the first upper pad 2532 can be exposed to the outside.

[0130] Figure 8 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the concept of the present invention. Except that the first semiconductor chip is mounted on the package substrate using a flip-chip bonding method, Figure 8 The semiconductor package shown can be used with Figure 4 The semiconductor package 200 shown is the same as or substantially similar to the semiconductor package shown.

[0131] Reference Figure 8The semiconductor package 200a may include a package substrate 210, a first semiconductor chip 220, a first interposer 250, and a molding layer 270. The first semiconductor chip 220 may be mounted on the package substrate 210 such that a first surface 220a on the first semiconductor chip 220, on which a first chip pad 221 is disposed, faces the upper surface of the package substrate 210. The first chip pad 221 of the first semiconductor chip 220 may be electrically connected to the upper substrate pad 211 of the package substrate 210 via a connecting portion 223.

[0132] The first interposer 250 can be mounted on the second surface 220b of the first semiconductor chip 220. Since the first interposer 250 is mounted on the second surface 220b of the first semiconductor chip 220 where the first chip pad 221 of the first semiconductor chip 220 is not disposed, the first interposer 250 can cover the entire second surface 220b of the first semiconductor chip 220.

[0133] The underfill material layer 225 can fill the space between the first semiconductor chip 220 and the packaging substrate 210, and can cover the connection portion 223. For example, the underfill material layer 225 may contain epoxy resin and can be formed by a capillary underfill method. In some exemplary embodiments, the underfill material layer 225 may be a non-conductive film. In some exemplary embodiments, the molding layer 270 can directly fill the space between the first semiconductor chip 220 and the packaging substrate 210. In this case, the underfill material layer 225 can be omitted.

[0134] Figure 9 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the concept of the present invention. In addition to further including a second semiconductor chip on the first semiconductor chip and a second interposer layer on the second semiconductor chip, Figure 9 The semiconductor package shown can be used with Figure 8 The semiconductor package 200a shown is the same as or substantially similar to the semiconductor package shown.

[0135] Reference Figure 9 The semiconductor package 200b may include a package substrate 210, a first semiconductor chip 220 on the package substrate 210, a second semiconductor chip 230 stacked on the first semiconductor chip 220, a first interposer layer 250 on the first semiconductor chip 220, a second interposer layer 260 on the second semiconductor chip 230, and a molding layer 270.

[0136] The second semiconductor chip 230 can be stacked on the first semiconductor chip 220 in an offset relationship. That is, a portion of the second semiconductor chip 230 protrudes relative to the first semiconductor chip 220 in a horizontal direction (e.g., the X direction and / or the Y direction). The second semiconductor chip 230 can be stacked on the first semiconductor chip 220 such that the first surface 230a on which the second chip pad 231 is disposed of on the second semiconductor chip 230 faces upward, and the second surface 230b of the second semiconductor chip 230 opposite to the first surface 230a faces the first semiconductor chip 220. An adhesive layer 233 can be disposed between the second semiconductor chip 230 and the first semiconductor chip 220 to adhere the second semiconductor chip 230.

[0137] The second chip pad 231 of the second semiconductor chip 230 may be arranged along one side of the second semiconductor chip 230. The second chip pad 231 may be electrically connected to the upper substrate pad 215 of the packaging substrate 210 via conductive wire 281.

[0138] In some exemplary embodiments, the first semiconductor chip 220 and the second semiconductor chip 230 may be different types of semiconductor chips. For example, when the first semiconductor chip 220 is a non-memory chip, the second semiconductor chip 230 may be a memory chip. In some exemplary embodiments, the first semiconductor chip 220 and the second semiconductor chip 230 may be the same type of semiconductor chip. In some exemplary embodiments, the semiconductor package 200b may be a system-in-package, wherein different types of semiconductor chips are electrically connected to each other to operate as a system.

[0139] A first interposer 250 may be disposed on the first semiconductor chip 220. The first interposer 250 may include a first interposer substrate 251 and a first heat dissipation pattern 253. The first interposer 250 may include a reference. Figures 1 to 3 The aforementioned intermediary layers 100 and 100a.

[0140] The bottom of the first heat dissipation pattern 253 may contact the first semiconductor chip 220, and the top of the first heat dissipation pattern 253 may be exposed to the outside. The first heat dissipation pattern 253 may be electrically insulated from the first semiconductor chip 220 and may contain a material with high thermal conductivity, so that the first heat dissipation pattern 253 can be used to release heat from the first semiconductor chip 220 to the outside. A first thermal interface material 240 may be sandwiched between the first interposer 250 and the first semiconductor chip 220 to enhance the thermal coupling between the first heat dissipation pattern 253 and the first semiconductor chip 220.

[0141] A second interposer 260 may be disposed on the second semiconductor chip 230. The second interposer 260 may include a second interposer substrate 261 and a second heat dissipation pattern 263. The second heat dissipation pattern 263 may include a second through electrode penetrating the second interposer substrate 261, an upper pad on the upper surface of the second interposer substrate 261, and a lower pad on the lower surface of the second interposer substrate 261. Figure 5 The first through electrode 2531, first upper pad 2532, and first lower pad 2533 of the first heat dissipation pattern 253 shown are similar. The top of the second heat dissipation pattern 263 may not be covered by the second interposer substrate 261 or may protrude above the second interposer substrate 261. The second interposer 260 may include reference... Figures 1 to 3 The aforementioned intermediary layers 100 and 100a.

[0142] The bottom of the second heat dissipation pattern 263 may contact the second semiconductor chip 230, and the top of the second heat dissipation pattern 263 may be exposed to the outside. The second heat dissipation pattern 263 may be electrically insulated from the second semiconductor chip 230 and may contain a material with high thermal conductivity, so that the second heat dissipation pattern 263 can be used to release heat from the second semiconductor chip 230 to the outside. A second thermal interface material 241 may be sandwiched between the second interposer 260 and the second semiconductor chip 230 to enhance the thermal coupling between the second heat dissipation pattern 263 and the second semiconductor chip 230.

[0143] The second interposer 260 may be stacked on the second semiconductor chip 230 without overlapping with the second chip pads 231 of the second semiconductor chip 230. For example, when the plurality of second chip pads 231 of the second semiconductor chip 230 are disposed adjacent to the side edge of the first surface 230a of the second semiconductor chip 230, the second interposer 260 may be spaced apart from the side edge of the first surface 230a of the second semiconductor chip 230 by a required distance (or, alternatively, a predetermined distance) so as not to cover the plurality of second chip pads 231 of the second semiconductor chip 230.

[0144] Figure 10A , Figure 10B and Figure 10C These are examples illustrating some exemplary embodiments based on the concepts of the present invention. Figure 9 Plan view of the first and second interposers of the semiconductor package shown.

[0145] Reference Figure 9 and Figure 10ATwo second semiconductor chips 230 may be stacked on top of a first semiconductor chip 220. A second interposer layer 260 may be stacked on each of the two second semiconductor chips 230. The two second semiconductor chips 230 may be spaced apart from each other, with a first interposer layer 250 between them. In this case, the first interposer layer 250 may cover the remaining portion of the second surface 220b of the first semiconductor chip 220, except for the portion on which the second semiconductor chip 230 is disposed.

[0146] The first interposer 250 may include a protruding portion (e.g., a portion protruding downward along the Z direction) to at least partially surround the sidewall of the second semiconductor chip 230. For example, when the second chip pad 231 of the second semiconductor chip 230 is disposed adjacent to the first sidewall of the second semiconductor chip 230, the first interposer 250 may surround the second sidewall, third sidewall, and fourth sidewall of the second semiconductor chip 230.

[0147] Reference Figure 9 and Figure 10B The first interposer 250 may include multiple segments disposed on the first semiconductor chip 220. For example, the first interposer 250 may include a first sub-interposer 250a on the central region of the second surface 220b of the first semiconductor chip 220 and two second sub-interposers 250b on the edge region of the second surface 220b of the first semiconductor chip 220. The first sub-interposer 250a may include a first sub-interposer substrate 251a and a first sub-heat dissipation pattern 253a. Each of the second sub-interposers 250b may include a second sub-interposer substrate 251b and a second sub-heat dissipation pattern 253b.

[0148] The first sub-interceptor layer 250a and the second sub-interceptor layer 250b may at least partially surround the sidewalls of the second semiconductor chip 230. For example, when the second chip pad 231 of the second semiconductor chip 230 is disposed adjacent to the first sidewall of the second semiconductor chip 230, the first sub-interceptor layer 250a may be disposed facing the second sidewall of the second semiconductor chip 230 opposite to the first sidewall of the second semiconductor chip 230, and the second sub-interceptor layer 250b may be disposed facing the opposing third and fourth sidewalls of the second semiconductor chip 230, respectively. The third and fourth sidewalls of the second semiconductor chip 230 may be perpendicular to the first and second sidewalls of the second semiconductor chip 230.

[0149] Reference Figure 9 and Figure 10CThe density of the plurality of first sub-heat dissipation patterns 253a included in the first sub-intermediate layer 250a may differ from the density of the plurality of second heat dissipation patterns 263 included in the second intermediate layer 260. For example, when the heat generation of the first semiconductor chip 220 is greater than the heat generation of the second semiconductor chip 230, the density of the plurality of first sub-heat dissipation patterns 253a included in the first sub-intermediate layer 250a may be increased to improve the heat dissipation of the first semiconductor chip 220.

[0150] In some exemplary embodiments, the density of the first heat dissipation patterns 253 (e.g., 253a and 253b) of the first interposer layer 250 may vary between different regions. For example, the density of the plurality of first sub-heat dissipation patterns 253a of the first sub-interposer layer 250a may be greater than the density of the plurality of second sub-heat dissipation patterns 253b of each of the second sub-interposer layers 250b.

[0151] Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor package according to the concept of the present invention. For ease of explanation, descriptions of the same content as above are briefly provided or omitted.

[0152] Reference Figure 11 Except that the first interposer 250 and the second interposer 260 are stacked in the vertical direction (e.g., the Z direction), the semiconductor package 200c can be coupled with... Figure 9 The semiconductor package 200b shown is substantially the same as or substantially similar to the semiconductor package shown.

[0153] For example, semiconductor package 200c may include a first interposer 250 on a first semiconductor chip 220 and a second interposer 260 on a second semiconductor chip 230. The first interposer 250 and the second interposer 260 may be stacked in the vertical direction. The second interposer 260 may cover the first surface 230a of the second semiconductor chip 230 and the upper surface of the first interposer 250.

[0154] In this configuration, the second heat dissipation pattern 263 of the second interposer 260 can be aligned vertically with the first heat dissipation pattern 253 of the first interposer 250. Therefore, heat from the first semiconductor chip 220 can be released to the outside through the first heat dissipation pattern 253 and the second heat dissipation pattern 263. Furthermore, a third thermal interface material 243 can be sandwiched between the first interposer 250 and the second interposer 260 to enhance the thermal coupling between the first heat dissipation pattern 253 and the second heat dissipation pattern 263.

[0155] Reference Figure 12Except that the second semiconductor chip 230 is mounted on the first semiconductor chip 220 via a flip-chip bonding method, the semiconductor package 200d can be coupled with... Figure 9 The semiconductor package 200b shown is substantially the same as or substantially similar to the semiconductor package shown.

[0156] For example, the second semiconductor chip 230 can be mounted on the first semiconductor chip 220 via the inter-chip connector 235 and the through silicon via (TSV) 227 in the first semiconductor chip 220. Furthermore, the second semiconductor chip 230 can be electrically connected to the packaging substrate 210 via the inter-chip connector 235 and the TSV 227 in the first semiconductor chip 220. A bottom filler layer 237 can fill the space between the second semiconductor chip 230 and the first semiconductor chip 220, and can enclose the inter-chip connector 235.

[0157] The second semiconductor chip 230 can be configured such that the first surface 230a on which the second chip pad 231 is disposed faces the first semiconductor chip 220. A second interposer 260 can be disposed on the second surface 230b of the second semiconductor chip 230. Since the second chip pad 231 is not disposed on the second surface 230b on which the second interposer 260 is disposed, the second interposer 260 can cover the entire second surface 230b of the second semiconductor chip 230. The bottom of the first heat dissipation pattern 253 included in the first interposer 250 can contact the first semiconductor chip 220. The top of the first heat dissipation pattern 253 included in the first interposer 250 may not be covered by the first interposer substrate 251 or may protrude above the first interposer substrate 251. The bottom of the second heat dissipation pattern 263 included in the second interposer 260 can contact the second semiconductor chip 230. The top of the second heat dissipation pattern 263 included in the second interposer 260 may not be covered by the second interposer substrate 261 or may protrude above the second interposer substrate 261.

[0158] Reference Figure 13 Except for the first interposer 250 and the second interposer 260 being stacked in the vertical direction, the semiconductor package 200e can be coupled with... Figure 12 The semiconductor package 200d shown is substantially the same as or substantially similar to the semiconductor package shown.

[0159] For example, semiconductor package 200e may include a first interposer 250 on a first semiconductor chip 220 and a second interposer 260 on a second semiconductor chip 230. The first interposer 250 and the second interposer 260 may be stacked in the vertical direction. The second interposer 260 may cover the second surface 230b of the second semiconductor chip 230 and the upper surface of the first interposer 250.

[0160] In this configuration, the second heat dissipation pattern 263 of the second interposer 260 and the first heat dissipation pattern 253 of the first interposer 250 can be aligned vertically. Therefore, heat from the first semiconductor chip 220 can be released to the outside through the first heat dissipation pattern 253 and the second heat dissipation pattern 263. Furthermore, a third thermal interface material 243 can be sandwiched between the first interposer 250 and the second interposer 260 to enhance the thermal coupling between the first heat dissipation pattern 253 and the second heat dissipation pattern 263.

[0161] Reference Figure 14 Except for the second surface 230b of the second semiconductor chip 230, which is exposed to the outside, the semiconductor package 200f can be coupled with... Figure 12 The semiconductor package 200d shown is substantially the same as or substantially similar to the semiconductor package shown.

[0162] For example, the molding layer 270 may cover the sidewalls of the second semiconductor chip 230 and expose the second surface 230b of the second semiconductor chip 230. Heat from the second semiconductor chip 230 can be released to the outside through the exposed second surface 230b of the second semiconductor chip 230.

[0163] Reference Figure 15 In addition to further including a heat sink 285, the semiconductor package 200g can be combined with... Figure 9 The semiconductor package 200b shown is substantially the same as or substantially similar to the semiconductor package shown.

[0164] For example, the semiconductor package 200g may include a heat sink 285 on a first interposer 250 and / or a second interposer 260. The heat sink 285 may be thermally coupled to a first heat dissipation pattern 253 of the first interposer 250 and / or a second heat dissipation pattern 263 of the second interposer 260. For example, the heat sink 285 may be connected to the upper pad of the first heat dissipation pattern 253 and / or the upper pad of the second heat dissipation pattern 263.

[0165] In some exemplary embodiments, a thermal interface material 287 may be disposed between the first interposer 250 and the heat sink 285 and / or between the second interposer 260 and the heat sink 285. The thermal interface material 287 can physically fix the heat sink 285 to the first interposer 250 and / or the second interposer 260, and can enhance the thermal coupling between the heat sink 285 and the first heat dissipation pattern 253 of the first interposer 250 and / or between the heat sink 285 and the second heat dissipation pattern 263 of the second interposer 260.

[0166] Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor package according to the concept of the present invention. For ease of explanation, descriptions of the same content as above are briefly provided or omitted.

[0167] Reference Figure 16 The semiconductor package 300 may include a first semiconductor chip 220, a first interposer 250 on the first semiconductor chip 220, a molding layer 270 for molding the first semiconductor chip 220 and the first interposer 250, and a redistribution structure 400.

[0168] The first semiconductor chip 220 can be configured such that the first surface 220a on which the first chip pad 221 is disposed faces downward. The redistribution structure 400 can be disposed on the first surface 220a of the first semiconductor chip 220. The first interposer layer 250 can be disposed on the second surface 220b of the first semiconductor chip 220.

[0169] The first interposer 250 may include a first interposer substrate 251 and a first heat dissipation pattern 253. The bottom of the first heat dissipation pattern 253 may contact the first semiconductor chip 220, and the top of the first heat dissipation pattern 253 may be exposed to the outside. A first thermal interface material 240 may be disposed between the first interposer 250 and the first semiconductor chip 220 to enhance the thermal coupling between the first heat dissipation pattern 253 and the first semiconductor chip 220.

[0170] The redistribution structure 400 may include a first insulating layer 411, a second insulating layer 413, and a redistribution pattern 420.

[0171] A first insulating layer 411 may be disposed on a first surface 220a of the first semiconductor chip 220 and a lower surface of the molding layer 270. The first insulating layer 411 may comprise an insulating material (e.g., oxides and / or nitrides). The first insulating layer 411 may include openings to expose a first chip pad 221 of the first semiconductor chip 220.

[0172] A redistribution pattern 420 may be disposed on the first insulating layer 411. A portion of the redistribution pattern 420 may extend along the surface of the first insulating layer 411, and another portion of the redistribution pattern 420 may be electrically and physically connected to the first chip pad 221 of the first semiconductor chip 220 through the opening.

[0173] A second insulating layer 413 may be disposed on the first insulating layer 411 and the redistribution pattern 420. The second insulating layer 413 may comprise an insulating material (e.g., oxides and / or nitrides). The second insulating layer 413 may include an opening to expose a portion of the redistribution pattern 420. An external connection terminal 290 may be disposed on the portion of the redistribution pattern 420 exposed through the opening.

[0174] Reference Figure 17 In addition to further including a second semiconductor chip 230 on the first semiconductor chip 220 and a second interposer 260 on the second semiconductor chip 230, the semiconductor package 300a can be coupled with... Figure 16 The semiconductor package 300 shown is substantially the same or substantially similar.

[0175] For example, the second semiconductor chip 230 can be mounted on the first semiconductor chip 220 via the inter-chip connector 235. The second semiconductor chip 230 can be electrically connected to the first semiconductor chip 220 via the inter-chip connector 235 and the through-silicon via 227 of the first semiconductor chip 220. Furthermore, the second semiconductor chip 230 can be electrically connected to the redistribution pattern 420 of the redistribution structure 400 via the inter-chip connector 235 and the through-silicon via 227 of the first semiconductor chip 220.

[0176] The second interposer 260 may be disposed on the second surface 230b of the second semiconductor chip 230, and may include a second interposer substrate 261 and a second heat dissipation pattern 263. A second thermal interface material 241 may be disposed between the second interposer 260 and the second semiconductor chip 230 to enhance the thermal coupling between the second heat dissipation pattern 263 and the second semiconductor chip 230.

[0177] The second semiconductor chip 230 can be configured such that the first surface 230a of the second semiconductor chip 230, on which the second chip pad 231 is disposed, faces the first semiconductor chip 220. A second interposer 260 can be disposed on the second surface 230b of the second semiconductor chip 230. Since the second chip pad 231 is not disposed on the second surface 230b of the second semiconductor chip 230, the second interposer 260 can cover the entire second surface 230b of the second semiconductor chip 230.

[0178] Reference Figure 18 Except for the first interposer 250 and the second interposer 260 being stacked in the vertical direction, the semiconductor package 300b can be coupled with... Figure 17 The semiconductor package 300a shown is substantially the same as or substantially similar to the semiconductor package shown.

[0179] For example, semiconductor package 300b may include a first interposer 250 on a first semiconductor chip 220 and a second interposer 260 on a second semiconductor chip 230. The first interposer 250 and the second interposer 260 may be stacked in the vertical direction. The second interposer 260 may cover the second surface 230b of the second semiconductor chip 230 and the upper surface of the first interposer 250.

[0180] In this configuration, the second heat dissipation pattern 263 of the second interposer 260 and the first heat dissipation pattern 253 of the first interposer 250 can be aligned vertically. Therefore, the heat from the first semiconductor chip 220 can be released to the outside through the first heat dissipation pattern 253 of the first interposer 250 and the second heat dissipation pattern 263 of the second interposer 260. Furthermore, a third thermal interface material 243 can be disposed between the first interposer 250 and the second interposer 260 to enhance the thermal coupling between the first heat dissipation pattern 253 and the second heat dissipation pattern 263.

[0181] Reference Figure 19 Except for the semiconductor package 300c, which does not include a second interposer (see...) Figure 17 As shown in Figure 260), and the second surface 230b of the second semiconductor chip 230 is exposed to the outside, the semiconductor package 300c can be coupled with Figure 17 The semiconductor package 300a shown is the same as or substantially similar to the one shown.

[0182] For example, the molding layer 270 may cover the sidewalls of the second semiconductor chip 230 and expose the second surface 230b of the second semiconductor chip 230. Heat from the second semiconductor chip 230 can be released to the outside through the exposed second surface 230b of the second semiconductor chip 230.

[0183] Reference Figure 20 In addition to the second semiconductor chip 230 being directly connected to the redistribution pattern 420, the semiconductor package 300d can be connected to... Figure 17 The semiconductor package 300a shown is substantially the same as or substantially similar to the semiconductor package shown.

[0184] Reference Figure 20The second semiconductor chip 230 can be disposed offset from the first semiconductor chip 220. That is, a portion of the second semiconductor chip 230 protrudes horizontally relative to the first semiconductor chip 220. A first surface 230a on the top of the second semiconductor chip 230, on which a second chip pad 231 is disposed, can contact the first semiconductor chip 220. The second chip pad 231 of the second semiconductor chip 230 can be laterally spaced from the sidewall of the first semiconductor chip 220. In this case, a portion of the redistribution pattern 420 can extend vertically through the opening of the molding layer 270 and can be physically and electrically connected to the second chip pad 231 of the second semiconductor chip 230.

[0185] Figure 21A and Figure 21B This illustrates an exemplary embodiment of manufacturing according to the concept of the present invention. Figure 9 A cross-sectional view of the method for producing the semiconductor package shown. For ease of explanation, descriptions of the same content as above are briefly provided or omitted.

[0186] Reference Figure 21A The first semiconductor chip 220 can be positioned on the packaging substrate 210. The first semiconductor chip 220 can be mounted on the packaging substrate 210 using a flip-chip bonding method. A first surface 220a of the first semiconductor chip 220, on which a first chip pad 221 is provided, can face the packaging substrate 210. After mounting the first semiconductor chip 220 on the packaging substrate 210, a second semiconductor chip 230 can be stacked on top of the first semiconductor chip 220. The second semiconductor chip 230 can be offset relative to the first semiconductor chip 220. A portion of the second semiconductor chip 230 can protrude horizontally relative to the first semiconductor chip 220. The second semiconductor chip 230 can be secured to the first semiconductor chip 220 using an adhesive layer 233.

[0187] After stacking the second semiconductor chip 230, a conductive line 281 can be formed by a wire bonding process to connect the second chip pad 231 of the second semiconductor chip 230 to the upper substrate pad 215 of the packaging substrate 210.

[0188] Subsequently, a first thermal interface material 240 covering at least a portion of the first semiconductor chip 220 and a second thermal interface material 241 covering at least a portion of the second semiconductor chip 230 can be formed. For example, the first thermal interface material 240 and the second thermal interface material 241 can be formed by applying a material with high thermal conductivity to the first semiconductor chip 220 and the second semiconductor chip 230 by an application method (e.g., a spraying method).

[0189] Reference Figure 21BThe first interposer 250 can be positioned on the first semiconductor chip 220, and the second interposer 260 can be positioned on the second semiconductor chip 230. With the first interposer 250 positioned on the first thermal interface material 240 and the second interposer 260 positioned on the second thermal interface material 241, the first thermal interface material 240 and the second thermal interface material 241 can be cured to fix the first interposer 250 and the second interposer 260 to the first semiconductor chip 220 and the second semiconductor chip 230, respectively.

[0190] Subsequently, a molding layer can be formed (see...) Figure 9 As shown in 270), a first semiconductor chip 220, a second semiconductor chip 230, a first interposer 250, and a second interposer 260 are molded. (See molding layer 270) Figure 9 As shown in 270), it can be configured to expose the top of the first heat dissipation pattern 253 of the first interposer 250 and the top of the second heat dissipation pattern 263 of the second interposer 260 to the outside. This can be achieved by referring to... Figure 6 , Figure 7A and Figure 7B The method described is the same as or substantially similar to the method used to form the molding layer (see [link]). Figure 9 As shown in Figure 270).

[0191] After the molding layer 270 is formed, it can be completed through a singulation process. Figure 9 The individualized semiconductor package 200a is shown.

[0192] Figure 22A , Figure 22B , Figure 22C and Figure 22D This illustrates an exemplary embodiment of manufacturing according to the concept of the present invention. Figure 17 A cross-sectional view of the method for producing the semiconductor package shown. For ease of explanation, descriptions of the same content as above are briefly provided or omitted.

[0193] Reference Figure 22A The first semiconductor chip 220 can be disposed on the carrier CA, such that the first surface 220a on the top of the first semiconductor chip 220, on which the first chip pad 221 is formed, contacts the carrier CA.

[0194] After the first semiconductor chip 220 is placed on the carrier CA, the second semiconductor chip 230 can be stacked on the first semiconductor chip 220 using a flip-chip bonding method. In this case, the first surface 230a of the second semiconductor chip 230, on which the second chip pad 231 is formed, faces the first semiconductor chip 220.

[0195] After stacking the second semiconductor chip 230, a first thermal interface material 240 covering at least a portion of the first semiconductor chip 220 and a second thermal interface material 241 covering at least a portion of the second semiconductor chip 230 can be formed. For example, the first thermal interface material 240 and the second thermal interface material 241 can be formed by applying a material with high thermal conductivity to the first semiconductor chip 220 and the second semiconductor chip 230 by an application method (e.g., a spraying method).

[0196] Reference Figure 22B The first interposer 250 can be positioned on the first semiconductor chip 220, and the second interposer 260 can be positioned on the second semiconductor chip 230. With the first interposer 250 positioned on the first thermal interface material 240 and the second interposer 260 positioned on the second thermal interface material 241, the first thermal interface material 240 and the second thermal interface material 241 can be cured to fix the first interposer 250 and the second interposer 260 to the first semiconductor chip 220 and the second semiconductor chip 230, respectively.

[0197] Reference Figure 22C A molding layer 270 can be formed to mold the first semiconductor chip 220, the second semiconductor chip 230, the first interposer 250, and the second interposer 260. The molding layer 270 can be formed to expose the top of the first heat dissipation pattern 253 of the first interposer 250 and the top of the second heat dissipation pattern 263 of the second interposer 260 to the outside. This can be achieved by referring to... Figure 6 , Figure 7A and Figure 7B The molding layer 270 is formed by the same or substantially similar method described herein.

[0198] Reference Figure 22D After forming the molding layer 270, it can be Figure 22C The resulting structure and Figure 22C The carrier CA shown is separated. Thereafter, a redistribution structure 400 can be formed on the surface of the molding layer 270 and on the first surface 220a on which the first chip pad 221 is formed above the first semiconductor chip 220.

[0199] For example, a first insulating layer 411 may be formed on the surface of the molding layer 270 and on the first surface 220a of the first semiconductor chip 220. To form the first insulating layer 411, an insulating layer may be formed to cover the surface of the molding layer 270 and the first surface 220a of the first semiconductor chip 220, and then a portion of the insulating layer may be removed to form an opening thereby exposing the first chip pad 221 of the first semiconductor chip 220.

[0200] Subsequently, a redistribution pattern 420 can be formed on the first insulating layer 411. A portion of the redistribution pattern 420 can be connected to the first chip pad 221 through an opening in the first insulating layer 411. To form the redistribution pattern 420, a conductive layer can be formed on the first insulating layer 411 and the first chip pad 221, and the conductive layer can then be patterned.

[0201] A second insulating layer 413 may be formed on the first insulating layer 411 and the redistribution pattern 420. In order to form the second insulating layer 413, an insulating layer may be formed to cover the first insulating layer 411 and the redistribution pattern 420, and then a portion of the insulating layer may be removed to form an opening, thereby exposing a portion of the redistribution pattern 420.

[0202] External connection terminals 290 may be formed on the portion of the redistribution pattern 420 exposed through the opening in the second insulating layer 413. The external connection terminals 290 may be, for example, solder balls or bumps. After forming the external connection terminals 290, a single process can be used to complete the process. Figure 17 The individualized semiconductor package 300a is shown.

[0203] While the concept of the invention has been shown and described with reference to some exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the exemplary embodiments without departing from the spirit and scope of the concept of the invention as set forth in the foregoing claims.

Claims

1. A semiconductor package, comprising: First semiconductor chip; A first interposer layer is disposed on the first semiconductor chip. The first interposer layer includes a first interposer layer substrate and a first heat dissipation pattern. The first heat dissipation pattern passes through the first interposer layer substrate and is electrically insulated from the first semiconductor chip. as well as A molding layer covering at least a portion of the first semiconductor chip and at least a portion of the first interposer layer. The first heat dissipation pattern includes a first through electrode passing through the first interposer substrate, a first upper pad on the upper surface of the first interposer substrate and connected to the first through electrode, and an upper cover layer covering the first upper pad. The molding layer covers at least a portion of the sidewalls of the first upper pad and at least a portion of the upper surface of the first intermediate layer substrate located between the first upper pads, and At least a portion of the upper surface and at least a portion of the sidewall of the first upper pad are not covered by the molding layer.

2. The semiconductor package of claim 1, wherein the width of the first upper pad in the horizontal direction is greater than the width of the first through electrode in the horizontal direction.

3. The semiconductor package of claim 1, wherein the first heat dissipation pattern further includes a first lower pad, the first lower pad being on the lower surface of the first interposer substrate and connected to the first through electrode.

4. The semiconductor package of claim 3, wherein the width of the first lower pad in the horizontal direction is greater than the width of the first through electrode in the horizontal direction.

5. The semiconductor package according to claim 3, further comprising: A first thermal interface material is disposed between the first interposer and the first semiconductor chip and covers the sidewall of the first lower pad.

6. The semiconductor package of claim 3, wherein the first heat dissipation pattern further includes a lower cover layer covering the first lower pad.

7. The semiconductor package according to claim 1, further comprising: The second semiconductor chip is on the first semiconductor chip; as well as A second interposer layer, on the second semiconductor chip, includes a second interposer layer substrate and a second heat dissipation pattern extending through the second interposer layer substrate. The second heat dissipation pattern is electrically insulated from the second semiconductor chip, and The top of the second heat dissipation pattern protrudes above the second interposer substrate.

8. The semiconductor package of claim 7, wherein the first interposer includes a protrusion surrounding a sidewall of the second semiconductor chip.

9. The semiconductor package of claim 1, wherein the first interposer layer comprises a first sub-interposer layer and a second sub-interposer layer spaced apart from each other.

10. The semiconductor package of claim 7, wherein... The first intermediary layer further includes a plurality of third heat dissipation patterns, and The second interposer layer includes a plurality of second heat dissipation patterns, wherein the plurality of second heat dissipation patterns include the second heat dissipation patterns, and The density of the plurality of third heat dissipation patterns is different from the density of the plurality of second heat dissipation patterns.

11. The semiconductor package of claim 1, further comprising: The second semiconductor chip is located on the first semiconductor chip. The first surface of the second semiconductor chip, which has a chip pad, faces the first semiconductor chip, and... The second semiconductor chip is electrically connected to the first semiconductor chip through a silicon via.

12. The semiconductor package of claim 1, wherein the first interposer substrate comprises an organic material.

13. A semiconductor package, comprising: First semiconductor chip; The second semiconductor chip is on the first semiconductor chip; A first interposer layer, on the first semiconductor chip, includes a first interposer layer substrate and a first heat dissipation pattern passing through the first interposer layer substrate; as well as The second interposer layer, on the second semiconductor chip, includes a second interposer layer substrate and a second heat dissipation pattern through the second interposer layer substrate; A molding layer covers the first semiconductor chip, the second semiconductor chip, the first interposer layer, and the second interposer layer. The first heat dissipation pattern includes a first upper pad on the upper surface of the first interposer substrate. The second heat dissipation pattern includes a second upper pad on the upper surface of the second interposer substrate and an upper cover layer covering the second upper pad. The molding layer covers at least a portion of the sidewalls of the second upper pad and at least a portion of the upper surface of the second intermediate layer substrate located between the second upper pads, and At least a portion of the upper surface and at least a portion of the sidewall of the second upper pad are not covered by the molding layer.

14. The semiconductor package of claim 13, wherein... The bottom of the first heat dissipation pattern contacts the first semiconductor chip, and The bottom of the second heat dissipation pattern contacts the second semiconductor chip.

15. The semiconductor package of claim 13, further comprising: A first thermal interface material is disposed between the first semiconductor chip and the first interposer layer; as well as A second thermal interface material is disposed between the second semiconductor chip and the second interposer layer. The first heat dissipation pattern includes a first lower pad on the lower surface of the first interposer substrate. The second heat dissipation pattern includes a second lower pad on the lower surface of the second interposer substrate. The first thermal interface material covers at least a portion of the first lower pad, and The second thermal interface material covers at least a portion of the second lower pad.

16. The semiconductor package of claim 13, wherein the second interposer is on the first interposer such that the second heat dissipation pattern of the second interposer is aligned with the first heat dissipation pattern of the first interposer in the vertical direction.

17. The semiconductor package of claim 13, further comprising: A packaging substrate on which the first semiconductor chip is mounted. A portion of the second semiconductor chip protrudes laterally relative to the first semiconductor chip, and The second semiconductor chip is electrically connected to the packaging substrate via conductive lines.

18. A semiconductor package, comprising: First semiconductor chip; The second semiconductor chip is on the first semiconductor chip; The third semiconductor chip is located on the first semiconductor chip; A first interposer layer is disposed on the first semiconductor chip, the first interposer layer comprising a first interposer layer substrate and a plurality of first heat dissipation patterns electrically insulated from the first semiconductor chip; The second interposer layer, on the second semiconductor chip, includes a second interposer layer substrate and a plurality of second heat dissipation patterns electrically insulated from the second semiconductor chip. A third interposer layer is provided on the third semiconductor chip. The third interposer layer includes a third interposer layer substrate and a plurality of third heat dissipation patterns that are electrically insulated from the third semiconductor chip. as well as A molding layer covers at least a portion of the first semiconductor chip, at least a portion of the first interposer layer, at least a portion of the second semiconductor chip, at least a portion of the second interposer layer, at least a portion of the third semiconductor chip, and at least a portion of the third interposer layer. Each of the plurality of first heat dissipation patterns includes a first through electrode passing through the first interposer substrate, a first upper pad on the upper surface of the first interposer substrate and connected to the first through electrode, and an upper cover layer covering the first upper pad. Each of the plurality of second heat dissipation patterns includes a second through electrode passing through the second interposer substrate and a second upper pad on the upper surface of the second interposer substrate and connected to the second through electrode. Each of the plurality of third heat dissipation patterns includes a third through electrode extending through the third interposer substrate and a third upper pad on the upper surface of the third interposer substrate and connected to the third through electrode. The molding layer covers at least a portion of the sidewalls of the first upper pad and at least a portion of the upper surface of the first intermediate layer substrate located between the first upper pads, and At least a portion of the upper surface and at least a portion of the sidewall of the first upper pad are not covered by the molding layer.

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