Non-volatile memory devices

Abstract

A nonvolatile memory device includes: a mold structure comprising a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate; a semiconductor pattern penetrating the mold structure and contacting the substrate; a first charge storage film; and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each gate electrode and the semiconductor pattern. Each gate electrode includes a first recess and a second recess, respectively, recessed inward from a side surface of the gate electrode. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a nonvolatile memory device and a method of manufacturing the same. More particularly, exemplary embodiments of the present disclosure relate to a nonvolatile memory device including an isolated charge storage film and a method of manufacturing the same. Background Art

[0002] Semiconductor memory devices are memory devices implemented using semiconductor materials such as, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices.

[0003] A volatile memory device is a memory device whose stored data is lost when power is lost. Volatile memory devices may include, for example, static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A non-volatile memory device is a memory device that retains its stored data even when power is removed. Non-volatile memory devices may include, for example, flash memory devices, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), resistive memory devices (e.g., phase change RAM (PRAM)), ferroelectric RAM (FRAM), and resistive RAM (RRAM).

[0004] To meet customer demands for better performance and lower costs, the integration density of non-volatile memory devices continues to increase. However, in two-dimensional (2D) or planar memory devices, the integration density is determined by (and therefore limited by) the area occupied by the unit memory cell. Therefore, in recent years, three-dimensional (3D) memory devices with a vertical arrangement of unit memory cells have been developed. Summary of the Invention

[0005] Exemplary embodiments of the present disclosure provide a nonvolatile memory device having improved integration density, the nonvolatile memory device including forming two charge storage films per word line.

[0006] Exemplary embodiments of the present disclosure also provide a method for manufacturing a nonvolatile memory device with improved integration density, the method including forming two charge storage films per word line.

[0007] According to an exemplary embodiment of the present disclosure, a nonvolatile memory device includes: a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate; a semiconductor pattern penetrating the mold structure and contacting the substrate; a first charge storage film; and a second charge storage film. The second charge storage film is separated from the first charge storage film. The first and second charge storage films are disposed between each gate electrode and the semiconductor pattern. Each gate electrode includes a first recess and a second recess, each recessed inward from a side surface of the gate electrode. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

[0008] According to an exemplary embodiment of the present disclosure, a nonvolatile memory device includes a mold structure comprising a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate. Each gate electrode includes first to third portions stacked sequentially. The nonvolatile memory device also includes: a semiconductor pattern penetrating the mold structure and contacting the substrate; a first charge storage film disposed between the first portion and the semiconductor pattern; and a second charge storage film disposed between the third portion and the semiconductor pattern. A side surface of the first portion extends further into the first portion than a side surface of the second portion, and a side surface of the third portion extends further into the third portion than a side surface of the second portion.

[0009] According to an exemplary embodiment of the present disclosure, a nonvolatile memory device includes: a mold structure including a first insulating pattern, a gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern extending through the mold structure and contacting the substrate; a first charge storage film; and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between the gate electrode and the semiconductor pattern. The gate electrode includes a first recess and a second recess, the first recess extending further into the gate electrode than a side surface of the first insulating pattern, and the second recess extending further into the gate electrode than a side surface of the second insulating pattern. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

[0010] According to an exemplary embodiment of the present disclosure, a method for manufacturing a non-volatile memory device includes forming a plurality of insulating films and a plurality of sacrificial films alternately stacked on a substrate. Each sacrificial film includes a first sacrificial film to a third sacrificial film stacked sequentially. The method also includes: forming a channel hole exposing the substrate by penetrating the plurality of insulating films and the plurality of sacrificial films; forming a first recess in the first sacrificial film and a second recess in the third sacrificial film by performing a recess formation process having an etching selectivity relative to the first sacrificial film and the third sacrificial film exposed by the channel hole; forming a first charge storage film filling at least a portion of the first recess and a second charge storage film filling at least a portion of the second recess; and forming a semiconductor pattern on the first charge storage film and the second charge storage film, the semiconductor pattern filling at least a portion of the channel hole and contacting the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a schematic circuit diagram provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0013] Figure 2 1 is a schematic layout diagram provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0014] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA.

[0015] Figure 4 According to an exemplary embodiment of the present disclosure Figure 3 Magnified view of region R1.

[0016] Figure 5A and Figure 5B are views provided to describe exemplary operations of a nonvolatile memory device according to exemplary embodiments of the present disclosure.

[0017] 6A to 6D According to an exemplary embodiment of the present disclosure Figure 3 An enlarged view of the area corresponding to region R1.

[0018] Figure 7 is a cross-sectional view provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0019] Figure 8 According to an exemplary embodiment of the present disclosure Figure 7 Magnified view of region R2.

[0020] Figure 9 1 is a schematic layout diagram provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0021] Figures 10 to 23 is a view illustrating an intermediate stage of manufacturing and is provided to describe a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0022] Figures 24 to 28 is a view illustrating an intermediate stage of manufacturing and is provided to describe a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0024] It should be understood that the terms "first," "second," "third," etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in an exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0025] It should also be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0026] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] For ease of description, spatially relative terms such as "under," "beneath," "below," "under," "above," "on," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as "under" or "below" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both above and below orientations.

[0028] It should also be understood that when a component, such as a film, region, layer, or element, is referred to as being "on," "connected to," "coupled to," or "adjacent" another component, the component can be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or intervening components may be present. It should also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or one or more intervening components may also be present. Other words used to describe the relationship between elements should be interpreted in a similar manner.

[0029] Herein, when a value is described as being substantially the same as or equal to another value, it will be understood that, within measurement error, these values ​​are equal to one another, or, if measurably unequal, these values ​​are sufficiently close in value to be functionally equal to one another, as will be understood by one of ordinary skill in the art. It will also be understood that when two components or directions are described as extending substantially parallel or perpendicular to one another, these two components or directions extend exactly parallel or perpendicular to one another, or extend approximately parallel or perpendicular to one another, within measurement error, as will be understood by one of ordinary skill in the art. Other uses of the word "substantially" should be interpreted in a similar manner.

[0030] In the following, reference will be made to Figures 1 to 9 A nonvolatile memory device according to exemplary embodiments of the present disclosure is described.

[0031] Figure 1 is a schematic circuit diagram provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0032] Reference Figure 1 , a nonvolatile memory device according to an exemplary embodiment may include a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR).

[0033] A plurality of bit lines (BL) may be arranged two-dimensionally. For example, a plurality of bit lines (BL) may be spaced apart from each other and extend in a first direction X. Each bit line (BL) may be connected in parallel to a plurality of cell strings (CSTR) arranged in the first direction X. A plurality of cell strings (CSTR) arranged in a second direction Y may be commonly connected to a common source line (CSL). For example, a plurality of cell strings (CSTR) may be disposed between a plurality of bit lines (BL) and a common source line (CSL).

[0034] According to an exemplary embodiment, a plurality of common source lines (CSL) may be arranged two-dimensionally. For example, the plurality of common source lines (CSL) may be spaced apart from each other and extend in the second direction Y. The plurality of common source lines (CSL) may be electrically applied with the same voltage, or alternatively, may be individually controlled while applying different voltages to the plurality of common source lines (CSL).

[0035] Each cell string (CSTR) may include a ground selection transistor (GST) connected to a common source line (CSL), a string selection transistor (SST) connected to a bit line (BL), and a plurality of memory cell transistors (MCTs) disposed between the ground selection transistor (GST) and the string selection transistor (SST). Each memory cell transistor (MCT) may include a data storage element. The ground selection transistor (GST), the string selection transistor (SST), and the memory cell transistors (MCT) may be connected to each other, for example, connected in series.

[0036] The common source line (CSL) can be commonly connected to the sources of multiple ground selection transistors (GST). In addition, the ground selection line (GSL), multiple word lines (WL1-WLn) and the string selection line (SSL) can be set between the common source line (CSL) and the bit line (BL). The ground selection line (GSL) can be used as the gate electrode of the ground selection transistor (GST), the multiple word lines (WL1-WLn) can be used as the gate electrode of the memory cell transistor (MCT), and the string selection line (SSL) can be used as the gate electrode of the string selection transistor (SST). Therefore, the ground selection line (GSL), the multiple word lines (WL1-WLn) and the string selection line (SSL) can also be collectively referred to as a plurality of gate electrodes (GSL, WL1, SSL), where n is an integer greater than 2.

[0037] Figure 2 1 is a schematic layout diagram provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA.

[0038] Reference Figure 2 and Figure 3 , a nonvolatile memory device according to an exemplary embodiment includes a substrate 100 , a mold structure (MS), a plurality of channel structures (CS), and a plurality of bit lines (BL).

[0039] The substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, etc. Alternatively, the substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0040] A mold structure (MS) may be formed on the substrate 100. The mold structure (MS) may include a plurality of gate electrodes (GSL, WL1, SSL) and a plurality of insulating patterns 110. For example, a plurality of gate electrodes (GSL, WL1, Each of the plurality of insulating patterns 110 and each of the plurality of insulating patterns 110 may be a stratified structure extending in the first direction X and the second direction Y.

[0041] The plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) may be alternately stacked with the plurality of insulating patterns 110. For example, the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) may be spaced apart from each other along the third direction Z and sequentially stacked. Here, each of the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) may be interposed between two adjacent insulating patterns among the plurality of insulating patterns 110. For example, the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) may be electrically separated from each other by the plurality of insulating patterns 110.

[0042] although Figure 3 The plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) are shown to have the same thickness, but exemplary embodiments are not limited thereto. For example, in exemplary embodiments, some or all of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may have different thicknesses from one another.

[0043] According to an exemplary embodiment, the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may include a ground selection line (GSL), a plurality of word lines (WL1, WL2 to WLn), and a string selection line (SSL). The ground selection line (GSL), the plurality of word lines (WL1, WL2 to WLn), and the string selection line (SSL) may be sequentially stacked on the substrate 100.

[0044] although Figure 3 Only four word lines are shown disposed between the ground selection line (GSL) and the string selection line (SSL), but exemplary embodiments are not limited thereto. For example, in exemplary embodiments, 8, 16, 32, 64, or more word lines may be stacked between the ground selection line (GSL) and the string selection line (SSL).

[0045] Each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may include a conductive material. For example, each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may include a metal (such as tungsten (W), cobalt (Co), or nickel (Ni)) or a semiconductor material (such as silicon). However, exemplary embodiments are not limited thereto.

[0046] Each insulating pattern 110 may include an insulating material. For example, each insulating pattern 110 may include silicon oxide. However, exemplary embodiments are not limited thereto.

[0047] According to an exemplary embodiment, the mold structure (MS) may be isolated by the word line cutting region (WLC). For example, the word line cutting region (WLC) may extend in the second direction Y and cut the mold structure (MS).

[0048] According to an exemplary embodiment, the isolation structure 150 may be formed in a word line cutting region (WLC). Figure 3 As shown, the isolation structure 150 may extend to the substrate 100 by penetrating the mold structure (MS) and may contact the substrate 100. Therefore, the isolation structure 150 may extend in the second direction Y and cut the mold structure (MS). According to exemplary embodiments, the isolation structure 150 may include a plug pattern 152 and a spacer 154.

[0049] The plug pattern 152 may contact the substrate 100 by penetrating the mold structure (MS). For example, the plug pattern 152 may penetrate the mold structure (MS) and may directly contact the substrate 100. According to an exemplary embodiment, the plug pattern 152 may be provided as a common source line (eg, Figure 1 The plug pattern 152 may include a conductive material. The plug pattern 152 may contact the impurity region 105 in the substrate 100. For example, the plug pattern 152 may penetrate the mold structure (MS) and directly contact the impurity region 105 provided in the substrate 100. The impurity region 105 may extend in the second direction Y, for example.

[0050] Spacers 154 may be interposed between the plug pattern 152 and the mold structure (MS). For example, the spacers 154 may extend along the side surfaces of the plug pattern 152. In an exemplary embodiment, the spacers 153 extend along the entire side surfaces of the plug pattern 152. The spacers 154 may include an insulating material. For example, the spacers 154 may electrically displace (e.g., separate) the plug pattern 152 from the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) of the mold structure (MS).

[0051] By penetrating the mold structure (MS), the plurality of channel structures (CS) may be in contact with (e.g., in direct contact with) the substrate 100. Furthermore, the plurality of channel structures (CS) may extend in a direction intersecting the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL). For example, each channel structure (CS) may be a pillar extending in the third direction Z. Each channel structure (CS) may include a semiconductor pattern 120 and an information storage film 140.

[0052] The semiconductor pattern 120 may be in contact with (e.g., in direct contact with) the substrate 100 by penetrating the mold structure (MS). For example, the semiconductor pattern 120 may be in contact with (e.g., in direct contact with) the substrate 100 by extending in the third direction Z. The semiconductor pattern 120 may extend in the third direction Z intersecting the upper surface of the substrate 100. For example, the semiconductor pattern 120 may extend substantially perpendicular to the upper surface of the substrate 100. Although Figure 3 The semiconductor pattern 120 is shown to be cup-shaped, but exemplary embodiments are not limited thereto. For example, in exemplary embodiments, the semiconductor pattern 120 may have various shapes such as a cylindrical shape, a square container shape, a column shape with a full interior, etc.

[0053] The semiconductor pattern 120 may include a semiconductor material such as, for example, single crystal silicon, polycrystalline silicon, an organic semiconductor material, a carbon nanostructure, etc. However, exemplary embodiments are not limited thereto.

[0054] The information storage film 140 may be interposed between the semiconductor pattern 120 and the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL). For example, the information storage film 140 may extend along the side surface of the semiconductor pattern 120. In one exemplary embodiment, the information storage film 140 may extend along the entire side surface of the semiconductor pattern 120.

[0055] The information storage film 140 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material having a higher dielectric constant than silicon oxide. The high-k dielectric material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0056] According to exemplary embodiments, the information storage film 140 may include a plurality of films. For example, the information storage film 140 may include a tunnel insulating film 142, charge storage films 144A and 144B, and a blocking insulating film 146 sequentially stacked on the semiconductor pattern 120. The tunnel insulating film 142 may include, for example, silicon oxide or a high-k dielectric material having a higher dielectric constant than silicon oxide (e.g., Al2O3 and HfO2). The charge storage films 144A and 144B may include, for example, silicon nitride. The blocking insulating film 146 may include, for example, silicon oxide or a high-k dielectric material having a higher dielectric constant than silicon oxide (e.g., Al2O3 and HfO2).

[0057] The information storage film 140 may include two charge storage films (e.g., a first charge storage film 144A and a second charge storage film 144B) separated from each other in each of the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL). For example, the first charge storage film 144A and the second charge storage film 144B may be spatially and electrically separated from each other in the third direction Z by a blocking insulating film 146 disposed between the first charge storage film 144A and the second charge storage film 144B. The first charge storage film 144A and the second charge storage film 144B may be disposed between each of the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) and the semiconductor pattern 120. For example, each of the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) may have corresponding portions of the first charge storage film 144A and the second charge storage film 144B disposed between it and the semiconductor pattern 120. In addition, the two charge storage films (the first charge storage film 144A and the second charge storage film 144B) may be formed in a buried form in each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL). Figure 4 The first charge storage film 144A and the second charge storage film 144B are described in more detail.

[0058] According to exemplary embodiments, each channel structure (CS) may further include a filling insulating pattern 130. The filling insulating pattern 130 may be formed to fill the interior of the cup-shaped semiconductor pattern 120. For example, the semiconductor pattern 120 may conformally extend along the side surfaces and bottom surface of the filling insulating pattern 130. The filling insulating pattern 130 may include, for example, silicon oxide. However, exemplary embodiments are not limited thereto.

[0059] According to an exemplary embodiment, each channel structure (CS) may further include a channel pad 160. The channel pad 160 may be formed to contact (eg, directly contact) an upper portion of the semiconductor pattern 120. For example, the channel pad 160 may be formed within the first interlayer insulating film 210 formed on the mold structure (MS).

[0060] although Figure 3 The channel pad 160 is shown as being formed on the upper surface of the semiconductor pattern 120, but exemplary embodiments are not limited thereto. For example, in one exemplary embodiment, the upper portion of the semiconductor pattern 120 may be formed to extend along the side surface of the channel pad 160. The channel pad 160 may include, for example, polysilicon doped with impurities. However, exemplary embodiments are not limited thereto.

[0061] A plurality of bit lines (BL) may be connected to a plurality of channel structures (CS). For example, each bit line (BL) may be connected to a corresponding channel structure (CS) via a bit line contact 170. For example, the bit line contact 170 may electrically connect the channel structure (CS) and the bit line (BL) by passing through the second interlayer insulating film 310 on the mold structure (MS).

[0062] According to example embodiments, the plurality of bit lines (BL) may extend substantially in parallel along a direction intersecting the word line cutting region (WLC). For example, each bit line (BL) may extend in a first direction X.

[0063] Figure 4 According to an exemplary embodiment of the present disclosure Figure 3 For reference, although Figure 4 Only one word line (eg, the first word line WL1) among the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) is shown, but the first charge storage film 144A and the second charge storage film 144B may be arranged relative to the other gate electrodes (GSL, SSL) is similarly formed.

[0064] Reference Figure 4 Each of the plurality of gate electrodes (GSL, WL1, WL2 ˜WLn, SSL) may include first to third portions 10 , 20 , 30 sequentially stacked on the substrate 100 .

[0065] According to an exemplary embodiment, the side surfaces of the first portion 10 and the third portion 30 may extend further into the first portion 10 and the third portion 30, respectively, than the side surfaces of the second portion 20. For example, the first portion 10 may include a first recess 10R that extends further into the first portion 10 than the side surfaces of the second portion 20, and the third portion 30 may include a second recess 30R that extends further into the third portion 30 than the side surfaces of the second portion 20. For example, the first recess 10R may be recessed inward from the side surface of the first portion 10, and the second recess 30R may be recessed inward from the side surface of the third portion 30. Since the second portion 20 may be interposed between the first portion 10 and the third portion 30, the first recess 10R and the second recess 30R may be spaced apart from each other, with the second portion 20 interposed therebetween. In an exemplary embodiment, the side surface of the second portion 20 may be substantially flat, and the side surfaces of the first portion 10 and the third portion 30 may be recessed into the first portion 10 and the third portion 30, respectively.

[0066] The first charge storage film 144A may be interposed between the first portion 10 and the semiconductor pattern 120, and the second charge storage film 144B may be interposed between the third portion 30 and the semiconductor pattern 120. The first charge storage film 144A may fill at least a portion of the first recess 10R, and the second charge storage film 144B may fill at least a portion of the second recess 30R. Therefore, the two charge storage films corresponding to the first word line WL1 (e.g., the first charge storage film 144A and the second charge storage film 144B) may be formed in a buried manner within the first word line WL1.

[0067] Although the first charge storage film 144A and the second charge storage film 144B are Figure 4 144A and the second charge storage film 144B may be formed to have different sizes from each other. For example, one of the first charge storage film 144A extending into the first portion 10 and the second charge storage film 144B extending into the third portion 30 may extend further into its corresponding portion than the other charge storage film, and / or the length of the surface of one of the first charge storage film 144A and the second charge storage film 144B that contacts the tunnel insulating film 142 and extends in the third direction Z may be greater than the length of the surface of the other charge storage film that contacts the tunnel insulating film 142 and extends in the third direction Z.

[0068] Since a plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may be alternately stacked with a plurality of insulating patterns 110, the first word line WL1 may be interposed between two insulating patterns 110. For example, the first word line WL1 may be interposed between a first insulating pattern 110A and a second insulating pattern 110B. The first insulating pattern 110A, the first word line WL1, and the second insulating pattern 110B may be sequentially stacked on the substrate 100.

[0069] According to an exemplary embodiment, the first charge storage film 144A and the second charge storage film 144B may be adjacent to the insulating pattern 110. For example, the first recess 10R may be adjacent to the first insulating pattern 110A, and the second recess 30R may be adjacent to the second insulating pattern 110B. Therefore, the first charge storage film 144A may be adjacent to the first insulating pattern 110A, and the second charge storage film 144B may be adjacent to the second insulating pattern 110B.

[0070] According to an exemplary embodiment, the first recess 10R may extend further into the first portion 10 than a side surface of the first insulation pattern 110A. Also, according to an exemplary embodiment, the second recess 30R may extend further into the third portion 30 than a side surface of the second insulation pattern 110B.

[0071] According to an exemplary embodiment, a blocking insulating film 146 may be interposed between the first charge storage film 144A and each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL), and between the second charge storage film 144B and each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL). For example, the blocking insulating film 146 may extend along the contours of the first recess 10R and the second recess 30R. The first charge storage film 144A may be disposed on the blocking insulating film 146 extending along the contour of the first recess 10R, and the second charge storage film 144B may be disposed on the blocking insulating film 146 extending along the contour of the second recess 30R.

[0072] According to an exemplary embodiment, the blocking insulating film 146 may continuously extend along side surfaces of the plurality of gate electrodes (GSL, WL1, WL2 ˜WLn, SSL) and side surfaces of the plurality of insulating patterns 110. For example, Figure 4 As shown, the blocking insulating film 146 may continuously extend along contours with respect to side surfaces of the first insulating pattern 110A, the first word line WL1 , and the second insulating pattern 110B.

[0073] According to an exemplary embodiment, the blocking insulating film 146 may extend continuously along the contours relative to the side surfaces of the first portion 10 (e.g., the first recess 10R), the side surfaces of the second portion 20, and the side surfaces of the third portion 30 (e.g., the second recess 30R). Furthermore, the first charge storage film 144A may be formed only on the blocking insulating film 146 extending along the contour of the first recess 10R, and the second charge storage film 144B may be formed only on the blocking insulating film 146 extending along the contour of the second recess 30R. Therefore, the first charge storage film 144A and the second charge storage film 144B may be electrically separated from each other in the third direction Z by the blocking insulating film 146.

[0074] According to an exemplary embodiment, the tunnel insulating film 142 may be interposed between the first charge storage film 144A and the semiconductor pattern 120 and between the second charge storage film 144B and the semiconductor pattern 120. For example, the tunnel insulating film 142 may extend along side surfaces of the first charge storage film 144A, side surfaces of the second charge storage film 144B, and side surfaces of the blocking insulating film 146. According to an exemplary embodiment, the tunnel insulating film 142 may extend along contours relative to the blocking insulating film 146 on the first insulating pattern 110A, the first charge storage film 144A, the blocking insulating film 146 on the second portion 20, the second charge storage film 144B, and the blocking insulating film 146 on the second insulating pattern 110B.

[0075] According to an exemplary embodiment, the side surface of the first portion 10 and / or the side surface of the third portion 30 may have a concave shape. For example, the first recess 10R and / or the second recess 30R may be formed to be concave in a direction away from the semiconductor pattern 120. For example, the first recess 10R facing the semiconductor pattern 120 may be recessed into (e.g., recessed into) the first portion 10, and the second recess 30R may be recessed into (e.g., recessed into) the third portion 30. In this specification, "and / or" includes each mentioned item and one or more combinations. For example, although Figure 4 The first recess 10R and the second recess 30R are both shown to have a concave shape, but the exemplary embodiment is not limited thereto. For example, in an exemplary embodiment, only one of the first recess 10R and the second recess 30R may be formed to have a concave shape.

[0076] According to an exemplary embodiment, a side surface of the first charge storage film 144A opposite to each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) and / or a side surface of the second charge storage film 144B opposite to each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may have a convex shape. For example, the blocking insulating film 146 may extend along the contour of the first recess 10R, and the first charge storage film 144A may be formed on the blocking insulating film 146 to fill the first recess 10R. Therefore, as Figure 4 As shown, the first charge storage film 144A may include a first surface 144S1 having a convex shape toward the first word line WL1. For example, the first surface 144S1 of the first charge storage film 144A may protrude into the first recess 10R.

[0077] According to exemplary embodiments, the side surface of the first charge storage film 144A opposite to the semiconductor pattern 120 and / or the side surface of the second charge storage film 144B opposite to the semiconductor pattern 120 may have a shape substantially parallel to the side surface of the semiconductor pattern 120. For example, the first charge storage film 144A may completely fill the trench formed by the blocking insulating film 146 within the first recess 10R. Figure 4 As shown, the first charge storage film 144A may include a second surface 144S2 substantially parallel to the side surface of the semiconductor pattern 120. For example, the second surface 144S2 of the first charge storage film 144A and the side surface of the semiconductor pattern 120 may both extend in the third direction Z.

[0078] Figure 5A and Figure 5B are views provided to describe exemplary operations of a nonvolatile memory device according to exemplary embodiments of the present disclosure.

[0079] As described above, the nonvolatile memory device according to the exemplary embodiment may include the first charge storage film 144A and the second charge storage film 144B separated from each other in each of the plurality of word lines (WL1, WL2 to WLn). The first charge storage film 144A and the second charge storage film 144B may store charges independently of each other.

[0080] For example, refer to Figure 5A , gate voltage V G Can be applied to the first word line WL1. Gate voltage V G It can be, for example, a positive voltage. S can be applied to the upper portion of the semiconductor pattern 120, with a first voltage V S Different second voltage V DCan be applied to the lower portion of the semiconductor pattern 120. For example, the first voltage V S It can be a ground voltage, the second voltage V D In this case, charges (electrons) provided from the upper portion of the semiconductor pattern 120 may be selectively trapped in the first charge storage film 144A.

[0081] In addition, for example, refer to Figure 5B , gate voltage V G Can be applied to the first word line WL1. Gate voltage V G It can be, for example, a positive voltage. S can be applied to the lower portion of the semiconductor pattern 120, with a first voltage V S Different second voltage V D Can be applied to the upper portion of the semiconductor pattern 120. For example, the first voltage V S It can be a ground voltage, the second voltage V D In this case, charges (electrons) provided from the lower portion of the semiconductor pattern 120 may be selectively trapped in the second charge storage film 144B.

[0082] Therefore, the nonvolatile memory device according to the exemplary embodiment can implement two data storage elements per word line. Therefore, a nonvolatile memory device with improved integration density can be provided.

[0083] 6A to 6D According to an exemplary embodiment of the present disclosure Figure 3 For the sake of convenience, the previously mentioned reference may be omitted or only briefly described. Figures 1 to 5B Further description of the described elements and aspects.

[0084] Reference Figure 6A In the nonvolatile memory device according to example embodiments, a side surface of the first charge storage film 144A opposite to the semiconductor pattern 120 and / or a side surface of the second charge storage film 144B opposite to the semiconductor pattern 120 may have a concave shape.

[0085] For example, the second surface 144S2 of the first charge storage film 144A may be concave relative to the semiconductor pattern 120. For example, the second surface 144S2 of the first charge storage film 144A facing the semiconductor pattern 120 may be concave in a direction away from the semiconductor pattern 120. According to an exemplary embodiment, the first charge storage film 144A does not completely fill the trench formed by the blocking insulating film 146 within the first recess 10R. For example, the second surface 144S2 of the first charge storage film 144A may extend further away from the semiconductor pattern 120 than the side surface of the blocking insulating film 146 opposite to the semiconductor pattern 120.

[0086] According to an exemplary embodiment, the tunnel insulating film 142 may extend along contours relative to the first charge storage film 144A, the second charge storage film 144B, and the blocking insulating film 146. In this case, a portion of the tunnel insulating film 142 may have a curved shape along the contours of the first charge storage film 144A and the second charge storage film 144B.

[0087] According to example embodiments, the semiconductor pattern 120 may extend along the outline of the tunnel insulating film 142. In this case, a portion of the semiconductor pattern 120 may have a curved shape along the outline of the tunnel insulating film 142.

[0088] Reference Figure 6B In the nonvolatile memory device according to example embodiments, the first recess 10R and / or the second recess 30R may expose a portion of the insulating pattern 110 .

[0089] For example, the first recess 10R may expose a portion of the upper surface of the first insulating pattern 110A. Since the blocking insulating film 146 may extend along the outline of the first word line WL1, the first charge storage film 144A may further include a third surface 144S3 opposite to the upper surface of the first insulating pattern 110A.

[0090] According to an exemplary embodiment, the first recess 10R may expose a portion of the bottom surface of the second portion 20. Since the blocking insulating film 146 may extend along the outline of the first word line WL1, the first charge storage film 144A may further include a fourth surface 144S4 opposite to the bottom surface of the second portion 20.

[0091] Similar to the first recess 10R, the second recess 30R may expose a portion of the bottom surface of the second insulating pattern 110B. According to an exemplary embodiment, the second recess 30R may expose a portion of the upper surface of the second portion 20 .

[0092] Reference Figure 6CIn the nonvolatile memory device according to example embodiments, the first charge storage film 144A and the second charge storage film 144B may have different widths from each other.

[0093] The “width” expressed here refers to the width in a direction intersecting the upper surface of the substrate 100. For example, in a third direction Z substantially perpendicular to the upper surface of the substrate 100, the first width W1 of the first charge storage film 144A may be different from the second width W2 of the second charge storage film 144B.

[0094] although Figure 6C Although the first width W1 of the first charge storage film 144A is shown to be greater than the second width W2 of the second charge storage film 144B, exemplary embodiments are not limited thereto. For example, in exemplary embodiments, the first width W1 of the first charge storage film 144A may be smaller than the second width W2 of the second charge storage film 144B.

[0095] According to an exemplary embodiment, the first width W1 of the first charge storage film 144A and the second width W2 of the second charge storage film 144B may be different depending on the position of each of the plurality of word lines (WL1, WL2 to WLn). For example, the first width W1 may be greater than the second width W2 for the first word line WL1 located at the bottom among the plurality of word lines (WL1, WL2 to WLn). Unlike the above, the first width W1 may be less than the second width W2 for the nth word line WLn located at the top among the plurality of word lines (WL1, WL2 to WLn).

[0096] Reference Figure 6D In the nonvolatile memory device according to example embodiments, the first charge storage film 144A and the second charge storage film 144B may have different depths from each other.

[0097] The “depth” expressed herein may refer to a depth in a direction intersecting the side surface of the semiconductor pattern 120. For example, in a first direction X substantially perpendicular to the side surface of the semiconductor pattern 120, a first depth D1 of the first charge storage film 144A may be different from a second depth D2 of the second charge storage film 144B.

[0098] although Figure 6D Although the first depth D1 of the first charge storage film 144A is shown to be greater than the second depth D2 of the second charge storage film 144B, exemplary embodiments are not limited thereto. For example, in exemplary embodiments, the first depth D1 of the first charge storage film 144A may be less than the second depth D2 of the second charge storage film 144B.

[0099] According to exemplary embodiments, the first depth D1 of the first charge storage film 144A and the second depth D2 of the second charge storage film 144B may be different depending on the position of each of the plurality of word lines (WL1, WL2 to WLn). For example, the first depth D1 may be greater than the second depth D2 for the first word line WL1 located at the bottom among the plurality of word lines (WL1, WL2 to WLn). Unlike the above, the first depth D1 may be less than the second depth D2 for the nth word line WLn located at the top among the plurality of word lines (WL1, WL2 to WLn).

[0100] Figure 7 is a cross-sectional view provided to describe a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Figure 8 According to an exemplary embodiment of the present disclosure Figure 7 For the sake of convenience, the previously mentioned references may be omitted or only briefly described. Figures 1 to 6D Further description of the described elements and aspects.

[0101] Reference Figure 7 and Figure 8 In the nonvolatile memory device according to example embodiments, the blocking insulating film 146 may extend along a surface of each of the plurality of gate electrodes (GSL, WL1, WL2 ˜WLn, SSL).

[0102] For example, Figure 8 As shown, the blocking insulating film 146 may further extend along the bottom and upper surfaces of the first word line WL1 (eg, in the first direction X). Therefore, portions of the blocking insulating film 146 may be interposed between the first insulating pattern 110A and the first word line WL1 and between the second insulating pattern 110B and the first word line WL1.

[0103] According to exemplary embodiments, the blocking insulating film 146 does not extend along the side surfaces of the first insulating pattern 110A and the side surfaces of the second insulating pattern 110B. Therefore, in these exemplary embodiments, the blocking insulating film 146 is not interposed between the first insulating pattern 110A and the tunnel insulating film 142 and between the second insulating pattern 110B and the tunnel insulating film 142.

[0104] According to an exemplary embodiment, the first charge storage film 144A and the second charge storage film 144B may be in contact with (e.g., in direct contact with) the insulating pattern 110. For example, the first charge storage film 144A may be in contact with (e.g., in direct contact with) the first insulating pattern 110A, and the second charge storage film 144B may be in contact with (e.g., in direct contact with) the second insulating pattern 110B.

[0105] Figure 9is a schematic layout diagram of a nonvolatile memory device provided to describe an exemplary embodiment of the present disclosure. Figures 1 to 6D Further description of the described elements and aspects.

[0106] Reference Figure 9 , in the nonvolatile memory device according to example embodiments, a plurality of channel structures (CS) may be arranged in a zigzag form.

[0107] A plurality of channel structures (CS) arranged in a zigzag form may further improve the integration density of the nonvolatile memory device.

[0108] In the following, reference will be made to Figures 2 to 6D 、 Figure 7 and Figure 8 as well as Figures 10 to 28 A method for manufacturing a nonvolatile memory device according to example embodiments is described.

[0109] Figures 10 to 23 is a view showing an intermediate stage of manufacturing and is provided to describe a method for manufacturing a nonvolatile memory device according to an exemplary embodiment. For ease of explanation, reference to the previously referenced Figures 1 to 6D Further description of the described elements and aspects.

[0110] Reference Figure 10 , a plurality of insulating patterns 110 and a plurality of sacrificial patterns 410 may be formed on the substrate 100 .

[0111] The plurality of sacrificial patterns 410 may be alternately stacked with the plurality of insulating patterns 110. For example, the plurality of sacrificial patterns 410 may be spaced apart from each other and sequentially stacked along the third direction Z. Here, each sacrificial pattern 410 may be interposed between two adjacent insulating patterns among the plurality of insulating patterns 110.

[0112] The plurality of sacrificial patterns 410 may include a material having an etch selectivity with respect to the plurality of insulating patterns 110. For example, when the plurality of insulating patterns 110 include silicon oxide, the plurality of sacrificial patterns 410 may include silicon nitride.

[0113] According to example embodiments, each sacrificial pattern 410 may include first to third sacrificial films 412, 414, 416 sequentially stacked on the substrate 100. For example, the second sacrificial film 414 may be interposed between the first sacrificial film 412 and the third sacrificial film 416.

[0114] According to an exemplary embodiment, the first sacrificial film 412 and the third sacrificial film 416 may include a material having an etching selectivity with respect to the second sacrificial film 414. For example, when the first to third sacrificial films 412, 414, 416 include silicon nitride (SiN), the nitrogen to silicon ratio (N / Si) of the first sacrificial film 412 and the third sacrificial film 416 may be different from the nitrogen to silicon ratio (N / Si) of the second sacrificial film 414. According to an exemplary embodiment, the nitrogen to silicon ratio (N / Si) of the first sacrificial film 412 and the third sacrificial film 416 may be less than the nitrogen to silicon ratio (N / Si) of the second sacrificial film 414.

[0115] The nitrogen to silicon ratio (N / Si) of the first sacrificial film 412 may be the same as the nitrogen to silicon ratio (N / Si) of the third sacrificial film 416 , or they may be different from each other.

[0116] Reference Figure 11 , a plurality of channel holes (CH) penetrating the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410 may be formed.

[0117] Channel holes (CH) may be formed to penetrate the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410 to expose a portion of the substrate 100 .

[0118] According to an exemplary embodiment, the channel hole (CH) may have a tapered shape. For example, as each channel hole (CH) gets closer to the substrate 100, the width of each channel hole (CH) may become narrower. The shape of the channel hole (CH) may be caused by the characteristics of the etching process used to form the channel hole (CH). However, exemplary embodiments are not limited thereto.

[0119] Reference Figure 12 and Figure 13 , a recess forming process may be performed with respect to the first sacrificial film 412 and the third sacrificial film 416. For reference, Figure 13 yes Figure 12 Magnified view of region R3.

[0120] The recess forming process may have an etching selectivity with respect to the first sacrificial film 412 and the third sacrificial film 416. For example, the recess forming process may selectively etch a portion of the first sacrificial film 412 exposed by the channel hole (CH) and a portion of the third sacrificial film 416 exposed by the channel hole (CH). In contrast, in an exemplary embodiment, during the recess forming process, the second sacrificial film 414 and the plurality of insulating patterns 110 are not etched to form a recess.

[0121] Therefore, the side surfaces of the first sacrificial film 412 and the third sacrificial film 416 may extend further into their respective films than the side surfaces of the second sacrificial film 414. For example, the first recess 10R may be formed in the first sacrificial film 412, and the second recess 30R may be formed in the third sacrificial film 416.

[0122] Although the widths of the first recess 10R and the second recess 30R are shown as being substantially the same, exemplary embodiments are not limited thereto. For example, in exemplary embodiments, the third width W11 of the first recess 10R and the fourth width W12 of the second recess 30R may be substantially the same, or they may be different. For example, when the thickness of the first sacrificial film 412 is greater than the thickness of the third sacrificial film 416, the third width W11 may be greater than the fourth width W12.

[0123] Furthermore, although the depths of the first recess 10R and the second recess 30R are shown as being substantially the same, exemplary embodiments are not limited thereto. For example, in exemplary embodiments, the third depth D11 of the first recess 10R and the fourth depth D12 of the second recess 30R may be substantially the same, or they may be different. For example, when the nitrogen to silicon ratio (N / Si) of the first sacrificial film 412 is less than the nitrogen to silicon ratio (N / Si) of the third sacrificial film 416, the third depth D11 may be greater than the fourth depth D12.

[0124] Reference Figure 14 and Figure 15 , a blocking insulating film 146 and a preliminary charge storage film 144 may be sequentially formed in each channel hole (CH). For reference, Figure 15 yes Figure 14 Magnified view of region R4.

[0125] First, a blocking insulating film 146 extending along the outline of the channel hole (CH) may be formed. The blocking insulating film 146 may extend along the side surfaces of the plurality of sacrificial patterns 410 and the side surfaces of the plurality of insulating patterns 110. For example, Figure 15 As shown, the blocking insulating film 146 may continuously extend along contours with respect to side surfaces of the first insulating pattern 110A, side surfaces of the sacrificial pattern 410 , and side surfaces of the second insulating pattern 110B.

[0126] Next, a preliminary charge storage film 144 may be formed on the blocking insulating film 146. The preliminary charge storage film 144 may extend along the outline of the blocking insulating film 146. According to example embodiments, the preliminary charge storage film 144 may be formed to fill the first and second recesses 10R and 30R.

[0127] Reference Figure 16 and Figure 17 , an etch-back process may be performed on the preliminary charge storage film 144. For reference, Figure 17 yes Figure 16 Magnified view of region R5.

[0128] According to exemplary embodiments, the etch-back process may be performed until the side surface of the blocking insulating film 146 is exposed. Thus, two charge storage films (eg, first and second charge storage films 144A and 144B) spaced apart from each other in each sacrificial pattern 410 may be formed.

[0129] Furthermore, two charge storage films (a first charge storage film 144A and a second charge storage film 144B) may be formed in a buried form in each sacrificial pattern 410. For example, Figure 17 As shown, the first charge storage film 144A may fill at least a portion of the first recess 10R, and the second charge storage film 144B may fill at least a portion of the second recess 30R.

[0130] Although the width of the first charge storage film 144A is shown to be substantially the same as the width of the second charge storage film 144B, exemplary embodiments are not limited thereto. For example, in exemplary embodiments, the first width W1 of the first charge storage film 144A may be substantially the same as the second width W2 of the second charge storage film 144B, or they may be different from each other. For example, when the thickness of the first sacrificial film 412 is greater than the thickness of the third sacrificial film 416, the first width W1 may be greater than the second width W2.

[0131] Furthermore, although the depths of the first charge storage film 144A and the second charge storage film 144B are shown as being substantially the same, exemplary embodiments are not limited thereto. For example, the first depth D1 of the first charge storage film 144A may be substantially the same as the second depth D2 of the second charge storage film 144B, or they may be different from each other. For example, when the nitrogen to silicon ratio (N / Si) of the first sacrificial film 412 is less than the nitrogen to silicon ratio (N / Si) of the third sacrificial film 416, the first depth D1 may be greater than the second depth D2.

[0132] Reference Figure 18 and Figure 19 , multiple channel structures (CS) can be formed. For reference, Figure 19 yes Figure 18 Magnified view of region R6.

[0133] For example, a tunnel insulating film 142 and a semiconductor pattern 120 may be sequentially formed within each channel hole (CH). The tunnel insulating film 142 may extend, for example, along the side surfaces of the first charge storage film 144A, the second charge storage film 144B, and the side surfaces of the blocking insulating film 146. For example, the semiconductor pattern 120 may be in contact with (e.g., in direct contact with) the substrate 100 due to its extension in the third direction Z. Thus, a plurality of channel structures (CS) passing through the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410 may be formed in contact with (e.g., in direct contact with) the substrate 100.

[0134] According to example embodiments, a filling insulating pattern 130 may be further formed on the semiconductor pattern 120. The filling insulating pattern 130 may be formed to fill the inside of the semiconductor pattern 120, which may be, for example, in a cup shape.

[0135] According to an exemplary embodiment, a channel pad 160 (see FIG. 1 ) in contact with (eg, in direct contact with) an upper portion of the semiconductor pattern 120 may be further formed. Figure 20 The channel pad 160 may be formed, for example, within the first interlayer insulating film 210 formed on the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410 .

[0136] Reference Figure 20 , a word line cutting region (WLC) may be formed within the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410 .

[0137] A word line cut region (WLC) may be formed to expose the substrate 100 by penetrating the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410. Thus, the word line cut region (WLC) may cut the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410.

[0138] According to example embodiments, the word line cut region (WLC) may be formed to extend in the second direction Y. According to example embodiments, the impurity region 105 may be formed in the substrate 100 in a region exposed by the word line cut region (WLC).

[0139] Reference Figure 21 , the plurality of sacrificial patterns 410 exposed by the word line cut region (WLC) may be removed.

[0140] The removal of the plurality of sacrificial patterns 410 may be performed, for example, by an anisotropic etching process. Thus, in an exemplary embodiment, a portion of a side surface of the blocking insulating film 146 may be exposed.

[0141] Reference Figure 22 , a plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) can be formed.

[0142] A plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) may be formed in the region where the plurality of sacrificial patterns 410 are removed. For example, the plurality of sacrificial patterns 410 may be replaced with a plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL). Furthermore, a mold structure (MS) including the plurality of gate electrodes (GSL, WL1, WL2-WLn, SSL) and the plurality of insulating patterns 110 may be formed on the substrate 100.

[0143] Reference Figure 23 , an isolation structure 150 may be formed in the word line cut region (WLC).

[0144] For example, the spacer 154 may be formed to extend along the outline of the word line cut region (WLC). Next, a plug pattern 152 filling the word line cut region (WLC) may be formed on the spacer 154. The plug pattern 152 may be formed to penetrate the mold structure (MS) and thereby contact (e.g., directly contact) the impurity region 105.

[0145] Next, refer to Figure 3 , a plurality of bit lines (BL) may be formed on the mold structure (MS).

[0146] A plurality of bit lines (BL) may be formed to be electrically connected to the plurality of channel structures (CS). For example, a second interlayer insulating film 310 may be formed on the mold structure (MS). Next, a bit line contact 170 may be formed that penetrates the second interlayer insulating film 310 and electrically connects the channel structure (CS) and the bit line (BL).

[0147] Therefore, a method for manufacturing a nonvolatile memory device with improved integration density can be provided, the method including forming two charge storage films per word line.

[0148] Figures 24 to 28 is a view showing an intermediate stage of manufacturing and is provided to describe a method for manufacturing a nonvolatile memory device according to an exemplary embodiment of the present disclosure. For ease of description, the previously referenced Figures 1 to 23 For further description of the elements and aspects described. Figure 24 is provided to describe the Figure 12 The following process diagram.

[0149] Reference Figure 24 , the first charge storage film 144A may be formed in the first recess 10R, and the second charge storage film 144B may be formed in the second recess 30R.

[0150] According to an exemplary embodiment, the first charge storage film 144A and the second charge storage film 144B may be formed to contact (eg, directly contact) each sacrificial pattern 410. For ease of explanation, since the formation of the first charge storage film 144A and the second charge storage film 144B is similar to that described above with reference to Figures 14 to 17 The formation process described is described, so further description thereof will not be repeated here.

[0151] Reference Figure 25 , a tunnel insulating film 142 and a semiconductor pattern 120 may be formed within each channel hole (CH).

[0152] According to an exemplary embodiment, a filling insulating pattern 130 may be further formed on the semiconductor pattern 120. According to an exemplary embodiment, a channel pad 160 in contact with (eg, in direct contact with) an upper portion of the semiconductor pattern 120 may be further formed.

[0153] For the convenience of explanation, since the formation of the tunnel insulating film 142, the semiconductor pattern 120, the filling insulating pattern 130 and the channel pad 160 is similar to that of the above reference Figure 18 and Figure 19 The formation process described is described, so further description thereof will not be repeated here.

[0154] Reference Figure 26 , a word line cutting region (WLC) may be formed within the plurality of insulating patterns 110 and the plurality of sacrificial patterns 410 .

[0155] For ease of explanation, since the formation of the word line cutting region (WLC) is similar to the above reference Figure 20 The formation process described is described, so further description thereof will not be repeated here.

[0156] Reference Figure 27 , the plurality of sacrificial patterns 410 exposed through the word line cut region (WLC) may be removed.

[0157] Therefore, the first charge storage film 144A and the second charge storage film 144B may be exposed. For ease of explanation, since the removal of the plurality of sacrificial patterns 410 is similar to that described above with reference to FIG. Figure 21 The removal process described in the previous section is omitted, so further description thereof will not be repeated here.

[0158] Reference Figure 28 , a blocking insulating film 146 and a plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) can be formed.

[0159] The blocking insulating film 146 may be formed in the region where the plurality of sacrificial patterns 410 are removed. For example, the blocking insulating film 146 may extend along contours with respect to the plurality of insulating patterns 110, the first charge storage film 144A, and the second charge storage film 144B.

[0160] Next, a plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may be formed on the blocking insulating film 146. The plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL) may be formed to fill the region where the plurality of sacrificial patterns 410 are removed. Therefore, the blocking insulating film 146 may also be interposed between the insulating pattern 110 and each of the plurality of gate electrodes (GSL, WL1, WL2 to WLn, SSL).

[0161] Next, refer to Figure 7 and Figure 8 , an isolation structure 150 may be formed in the word line cutting region (WLC). In addition, a plurality of bit lines (BL) may be formed on the mold structure (MS).

[0162] For ease of explanation, since the formation of the isolation structure 150 and the plurality of bit lines (BL) is similar to that of the above reference Figure 23 and Figure 3 The formation process described is described, so further description thereof will not be repeated here.

[0163] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined in the appended claims.

[0164] This application claims priority from Korean Patent Application No. 10-2019-0067910, filed on Jun. 10, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A nonvolatile memory device comprising: a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate; a semiconductor pattern penetrating the mold structure and contacting the substrate; a first charge storage film; as well as a second charge storage film separated from the first charge storage film, wherein the first charge storage film and the second charge storage film are provided between each of the gate electrodes and the semiconductor pattern, Each of the gate electrodes includes a first recess and a second recess respectively recessed inward from a side surface of the gate electrode, and The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

2. The nonvolatile memory device according to claim 1 , wherein the semiconductor pattern extends in a direction intersecting with the upper surface of the substrate, and The first charge storage film and the second charge storage film are spaced apart from each other in the direction.

3. The nonvolatile memory device according to claim 1 , wherein the first charge storage film includes a first surface opposite to a corresponding gate electrode among the plurality of gate electrodes, and The first surface has a convex shape toward the corresponding gate electrode.

4. The nonvolatile memory device according to claim 3 , wherein the first charge storage film further comprises a second surface opposite to the semiconductor pattern, and The second surface is parallel to a side surface of the semiconductor pattern.

5. The nonvolatile memory device according to claim 3 , wherein the first charge storage film further comprises a second surface opposite to the semiconductor pattern, and The second surface has a shape that is concave in a direction away from a side surface of the semiconductor pattern.

6. The nonvolatile memory device according to claim 1 , further comprising: A blocking insulating film extends along the contours of the first recess and the second recess between the first charge storage film and the second charge storage film and each of the gate electrodes.

7. The nonvolatile memory device according to claim 6, wherein the first charge storage film and the second charge storage film include silicon nitride, and the blocking insulating film includes silicon oxide or a high-k dielectric material having a larger dielectric constant than silicon oxide.

8. The nonvolatile memory device according to claim 1 , further comprising: A tunnel insulating film extends along a side surface of the semiconductor pattern between the first and second charge storage films and the semiconductor pattern. 9 . The nonvolatile memory device according to claim 8 , wherein the first charge storage film and the second charge storage film include silicon nitride, and the tunnel insulating film includes silicon oxide or a high-k dielectric material having a larger dielectric constant than silicon oxide. 10 . The nonvolatile memory device of claim 1 , wherein a width of the first charge storage film and a width of the second charge storage film are different from each other in a direction intersecting an upper surface of the substrate. 11 . The nonvolatile memory device of claim 1 , wherein a depth of the first charge storage film and a depth of the second charge storage film are different from each other in a direction intersecting a side surface of the semiconductor pattern. 12 . The nonvolatile memory device according to claim 1 , wherein the first charge storage film and the second charge storage film store charges separately and independently.

13. A nonvolatile memory device comprising: A mold structure comprising a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, wherein each of the gate electrodes comprises a first portion, a second portion, and a third portion sequentially stacked; a semiconductor pattern penetrating the mold structure and contacting the substrate; a first charge storage film disposed between the first portion and the semiconductor pattern; as well as a second charge storage film disposed between the third portion and the semiconductor pattern, The side surface of the first portion extends further into the first portion than the side surface of the second portion, and the side surface of the third portion extends further into the third portion than the side surface of the second portion. 14 . The nonvolatile memory device of claim 13 , wherein the side surface of the first portion and the side surface of the third portion are opposite to the semiconductor pattern and each have a concave shape.

15. The nonvolatile memory device according to claim 13, further comprising: A blocking insulating film extends along the contour of the side surfaces of the first portion to the third portion between the first charge storage film and the second charge storage film and each of the gate electrodes. 16 . The nonvolatile memory device of claim 15 , wherein the blocking insulating film further extends along a side surface of each of the insulating patterns. 17 . The nonvolatile memory device according to claim 15 , wherein the blocking insulating film further extends along a bottom surface of the first portion and an upper surface of the third portion.

18. A nonvolatile memory device comprising: a mold structure comprising a first insulating pattern, a gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure and contacting the substrate; a first charge storage film; as well as a second charge storage film separated from the first charge storage film, wherein the first charge storage film and the second charge storage film are disposed between the gate electrode and the semiconductor pattern, wherein the gate electrode includes a first recess and a second recess, the first recess extending further into the gate electrode than a side surface of the first insulating pattern, and the second recess extending further into the gate electrode than a side surface of the second insulating pattern, and The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

19. The nonvolatile memory device according to claim 18, further comprising: A blocking insulating film extends between the first and second charge storage films and the gate electrode along contours relative to the side surfaces of the first insulating pattern, the gate electrode, and the second insulating pattern. 20 . The nonvolatile memory device of claim 18 , wherein the first recess exposes a portion of an upper surface of the first insulating pattern, and the second recess exposes a portion of a bottom surface of the second insulating pattern.

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