Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a fin-type pattern located on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction; a first wiring pattern located on the fin-type pattern, the first wiring pattern being spaced apart from the fin-type pattern in the third direction; and a gate electrode extending in a second direction perpendicular to the first direction and the third direction and surrounding the first wiring pattern, the gate electrode including a first portion superposed with the fin-type pattern in the second direction and a second portion corresponding to a remaining portion of the gate electrode other than the first portion.

Description

[0001] Korean Patent Application No. 10-2019-0068541, entitled "Semiconductor device", filed with the Korean Intellectual Property Office on June 11, 2019, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiment relates to a semiconductor device. Background Technology

[0003] With the rapid popularization of information media, the functionality of semiconductor devices has been significantly developed. Recent semiconductor products demand low production costs to enhance competitiveness and high integration density to provide high quality. To increase the integration density of semiconductor products, semiconductor devices can be scaled down. Summary of the Invention

[0004] The embodiment relates to a semiconductor device comprising: a fin pattern located on a substrate, the fin pattern extending in a first direction and projecting from the substrate in a third direction; a first wiring pattern located on the fin pattern and spaced apart from the fin pattern in a third direction; and a gate electrode extending in a second direction perpendicular to the first and third directions and surrounding the first wiring pattern, the gate electrode comprising a first portion superimposed on the fin pattern in the second direction and a second portion corresponding to the remainder of the gate electrode other than the first portion.

[0005] An embodiment may also provide a semiconductor device comprising: a fin pattern projecting from a substrate along a third direction; and a first wiring pattern located on the fin pattern, the first wiring pattern being spaced apart from the fin pattern in the third direction. The distance between the top surface of the fin pattern and an end of the first wiring pattern in a second direction may be equal to or greater than the distance between the top surface of the fin pattern and a portion of the first wiring pattern excluding the end, the second direction being perpendicular to the third direction and intersecting the direction along which the fin pattern extends.

[0006] The embodiment may also provide a semiconductor device comprising: a fin pattern protruding from a substrate, the fin pattern having a top surface excluding a portion protruding in the direction along which the fin pattern protrudes from the substrate; a wiring pattern spaced apart from the fin pattern; and a gate electrode surrounding the wiring pattern. Attached Figure Description

[0007] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1a perspective view of a semiconductor device according to an example embodiment is shown;

[0009] Figure 2 a plan view of a semiconductor device is shown Figure 1

[0010] Figure 3 a cross-sectional view taken along line B-B' of Figure 2

[0011] Figure 4 a magnified cross-sectional view of region P of Figure 3

[0012] Figure 5 a cross-sectional view taken along line A-A' of Figure 2

[0013] Figure 6 a cross-sectional view taken along line B-B' of a semiconductor device according to an example embodiment is shown Figure 2

[0014] Figure 7 a magnified cross-sectional view of region Q of Figure 6

[0015] Figure 8 a cross-sectional view taken along line B-B' of a semiconductor device according to an example embodiment is shown Figure 2

[0016] Figure 9 a magnified cross-sectional view of region SO of Figure 8

[0017] Figure 10 a cross-sectional view taken along line B-B' of a semiconductor device according to an example embodiment is shown Figure 2

[0018] Figure 11 a magnified cross-sectional view of region SI of Figure 10

[0019] Figure 12 a cross-sectional view taken along line B-B' of a semiconductor device according to an example embodiment is shown Figure 2

[0020] Figure 13 a magnified cross-sectional view of region S2 of Figure 12

[0021] Figure 14 a cross-sectional view taken along line B-B' of a semiconductor device according to an example embodiment is shown Figure 2 ​​​​​​​​​​​​​

[0022] Figure 15 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ;

[0023] Figure 16 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ;

[0024] Figure 17 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 16 ;

[0025] Figure 18 and Figure 19 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' and A-A' of Figure 2 , respectively;

[0026] Figure 20 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ;

[0027] Figure 21 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ;

[0028] Figure 22 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ;

[0029] Figure 23 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ;

[0030] Figure 24 a sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 ; and

[0031] Figures 25 to 39 a schematic diagram illustrating stages in a method of manufacturing a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0032] The semiconductor device according to the example embodiment is shown in the drawings as, for example, a multi-bridge channel field-effect transistor (MBCFET) including nanowire or nanosheet channel regions. However, examples of the semiconductor device according to the example embodiment may include tunnel field-effect transistors (FETs), fin FETs (FinFETs), gate-surround FETs (GAAFETs), and three-dimensional (3D) transistors, and may also include bipolar junction transistors, laterally diffused metal-oxide-semiconductor (LDMOS) transistors, etc.

[0033] The following will refer to Figures 1 to 5 A semiconductor device according to an example embodiment is described. For convenience, in Figures 1 to 5 Separating membranes such as shallow trench isolation (STI) are not shown.

[0034] Figure 1 A perspective view of a semiconductor device according to an example embodiment is shown. Figure 2 It shows Figure 1 A plan view of a semiconductor device. Figure 3 It shows along Figure 2 The sectional view taken by line B-B'. Figure 4 It shows Figure 3 An enlarged sectional view of region P. Figure 5 It shows along Figure 2 A sectional view taken by line A-A'.

[0035] Reference Figures 1 to 5 The semiconductor device includes a substrate 100, a field insulating film 105, a first wiring pattern 110, an interface film 120, a gate insulating film 130, a gate electrode 140, a gate spacer 150, a source / drain region 160, and an interlayer insulating film 190.

[0036] The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In embodiments, the substrate 100 may be a silicon (Si) substrate or may include another material, such as silicon germanide (SiGe), SiGe on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0037] In an embodiment, substrate 100 may be an epitaxial layer formed on a substrate. For convenience, substrate 100 will be described below as a substrate comprising Si.

[0038] The substrate 100 may include fin-shaped protrusions 100P. The fin-shaped protrusions 100P may also be referred to as a "fin pattern". The fin-shaped protrusions 100P may protrude from the top surface of the substrate 100 and may extend in a first direction X. The fin-shaped protrusions 100P may be formed by etching a portion of the substrate 100, or the fin-shaped protrusions 100P may be an epitaxial layer grown from the substrate 100.

[0039] The fin-shaped protrusion 100P can include a semiconductor elemental material, such as exemplified by Si or germanium (Ge). Further, the fin-shaped protrusion 100P can include a compound semiconductor. For example, the fin-shaped protrusion 100P can include a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group III-V compound semiconductor can be a binary, ternary, or quaternary compound obtained by combining at least one group III element such as aluminum (Al), gallium (Ga), and indium (In) and at least one group V element such as phosphorus (P), arsenic (As), and antimony (Sb).

[0040] A field insulating film 105 can be formed on the substrate 100. The field insulating film 105 can surround at least a portion of the sidewall of the fin-shaped protrusion 100P. The fin-shaped protrusion 100P can be partially defined by the field insulating film 105.

[0041] The field insulating film 105 can include, for example, at least one of an oxide film, a nitride film, an oxynitride film, and a combination thereof.

[0042] A first wiring pattern 110 can be provided on the substrate 100. The first wiring pattern 110 can be spaced apart from the substrate 100. The first wiring pattern 110, like the fin-shaped protrusion 100P, can extend in the first direction X.

[0043] The first wiring pattern 110 can be formed over the fin-shaped protrusion 100P to be spaced apart from the fin-shaped protrusion 100P. The first wiring pattern 110 can be vertically superposed with the fin-shaped protrusion 100P. In an embodiment, the first wiring pattern 110 can be formed on the fin-shaped protrusion 100P without being formed on the field insulating film 105.

[0044] The first wiring pattern 110 can include a semiconductor elemental material, such as exemplified by Si or Ge. Further, the first wiring pattern 110 can include a compound semiconductor. For example, the first wiring pattern 110 can include a group IV-IV compound semiconductor or a group III-V compound semiconductor. The first wiring pattern 110 can include the same material as or a different material from the fin-shaped protrusion 100P.

[0045] The first wiring pattern 110 can function as a channel region of a transistor. For example, the first wiring pattern 110 can function as a channel region of an N-type metal oxide semiconductor (NMOS) transistor. In another example, the first wiring pattern 110 can function as a channel region of a P-type metal oxide semiconductor (PMOS) transistor.

[0046] An interface film 120 can be formed along a periphery (or a perimeter) of the first wiring pattern 110. The interface film 120 can surround (e.g., completely surround) the first wiring pattern 110.

[0047] An interface film 120 can be formed on the fin-type protrusion 100P. As Figure 5 The interface film 120 can be formed on the bottom of the trench TR1, as shown in FIG. 12B. The interface film 120 is shown as not being formed on the sidewall of the trench TR1, but in an embodiment, the interface film 120 can be formed on the sidewall of the trench TR1 depending on the way the interface film 120 is formed. In an example embodiment, the interface film 120 can not be provided.

[0048] The interface film 120 can include, for example, silicon oxide, or the like. Depending on the type of the substrate 100, the type of the first wiring pattern 110, or the type of the gate insulating film 130, the interface film 120 can include a material other than silicon oxide.

[0049] The gate insulating film 130 can be formed on the interface film 120. The gate insulating film 130 can be formed along the periphery of the first wiring pattern 110. The gate insulating film 130 can surround (e.g., completely surround) the interface film 120.

[0050] The gate insulating film 130 can be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The gate insulating film 130 can extend along the inner sidewall of the gate spacer 150. Thus, the gate insulating film 130 can extend along the sidewall and the bottom of the trench TR1 and along the periphery of the first wiring pattern 110.

[0051] The gate insulating film 130 can include, for example, a high-dielectric-constant material having a larger dielectric constant than silicon oxide, silicon nitride, and silicon oxynitride.

[0052] The gate electrode 140 can extend over the substrate 100 in a second direction Y that crosses the first direction X. As Figure 2 The gate electrode 140 can cross the fin-type protrusion 100P and the first wiring pattern 110, as shown in FIG. 12B.

[0053] The gate electrode 140 can be formed to surround (e.g., completely surround) the first wiring pattern 110, and can exist between the fin-type protrusion 100P and the first wiring pattern 110.

[0054] The gate electrode 140 can be formed on the gate insulating film 130. The gate electrode 140 can fill the trench TR1.

[0055] The gate electrode 140 can include a lower conductive film 142, a work function film 144, a barrier film 146, and a filled conductive film 148.

[0056] The lower conductive film 142 can be formed on the gate insulating film 130. The lower conductive film 142 can be formed along the profile of the gate insulating film 130.

[0057] The lower conductive film 142 can be formed along the periphery of the first wiring pattern 110. The lower conductive film 142 can surround (e.g., completely surround) the gate insulating film 130.

[0058] The lower conductive film 142 can also be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The lower conductive film 142 can extend along the inner side wall of the gate spacer 150. Thus, the lower conductive film 142 can extend along the side wall and the bottom of the trench TR1 and along the periphery of the first wiring pattern 110.

[0059] The lower conductive film 142 can include, for example, a metal nitride. For example, the lower conductive film 142 can include at least one of TiN, TaN, WN, and a combination thereof. The lower conductive film 142 can be formed to an appropriate thickness according to the type of semiconductor device to be formed.

[0060] The lower conductive film 142 will be described below as including TiN.

[0061] In a process of manufacturing a semiconductor device, the lower conductive film 142 can be used to repair oxygen atom defects in the gate insulating film 130. For example, the lower conductive film 142 can repair oxygen atom defects in the gate insulating film 130 by heat treatment.

[0062] The work function film 144 can be formed on the lower conductive film 142. The work function film 144 can be formed along the profile of the lower conductive film 142.

[0063] The work function film 144 can be formed along the periphery of the first wiring pattern 110. Thus, the work function film 144 can surround the lower conductive film 142.

[0064] The work function film 144 can also be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The work function film 144 can extend along the inner side wall of the gate spacer 150. Thus, the work function film 144 can extend along the side wall and the bottom of the trench TR1 and along the periphery of the first wiring pattern 110.

[0065] The work function film 144 can include carbon (C). The work function film 144 can also include, for example, at least one of Ti, Ta, W, Ru, Nb, Mo, Hf, La, Al, and a combination thereof.

[0066] In an example embodiment, the work function film 144 can be an N-type work function film. For example, the work function film 144 can include TiAlC or TiAlCN. Further, for example, the work function film 144 can include a material obtained by replacing Ti in TiAlC or TiAlCN with one of Ta, W, Ru, Nb, Mo, Hf, and La.

[0067] The work function film 144 will be described below as including TiAlC.

[0068] A barrier film 146 can be formed on the work function film 144. The barrier film 146 can be formed along the profile of the work function film 144.

[0069] The barrier film 146 can also be formed on the top surface of the field insulating film 105 and on the fin-shaped protrusion 100P. The barrier film 146 can extend along the inner side wall of the gate spacer 150. Thus, the barrier film 146 can extend along the side wall and the bottom of the trench TR1.

[0070] Although not specifically shown, an oxide film can be interposed between the barrier film 146 and the work function film 144. The oxide film can be a film resulting from natural oxidation of the surface of the work function film 144. For example, the oxide film can be formed due to oxidation of the work function film 144 in a process of manufacturing a semiconductor device.

[0071] In an example embodiment, the barrier film 146 can be in direct contact with the work function film 144. Thus, no intermediate film can be interposed between the barrier film 146 and the work function film 144.

[0072] A filled conductive film 148 can be provided on the barrier film 146. The filled conductive film 148 can fill the portion of the trench TR1 that remains unfilled after the interface film 120, the gate insulating film 130, the lower conductive film 142, the work function film 144, and the barrier film 146 are formed.

[0073] The filled conductive film 148 can include, for example, at least one of W, Al, Co, Cu, Ru, Ni, Pt, Ni-Pt, and combinations thereof.

[0074] A gate spacer 150 can be formed on two or opposite side walls of the gate electrode 140, the side walls extending in the second direction Y. For example, as shown in FIG. 1B, the gate spacer 150 can be formed on both sides of the gate electrode 140 to face each other. The gate spacer 150 can define the trench TR1 that intersects the first wiring pattern 110. Figure 5

[0075] The gate spacer 150 can include an outer spacer 152 and an inner spacer 154. The inner spacer 154 can be provided between the fin-shaped protrusion 100P and the first wiring pattern 110. Although not specifically shown, the inner spacer 154 can have a width in the second direction Y that is substantially the same as the width of the first wiring pattern 110 in the second direction Y.

[0076] The outer spacer 152 can be provided on the inner spacer 154. Figure 5 ​The inner spacers 154 and the outer spacers 152 are sequentially provided on the first wiring pattern 110 or the like. Therefore, depending on the structure of the stack for forming the first wiring pattern 110, only the outer spacers 152 can be provided on the first wiring pattern 110.

[0077] As shown in Figure 3 and Figure 4 The gate electrode 140 can include a first portion 140_P0 that overlaps the fin-type protrusion 100P in the second direction Y and a second portion 140_P1 that occupies or corresponds to the rest of the gate electrode 140.

[0078] The first portion 140_P0 of the gate electrode 140 (which is provided below the top surface of the fin-type protrusion 100P in the third direction Z) includes a first lower conductive film 142_P0 and a first work function film 144_P0.

[0079] The second portion 140_P1 of the gate electrode 140 (which is provided above the top surface of the fin-type protrusion 100P in the third direction Z) includes a second lower conductive film 142_P1 and a second work function film 144_P1.

[0080] In an example embodiment, the distance between the bottom surface of the first portion 140_P0 of the gate electrode 140 and the top surface of the fin-type protrusion 100P in the third direction Z can be 50 nm or less.

[0081] Since the bottom of the gate electrode 140 (which does not overlap the fin-type protrusion 100P) is formed below the top surface of the fin-type protrusion 100P in the third direction Z (which is the direction in which the fin-type protrusion 100P protrudes), a protruding portion can not be formed at the edge of the top surface of the fin-type protrusion 100P. Therefore, the channel roughness can be reduced, and as a result, the mobility of the charge can be improved.

[0082] The source / drain region 160 can be formed adjacent to the gate electrode 140. For example, as shown in Figure 5 , the source / drain region 160 can be formed on both or opposite sidewalls of the gate electrode 140.

[0083] The source / drain region 160 can include an epitaxial layer formed on the fin-type protrusion 100P. The source / drain region 160 can be a raised source / drain region whose top surface is above the top surface of the substrate 100. In another embodiment, the source / drain region 160 can be an impurity region formed in the substrate 100.

[0084] The interlayer insulating film 190 can be formed on the substrate 100. The interlayer insulating film 190 can surround the outer sidewall of the gate spacer 150 that defines the trench TR1.

[0085] The interlayer insulating film 190 can include at least one of a low dielectric constant material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0086] Figure 6 A cross-sectional view of the semiconductor device according to an example embodiment taken along a line B-B' of Figure 2 , Figure 7 An enlarged cross-sectional view of a region Q of Figure 6 is shown.

[0087] Referring to Figure 4 , Figure 6 and Figure 7 , the gate electrode 140 can include a first portion 140_P0 that is superposed on the fin-type protrusion 100P in the second direction Y and a second portion 140_P1 that occupies or corresponds to the rest of the gate electrode 140. The distance between the sidewall of the fin-type protrusion 100P and the gate electrode 140 can increase away from (i.e., in the third direction Z) the top surface of the fin-type protrusion 100P. For example, the distance in the second direction Y between the sidewall of the fin-type protrusion 100P and the first portion 140_P0 of the gate electrode 140 can increase away from the top surface of the fin-type protrusion 100P.

[0088] In an example embodiment, the field insulating film 105 can be formed to at least partially surround two sidewalls or opposite sidewalls of the fin-type protrusion 100P and can define the fin-type protrusion 100P. The field insulating film 105 can include a first region 105_R0 that is superposed on the first portion 140_P0 of the gate electrode 140 in the second direction Y and a second region 105_R1 that occupies or corresponds to the rest of the field insulating film 105. Thus, the first region 105_R0 can be defined as a region that is superposed on the gate electrode 140 and the gate insulating film 130 in the second direction Y.

[0089] In more detail, as shown in Figure 6 and Figure 7 , the field insulating film 105 can include a first region 105_R0 formed above the bottom surface of the gate insulating film 130 and a second region 105_R1 formed below the bottom surface of the gate insulating film 130. Thus, the field insulating film 105 can be formed to not surround the entire sidewall of the fin-type protrusion 100P but only a portion of the sidewall of the fin-type protrusion 100P. As shown in Figure 7 , the first region 105_R0 formed above the bottom surface of the gate insulating film 130 can have a wedge-shaped portion interposed between the sidewall of the fin-type protrusion 100P and a portion of the gate insulating film 130 laterally adjacent to the first region 105_R0.

[0090] Figure 8 A cross-sectional view of the semiconductor device according to an example embodiment taken along a line B-B' ofFigure 2 a cross-sectional view taken along line B-B' of Figure 9 shows Figure 8 an enlarged cross-sectional view of a region SO of Figure 3 will be mainly focused on differences from Figure 8 and Figure 9 semiconductor devices.

[0091] Referring to Figure 8 and Figure 9 , the semiconductor device can further include a field pad 103_0. The field pad 103_0 can be formed between the field insulating film 105 and the base 100, between the field insulating film 105 and the fin-type protrusion 100P, between the gate insulating film 130 and the fin-type protrusion 100P, and between the gate insulating film 130 and the interface film 120. For example, the field pad 103_0 can be formed along a sidewall of the fin-type protrusion 100P (which is surrounded by the field insulating film 105 and the gate insulating film 130), along a sidewall of the interface film 120 (which is surrounded by the gate insulating film 130), and along a top surface of the base 100. The field pad 103_0 can be formed to protrude beyond a top surface of the field insulating film 105.

[0092] In another example embodiment, the field pad 103_0 can not be formed on the sidewall of the interface film 120, compared to those shown in Figure 8 and Figure 9 . In this case, the field pad 103_0 can be formed to be substantially the same height as a top portion of the fin-type protrusion 100P.

[0093] In an example embodiment, the field pad 103_0 can include at least one of polysilicon, amorphous silicon, silicon oxynitride, silicon nitride, and silicon oxide. In an example embodiment, the field pad 103_0 can be formed to include a double layer of one of polysilicon and amorphous silicon and silicon oxide.

[0094] Figure 10 shows a cross-sectional view taken along line B-B' of Figure 2 a semiconductor device according to an example embodiment, Figure 11 shows an enlarged cross-sectional view of a region S1 of Figure 10 will be mainly focused on differences from Figure 6 and Figure 10 semiconductor devices. Figure 11

[0095] Referring to Figure 10 and Figure 11 ​The semiconductor device can further include a field liner 103_1. The field liner 103_1 can be formed under the lower conductive film 142A and the work function film 144_1 along the sidewall of the fin-type protrusion 100P surrounded by the field insulating film 105, along the sidewall of the interface film 120, and along the top surface of the base 100. The field liner 103_1 can be in contact with at least a portion of the gate insulating film 130A. In an example embodiment, the field liner 103_1 can be formed so as not to protrude beyond the top surface of the field insulating film 105. Thus, the top surface of the field liner 103_1 and the top surface of the field insulating film 105 can have substantially the same height.

[0096] In an example embodiment, the distance between the field liner 103_1 and the gate insulating film 130A in the second direction Y can increase away from the top of the fin-type protrusion 100P (i.e., in the downward Z direction).

[0097] Figure 12 A cross-sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 is shown, Figure 13 An enlarged cross-sectional view of the region S2 of Figure 12 is shown. Hereinafter, the semiconductor device of Figure 10 will be mainly described focusing on the difference from the semiconductor device of Figure 12 and Figure 13 .

[0098] Referring to Figure 12 and Figure 13 , the semiconductor device can further include a field liner 103_2. The field liner 103_2 can be formed along the top surface of the base 100 and along a portion of the sidewall of the fin-type protrusion 100P. The sidewall of the fin-type protrusion 100P can include a portion in contact with the field liner 103_2 and a portion in contact with the gate insulating film 130B. The sidewall of the interface film 120 can be formed so as not to be in contact with the field liner 103_2 but in contact with the gate insulating film 130B.

[0099] Since the field liner 103_2 is formed in contact with the portion of the sidewall of the fin-type protrusion 100P, the bottom surface of the gate insulating film 130B, the lower conductive film 142B, and the work function film 144_1 can be formed to have an inflection point.

[0100] Figure 14 A cross-sectional view of the semiconductor device according to an example embodiment taken along the line B-B' of Figure 2 is shown. Hereinafter, the semiconductor device of Figure 12 will be mainly described focusing on the difference from the semiconductor device of Figure 14 .

[0101] Referring to Figure 14The semiconductor device can include an interface film 120A formed on a top surface of the fin-type protrusion 100P and having a smooth edge at a sidewall and the top surface thereof.

[0102] Figure 15 A cross-sectional view of the semiconductor device according to the example embodiment taken along a line B-B' of Figure 2 is shown.

[0103] Referring to Figure 15 , a bottom surface of the gate electrode 140 can be formed to be recessed in the third direction Z, i.e., downwardly recessed in Figure 15 , for example, to form a concave surface. In the example embodiment, bottom surfaces of the gate insulating film 130_2, the lower conductive film 142_2, and the work function film 144_2, which are formed on the fin-type protrusion 100P, can be formed to be recessed in the third direction Z. For example, the fin-type protrusion 100P can be formed to protrude from the base 100 in the third direction Z.

[0104] Figure 16 A cross-sectional view of the semiconductor device according to the example embodiment taken along a line B-B' of Figure 2 is shown, Figure 17 an enlarged cross-sectional view of a region R of Figure 16 is shown.

[0105] Referring to Figure 16 and Figure 17 , the first wiring pattern 110' can be formed in a shape of a figure including a combination of straight lines and curves, for example, a stadium shape. A cross section of the first wiring pattern 110' can have a rectangular shape with rounded corners, for example. In an embodiment, the first wiring pattern 110' can be formed in a shape of a figure including a combination of curves.

[0106] As shown in Figure 17 , a first distance H1 between either end of the first wiring pattern 110' and the fin-type protrusion 100P can be greater than or equal to a second distance H2 and a third distance H3 between other portions of the first wiring pattern 110' and the fin-type protrusion 100P. For example, a cross section of the first wiring pattern 110' can have a rectangular shape with rounded corners, the second distance H2 can be a distance from a center of the first wiring pattern 110' in the second direction Y to a top surface of the fin-type protrusion 100P, and the third distance H3 can be a distance from any arbitrary point between the center and an end of the first wiring pattern 110' in the second direction Y to the top surface of the fin-type protrusion 100P.

[0107] When a height at either end of the first wiring pattern 110' is greater than a height at other portions of the first wiring pattern 110', channel roughness of a transistor can be improved, as a result, mobility of charges can be improved.

[0108] Figure 18 and Figure 19 Cross-sectional views of a semiconductor device according to an example embodiment are shown, taken along lines B-B' and A-A' of Figure 2

[0109] Referring to Figure 18 and Figure 19 , the semiconductor device can include a plurality of wiring patterns, for example, a first wiring pattern 110 and a second wiring pattern 210. Figure 18 and Figure 19 The semiconductor device is shown to include two wiring patterns, but the semiconductor device can be configured to include three or more wiring patterns. Hereinafter, the semiconductor device according to Figures 3 to 5 differences from the semiconductor device according to Figure 18 and Figure 19 will be mainly described.

[0110] The second wiring pattern 210 can be disposed above the first wiring pattern 110 and can be spaced apart from the first wiring pattern 110. Thus, the second wiring pattern 210 can be formed on the substrate 100 to be spaced apart from the first wiring pattern 110 in the third direction Z. The second wiring pattern 210 can extend in the first direction X. Thus, the fin-type protrusion 100P, the first wiring pattern 110, and the second wiring pattern 210 can all extend in the same direction, for example, in the first direction X.

[0111] The second wiring pattern 210 can be vertically stacked with the first wiring pattern 110 and the fin-type protrusion 100P. Thus, the second wiring pattern 210 can not be formed on the field insulating film 105, but on the fin-type protrusion 100P and the first wiring pattern 110.

[0112] The second wiring pattern 210 can include a semiconductor element material such as Si or Ge. Further, the second wiring pattern 210 can include a compound semiconductor such as exemplified by a Group IV-IV compound semiconductor or a Group III-V compound semiconductor.

[0113] The second wiring pattern 210 can include the same material as or a different material from the first wiring pattern 110 and the fin-type protrusion 100P.

[0114] The first wiring pattern 110 and the second wiring pattern 210 can be used as a channel region of a transistor. For example, the first wiring pattern 110, the second wiring pattern 210, or both can be used as a channel region of an NMOS transistor. In another example, the first wiring pattern 110, the second wiring pattern 210, or both can be used as a channel region of a PMOS transistor.

[0115] ​The interface film 120 can be formed along the periphery of the first wiring pattern 110 and the second wiring pattern 210. For example, the interface film 120 can form interface films 120a and 120b along the periphery of the first wiring pattern 110 and the second wiring pattern 210, respectively. Thus, the interface films 120a and 120b can surround (e.g., completely surround) the first wiring pattern 110 and the second wiring pattern 210, respectively.

[0116] The interface film 120 can be formed on the fin-type protrusion 100P. As Figure 19 The interface film 120 can be formed on the bottom of the trench TR2, as

[0117] The interface film 120 can include, for example, silicon oxide, but example embodiments are not limited thereto. The interface film 120 can also include a material other than silicon oxide, depending on the type of the substrate 100, the type of the first wiring pattern 110, the type of the second wiring pattern 210, or the type of the gate insulating film 130.

[0118] The gate insulating film 130 can be formed on the interface film 120. For example, the gate insulating film 130 can form gate insulating films 130a and 130b along the periphery of the first wiring pattern 110 and the second wiring pattern 210, respectively. Thus, the gate insulating films 130a and 130b can surround (e.g., completely surround) the interface film 120.

[0119] The gate insulating film 130 can also be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The gate insulating film 130 can extend along the inner sidewall of the gate spacer 150. Thus, the gate insulating film 130 can extend along the sidewall and the bottom of the trench TR2 and along the periphery of the first wiring pattern 110 and the second wiring pattern 210.

[0120] The gate electrode 140 can extend in the second direction Y over the substrate 100. As Figure 2 The gate electrode 140 can cross the fin-type protrusion 100P and the first wiring pattern 110 and the second wiring pattern 210, as

[0121] The gate electrode 140 can be formed to surround (e.g., completely surround) the first wiring pattern 110 and the second wiring pattern 210. The gate electrode 140 can be formed between the fin-type protrusion 100P and the first wiring pattern 110 and between the first wiring pattern 110 and the second wiring pattern 210.

[0122] The gate electrode 140 can be formed on the gate insulating film 130. The gate electrode 140 can fill the trench TR2.

[0123] The lower conductive film 142 can be formed along the periphery of the first wiring pattern 110 and the second wiring pattern 210. Thus, the lower conductive film 142 can surround (e.g., completely surround) the gate insulating films 130a and 130b.

[0124] The lower conductive film 142 can also be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The lower conductive film 142 can extend along the inner sidewall of the gate spacer 150. Thus, the lower conductive film 142 can extend along the sidewall and the bottom of the trench TR2 and along the periphery of the first wiring pattern 110 and the second wiring pattern 210.

[0125] The work function film 144 can be formed along the periphery of the first wiring pattern 110 and the second wiring pattern 210. Thus, the work function film 144 can surround (e.g., completely surround) the lower conductive film 142.

[0126] The work function film 144 can also be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The work function film 144 can extend along the inner sidewall of the gate spacer 150. Thus, the work function film 144 can extend along the sidewall and the bottom of the trench TR2 and along the periphery of the first wiring pattern 110.

[0127] The barrier film 146 can be formed on the top surface of the field insulating film 105 and on the fin-type protrusion 100P. The barrier film 146 can extend along the inner sidewall of the gate spacer 150. Thus, the barrier film 146 can extend along the sidewall and the bottom of the trench TR2.

[0128] The gate spacer 150 can be formed on both or opposite sidewalls of the gate electrode 140, which extend in the second direction Y. For example, as shown in FIG. 1B, the gate spacer 150 can be formed on both or opposite sides of the gate electrode 140 to face each other. The gate spacer 150 can define the trench TR2, which intersects the second wiring pattern 210. Figure 19

[0129] The gate spacer 150 can include an outer spacer 152 and an inner spacer 154. The inner spacer 154 can be disposed between the fin-type protrusion 100P and the first wiring pattern 110 and between the first wiring pattern 110 and the second wiring pattern 210. Although not specifically shown, the width of the inner spacer 154 in the second direction Y can be substantially the same as the width of the first wiring pattern 110 and the second wiring pattern 210 in the second direction Y.

[0130] The outer spacer 152 can be disposed on the inner spacer 154.​Figure 19 The inner spacers 154 and the outer spacers 152 are sequentially provided on the second wiring pattern 210 or the like. Therefore, depending on the structure of the stack for forming the second wiring pattern 210, only the outer spacers 152 can be provided on the second wiring pattern 210.

[0131] Figure 20 A cross-sectional view of the semiconductor device according to the example embodiment taken along a line B-B' of Figure 2 will mainly focus on the difference from the semiconductor device including only the first wiring pattern 110 of Figure 6 will mainly focus on the difference from the semiconductor device including only the first wiring pattern 110 of Figure 20 .

[0132] Referring to Figure 4 and Figure 20 , the gate electrode 140 can include a first portion 140_P0 superposed on the fin-type protrusion 100P in the second direction Y and a second portion 140_P1 occupying or corresponding to the remaining portion of the gate electrode 140. The distance between the sidewall of the fin-type protrusion 100P and the gate electrode 140 can increase in the third direction Z away from the top surface of the fin-type protrusion 100P. For example, the distance in the second direction Y between the sidewall of the fin-type protrusion 100P and the first portion 140_P0 of the gate electrode 140 can increase in the downward direction away from the top surface of the fin-type protrusion 100P.

[0133] In the example embodiment, the field insulating film 105 can be formed to at least partially surround the two sidewalls of the fin-type protrusion 100P and can define the fin-type protrusion 100P. The field insulating film 105 can include a first region 105_R0 superposed on the first portion 140_P0 of the gate electrode 140 in the second direction Y and a second region 105_R1 occupying or corresponding to the remaining portion of the field insulating film 105. Therefore, the first region 105_R0 can be defined as a region superposed on the gate electrode 140 and the gate insulating film 130_1 in the second direction Y.

[0134] In more detail, as shown in Figure 20 and Figure 7 , the field insulating film 105 can include a first region 105_R0 formed above the bottom surface of the gate insulating film 130_1 and a second region 105_R1 formed below the bottom surface of the gate insulating film 130_1. Therefore, the field insulating film 105 can be formed not to surround the entire sidewall of the fin-type protrusion 100P but only a portion of the sidewall of the fin-type protrusion 100P.

[0135] Figure 21 A cross-sectional view of the semiconductor device according to the example embodiment taken along a line B-B' of Figure 2 will mainly focus on the difference from the semiconductor device including only the first wiring pattern 110 ofFigure 15 of the semiconductor device including only the first wiring pattern 110 Figure 21 of the semiconductor device.

[0136] Referring to Figure 21 , a bottom surface of the gate electrode 140 can be formed to be recessed in the third direction Z. In an example embodiment, bottom surfaces of the gate insulating film 130_2, the lower conductive film 142_2, and the work function film 144_2, which are formed on the fin-type protrusion 100P, can be formed to be recessed in the third direction Z, for example, to form a concave surface. For example, the fin-type protrusion 100P can be formed to protrude from the base 100 in the third direction Z.

[0137] Figure 22 shows a cross-sectional view of the semiconductor device according to an example embodiment taken along a line B-B' of Figure 2 . In the following, the differences from the semiconductor device including only the first wiring pattern 110 Figure 16 and Figure 17 of the semiconductor device including only the first wiring pattern 110 Figure 22 of the semiconductor device.

[0138] Referring to Figure 22 , each of the first wiring pattern 110' and the second wiring pattern 210' can be formed in a shape of a pattern including a combination of straight lines and curves. A cross section of the first wiring pattern 110' and the second wiring pattern 210' can have, for example, a rectangular shape with rounded corners. In an embodiment, each of the first wiring pattern 110' and the second wiring pattern 210' can be formed in a shape of a pattern including a combination of curves.

[0139] Figure 23 shows a cross-sectional view of the semiconductor device according to an example embodiment taken along a line B-B' of Figure 2 .

[0140] Referring to Figure 23 , in an example embodiment, a first width W1 of the first wiring pattern 110'_0 in the second direction Y can be different from a second width W2 of the second wiring pattern 210'_0 in the second direction Y. For example, the second width W2 of the second wiring pattern 210'_0 can be smaller than the first width W1 of the first wiring pattern 110'_0. The first width W1 of the first wiring pattern 110'_0 and the second width W2 of the second wiring pattern 210'_0 can be the maximum widths of the first wiring pattern 110'_0 and the second wiring pattern 210'_0 in the second direction Y, respectively.

[0141] In the example embodiment, the width of the fin-type protrusion 100P in the second direction Y can be greater than the first width W1 of the first wiring pattern 110'_0 and the second width W2 of the second wiring pattern 210'_0. Thus, the first width W1 of the first wiring pattern 110'_0 can be greater than the second width W2 of the second wiring pattern 210'_0, and the width of the fin-type protrusion 100P in the second direction Y can be greater than the first width W1 of the first wiring pattern 110'_0. The width of the fin-type protrusion 100P in the second direction Y can refer to the width of the top surface of the fin-type protrusion 100P in the second direction Y.

[0142] Figure 24 A cross-sectional view taken along a line B-B' of the semiconductor device according to an example embodiment is shown. Figure 2

[0143] Referring to Figure 24 In the example embodiment, the distance between the fin-type protrusion 100P and the first wiring pattern 110 can be different from the distance between the first wiring pattern 110 and the second wiring pattern 210. As shown in Figure 24 the distance H4 between the fin-type protrusion 100P and the first wiring pattern 110 in the third direction Z can be greater than the distance H5 between the first wiring pattern 110 and the second wiring pattern 210 in the third direction Z. The distance H4 between the fin-type protrusion 100P and the first wiring pattern 110 can refer to the distance between the top surface of the fin-type protrusion 100P and the bottom surface of the first wiring pattern 110, i.e., the shortest distance between the fin-type protrusion 100P and the first wiring pattern 110. Further, the distance H5 between the first wiring pattern 110 and the second wiring pattern 210 can refer to the distance between the top surface of the first wiring pattern 110 and the bottom surface of the second wiring pattern 210, i.e., the shortest distance between the first wiring pattern 110 and the second wiring pattern 210.

[0144] In the example embodiment, the distance H4 between the fin-type protrusion 100P and the first wiring pattern 110 can refer to the distance in the third direction Z between the portion of the gate insulating film 130 disposed on the top surface of the fin-type protrusion 100P and the portion of the gate insulating film 130 disposed adjacent to the bottom surface of the first wiring pattern 110. The distance H5 between the first wiring pattern 110 and the second wiring pattern 210 can refer to the distance in the third direction Z between the portion of the gate insulating film 130 disposed on the top surface of the first wiring pattern 110 and the portion of the gate insulating film 130 disposed adjacent to the bottom surface of the second wiring pattern 210.

[0145] Figures 25 to 39 A schematic diagram showing stages in a method of manufacturing a semiconductor device according to an example embodiment is shown. For convenience, Figures 25 to 39 ​How to manufacture a semiconductor device including two wiring patterns and the like is shown. Thus, Figures 25 to 39 Embodiments of the present application are also applicable to a semiconductor device including only one wiring pattern or three or more wiring patterns.

[0146] Specifically, Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 and Figure 38 are cross-sectional views taken along the line E-E' of Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 and Figure 39 are cross-sectional views taken along the line F-F' of Figure 25 .

[0147] Referring to Figures 25 to 27 , the substrate 100 can have a sacrificial film 2001 in a stack of alternating layers and an active film 2002 formed on the sacrificial film 2001. Figure 25 It is shown that three sacrificial films 2001 and two active films 2002 are formed on the substrate 100 and the like. As an example, Figure 25 It is also shown that the uppermost layer of the stack of the sacrificial film 2001 and the active film 2002 is the sacrificial film 2001. The active film 2002 can include a material having etching selectivity with respect to the sacrificial film 2001. The sacrificial film 2001 and the active film 2002 can be formed by, for example, epitaxial growth.

[0148] Thereafter, a first mask pattern 2101 can be formed on the uppermost sacrificial film 2001. The first mask pattern 2101 can extend in the first direction X.

[0149] Referring to Figure 28 and Figure 29 , a fin-type structure F1 can be formed by performing etching using the first mask pattern 2101 as a mask. The fin-type structure F1 can include a fin-type protrusion 100P and a sacrificial pattern 111 and an active pattern 112 alternately stacked on the fin-type protrusion 100P.

[0150] Thereafter, a field insulating film 105 can be formed on the substrate 100 to at least partially cover the sidewalls of the fin-type structure F1 (see Figure 31 ). During formation of the field insulating film 105, the first mask pattern 2101 can be removed. The field insulating film 105 can be formed below the top surface of the fin-type protrusion 100P. Thus, as described above with reference to Figure 3 and Figure 4As described, the top surface of the field insulating film 105 can be below the top surface of the fin-type protrusion 100P.

[0151] Referring to Figure 30 and Figure 31 A dummy gate electrode 140P can be formed crossing the fin-type structure F1 and extending in the second direction Y.

[0152] The dummy gate electrode 140P can be formed by using the second mask pattern 2102 as a mask.

[0153] Although not specifically shown, a dummy gate insulating film or a fin-type structure passivation film can be further formed between the dummy gate electrode 140P and the fin-type structure F1.

[0154] A pre-gate spacer 150P can be formed on the sidewall of the dummy gate electrode 140P.

[0155] Referring to Figure 32 and Figure 33 A source / drain region 160 can be formed on both sides of the dummy gate electrode 140P.

[0156] In an example embodiment, portions of the sacrificial pattern 111 and portions of the active pattern 112 can be removed to form the source / drain region 160.

[0157] Thereafter, portions of the sacrificial pattern 111 that are superimposed with the pre-gate spacer 150P can be additionally removed.

[0158] An inner spacer 154 can be formed at the position where the sacrificial pattern 111 is additionally removed.

[0159] Thereafter, the source / drain region 160 can be formed on both sides of the dummy gate electrode 140P.

[0160] Thereafter, an interlayer insulating film 190 covering the source / drain region 160 can be formed on the substrate 100.

[0161] The interlayer insulating film 190 can expose the dummy gate electrode 140P.

[0162] During formation of the interlayer insulating film 190, the second mask pattern 2102 can be removed. Further, during formation of the interlayer insulating film 190, an outer spacer 152 can be formed on the inner spacer 154.

[0163] In this way, a gate spacer 150 including the inner spacer 154 and the outer spacer 152 can be formed.

[0164] Referring to Figure 34 and Figure 35The first wiring pattern 110 and the second wiring pattern 210 can be formed on the substrate 100 by removing the dummy gate electrode 140P and the sacrificial pattern 111.

[0165] The first wiring pattern 110 can be formed to be spaced apart from the fin-type protrusion 100P, and the second wiring pattern 210 can be formed to be spaced apart from the first wiring pattern 110.

[0166] After the sacrificial pattern 111 is removed, a surface treatment process can be performed on the fin-type protrusion 100P, the first wiring pattern 110, and the second wiring pattern 210. The surface treatment process can be performed using, for example, one of an H2 bake, a rapid thermal process (RTP), a hydrogen plasma anneal (HPA), and a wet process. By performing the surface treatment process on the fin-type protrusion 100P, the first wiring pattern 110, and the second wiring pattern 210 after the sacrificial pattern 111 is removed, channel roughness on a top surface and sidewalls of the fin-type protrusion 100P, a side surface of the first wiring pattern 110, and a side surface of the second wiring pattern 210 can be improved (i.e., reduced).

[0167] Referring to Figure 36 and Figure 37 An interface film 120 can be formed along a periphery of the first wiring pattern 110 and the second wiring pattern 210. For example, the interface film 120 can be formed by oxidizing a surface of the first wiring pattern 110 and the second wiring pattern 210.

[0168] Thereafter, a gate insulating film 130, a lower conductive film 142, a work function film 144, and a barrier film 146 can be sequentially formed along a periphery of the first wiring pattern 110 and the second wiring pattern 210 and along a sidewall and a bottom of the trench TR2.

[0169] A bottom of the gate electrode 140 can be formed below a top surface of the fin-type protrusion 100P. Thus, as described above with reference to Figure 18 a portion of the lower conductive film 142 and a portion of the gate insulating film 130 below a top surface of the fin-type protrusion 100P in the third direction Z. Thus, the gate electrode 140 can be formed uniformly on the top surface of the fin-type protrusion 100P. For example, the gate electrode 140 or the gate insulating film 130 can be formed to not protrude in the third direction Z along an edge of the top surface of the fin-type protrusion 100P, as a result, channel mobility can be improved.

[0170] Although not specifically shown, the gate insulating film 130, the lower conductive film 142, the work function film 144, and the barrier film 146 can be formed along a top surface of the interlayer insulating film 190.

[0171] In an example embodiment, the forming of the work function film 144 and the forming of the barrier film 146 can be performed in-situ.

[0172] Referring to Figure 38 and Figure 39 A film treatment (FT) process can be performed on the work function film 144. As a result, a carbon concentration gradient in the work function film 144 can be controlled. The FT process can include at least one of, for example, a plasma treatment, an annealing, an ultraviolet (UV) treatment, and a combination thereof. For example, the FT process can include a hydrogen plasma treatment.

[0173] Thereafter, referring back to Figure 18 and Figure 19 A fill conductive film 148 can be formed on the barrier film 146. Accordingly, a gate electrode 140 including the lower conductive film 142, the work function film 144, the barrier film 146, and the fill conductive film 148 can be formed.

[0174] By way of summary and review, as a scaling technique for increasing the density of a semiconductor device, a gate-all-around structure in which a silicon body in a nanowire shape is formed on a substrate and a gate is formed to surround the silicon body has been proposed. Since the gate-all-around structure uses a three-dimensional (3D) channel, scaling can be facilitated. Further, current control capability can be improved without increasing the length of the gate. Further, a short channel effect (SCE), i.e., a phenomenon in which the potential of a channel region is affected by a drain voltage, can be effectively suppressed.

[0175] As described above, embodiments relate to a semiconductor device including a gate electrode formed under a top surface of a fin-type pattern. Embodiments can provide a semiconductor device capable of improving operational performance and reliability by improving the roughness of a surface of a channel region. Embodiments can provide a semiconductor device capable of improving channel mobility by removing any protruding portions on a surface of a fin-type pattern. Embodiments can provide a method of manufacturing a semiconductor device capable of improving operational performance and reliability by improving the roughness of a surface of a channel region. Embodiments can provide a method of manufacturing a semiconductor device capable of improving channel mobility by removing any protruding portions on a surface of a fin-type pattern.

[0176] Example embodiments have been disclosed and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, unless otherwise specifically stated. In some instances, as will be apparent to those of ordinary skill in the art, features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, one of ordinary skill in the art will recognize that the inventive features and concepts disclosed herein can be practiced with modification and alteration, and that the inventive features and concepts disclosed herein can be employed in other, subject matter not expressly disclosed, but which will be within the scope of the inventive spirit and scope of the claims.

Claims

1. A semiconductor device comprising: a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction; a first wiring pattern on the fin-type pattern, the first wiring pattern being spaced apart from a top surface of the fin-type pattern in the third direction; a field insulating film at least partially surrounding two side walls of the fin-type pattern to define the fin-type pattern; an interface film on the top surface of the fin-type pattern; and a gate electrode extending in a second direction perpendicular to the first direction and the third direction and surrounding the first wiring pattern, wherein the side walls of the fin-type pattern include a first portion covering the field insulating film and a second portion connected to the top surface of the fin-type pattern on the first portion, and wherein the gate electrode includes a first portion superposed on the second portion of the side walls of the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode other than the first portion of the gate electrode. The field insulating film includes a first region superposed on the first portion of the gate electrode and a second region corresponding to a remainder of the field insulating film other than the first region.

2. The semiconductor device of claim 1, wherein, A bottom surface of the gate electrode is recessed in the third direction.

3. The semiconductor device of claim 1, wherein, 4. The semiconductor device according to claim 1, further comprising: gate spacers at least partially superposed on the first wiring pattern in the third direction; and a source region and a drain region respectively provided on both sides of the first wiring pattern, wherein the gate electrode is provided between the gate spacers.

5. The semiconductor device according to claim 4, wherein: the gate spacers define trenches, and the semiconductor device further comprises a gate insulating film extending along side walls of the trenches and along a periphery of the first wiring pattern.

6. The semiconductor device according to claim 1, further comprising a second wiring pattern spaced apart from the first wiring pattern in the third direction and intersecting the gate electrode. A width of the first wiring pattern in the second direction is greater than a width of the second wiring pattern in the second direction. A distance between the fin-type pattern and the first wiring pattern in the third direction is greater than a distance between the first wiring pattern and the second wiring pattern in the third direction.

7. The semiconductor device of claim 6, wherein, A distance between the side walls of the fin-type pattern and the gate electrode increases away from the top surface of the fin-type pattern.

8. The semiconductor device of claim 6, wherein, A distance between a bottom surface of the first portion of the gate electrode and the top surface of the fin-type pattern in the third direction is 50 nm or less.

9. The semiconductor device of claim 1, wherein, 11. The semiconductor device according to claim 1, further comprising a field liner on a top surface of the substrate, the field liner being on at least a portion of the side walls of the fin-type pattern.

10. The semiconductor device of claim 1, wherein, 12. A semiconductor device comprising: a fin-type pattern protruding from a substrate; and a first wiring pattern on the fin-type pattern, the first wiring pattern being spaced apart from the fin-type pattern in a third direction; a field insulating film at least partially surrounding two side walls of the fin-type pattern to define the fin-type pattern; an interface film on a top surface of the fin-type pattern; and a gate electrode intersecting the first wiring pattern, ​ ​ ​ ​ wherein a distance between the top surface of the fin-type pattern and the end portion of the first wiring pattern is equal to or greater than a distance between the top surface of the fin-type pattern and a portion of the first wiring pattern other than the end portion, wherein the sidewall of the fin-type pattern includes a first portion covering the field insulating film and a second portion connected to the top surface of the fin-type pattern on the first portion, and wherein the gate electrode includes a first portion superimposed on the second portion of the sidewall of the fin-type pattern in a second direction perpendicular to the third direction and intersecting a direction in which the fin-type pattern extends, and a second portion corresponding to a remaining portion of the gate electrode other than the first portion of the gate electrode.

13. The semiconductor device of claim 12, wherein, The distance between the sidewall of the fin-type pattern and the gate electrode increases away from the top surface of the fin-type pattern.

14. The semiconductor device according to claim 12, further comprising a second wiring pattern spaced apart from the first wiring pattern, wherein a distance between the second wiring pattern and the top surface of the first wiring pattern at an end portion of the second wiring pattern in the second direction is equal to or greater than a distance between the second wiring pattern and the top surface of the first wiring pattern at a portion of the second wiring pattern other than the end portion.

15. The semiconductor device of claim 14, wherein, The first wiring pattern includes a first region superimposed on the second wiring pattern and a second region not superimposed on the second wiring pattern.

16. The semiconductor device of claim 14, wherein, An edge of the first wiring pattern and an edge of the second wiring pattern are curved.

17. A semiconductor device, the semiconductor device comprising: a fin-type pattern protruding from a substrate; a wiring pattern spaced apart from a top surface of the fin-type pattern; a field insulating film at least partially surrounding two sidewalls of the fin-type pattern to define the fin-type pattern; an interface film on the top surface of the fin-type pattern; and a gate electrode surrounding the wiring pattern, wherein the gate electrode includes a first portion superimposed on at least a portion of the sidewall of the fin-type pattern in a second direction and a second portion corresponding to a remaining portion of the gate electrode other than the first portion of the gate electrode.

18. The semiconductor device according to claim 17, wherein: a bottom surface of the gate electrode is located below the top surface of the fin-type pattern, and a distance between the top surface of the fin-type pattern and the bottom surface of the gate electrode is 50 nm or less. ​

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