Integrated circuit device and method of manufacturing the same

Abstract

An integrated circuit device and a method of manufacturing the same are disclosed, in which the integrated circuit device includes a lower electrode including a niobium (Nb)-containing layer doped with titanium (Ti), a dielectric layer on the lower electrode, and an upper electrode covering the dielectric layer.

Description

Technical Field

[0001] The implementation method relates to an integrated circuit device and a method for manufacturing the same. Background Technology

[0002] As integrated circuit devices are scaled down, the space occupied by capacitors will decrease. Summary of the Invention

[0003] The embodiment relates to an integrated circuit device, the integrated circuit device comprising: a lower electrode including a niobium (Nb) layer doped with titanium (Ti); a dielectric layer on the lower electrode; and an upper electrode covering the dielectric layer.

[0004] The embodiments also relate to an integrated circuit device, the integrated circuit device comprising: a substrate including an active region; a conductive region on the active region; and a capacitor on the conductive region, the capacitor comprising: a lower electrode including an Nb-containing layer doped with Ti; a dielectric layer formed on the lower electrode; and an upper electrode covering the dielectric layer.

[0005] The embodiments also relate to an integrated circuit device, the integrated circuit device comprising: a substrate including an active region; a conductive region formed on the active region; and a capacitor on the conductive region, the capacitor comprising: a lower electrode including at least one selected from a Ti-doped Nb nitride layer, a Ti-doped Nb oxide layer and a Ti-doped Nb oxynitride layer; a dielectric layer on the lower electrode and including a metal oxide layer; and an upper electrode covering the dielectric layer.

[0006] The embodiments also relate to a method of manufacturing an integrated circuit device, the method comprising: forming a lower electrode on a substrate including an Nb-containing layer doped with Ti; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer. Attached Figure Description

[0007] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] FIG. 1 A cross-sectional view showing the main configuration of an integrated circuit device according to an example embodiment is shown;

[0009] FIG. 2 A cross-sectional view showing the main configuration of an integrated circuit device according to an example embodiment is shown;

[0010] FIG. 3 A cross-sectional view showing the main configuration of an integrated circuit device according to an example embodiment is shown;

[0011] FIG. 4A cross-sectional view showing the main configuration of an integrated circuit device according to an example embodiment is shown;

[0012] FIG. 5 A cross-sectional view showing the main configuration of an integrated circuit device according to an example embodiment is shown;

[0013] FIG. 6 A cross-sectional view showing the main configuration of an integrated circuit device according to an example embodiment is shown;

[0014] FIG. 7 A schematic planar layout of an integrated circuit device according to an example embodiment is shown;

[0015] FIG. 8A A cross-sectional view of an integrated circuit device according to an example embodiment is shown. FIG. 8B yes FIG. 8A An enlarged cross-sectional view of the local region Q1;

[0016] FIG. 9A A cross-sectional view of an integrated circuit device according to an example embodiment is shown. FIG. 9B yes FIG. 9A A magnified cross-sectional view of the local region Q2;

[0017] FIG. 10 A cross-sectional view of an integrated circuit device according to an example embodiment is shown;

[0018] FIG. 11 A cross-sectional view of an integrated circuit device according to an example embodiment is shown;

[0019] FIG. 12 A cross-sectional view of an integrated circuit device according to an example embodiment is shown;

[0020] FIG. 13 A cross-sectional view of an integrated circuit device according to an example embodiment is shown;

[0021] FIG. 14 A cross-sectional view of an integrated circuit device according to an example embodiment is shown;

[0022] FIG. 15 This is a graph showing the results obtained by evaluating the capacitance of the capacitor of an integrated circuit device according to an exemplary embodiment, together with a comparative example.

[0023] FIG. 16A to FIG. 16I A cross-sectional view showing the process of a method for manufacturing an integrated circuit device according to an example embodiment;

[0024] FIG. 17A to FIG. 17E A cross-sectional view showing the process of a method for manufacturing an integrated circuit device according to an example embodiment; and

[0025] FIG. 18A and FIG. 18B A cross-sectional view of the process of manufacturing an integrated circuit device according to an example embodiment is shown. Detailed Implementation

[0026] FIG. 1 This is a cross-sectional view of the main configuration of an integrated circuit device 100A according to an example embodiment.

[0027] Reference FIG. 1 The integrated circuit device 100A includes a substrate 102, a lower structure 120 formed on the substrate 102, and a capacitor C11 formed on the lower structure 120.

[0028] Substrate 102 may comprise a semiconductor element such as silicon (Si) or germanium (Ge) or a compound semiconductor such as SiC, GaAs, InAs, or InP. Substrate 102 may comprise a structure including a semiconductor substrate, at least one insulating layer formed on the semiconductor substrate, or at least one conductive region. The conductive region may be formed, for example, by a doped well or a doped structure. In an example embodiment, substrate 102 may have various device isolation structures, such as shallow trench isolation (STI) structures.

[0029] In one example embodiment, the lower structure 120 may include an insulating layer. In other example embodiments, the lower structure 120 may include various conductive regions (e.g., wiring layers, contact plugs, and transistors) and insulating layers for insulating the conductive regions from each other.

[0030] The capacitor C11 may include a lower electrode LE11 and an upper electrode UE11 facing each other, and a dielectric layer 140 between the lower electrode LE11 and the upper electrode UE11. The lower electrode LE11 may include a main lower electrode layer 130. The top surface of the main lower electrode layer 130 may contact the bottom surface of the dielectric layer 140.

[0031] In one example embodiment, the main lower electrode layer 130 may be formed of a niobium (Nb) layer doped with titanium (Ti). In another example embodiment, the main lower electrode layer 130 may include a Ti-doped Nb nitride layer (hereinafter referred to as a "Ti-doped NbN layer"). The ratio of Ti atoms to Nb atoms in the Ti-doped NbN layer may be from 9:1 to 1:99. If the Nb atom content ratio in the main lower electrode layer 130 is too small, it may be difficult to ensure the required conductivity of the lower electrode LE11. If the Nb atom content ratio in the main lower electrode layer 130 is too large, it may have a negative impact on the required electrical characteristics of the capacitor C11.

[0032] In other example embodiments, the main lower electrode layer 130 may include an NbN layer comprising multiple dopants. The multiple dopants may include a first dopant formed of Ti and dopants formed of cobalt (Co), tin (Sn), vanadium (V), tantalum (Ta). The second dopant is formed from at least one of Db, phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In the main lower electrode layer 130, the content ratio of the first dopant to Nb atoms can be in the range of 9:1 to 1:99. In the main lower electrode layer 130, the atomic content ratio of the second dopant to Nb atoms can be from about 0.01 to about 0.15.

[0033] The main lower electrode layer 130 can have a thickness TH1 of about 5 nm to about 30 nm.

[0034] The dielectric layer 140 may include a high-dielectric-constant layer. The term "high-dielectric-constant layer" as used in this specification means a dielectric layer having a dielectric constant greater than that of a silicon oxide layer. In one example embodiment, the dielectric layer 140 may be formed of a metal oxide comprising at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), Nb, cerium (Ce), lanthanum (La), Ta, and Ti. In one example embodiment, the dielectric layer 140 may have a monolayer structure comprising a single high-dielectric-constant layer. In other example embodiments, the dielectric layer 140 may have a multilayer structure comprising multiple high-dielectric-constant layers. The high-dielectric-constant layer may be one of an HfO2 layer, a ZrO2 layer, an Al2O3 layer, a CeO2 layer, a La2O3 layer, a Ta2O3 layer, and a TiO2 layer. In one example embodiment, the dielectric layer 140 may have approximately to approximately The thickness.

[0035] The upper electrode UE11 may face the lower electrode LE11, and the dielectric layer 140 is located between the upper electrode UE11 and the lower electrode LE11. The upper electrode UE11 may include an upper electrode layer 150. The upper electrode layer 150 may be formed of a metal, a metal nitride, a metal oxide, or a combination of the above materials. For example, the upper electrode UE11 may be formed of TiN, MoN, CoN, TaN, TiAlN, TaAlN, W, Ru, RuO2, SrRuO3, Ir, IrO2, Pt, PtO, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO ((La,Sr)CoO3), or a combination of the above materials.

[0036] FIG. 2 This is a cross-sectional view of the main configuration of an integrated circuit device 100B according to an example embodiment. FIG. 2 In, with FIG. 1The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0037] Reference FIG. 2 The integrated circuit device 100B includes a capacitor C12. The capacitor C12 has a... FIG. 1 The capacitor C11 shown has a similar configuration. Capacitor C12 includes a lower electrode LE12, an upper electrode UE11, and a dielectric layer 140 between the lower electrode LE12 and the upper electrode UE11. The lower electrode LE12 includes a main lower electrode layer 132 and a lower interface electrode layer 134. The main lower electrode layer 132 is spaced apart from the dielectric layer 140, and the lower interface electrode layer 134 is disposed therebetween. The top surface of the main lower electrode layer 132 can contact the bottom surface of the lower interface electrode layer 134.

[0038] In one example embodiment, the main lower electrode layer 132 may be formed of a metal, a metal nitride, a metal oxide, or a combination thereof. For example, the main lower electrode layer 132 may be formed of TiN, MoN, CoN, TaN, TiAlN, TaAlN, W, Ru, RuO2, SrRuO3, Ir, IrO2, Pt, PtO, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO ((La,Sr)CoO3), or a combination thereof. In one example embodiment, the main lower electrode layer 132 may not include Nb, or in other example embodiments, the main lower electrode layer 132 may include a Ti-doped NbN layer (in which case, the main lower electrode layer 132 may have the same characteristics as the reference layer). FIG. 1 The configuration of the main lower electrode layer 130 described is the same as the configuration described.

[0039] In this example embodiment, the lower interface electrode layer 134 is located between the main lower electrode layer 132 and the dielectric layer 140. The bottom surface of the lower interface electrode layer 134 can contact the top surface of the main lower electrode layer 132, and the top surface of the lower interface electrode layer 134 can contact the bottom surface of the dielectric layer 140.

[0040] The lower interface electrode layer 134 may include a Ti-doped Nb oxide layer (hereinafter referred to as a "Ti-doped NbO layer") or a Ti-doped Nb oxynitride layer (hereinafter referred to as a "Ti-doped NbON layer"). In one example embodiment, the ratio of Ti atoms to Nb atoms in each of the Ti-doped NbO layer and the Ti-doped NbON layer may be from 9:1 to 1:99.

[0041] The thickness TH21 of the main lower electrode layer 132 may differ from the thickness TH22 of the lower interface electrode layer 134. In one example embodiment, the thickness TH22 of the lower interface electrode layer 134 may be less than the thickness TH21 of the main lower electrode layer 132. For example, the thickness TH21 of the main lower electrode layer 132 may be about 5 nm to about 30 nm, and the thickness TH22 of the lower interface electrode layer 134 may be about [missing information]. to approximately If the thickness TH22 of the lower interface electrode layer 134 is too large, the conductivity of the lower interface electrode layer 134 may deteriorate, and the lower interface electrode layer 134 may be used as a dielectric with a relatively low dielectric constant. Therefore, the capacitance of capacitor C12 may deteriorate.

[0042] FIG. 3 This is a cross-sectional view of the main configuration of an integrated circuit device 100C according to an example embodiment. FIG. 3 In, with FIG. 1 and FIG. 2 The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0043] Reference FIG. 3 The integrated circuit device 100C includes a capacitor C13. The capacitor C13 has a... FIG. 1 The capacitor C11 shown has a similar configuration. Capacitor C13 includes a lower electrode LE13, an upper electrode UE13, and a dielectric layer 140 between the lower electrode LE13 and the upper electrode UE13. The lower electrode LE13 includes a main lower electrode layer 130 and a lower interface electrode layer 136, and the upper electrode UE13 includes an upper electrode layer 150 and an upper interface electrode layer 138. The lower interface electrode layer 136 is located between the main lower electrode layer 130 and the dielectric layer 140, and the upper interface electrode layer 138 is located between the dielectric layer 140 and the upper electrode layer 150.

[0044] The bottom surface of the lower interface electrode layer 136 can contact the top surface of the main lower electrode layer 130, and the top surface of the lower interface electrode layer 136 can contact the bottom surface of the dielectric layer 140. The bottom surface of the upper interface electrode layer 138 can contact the top surface of the dielectric layer 140, and the top surface of the upper interface electrode layer 138 can contact the bottom surface of the upper electrode layer 150. In an example embodiment, the upper interface electrode layer 138 can be omitted in the capacitor C13. In this case, the top surface of the dielectric layer 140 can contact the bottom surface of the upper electrode layer 150.

[0045] The lower interface electrode layer 136 and the upper interface electrode layer 138 may respectively comprise a Ti-doped NbO layer and a Ti-doped NbON layer. Detailed configuration and reference of the lower interface electrode layer 136 and the upper interface electrode layer 138 are provided below. FIG. 2The lower interface electrode layer 134 is configured identically. The first thickness TH31 of the lower interface electrode layer 136 and the second thickness TH32 of the upper interface electrode layer 138 can be approximately... to approximately When the first thickness TH31 and the second thickness TH32 are too thick, the conductivity of each of the lower interface electrode layer 136 and the upper interface electrode layer 138 may deteriorate, and the lower interface electrode layer 136 and the upper interface electrode layer 138 may be used as dielectrics with relatively low dielectric constants. Therefore, the capacitance of capacitor C13 may deteriorate.

[0046] FIG. 4 This is a cross-sectional view of the main configuration of an integrated circuit device 100D according to an example embodiment. FIG. 4 In, with FIG. 1 to FIG. 3 The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0047] Reference FIG. 4 The integrated circuit device 100D includes a capacitor C14. The capacitor C14 has a... FIG. 2 The capacitor C12 of the integrated circuit device 100B shown has a similar configuration. The capacitor C14 includes a lower electrode LE14, an upper electrode UE14, and a dielectric layer 140 between the lower electrode LE14 and the upper electrode UE14. The lower electrode LE14 may have a configuration similar to that of the referenced capacitor. FIG. 2 The lower electrode LE12 described has the same configuration. The upper electrode UE14 includes an upper electrode layer 150 and an upper interface electrode layer 138. The upper electrode UE14 may have the same configuration as the referenced one. FIG. 3 The upper electrode UE13 described has the same configuration. In one example embodiment, the upper interface electrode layer 138 can be omitted in the capacitor C14. In this case, the top surface of the dielectric layer 140 can contact the bottom surface of the upper electrode layer 150.

[0048] FIG. 5 This is a cross-sectional view of the main configuration of an integrated circuit device 100E according to an example embodiment. FIG. 5 In, with FIG. 1 The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0049] Reference FIG. 5 The integrated circuit device 100E includes a capacitor C15. The capacitor C15 has a... FIG. 1 The capacitor C11 of the integrated circuit device 100A shown has a similar configuration. The capacitor C15 includes a lower electrode LE15 comprising multiple layers.

[0050] The lower electrode LE15 may include a first lower electrode layer L1, a second lower electrode layer L2, and a third lower electrode layer L3 sequentially stacked on the substrate 102. At least one of the first to third lower electrode layers L1, L2, and L3 may include a Ti-doped Nb-containing layer. When each of the first to third lower electrode layers L1, L2, and L3 includes a Ti-doped Nb-containing layer, the Nb atom to Ti atom content ratio may vary in each of the first to third lower electrode layers L1, L2, and L3. In the lower electrode LE15, the Nb atom to Ti atom content ratio may gradually increase toward the dielectric layer 140. For example, the Nb atom to Ti atom content ratio may be greatest in the third lower electrode layer L3, which is closest to the dielectric layer 140 among the first lower electrode layers L1, second lower electrode layers L2, and third lower electrode layers L3.

[0051] In one example embodiment, each of the first to third lower electrode layers L1, L2, and L3 includes a Ti-doped NbN layer, and the ratio of Ti atoms to Nb atoms in each of the first to third lower electrode layers L1, L2, and L3 can range from about 9:1 to about 1:99. In the first to third lower electrode layers L1, L2, and L3, the Nb atom content gradually increases towards the dielectric layer 140, and can be the highest in the third lower electrode layer L3, which is closest to the dielectric layer 140.

[0052] In some other example embodiments, in the first to third lower electrode layers L1, L2, and L3, the first lower electrode layer L1, which is furthest from the dielectric layer 140, does not include Nb, and each of the second lower electrode layers L2 and L3 may include a Ti-doped NbN layer. In this case, the ratio of Ti atoms to Nb atoms in the second lower electrode layer L2 and L3 may be in the range of about 9:1 to about 1:99. The ratio of Nb atoms to Ti atoms in each of the second lower electrode layer L2 and L3 may vary. For example, the first lower electrode layer L1 may include a TiN layer, each of the second lower electrode layer L2 and L3 may include a Ti-doped NbN layer, and the ratio of Nb atoms to Ti atoms in the third lower electrode layer L3 may be greater than the ratio of Nb atoms to Ti atoms in the second lower electrode layer L2.

[0053] At least one of the first to third lower electrode layers L1, L2, and L3 may include an additional dopant formed of at least one of Co, Sn, V, Ta, Db, P, As, Sb, and Bi. In the first to third lower electrode layers L1, L2, and L3, the atomic ratio of the additional dopant to Nb atoms may be from about 0.01 to about 0.15.

[0054] The lower electrode LE15 may have a thickness TH5 of about 5 nm to about 30 nm. The thickness of each of the first to third lower electrode layers L1, L2 and L3 may vary. The thickness of each of the first to third lower electrode layers L1, L2 and L3 may vary, and at least a portion of the first to third lower electrode layers L1, L2 and L3 may have the same thickness.

[0055] exist FIG. 5 The diagram illustrates a case where the lower electrode LE15 comprises three main lower electrode layers, namely, first to third lower electrode layers L1, L2, and L3. In various example embodiments, the lower electrode LE15 may have a multilayer structure comprising two, four, or more main lower electrode layers with different Nb atomic ratios. The Nb atomic ratio of each of the plurality of main lower electrode layers may gradually increase toward the dielectric layer 140.

[0056] In one example embodiment, the lower electrode LE15 may further include a lower interface electrode layer between the third lower electrode layer L3 and the dielectric layer 140. For example, the lower interface electrode layer may have the same characteristics as the reference layer. FIG. 3 The configuration of the lower interface electrode layer 136 described is the same.

[0057] FIG. 6 This is a cross-sectional view of the main configuration of an integrated circuit device 100F according to an example embodiment. FIG. 6 In, with FIG. 1 The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0058] Reference FIG. 6 The integrated circuit device 100F includes a capacitor C16. The capacitor C16 has a... FIG. 2 The capacitor C12 of the integrated circuit device 100B shown has a similar configuration. The capacitor C16 includes a lower electrode LE16, an upper electrode UE11, and a dielectric layer 140 between the lower electrode LE16 and the upper electrode UE11. The lower electrode LE16 includes a main lower electrode layer 132 and a multi-interface electrode layer MIL. The multi-interface electrode layer MIL may be located between the main lower electrode layer 132 and the dielectric layer 140.

[0059] The multi-interface electrode layer (MIL) may include a first lower interface electrode layer 134A and a second lower interface electrode layer 134B sequentially stacked on the main lower electrode layer 132. The bottom surface of the first lower interface electrode layer 134A may contact the top surface of the main lower electrode layer 132, and the top surface of the second lower interface electrode layer 134B may contact the bottom surface of the dielectric layer 140.

[0060] Each of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B may include a Ti-doped NbO layer or a Ti-doped NbON layer. The Nb atom to Ti atom content ratio can vary in each of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B. The Ti atom to Nb atom content ratio in each of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B can range from about 9:1 to about 1:99. For example, the Nb atom to Ti atom content ratio in the second lower interface electrode layer 134B can be greater than the Nb atom to Ti atom content ratio in the first lower interface electrode layer 134A.

[0061] At least one of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B may include an additional dopant formed of at least one of Co, Sn, V, Ta, Db, P, As, Sb, and Bi. In each of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B, the atomic ratio of the additional dopant to Nb atoms may be from about 0.01 to about 0.15.

[0062] The total thickness TH6 of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B can be approximately [missing information]. to approximately Each of the first lower interface electrode layer 134A and the second lower interface electrode layer 134B may have a reference... FIG. 2 The configuration of the lower interface electrode layer 134 described is the same.

[0063] exist FIG. 6 The diagram illustrates a case where the multi-interface electrode layer (MIL) includes a first lower interface electrode layer 134A and a second lower interface electrode layer 134B. In an example embodiment, the MIL may include three or more lower interface electrode layers with different Nb atomic content ratios. The Nb atomic content ratio in each of the plurality of lower interface electrode layers constituting the MIL may gradually increase toward the dielectric layer 140.

[0064] FIG. 7 This is a schematic planar layout illustrating an integrated circuit device 200 according to an example embodiment. FIG. 7 The image shows a partial planar layout of the memory cell array region of the integrated circuit device 200.

[0065] Reference FIG. 7The integrated circuit device 200 may include a plurality of active regions ACT, which are arranged to extend in a plane at an angle relative to the X and Y directions. A plurality of word lines WL may extend parallel in the X direction to intersect the plurality of active regions ACT. On the plurality of word lines WL, a plurality of bit lines BL may extend parallel in the Y direction intersecting the X direction. The plurality of bit lines BL may be connected to the active regions ACT via direct contact DC.

[0066] Multiple buried contacts BC can be formed between two adjacent bit lines BL. Multiple conductive landing pads LP can be formed on the multiple buried contacts BC. The multiple conductive landing pads LP can be arranged such that they at least partially overlap with the multiple buried contacts BC. A lower electrode LE can be formed on the multiple conductive landing pads LP. The lower electrode LE can be connected to the multiple active regions ACT through the multiple buried contacts BC and the multiple conductive landing pads LP.

[0067] FIG. 8A This is a cross-sectional view of an integrated circuit device 200A according to an example embodiment. FIG. 8B yes FIG. 8A A magnified cross-sectional view of the local region Q1. FIG. 8A and FIG. 8B In, with FIG. 1 The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0068] Reference FIG. 8A and FIG. 8B The integrated circuit device 200A can constitute FIG. 7 A portion of the integrated circuit device 200 shown. FIG. 8A and FIG. 8B In this design, some components of the integrated circuit device 200A are omitted or simplified. However, it will be understood that the configuration of the integrated circuit device 200A is not limited to... FIG. 8A and FIG. 8B The configuration shown includes the feature configurations described below.

[0069] Integrated circuit device 200A includes a substrate 102 containing the plurality of active regions ACT and a lower structure 220 formed on the substrate 102. In the substrate 102, the plurality of active regions ACT may be defined by a plurality of isolation layers 112. Conductive regions 224 may be connected to the plurality of active regions ACT through the lower structure 220.

[0070] Each of the plurality of isolation layers 112 may include an oxide layer, a nitride layer, or a combination thereof. The lower structure 220 may include an insulating layer comprising a silicon oxide layer, a silicon nitride layer, or a combination thereof. In other example embodiments, the lower structure 220 may include various conductive regions (e.g., wiring layers, contact plugs, transistors) and insulating layers for insulating the wiring layers, contact plugs, and transistors from each other. The conductive regions 224 may be formed of polysilicon, metal, conductive metal nitrides, metal silicides, or a combination of polysilicon, metal, conductive metal nitrides, and metal silicides. The lower structure 220 may include references. FIG. 7 The described multiple bit lines BL. Conductive region 224 may include references. FIG. 7 The buried contact BC and the conductive drop pad LP are described.

[0071] An insulating pattern 226P having multiple openings 226H can be arranged on the lower structure 220 and the conductive region 224. The insulating pattern 226P can be formed of silicon nitride, silicon oxide nitride, or a combination of silicon nitride and silicon oxide nitride.

[0072] A capacitor C21 may be disposed on the conductive region 224. The capacitor C21 includes a lower electrode LE21, an upper electrode UE21, and a dielectric layer 240 between the lower electrode LE21 and the upper electrode UE21. The lower electrode LE21 may include a main lower electrode layer 230. The main lower electrode layer 230 may extend longitudinally from the top surface of the conductive region 224 in a vertical direction (Z direction) away from the substrate 102 through an opening 226H in the insulating pattern 226P, and may be cylindrical or cup-shaped to confine an internal space in which the bottom facing the substrate 102 is blocked. The dielectric layer 240 may conformally cover the outer surface of the main lower electrode layer 230 and the inner surface of the internal space of the main lower electrode layer 230. The upper electrode UE21 may include an upper electrode layer 250. The upper electrode layer 250 may include a portion of the dielectric layer 240 that fills the internal space of the main lower electrode layer 230 and a portion of the dielectric layer 240 that faces the outer surface of the lower electrode LE21 and is therebetween.

[0073] Detailed configuration and reference of the lower electrode layer 230, dielectric layer 240 and upper electrode layer 250 FIG. 1 The detailed configurations of the main lower electrode layer 130, dielectric layer 140, and upper electrode layer 150 are the same.

[0074] FIG. 9A This is a cross-sectional view of an integrated circuit device 200B according to an example embodiment. FIG. 9B yes FIG. 9A A magnified cross-sectional view of the local region Q2. FIG. 9A and FIG. 9B In, with FIG. 1 ,FIG. 8A and FIG. 8B The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0075] Reference FIG. 9A and FIG. 9B The integrated circuit device 200B can constitute FIG. 7 A portion of the integrated circuit device 200 shown. FIG. 9A and FIG. 9B In this design, some components of the integrated circuit device 200B are omitted or simplified. However, it will be understood that the configuration of the integrated circuit device 200B is not limited to... FIG. 9A and FIG. 9B The configuration shown includes the feature configurations described below.

[0076] Integrated circuit device 200B has the same characteristics as the reference. FIG. 3 and FIG. 12 The integrated circuit device 200A described has a similar configuration. Integrated circuit device 200B includes a capacitor C22 disposed on a conductive region 224. The capacitor C22 includes a lower electrode LE22, an upper electrode UE22, and a dielectric layer 240 between the lower electrode LE22 and the upper electrode UE22.

[0077] The lower electrode LE22 includes a main lower electrode layer 232 and a lower interface electrode layer 234. (Image...) FIG. 12 and FIG. 8A Similar to the main lower electrode layer 230 shown, the main lower electrode layer 232 can be cylindrical or cup-shaped. The lower interface electrode layer 234 can conformally cover the outer surface of the main lower electrode layer 232 and the inner surface of the internal space of the main lower electrode layer 232. The dielectric layer 240 can conformally cover the outer surface of the lower electrode LE22 and the inner surface of the internal space of the lower electrode LE22. The dielectric layer 240 can be spaced apart from the main lower electrode layer 232, with the lower interface electrode layer 234 therebetween. The upper electrode UE22 may include an upper electrode layer 250.

[0078] Detailed configuration and reference of the main lower electrode layer 232 and the lower interface electrode layer 234 FIG. 12 The detailed configurations of the main lower electrode layer 132 and the lower interface electrode layer 134 are the same.

[0079] FIG. 8A This is a cross-sectional view of a portion of an integrated circuit device 200C according to an example embodiment. FIG. 8B In the middle, it is shown that... FIG. 12 The part corresponding to the local region Q1. FIG. 8A In, with FIG. 8B and FIG. 8A The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0080] Reference FIG. 8B The integrated circuit device 200C has the same characteristics as the reference device. FIG. 2 and FIG. 3 The integrated circuit device 200A described has a similar configuration. Integrated circuit device 200C includes a capacitor C23 disposed on a conductive region 224. The capacitor C23 includes a lower electrode LE23, an upper electrode UE23, and a dielectric layer 240 between the lower electrode LE23 and the upper electrode UE23.

[0081] The lower electrode LE23 includes a main lower electrode layer 230 and a lower interface electrode layer 236. The upper electrode UE23 includes an upper electrode layer 250 and an upper interface electrode layer 238. The lower interface electrode layer 236 is located between the main lower electrode layer 230 and the dielectric layer 240. The upper interface electrode layer 238 is located between the dielectric layer 240 and the upper electrode layer 250.

[0082] The lower interface electrode layer 236 conformally covers the outer surface of the main lower electrode layer 230 and the inner surface of the internal space of the main lower electrode layer 230. The dielectric layer 240 conformally covers the outer surface of the lower electrode LE23 and the inner surface of the internal space of the lower electrode LE23. The dielectric layer 240 may be spaced apart from the main lower electrode layer 230, with the lower interface electrode layer 236 therebetween. The upper interface electrode layer 238 may conformally cover the outer surface of the lower electrode LE23 and the inner surface of the internal space of the lower electrode LE23 on the dielectric layer 240. In an example embodiment, the upper interface electrode layer 238 may be omitted in the capacitor C23. In this case, the dielectric layer 240 may contact the upper electrode layer 250.

[0083] Detailed configuration and reference of the lower interface electrode layer 236 and the upper interface electrode layer 238 FIG. 13 The detailed configurations of the lower interface electrode layer 136 and the upper interface electrode layer 138 are the same.

[0084] FIG. 13 This is a cross-sectional view of a portion of an integrated circuit device 200D according to an example embodiment. FIG. 8A In the middle, it is shown that... FIG. 8B The part corresponding to the local region Q2. FIG. 13 In, with FIG. 8A and FIG. 8B The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0085] Reference FIG. 1 The integrated circuit device 200D has the same characteristics as the reference. FIG. 14 and FIG. 14The integrated circuit device 200B described has a similar configuration. Integrated circuit device 200D includes a capacitor C24 disposed on a conductive region 224. The capacitor C24 includes a lower electrode LE24, an upper electrode UE24, and a dielectric layer 240 between the lower electrode LE24 and the upper electrode UE24.

[0086] The lower electrode LE24 can have the same characteristics as... FIG. 9A and FIG. 9B The configuration of the lower electrode LE22 shown is the same. The upper electrode UE24 includes an upper electrode layer 250 and an upper interface electrode layer 238. The upper interface electrode layer 238 may be located between the dielectric layer 240 and the upper electrode layer 250. The upper interface electrode layer 238 may conformally cover the outer surface of the lower electrode LE24 and the inner surface of the internal space of the lower electrode LE24 on the dielectric layer 240. In an example embodiment, the upper interface electrode layer 238 may be omitted in the capacitor C24. In this case, the dielectric layer 240 may contact the upper electrode layer 250. Detailed configuration of the upper interface electrode layer 238 is shown in the reference. FIG. 14 The configuration of the upper interface electrode layer 138 described is the same.

[0087] FIG. 9A This is a cross-sectional view of a portion of an integrated circuit device 300 according to an example embodiment. FIG. 9B In the middle, it is shown that... FIG. 2 The part corresponding to the local region Q1. FIG. 1 to FIG. 14 In, with FIG. 15 and FIG. 15 The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0088] Reference FIG. 1 The integrated circuit device 300 has the same characteristics as the reference. FIG. 2 and FIG. 15 The integrated circuit device 200A described has a similar configuration. Integrated circuit device 300 includes a capacitor C25 disposed on a conductive region 224. The capacitor C25 includes a lower electrode LE3, an upper electrode UE3, and a dielectric layer 240 between the lower electrode LE3 and the upper electrode UE3.

[0089] The lower electrode LE3 includes a main lower electrode layer 330 and a lower interface electrode layer 334. The upper electrode UE3 includes an upper electrode layer 250. The main lower electrode layer 330 may have the same characteristics as the reference electrode. FIG. 15 and FIG. 16A to FIG. 16IThe configuration of the main lower electrode layer 230 described is the same. In the main lower electrode layer 330, a step ST may be formed on the outer wall adjacent to the opening 226H of the insulating pattern 226P. In the main lower electrode layer 330, the portion filling the opening 226H of the insulating pattern 226P may have a first width W3 in the horizontal direction (e.g., in the X direction). The horizontal width of the portion of the main lower electrode layer 330 above the step ST may be less than the first width W3. That is, in the main lower electrode layer 330, the first width W3 in the horizontal direction of the portion at a level lower than the step ST may be greater than the width of the portion at a level higher than the step ST.

[0090] The lower interface electrode layer 334 may be located between the main lower electrode layer 330 and the dielectric layer 240. The lowest surface of the lower interface electrode layer 334 may be horizontally higher than the lowest surface of the main lower electrode layer 330. In this specification, the term "horizontal" refers to the distance from the substrate 102 in the vertical direction (Z-direction or -Z-direction). The outermost lower portion 334T of the lower interface electrode layer 334 may contact the step ST of the main lower electrode layer 330. The outermost lower portion 334T of the lower interface electrode layer 334 may be closer to the horizontal center of the main lower electrode layer 330 than the inner wall of the opening 226H of the insulating pattern 226P. The lower interface electrode layer 334 may include a Ti-doped NbO layer or a Ti-doped NbON layer. Detailed configuration and reference of the lower interface electrode layer 334 are provided. FIG. 16A to FIG. 16I The lower interface electrode layer 134 described or referenced FIG. 8A The detailed configuration of the lower interface electrode layer 136 described is the same.

[0091] The dielectric layer 240 can conformally cover the outer surface of the lower electrode LE3 and the inner surface of the internal space of the lower electrode LE3 on the lower interface electrode layer 334. The upper electrode UE3 may include the upper electrode layer 250.

[0092] FIG. 8B This is a cross-sectional view of an integrated circuit device 400A according to an example embodiment. (Refer to...) FIG. 16A ,and FIG. 16B and FIG. 16C The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0093] Reference FIG. 16D The integrated circuit device 400A has the same characteristics as the reference. FIG. 16C and FIG. 16E The integrated circuit device 200A described has a similar configuration. Integrated circuit device 400A includes a capacitor C41 disposed on a conductive region 224. The capacitor C41 includes a lower electrode LE41, an upper electrode UE41, and a dielectric layer 240 between the lower electrode LE41 and the upper electrode UE41.

[0094] The lower electrode LE41 may include a main lower electrode layer 430. The main lower electrode layer 430 may be cylindrical and extend longitudinally in a vertical direction (Z direction) away from the top surface of the conductive region 224 through an opening 226H passing through the insulating pattern 226P. The dielectric layer 240 may conformally cover the outer surface of the main lower electrode layer 430. The upper electrode UE41 may include an upper electrode layer 250. Detailed configuration and reference of the main lower electrode layer 430 are provided. FIG. 16D The detailed configuration of the main lower electrode layer 130 is the same as described.

[0095] FIG. 1 This is a cross-sectional view of an integrated circuit device 400B according to an example embodiment. FIG. 16F In, with FIG. 16E and FIG. 16E The same reference numerals in the accompanying drawings denote the same components, and their detailed descriptions are omitted.

[0096] Reference FIG. 16G The integrated circuit device 400B has the same characteristics as the reference. FIG. 16F and FIG. 16H The integrated circuit device 200B described has a similar configuration. Integrated circuit device 400B includes a capacitor C42 disposed on a conductive region 224. The capacitor C42 includes a lower electrode LE42, an upper electrode UE42, and a dielectric layer 240 between the lower electrode LE42 and the upper electrode UE42.

[0097] The lower electrode LE42 includes a main lower electrode layer 432 and a lower interface electrode layer 434. The main lower electrode layer 432 may be cylindrical and extend longitudinally in a vertical direction (Z direction) away from the top surface of the conductive region 224 through an opening 226H passing through the insulating pattern 226P. Detailed configuration of the main lower electrode layer 432 and the lower interface electrode layer 434 is shown in the reference. FIG. 16I The detailed configurations of the main lower electrode layer 132 and the lower interface electrode layer 134 are the same.

[0098] The dielectric layer 240 may conformally cover the outer surface of the main lower electrode layer 432 on the lower interface electrode layer 434. The upper electrode UE42 may include an upper electrode layer 250.

[0099] Reference FIG. 17A to FIG. 17E Each described integrated circuit device includes a Ti-doped Nb-containing layer in the portion of the lower electrode of the capacitor adjacent to at least the dielectric layer. Therefore, the formation of a depletion layer due to undesirable oxidation of the lower electrode can be prevented at the interface between the lower electrode and the dielectric layer, thus minimizing the difference between the minimum capacitance Cmin and the maximum capacitance Cmax and increasing the capacitance.

[0100] FIG. 17A to FIG. 17E This is a graph showing the results obtained by evaluating the capacitance of the capacitor of an integrated circuit device according to an exemplary embodiment, together with a comparative example.

[0101] for FIG. 9A The evaluation prepared Example 1, Example 2, and a reference example. Example 1 (with...) FIG. 9B In the capacitor shown in Example 2, the main lower electrode layer 130 includes a Ti-doped NbN layer, the dielectric layer 140 includes a multilayer dielectric layer in which ZrO2 layers and Al2O3 layers are stacked, and the upper electrode layer 150 includes a TiN layer. FIG. 17A In the capacitor shown, the main lower electrode layer 132 comprises a TiN layer, the lower interface electrode layer 134 comprises a Ti-doped NbO layer, and each of the dielectric layer 140 and the upper electrode layer 150 has the same structure as in Example 1. The reference example is the same as Example 1 except that it has a capacitor in which the lower electrode is a TiN monolayer.

[0102] exist FIG. 16A to FIG. 16G In the evaluation results, the Cmin values ​​of the capacitors in Examples 1 and 2 increased compared to the capacitor in the reference example. From... FIG. 9A The results show that in the capacitors of Examples 1 and 2, the portion of the lower electrode adjacent to at least the dielectric layer contains an Nb-containing layer doped with Ti. Therefore, almost no depletion layer is formed at the interface between the lower electrode and the dielectric layer, resulting in an increase in the Cmin value. Thus, in the capacitors of Examples 1 and 2, the capacitance is improved compared to the capacitor of the reference example.

[0103] A method for manufacturing an integrated circuit device according to an example embodiment will now be described in detail.

[0104] FIG. 9B This is a cross-sectional view illustrating the process of manufacturing an integrated circuit device according to an example embodiment. (Refer to...) FIG. 17B describe FIG. 17A and FIG. 17A An example manufacturing method for the integrated circuit device 200A shown.

[0105] Reference FIG. 16E A lower structure 220 and a conductive region 224 connected to the active region ACT through the lower structure 220 are formed on a substrate 102 defined by an isolation layer 112. Then, an insulating layer 226 is formed covering the lower structure 220 and the conductive region 224.

[0106] The insulating layer 226 may be formed of an insulating material that has etch selectivity relative to the underlying structure 220. The insulating layer 226 may be formed of silicon nitride, silicon oxide, or a combination of silicon nitride and silicon oxide.

[0107] Reference FIG. 16E A molding layer 228 is formed on the insulating layer 226.

[0108] The molding layer 228 may be formed of an insulating material that has etch selectivity relative to the insulating layer 226. In some embodiments, the molding layer 228 may include an oxide layer, such as a borosilicate glass (BPSG) layer.

[0109] Reference FIG. 17B A sacrificial layer SL and a mask pattern MP are sequentially formed on the molding layer 228.

[0110] The sacrificial layer SL may include an oxide layer. The mask pattern MP may include a nitride layer, an oxide layer, a polysilicon layer, a photoresist layer, or a combination of the above layers.

[0111] Reference FIG. 17A ,exist FIG. 17C In the resulting structure, the sacrificial layer SL, molding layer 228, and insulating layer 226 are anisotropically etched using a mask pattern MP as an etching mask and an insulating layer 226 as an etch stop layer, thus forming the sacrificial pattern SLP, molding pattern 228P, and insulating pattern 226P that confine the via BH. The opening 226H of the exposed conductive region 224 can be formed in the insulating pattern 226P.

[0112] Reference FIG. 17C From FIG. 17D After removing the mask pattern MP from the obtained structure, an initial lower electrode layer 230L is formed, covering the surfaces of the conductive region 224 inside the hole BH, the surfaces of the insulating pattern 226P inside the hole BH, the surfaces of the molded pattern 228P inside the hole BH, and the surfaces of the sacrificial pattern SLP inside the hole BH, as well as the top surface of the sacrificial pattern SLP. The initial lower electrode layer 230L can conformally cover the top surface of the conductive region 224 exposed through the hole BH and the sidewalls of the molded pattern 228P exposed through the hole BH. After forming the initial lower electrode layer 230L, a portion of the hole BH can remain empty.

[0113] Material and reference of the initial lower electrode layer 230L FIG. 16H The material of the main lower electrode layer 130 is the same as described. To form the initial lower electrode layer 230L, an atomic layer deposition (ALD) process can be used.

[0114] When the initial lower electrode layer 230L includes a Ti-doped NbN layer, in the example ALD process for forming the initial lower electrode layer 230L, after the substrate 102 is loaded into the reaction chamber, an ALD cell cycle including processes for supplying reactive materials to the conductive regions 224, the molded pattern 228P, and the surface exposed by the through-hole BH of the sacrificial pattern SLP on the substrate 102 can be performed multiple times until the initial lower electrode layer 230L is obtained. The ALD unit cycle may include: a first process of forming an Nb chemisorption layer by supplying an Nb precursor to an exposed surface; a second process of removing unwanted Nb precursor remaining on the substrate 102 and discharging the removed Nb precursor to the outside of the reaction chamber; a third process of forming a Ti dopant chemisorption layer on a portion of the exposed surface on the substrate 102 where an Nb chemisorption layer is not formed by supplying a Ti dopant precursor to the structure in which the Nb chemisorption layer is formed; a fourth process of removing unwanted Ti dopant precursor and discharging the removed Ti dopant precursor to the outside of the reaction chamber; a fifth process of forming a Ti-doped NbN layer by supplying a nitrogen-containing reaction gas to the structure in which the Nb chemisorption layer and the Ti dopant chemisorption layer are formed; and a sixth process of removing unwanted portions of the nitrogen-containing reaction gas and discharging the removed portions to the outside of the reaction chamber.

[0115] In one example embodiment, the Nb precursor may be formed from a compound with the chemical formula Nb(NRR')5, a compound with the chemical formula (NRR')3Nb=NR", or a combination of the above compounds. In the above chemical formulas, each of R, R', and R" is H, C1 to C10 alkyl, alkenyl, cycloalkyl, cycloalkenyl, or aryl. Other Nb precursors may also be used.

[0116] In one example embodiment, the Ti dopant precursor may be formed from tetraisopropoxytitanium (Ti(O-iProp)4), titanium halide, cyclopentadienyltitanium, diisopropoxybis(2,2,6,6-tetramethyl-3,5-heptanedionate)titanium (Ti(O-iProp)2(thd)2), bis(4-(2-methylethoxy)imino-2-valerate)titanium (Ti(2meip)2), bis[4-(ethoxy)imino-2-valerate]titanium (Ti(eip)2), bis[2,2-dimethyl-5-(2-methylethoxy)imino-3-heptanoate]titanium (Ti(22dm2meih)2) or a combination of the above compounds.

[0117] To perform the purging, an inert gas (such as Ar, He, or Ne) or N2 gas can be used. The reaction gas containing nitrogen atoms can be formed from NH3, N2H4, hydrazine derivatives, or combinations thereof. The hydrazine derivatives can be C1 to C10 alkylhydrazines, C1 to C10 dialkylhydrazines, or combinations thereof.

[0118] When the initial lower electrode layer 230L includes an NbN layer containing multiple dopants (including Ti), the aforementioned ALD cell cycle can be performed multiple times in the example ALD process for forming the initial lower electrode layer 230L. After performing the fourth process in the aforementioned ALD cell cycle and before performing the fifth process, a seventh process can be performed, which involves supplying at least one of Co precursor, Sn precursor, V precursor, Ta precursor, Db precursor, P precursor, As precursor, Sb precursor, and Bi precursor, and an eighth process can be performed, which involves removing unwanted portions of the precursor supplied in the seventh process and discharging the removed portions to the outside of the reaction chamber.

[0119] Reference FIG. 17E , through from FIG. 16I The resulting structure partially removes the top portion of the initial lower electrode layer 230L, forming the main lower electrode layer 230 from the initial lower electrode layer 230L. The main lower electrode layer 230 can constitute the lower electrode LE21.

[0120] To form the main lower electrode layer 230 until the top surface of the molded pattern 228P is exposed, a portion of the initial lower electrode layer 230L and the sacrificial pattern SLP (see reference) can be removed using an etch-back or chemical mechanical polishing (CMP) process. FIG. 10 ).

[0121] Reference FIG. 11 , through from FIG. 16A to FIG. 16I The resulting structure removes the molded pattern 228P, exposing the outer surface of the cylindrical lower electrode LE21.

[0122] Reference FIG. 17A to FIG. 17E A dielectric layer 240 is formed on the lower electrode LE21.

[0123] The dielectric layer 240 can conformally cover the exposed surface of the lower electrode LE21. The dielectric layer 240 can be formed by an ALD process.

[0124] Reference FIG. 10 The upper electrode UE21 is formed by forming an upper electrode layer 250 on the dielectric layer 240. To form the upper electrode layer 250, a chemical vapor deposition (CVD) process, a metal-organic CVD (MOCVD) process, or an ALD process can be used. The capacitor C21 can be composed of a lower electrode LE21, a dielectric layer 240, and an upper electrode UE21.

[0125] FIG. 16A to FIG. 16G This is a cross-sectional view illustrating the process of manufacturing an integrated circuit device according to an example embodiment. (Refer to...) FIG. 17B describe FIG. 17C and FIG. 16H An example manufacturing method for the integrated circuit device 200B shown.

[0126] Reference FIG. 17B , execution and reference FIG. 11 The process described is similar to that described. In the current example, instead of forming a main lower electrode layer 230, a main lower electrode layer 232 is formed on the conductive region 224.

[0127] Material and reference of the main lower electrode layer 232 FIG. 17A to FIG. 17D and FIG. 17B The description is the same. To form the main lower electrode layer 232, CVD, MOCVD, or ALD processes can be used.

[0128] Reference FIG. 18A ,exist FIG. 18B On the obtained structure, a lower interface electrode layer 234 is formed.

[0129] In one example implementation, in order to form the lower interface electrode layer 234, firstly, it is possible to... FIG. 18A An initial lower interface electrode layer is formed on the resulting structure, which conformally covers the exposed surface of the main lower electrode layer 232 and the exposed surface of the insulating pattern 226P. The initial lower interface electrode layer may include an NbO layer or an NbON layer. An ALD process can be used to form the initial lower interface electrode layer. Then, with the initial lower interface electrode layer covering the main lower electrode layer 232, a heat treatment can be performed on the resulting structure in which the initial lower interface electrode layer is formed. This heat treatment can be performed at a temperature in the range of about 500°C to about 1150°C. When the main lower electrode layer 232 is formed of TiN, Ti atoms in the main lower electrode layer 232 can diffuse into the initial lower interface electrode layer during the heat treatment. As a result, the NbO layer or NbON layer constituting the initial lower interface electrode layer is doped with Ti atoms, thus obtaining a lower interface electrode layer 234 formed of a Ti-doped NbO layer or a Ti-doped NbON layer.

[0130] In other example embodiments, to form the lower interface electrode layer 234, a Ti-doped NbO layer or a Ti-doped NbON layer can be formed using an ALD process. In this case, to form the Ti-doped NbO layer or the Ti-doped NbON layer, an ALD cell cycle including a process for supplying reactive materials can be performed multiple times. The ALD cell cycle can be similar to the one described above. FIG. 18BThe described ALD cell cycle includes processes one through six. In the fifth process, instead of a reaction gas containing nitrogen atoms, a reaction gas containing oxygen atoms, nitrogen atoms, or a combination of the above atoms, or a mixture of a reaction gas containing oxygen atoms and a reaction gas containing nitrogen atoms, is supplied. In the sixth process, after performing the fifth process, unwanted material remaining on the substrate is removed, and the removed material can be discharged to the outside of the reaction chamber. The reaction gas containing oxygen atoms can be formed from O2, O3, H2O, NO, NO2, N2O, CO2, H2O2, HCOOH, CH3COOH, (CH3CO)2O, plasma O2, remote plasma O2, plasma N2O, plasma H2O, or a combination of the above compounds. Examples and references for reaction gases containing nitrogen atoms are provided. FIG. 12 The description is the same. The reactive gas containing oxygen and nitrogen atoms can be formed from NO, NO2, N2O, plasma N2O, or a combination of these compounds.

[0131] exist FIG. 18A The image shows that the initial lower interface electrode layer 234A is completely formed on the surface. FIG. 18B The resulting structure is exposed on the surface. In another example embodiment, the initial lower interface electrode layer 234A can be formed only on the exposed surface of the main lower electrode layer 232 by using a selective ALD process. See also FIG. 8A By removing a portion of the initial lower interface electrode layer 234A, only the portion covering the surface of the main lower electrode layer 232 remains in the initial lower interface electrode layer 234A, thereby forming the lower interface electrode layer 234. After removing a portion of the initial lower interface electrode layer 234A, the top surface of the insulating pattern 226P can be exposed. When multiple main lower electrode layers 232 are formed on the substrate 102, such as FIG. 18A As shown, after removing a portion of the initial lower interface electrode layer 234A, the lower interface electrode layer 234 can be divided into multiple portions that respectively cover the plurality of main lower electrode layers 232. The main lower electrode layers 232 and the lower interface electrode layer 234 remaining on the main lower electrode layers 232 can constitute the lower electrode LE22.

[0132] Reference FIG. 16A to FIG. 16G By referring to FIG. 18B A similar method is used to form a dielectric layer 240 on the lower electrode LE22.

[0133] Reference FIG. 16H By referring to FIG. 12 Using the same method described, an upper electrode layer 250 is formed on the dielectric layer 240, thus forming an upper electrode UE22. The capacitor C22 may be composed of a lower electrode LE22, the dielectric layer 240, and the upper electrode UE22.

[0134] In order to manufacture FIG. 13 and FIG. 16A to FIG. 16I The integrated circuit devices 200C and 200D shown can be used with reference to FIG. 16E to FIG. 16G The methods described, references FIG. 16H The method described or the method obtained by combining the above methods.

[0135] In one example implementation, in order to manufacture FIG. 16I The integrated circuit device 200C shown is executed by reference. FIG. 14 The described process allows for the formation of a main lower electrode layer 230 on the conductive region 224. Then, by referring to... FIG. 17A to FIG. 17E and FIG. 17A A method similar to the described method (which includes the process of forming the lower interface electrode layer 234) can be used to form the lower interface electrode layer 236 on the exposed surface of the main lower electrode layer 230. Then, by referring to... FIG. 17B to FIG. 17E A method similar to the one described can be used to form a dielectric layer 240 on the lower interface electrode layer 236. Then, by referring to... FIG. 8A to FIG. 14 The method described (which includes the process of forming the lower interface electrode layer 234) is similar to the method in which an upper interface electrode layer 238 is formed on the dielectric layer 240, and an upper electrode layer 250 is formed on the upper interface electrode layer 238, thereby forming an upper electrode UE23.

[0136] In one example implementation, in order to manufacture FIG. 16A to FIG. 18B The integrated circuit device 200D shown is executed in accordance with the reference. FIG. 1 to FIG. 6 A process similar to the described process can be used to form a lower electrode LE24, including a main lower electrode layer 232 and a lower interface electrode layer 234, and a dielectric layer 240 on the conductive region 224. Then, by referring to... FIG. 16A to FIG. 18B The method described (which includes the process of forming the initial lower interface electrode layer 234A) is similar to the method in which an upper interface electrode layer 238 is formed on the dielectric layer 240, and an upper electrode layer 250 is formed on the upper interface electrode layer 238, thereby forming the upper electrode UE24.

[0137] FIG. 16A to FIG. 18B and FIG. 5 This is a cross-sectional view illustrating the process of manufacturing an integrated circuit device according to an example embodiment. (Refer to...) FIG. 16E and FIG. 6 describe FIG. 17B An example manufacturing method of the integrated circuit device 300 shown. ​ and ​ In the middle, it is shown that... ​ The cross-sectional configuration of the part corresponding to Q1 according to the process sequence.

[0138] Reference ​ By referring to ​ The described method (which includes a process for forming the primary lower electrode layer 230) is similar to the method used to form an initial primary lower electrode layer P330 on the conductive region 224. In one example embodiment, the initial primary lower electrode layer P330 may comprise a Ti-doped NbN layer.

[0139] Reference ​ By referring to ​ A similar method is described, in which a dielectric layer 240 is formed on the exposed surfaces of the initial main lower electrode layer P330 and the exposed surfaces of the insulating pattern 226P. In one example embodiment, the dielectric layer 240 may be formed of a metal oxide layer. In the current example, after at least a portion of the dielectric layer 240 is formed, oxygen atoms in the dielectric layer 240 may diffuse into the initial main lower electrode layer P330. In one example, oxygen atoms in the dielectric layer 240 may diffuse into the initial main lower electrode layer P330 simultaneously with the formation of the dielectric layer 240 due to the process temperature during the formation of the dielectric layer 240. In another example, after the formation of the dielectric layer 240, an additional heat treatment is performed, so that oxygen atoms in the dielectric layer 240 may diffuse into the initial main lower electrode layer P330. The heat treatment may be performed at a temperature in the range of about 500°C to about 1150°C. As a result, in the initial main lower electrode layer P330, the region adjacent to the dielectric layer 240 can be changed to a lower interface electrode layer 334 comprising oxygen atoms. In an example embodiment, the main lower electrode layer 330 comprises a Ti-doped NbN layer, and the lower interface electrode layer 334 can be formed from a Ti-doped NbON layer. In the initial main lower electrode layer P330, the portion other than that changed to the lower interface electrode layer 334 can remain as the main lower electrode layer 330. The main lower electrode layer 330 and the lower interface electrode layer 334 can constitute the lower electrode LE3.

[0140] Then, an upper electrode UE3 formed by the upper electrode layer 250 is formed on the dielectric layer 240, thus enabling the fabrication of... ​ The integrated circuit device 300 shown is shown.

[0141] In order to manufacture ​ The integrated circuit device 400A shown can be used with reference. ​ The method described. (Refer to...) ​ In the described process, a cylindrical main lower electrode layer 430 can be formed instead of the main lower electrode layer 230. Then, a reference process can be performed. ​ and ​ The described process.

[0142] In order to manufacture ​The integrated circuit device 400B shown can be used with reference to ​ The method described. (Refer to...) ​ In the described process, a cylindrical main lower electrode layer 432 can be formed instead of the main lower electrode layer 232. Then, a reference process can be performed. ​ The described process.

[0143] manufacture ​ The methods for the integrated circuit devices 200A, 200B, 200C, 200D, 300, 400A, and 400B shown are as follows: ​ As described, but it will be apparent to those skilled in the art that integrated circuit devices of various structures can be manufactured through various modifications thereof. For example, in order to manufacture ​ The integrated circuit devices 100A, 100B, 100C, 100D, 100E, and 100F shown can be used with reference to ​ The described method or by combining references ​ The method described is the method obtained. Specifically, in order to form ​ The lower electrode LE15 of the integrated circuit device 100E shown can be used by changing the reference in various ways. ​ The method described is obtained by forming the initial lower electrode layer 230L. Furthermore, in order to form including... ​ The multi-interface electrode layer MIL in the lower electrode LE16 of the integrated circuit device 100F shown can be used by changing the reference in various ways. ​ The method described is obtained by forming the initial lower interface electrode layer 234A.

[0144] As described above, embodiments relate to an integrated circuit device including a capacitor and a method of manufacturing the same. Embodiments may provide an integrated circuit device having a structure in which desired electrical characteristics can be maintained by providing high capacitance. Embodiments may provide a method of manufacturing an integrated circuit device having a structure in which desired electrical characteristics can be maintained by providing high capacitance.

[0145] Exemplary embodiments have been disclosed herein, and although specific terminology is used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some cases, as will be apparent to those skilled in the art up to the time of filing of this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

[0146] Korean Patent Application No. 10-2019-0068801, filed on June 11, 2019 with the Korean Intellectual Property Office and entitled “Integrated Circuit Device and Method of Manufacturing the Same”, is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: The lower electrode includes a niobium (Nb) layer doped with titanium (Ti) in the portion of the lower electrode adjacent to the dielectric layer. The dielectric layer on the lower electrode; as well as The upper electrode covering the dielectric layer.

2. The integrated circuit device according to claim 1, wherein the lower electrode comprises a main lower electrode layer, and the main lower electrode layer comprises a Ti-doped Nb nitride layer.

3. The integrated circuit device according to claim 1, wherein: The lower electrode includes a main lower electrode layer, which comprises an Nb nitride layer containing multiple dopants. The multiple dopants include a first dopant formed from Ti and a second dopant formed from at least one selected from cobalt (Co), tin (Sn), vanadium (V), tantalum (Ta), argon (Db), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).

4. The integrated circuit device according to claim 1, wherein the lower electrode comprises: The main lower electrode layer includes a Ti-doped Nb nitride layer; as well as The lower interface electrode layer between the main lower electrode layer and the dielectric layer includes a Ti-doped Nb oxide layer or a Ti-doped Nb nitride layer.

5. The integrated circuit device according to claim 1, wherein the lower electrode comprises: The main lower electrode layer is spaced apart from the dielectric layer; as well as The lower interface electrode layer between the main lower electrode layer and the dielectric layer includes a Ti-doped Nb oxide layer or a Ti-doped Nb nitride layer.

6. The integrated circuit device according to claim 5, wherein: The main lower electrode layer includes a TiN layer, and The thickness of the lower interface electrode layer is less than the thickness of the main lower electrode layer.

7. The integrated circuit device of claim 5, wherein the upper electrode comprises: The main upper electrode layer is spaced apart from the dielectric layer; as well as An upper interface electrode layer is located between the main upper electrode layer and the dielectric layer, the upper interface electrode layer comprising a Ti-doped Nb oxide layer or a Ti-doped Nb oxynitride layer.

8. The integrated circuit device of claim 1, wherein the lower electrode comprises a plurality of lower electrode layers with different Nb atomic content ratios, the Nb atomic content ratio of the plurality of lower electrode layers being the largest in the lower electrode layer closest to the dielectric layer.

9. The integrated circuit device of claim 1, wherein the lower electrode comprises a plurality of lower electrode layers with different Nb atomic content ratios, provided that the lower electrode layer furthest from the dielectric layer does not contain Nb.

10. The integrated circuit device according to claim 1, wherein: The lower electrode includes: A main lower electrode layer spaced apart from the dielectric layer; and A multi-interface electrode layer includes multiple lower interface electrode layers with different Nb atomic content ratios located between the main lower electrode layer and the dielectric layer. The multi-interface electrode layer includes a Ti-doped Nb oxide layer or a Ti-doped Nb nitride oxide layer, and The Nb atom content in each of the plurality of lower interface electrode layers gradually increases toward the dielectric layer.

11. An integrated circuit device, comprising: The substrate includes the active region; The conductive region on the active region; as well as A capacitor on the conductive region, the capacitor comprising: The lower electrode includes a niobium (Nb) layer doped with titanium (Ti) in the portion of the lower electrode adjacent to the dielectric layer. The dielectric layer formed on the lower electrode; and The upper electrode covering the dielectric layer.

12. The integrated circuit device according to claim 11, wherein: The lower electrode includes a main lower electrode layer, which includes a Ti-doped Nb nitride layer. The dielectric layer includes a metal oxide layer.

13. The integrated circuit device of claim 11, wherein the lower electrode comprises: There is no Nb-containing bottom electrode layer; as well as The lower interface electrode layer includes a Ti-doped Nb oxide layer or a Ti-doped Nb oxynitride layer.

14. The integrated circuit device of claim 11, wherein the lower electrode comprises: A cylindrical main lower electrode layer extends longitudinally in a vertical direction away from the substrate on the conductive region; as well as The lower interface electrode layer includes a Ti-doped Nb oxide layer or a Ti-doped Nb nitride oxide layer, which covers the outer surface of the cylindrical main lower electrode layer and the inner surface of the internal space of the cylindrical main lower electrode layer.

15. The integrated circuit device of claim 11, wherein the lower electrode comprises: A cylindrical main lower electrode layer extends longitudinally in a vertical direction away from the substrate on the conductive region; as well as The lower interface electrode layer includes a Ti-doped Nb oxide layer or a Ti-doped Nb nitride oxide layer, which covers the outer surface of the cylindrical main lower electrode layer.

16. The integrated circuit device of claim 11, wherein the upper electrode comprises: There is no Nb-containing main top electrode layer, which is spaced apart from the dielectric layer; as well as The upper interface electrode layer is located between the main upper electrode layer and the dielectric layer and includes a Ti-doped Nb oxide layer or a Ti-doped Nb nitride layer.

17. The integrated circuit device of claim 11, wherein the lower electrode further comprises at least one additional dopant selected from Co, Sn, V, Ta, Db, P, As, Sb and Bi.

18. An integrated circuit device, comprising: The substrate includes the active region; The conductive region on the active region; as well as A capacitor on the conductive region, the capacitor comprising: The lower electrode includes, in the portion of the lower electrode adjacent to the dielectric layer, at least one selected from a Ti-doped Nb nitride layer, a Ti-doped Nb oxide layer, and a Ti-doped Nb oxynitride layer. The dielectric layer on the lower electrode includes a metal oxide layer; as well as The upper electrode covering the dielectric layer.

19. The integrated circuit device of claim 18, wherein the lower electrode comprises a main lower electrode layer, the main lower electrode layer comprises a Ti-doped Nb nitride layer, and the top surface of the main lower electrode layer contacts the bottom surface of the dielectric layer.

20. The integrated circuit device of claim 18, wherein the lower electrode comprises: The main lower electrode layer is spaced apart from the dielectric layer and includes TiN; as well as A lower interface electrode layer is located between the main lower electrode layer and the dielectric layer. The lower interface electrode layer has a top surface that contacts the dielectric layer and includes a Ti-doped Nb oxide layer or a Ti-doped Nb oxynitride layer.

21. A method for manufacturing an integrated circuit device, the method comprising: A lower electrode is formed, comprising a niobium (Nb)-containing layer doped with titanium (Ti); A dielectric layer is formed on the lower electrode such that the portion of the lower electrode adjacent to the dielectric layer includes the Ti-doped Nb-containing layer; as well as An upper electrode is formed on the dielectric layer.

22. The method of claim 21, wherein forming the lower electrode comprises forming a main lower electrode layer by performing multiple atomic layer deposition unit cycles, the atomic layer deposition unit cycle comprising: A Nb chemisorption layer is formed by supplying the Nb precursor to the substrate; A Ti dopant precursor is supplied to the resulting structure in which the Nb chemisorption layer is formed, and a Ti dopant chemisorption layer is formed on the exposed surface of the substrate in the portion where the Nb chemisorption layer is not formed; and A reactive gas containing nitrogen atoms is supplied to the resulting structure in which the Nb chemisorption layer and the Ti dopant chemisorption layer are formed, and a Ti-doped Nb nitride layer is formed.

23. The method of claim 21, wherein forming the lower electrode comprises: A main lower electrode layer is formed on a substrate, the main lower electrode layer comprising Ti atoms; An initial lower interface electrode layer is formed on the main lower electrode layer, the initial lower interface electrode layer comprising an Nb oxide layer or an Nb oxynitride layer; as well as With the initial lower interface electrode layer covering the main lower electrode layer, Ti atoms are diffused from the main lower electrode layer into the interior of the initial lower interface electrode layer to form a lower interface electrode layer comprising a Ti-doped Nb oxide layer or a Ti-doped Nb nitride oxide layer.

24. The method of claim 21, wherein forming the lower electrode comprises: A main lower electrode layer is formed on a substrate, the main lower electrode layer comprising TiN; An initial lower interface electrode layer is formed on the main lower electrode layer, the initial lower interface electrode layer comprising an Nb oxide layer or an Nb oxynitride layer; as well as By performing heat treatment on the resulting structure in which the main lower electrode layer is covered by the initial lower interface electrode layer, Ti atoms diffuse from the main lower electrode layer into the interior of the initial lower interface electrode layer, a lower interface electrode layer comprising a Ti-doped Nb oxide layer or a Ti-doped Nb nitride layer is formed. During the formation of the dielectric layer, the dielectric layer contacts the lower interface electrode layer.

25. The method of claim 21, wherein forming the lower electrode comprises: A main lower electrode layer is formed on a substrate, the main lower electrode layer comprising TiN; and A lower interface electrode layer is formed on the main lower electrode layer by performing multiple atomic layer deposition unit cycles. The lower interface electrode layer includes the Ti-doped Nb-containing layer. The atomic layer deposition unit cycle includes: A Nb chemisorption layer is formed by supplying the Nb precursor to the substrate; A Ti dopant precursor is supplied to the resulting structure in which the Nb chemisorption layer is formed, and a Ti dopant chemisorption layer is formed on the exposed surface of the substrate in the portion where the Nb chemisorption layer is not formed; and A reactive gas comprising a combination of nitrogen atoms, oxygen atoms, or more atoms is supplied to the resulting structure in which the Nb chemisorption layer and the Ti dopant chemisorption layer are formed, thereby forming a Ti-doped Nb oxide layer or a Ti-doped Nb oxynitride layer.

Images