Cluster parity for NAND data placement patterns

Abstract

In some examples, improvements to data placement architecture in NAND are disclosed that provide additional data protection through an improved NAND data placement pattern that allows recovery from certain failure cases. The present invention stripes data diagonally across page rows and planes to enhance data protection. Parity bits are stored in SLC blocks for additional protection until block writes are complete, and then the parity bits can be deleted.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application Serial No. 62 / 675,451, filed on May 23, 2018, and U.S. Provisional Application Serial No. 62 / 644,282, filed on March 16, 2018, both of which are incorporated herein by reference in their entirety. Background Art

[0003] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory.

[0004] Volatile memory requires power to retain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others.

[0005] Non-volatile memory can retain stored data when power is not supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint TM Memory, etc.

[0006] Flash memory is used as non-volatile memory in various electronic applications. Flash memory devices typically include one or more groups of single transistor, floating gate or charge trap memory cells that allow for high memory density, high reliability and low power consumption.

[0007] Two common types of flash memory array architectures include the NAND and NOR architectures, named after the logical form in which the basic memory cell configuration of each is arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series (source to drain) between a source line and a bit line.

[0008] Both NOR and NAND architecture semiconductor memory arrays are accessed through a decoder that activates a particular memory cell by selecting a word line coupled to the gate of the particular memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell can place its data value on the bit line, causing different currents to flow depending on the state of programming the particular cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain side select gate (SGD) line. The word line coupled to the gates of the unselected memory cells of each group is driven with a specified pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., pass current in a manner that is not limited by their stored data values). Current then flows from the source line to the bit line through each series coupled group limited only by the selected memory cells of each group to place the current encoded data value of the selected memory cell on the bit line.

[0009] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (eg, 1 or 0) to represent one data bit.

[0010] However, flash memory cells can also represent one of more than two programming states, allowing higher density memory to be manufactured without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some examples, MLCs may refer to memory cells that can store two bits of data per cell (e.g., one of four programming states), three-level cells (TLCs) may refer to memory cells that can store three bits of data per cell (e.g., one of eight programming states), and four-level cells (QLCs) may store four bits of data per cell. MLCs are used herein in a broader context, i.e., may refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programming states).

[0011] Conventional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. In order to increase memory capacity within a given area and reduce costs, the size of individual memory cells has been reduced. However, there are technical limitations to the reduction in size of individual memory cells and, therefore, the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures (e.g., 3D NAND architecture semiconductor memory devices) are being developed to further increase memory density and reduce memory costs.

[0012] Such 3D NAND devices typically include a string of memory cells coupled in series (e.g., drain to source) between one or more source-side select gates (SGS) proximate to the source and one or more drain-side select gates (SGD) proximate to the bit line. In an example, the SGS or SGD may include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, etc. In some examples, the string will extend vertically through multiple vertical spacer layers containing corresponding word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to a string of memory cells to form a channel of the memory cells of the string. In the example of a vertical string, the polysilicon structure may be in the form of a vertically extending column. In some examples, the string may be "folded" and therefore arranged relative to a U-shaped column. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.

[0013] Memory arrays or devices may be combined together to form a memory bank of a memory system, such as a solid state drive (SSD), universal flash storage (UFS), or a memory card. TM ) devices, Multimedia Card (MMC) solid-state storage devices, embedded MMC devices (eMMC TM ), etc. SSDs are particularly useful as primary storage devices for computers having advantages over conventional hard drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, an SSD may have reduced seek times, latency, or other delays (e.g., electromechanical, etc.) associated with magnetic disk drives. An SSD uses non-volatile memory cells (e.g., flash memory cells) to eliminate internal battery supply requirements, thereby allowing the drive to be more versatile and compact.

[0014] An SSD may include several memory devices (including several dies or logical units (such as logical unit numbers or LUNs)), and may include one or more processors or other controllers that perform logical functions required to operate the memory devices or interface with external systems. Such an SSD may include one or more flash memory dies, which include several memory arrays and peripheral circuitry thereon. The flash memory arrays may include several blocks of memory cells organized into several physical pages. In many examples, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands associated with memory operations from a host, such as read or write operations to transfer data (such as user data and associated integrity data, such as error data and address data, etc.) between a memory device and a host, or erase operations to erase data from a memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the drawings, which are not necessarily drawn to scale, the same numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in the present invention by way of example and not by way of limitation.

[0016] Figure 1 An example of an environment including a memory device is described.

[0017] Figures 2 to 3 A schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array.

[0018] Figure 4 An example block diagram illustrating a memory module.

[0019] Figure 5 Illustrate the possible effects of NAND programming failure.

[0020] Figure 6 The possible effects of asynchronous power loss during programming of NAND are illustrated.

[0021] Figure 7 and 8 Improved NAND data placement patterns for data on a TLC NAND array according to some examples of the present invention are illustrated.

[0022] Fig. 9 The logical placement of parity pages in a volatile memory or other component of a NAND of a controller according to some examples of the present invention is illustrated.

[0023] Fig.10 Schematic diagram illustrating storage of parity values ​​for storing parity pages in non-volatile NAND.

[0024] Fig.11 Flowchart illustrating a method 1100 of applying an improved NAND data placement pattern to store data on a NAND die of a NAND device according to some examples of the present invention.

[0025] Fig.12 Examples of uncorrectable errors of NAND according to some examples of the present invention are illustrated.

[0026] Fig.13 The storage of a plurality of parity values ​​arranged into a plurality of clusters according to some examples of the present invention is illustrated.

[0027] Fig.14 The storage of a plurality of compressed parity values ​​according to some examples of the present invention is illustrated.

[0028] Fig.15A flow chart illustrating a method of clustering parity values ​​in an improved NAND data placement pattern for NAND devices according to some examples of the present invention.

[0029] Fig.16 A schematic diagram illustrating a memory controller according to some examples of the present invention.

[0030] Fig.17 is a block diagram illustrating an example of a machine upon which one or more embodiments may be implemented. DETAILED DESCRIPTION

[0031] In some examples, methods are disclosed to organize data written to a memory device, such as a NAND memory device, to be protected from certain types of failures. For example, a first portion is programmed on a first page row and a first plane, a second portion is programmed on a second page row and a second plane, a third portion is programmed on a third page row and a third plane, and a fourth portion is programmed on a fourth page row and a fourth plane. The first page row, the second page row, the third page row, the first plane, the second plane, and the third plane are selected so that the first portion, the second portion, and the third portion are stored in memory cells on different page rows and different planes relative to each other.

[0032] Electronic devices such as mobile electronic devices (e.g., smart phones, tablet computers, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected devices or devices (e.g., Internet of Things (IoT) devices, etc.) have different storage requirements that depend, among other things, on the type of electronic device, usage environment, performance expectations, etc.

[0033] An electronic device may be divided into several main components: a processor (e.g., a central processing unit (CPU) or other main processor), a memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices, such as dynamic RAM (DRAM), mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.), and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, read-only memory (ROM), SSD, MMC or other memory card structure or assembly, etc.). In some examples, the electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor, or one or more transceiver circuits, etc.

[0034] Figure 1An example of an environment 100 including a host device 105 and a memory device 110 configured to communicate via a communication interface is described. The host device 105 or the memory device 110 may be included in various products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.) to support processing, communication, or control of the product 150.

[0035] Memory device 110 includes memory controller 115 and memory array 120, which includes, for example, several individual memory dies (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked to increase the number of layers, physical pages, and accordingly increase the density of memory devices (e.g., storage devices). In an example, memory device 110 may be a discrete memory or storage device component of host device 105. In other examples, memory device 110 may be part of an integrated circuit (e.g., a system on a chip (SOC), etc.) stacked with one or more other components of host device 105 or otherwise included with one or more other components of host device 105.

[0036] One or more communication interfaces may be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface, or a SATA interface. TM interface or one or more other connectors or interfaces. Host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some examples, host 105 may be a Fig.17 The machine 1700 discusses some or all of the components of the machine.

[0037] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array to, for example, transfer (e.g., write or erase) data to or transfer (e.g., read) data from one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array. The memory controller 115 may include, among other things, circuitry or firmware including one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory array 120. The memory controller 115 may include a memory manager 125 and an array controller 135.

[0038] The memory manager 125 may include, among other things, circuitry or firmware, such as a number of components or integrated circuits associated with various memory management functions. For purposes of this description, example memory operations and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands to the array controller 135 or one or more other components of the memory device 110 (e.g., for accomplishing various memory management functions).

[0039] The memory manager 125 may include a set of management tables 130 configured to save various information associated with one or more components of the memory device 110, such as various information associated with a memory array or one or more memory cells coupled to the memory controller 115. For example, the management tables 130 may include information about block age, block erase counts, error history, or one or more error counts (such as write operation error counts, read bit error counts, read operation error counts, erase error counts, etc.) of one or more blocks of memory cells coupled to the memory controller 115. In certain examples, a bit error may be referred to as an uncorrectable bit error if the number of detected errors of one or more of the error counts is above a threshold. The management tables 130 may, among other things, save counts of correctable or uncorrectable bit errors.

[0040] The array controller 135 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory operations may be based on host commands received, for example, from the host 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection or correction, etc.).

[0041] The array controller 135 may include an error correction code (ECC) component 140, which may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to actively detect and recover from error occurrences (e.g., bit errors, operational errors, etc.) associated with various operations or storage of data while maintaining the integrity of data transferred between the host 105 and the memory device 110 or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0042] In some examples, the memory array may include several NAND dies, and one or more functions of the memory controller 115 for a particular NAND die may be implemented on an on-die controller on that particular die. Other organizations and demarcations of control functionality may also be utilized, such as controllers per die, plane, superblock, block, page, and the like.

[0043] The memory array 120 may include a number of memory cells arranged into, for example, a number of devices, semiconductor dies, planes, sub-blocks, blocks, or pages. As one example, a 48GB TLC NAND memory device may include 18,592 data bytes (B) per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two bits of data per cell (i.e., 4 programmable states)) may include 18,592 data bytes (B) per page (16,384+2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the required write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may include other numbers or arrangements. In some examples, a memory device, or a portion thereof, can be selectively operated in an SLC mode or a desired MLC mode (eg, TLC, QLC, etc.).

[0044] In operation, data is typically written to or read from the NAND memory device 110 in pages, and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as desired. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0045] Although a page of data may include several bytes of user data (e.g., a data payload including several sectors of data) and its corresponding metadata, the size of a page generally refers only to the number of bytes used to store the user data. As an example, a page of data having a page size of 4 KB may include 4 KB of user data (e.g., 8 sectors presenting a sector size of 512B) and metadata corresponding to several bytes of user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0046] Different types of memory cells or memory arrays 120 may provide different page sizes, or require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata required to ensure the integrity of a page of data (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Thus, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0047] Figure 2 The description includes organization into blocks (e.g., block A 201A, block B 201B, etc.) and sub-blocks (e.g., sub-block A0 201A0, sub-block A n 201A n , sub-block B0 201B0, sub-block B n 201B n etc.) of a number of memory cells (e.g., the first to third A0 memory strings 205A0 to 207A0, the first to third A n Memory string 205A n To 207A n , first to third B0 memory strings 205B0 to 207B0, first to third B n Memory string 205B n To 207B nMemory array 200 is a schematic diagram of an example of a 3D NAND architecture semiconductor memory array 200 of a memory device. Memory array 200 represents a portion of a larger number of similar structures commonly found in blocks, devices, or other units of memory devices.

[0048] Each string of memory cells includes source lines (SRC) 235 or source side select gates (SGS) (eg, first to third A0 SGS 231A0 to 233A0, first to third A1 SGS 231A0 to 233A0, first to third A2 SGS 231A0 to 233A0, first to third A3 SGS 231A0 to 233A0, first to third A4 SGS 231A0 to n SGS231A n To 233A n , first to third B0 SGS231B0 to 233B0, first to third B n SGS231B n -233B n , etc.) and the drain side select gate (SGD) (e.g., the first to third A0 SGD 226A0 to 228A0, the first to third A n SGD 226A n To 228A n , first to third B0SGD 226B0 to 228B0, first to third B n SGD 226B n To 228B n Each string of memory cells in the 3D memory array may be arranged as a data line (e.g., bit lines (BL) BL0-BL2 220-222) along the X direction and as a physical page along the Y direction.

[0049] Within a physical page, each layer represents a row of memory cells, and each string of memory cells represents a column. A sub-block may represent one or more physical pages. A block may include a number of sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although illustrated herein as having two blocks, each with two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having 8 layers of memory cells, in other examples, the memory array 200 may include more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or layers. For example, each string of memory cells may include more or fewer layers (e.g., 16, 32, 64, 128, etc.) and one or more additional semiconductor material layers above or below the charge storage transistors (e.g., select gates, data lines, etc.) as desired. As an example, a 48GB TLC NAND memory device may include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0050] Each memory cell in the memory array 200 includes a control gate (CG) coupled to (e.g., electrically or otherwise operably connected to) an access line (e.g., word lines (WL) WL00 to WL70 210A to 217A, WL01 to WL71 210B to 217B, etc.), which optionally couples the control gate (CG) in common across a particular layer or a portion of a layer. A particular layer in the 3D memory array, and correspondingly a particular memory cell in a string, may be accessed or controlled using a corresponding access line. Groups of select gates may be accessed using various select lines. For example, the first through third A0 SGD 226A0 to 228A0 may be accessed using A0 SGD line SGDA0 225A0, and the first through third A0 SGD 226A0 to 228A0 may be accessed using A0 SGD line SGDA0 225A0. n SGD 226A n To 228A n A n SGD LineSGDA n 225A n The first to third B0 SGD 226B0 to 228B0 can be accessed using the B0 SGD line SGDB0 225B0, and the first to third B n SGD 226B n To 228B n Can use B n SGD LineSGDB n 225B n Access. First to third A0 SGS231A0 to 233A0 and first to third A n SGS231A n To 233A n The gate select line SGS0 230A can be used to access the first to third B0 SGS231B0 to 233B0 and the first to third B n SGS231B n To 233B n Access is possible using gate select line SGS1 230B.

[0051] In an example, the memory array 200 may include several layers of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) or select gate (or a portion of a CG or select gate) of each memory cell of a respective layer of the array. A particular string of memory cells in the array may be accessed, selected, or controlled using a combination of a bit line (BL) and a select gate, etc., and a particular memory cell at one or more layers in a particular string may be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0052] Figure 3An example schematic diagram illustrating a portion of a NAND architecture semiconductor memory array 300 including a plurality of memory cells 302 and sense amplifiers or devices 360 arranged in a two-dimensional array of strings (e.g., first through third strings 305-307) and layers (e.g., illustrated as respective word lines (WLs) WL0-WL7 310-317, drain side select gate (SGD) lines 325, source side select gate (SGS) lines 330, etc.). For example, the memory array 300 may illustrate, for example, Figure 2 Schematic diagram of an example of a portion of a physical page of memory cells of a 3D NAND architecture semiconductor memory device illustrated in FIG.

[0053] Each string of memory cells is coupled to a source line (SRC) using a respective source side select gate (SGS) (e.g., first to third SGS 331 to 333) and is coupled to a respective data line (e.g., first to third bit lines (BL) BL0 to BL2 320 to 322) using a respective drain side select gate (SGD) (e.g., first to third SGD 326 to 328). Although Figure 3 310-317) and three data lines (BL0-BL2 326-328) are illustrated in the example of , but other examples may include strings of memory cells with more or fewer layers or data lines as desired.

[0054] In a NAND architecture semiconductor memory array, such as the example memory array 300, the state of a selected memory cell 302 can be accessed by sensing a current or voltage change associated with a particular data line containing the selected memory cell. The memory array 300 can be accessed (e.g., by control circuitry, one or more processors, digital logic, etc.) using one or more drivers. In an example, the one or more drivers can activate a particular memory cell or group of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates depending on the type of operation that needs to be performed on the particular memory cell or group of memory cells.

[0055] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) may be applied to a selected word line (e.g., WL4) and, thus, to the control gate of each memory cell coupled to the selected word line (e.g., the first to third control gates (CG) 341 to 343 of the memory cells coupled to WL4). The programming pulses may, for example, start at or near 15V, and in certain examples may increase in magnitude during each programming pulse application. When the program voltage is applied to the selected word line, a potential, such as a ground potential (e.g., Vss), may be applied to the data line (e.g., bit line) and substrate (and, thus, the channel between the source and drain) of the memory cell intended for programming, resulting in charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the target memory cell.

[0056] In contrast, a pass voltage (Vpass) may be applied to one or more word lines having memory cells not intended for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) having memory cells not intended for programming to, for example, inhibit charge transfer from the channel to the floating gates of such non-target memory cells. The pass voltage may vary, for example, depending on the proximity of the applied pass voltage to the word lines intended for programming. The inhibit voltage may include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or supply (e.g., a battery, an AC to DC converter, etc.).

[0057] As an example, if a programming voltage (e.g., 15V or greater) is applied to a particular word line (e.g., WL4), a pass voltage of 10V may be applied to one or more other word lines (e.g., WL3, WL5, etc.) to inhibit programming of non-target memory cells or to maintain values ​​stored on such memory cells that are not intended for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to inhibit programming of the non-target memory cells may decrease. For example, when a programming voltage of 15V is applied to WL4, a pass voltage of 10V may be applied to WL3 and WL5, a pass voltage of 8V may be applied to WL2 and WL6, a pass voltage of 7V may be applied to WL1 and WL7, and so on. In other examples, the pass voltage or number of word lines, etc. may be higher or lower or more or less.

[0058] A sense amplifier 360 coupled to one or more of the data lines, such as the first, second, or third bit lines (BL0-BL2) 320-322, can detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the particular data line.

[0059] Between applying one or more programming pulses (e.g., Vpgm), a verify operation may be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, it may be inhibited from further programming. If the selected memory cell has not reached its intended programming state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programming state after a certain number (e.g., a maximum number) of programming pulses, the selected memory cell or a string, block, or page associated with the selected memory cell may be marked as defective.

[0060] To erase a memory cell or group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate (and therefore the channel between the source and drain) of the memory cell intended for erasure (e.g., using one or more bit lines, select gates, etc.), while the word lines of the target memory cells are maintained at a potential, such as ground potential (e.g., Vss), thereby causing charge transfer from the floating gates of the target memory cells to the channel (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0061] Figure 4 An example block diagram illustrating a memory device 400 including a memory array 402 having a plurality of memory cells 404 and one or more circuits or components for providing communication with or performing one or more memory operations on the memory array 402. The memory device 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, an input / output (I / O) circuit 426, and a memory control unit 430.

[0062] The memory cells 404 of the memory array 402 may be arranged into blocks, such as a first block 402A and a second block 402B. Each block may include sub-blocks. For example, the first block 402A may include a first sub-block 402A0 and a second sub-block 402A n , and the second block 402B may include a first sub-block 402B0 and a second sub-block 402B n Each sub-block may include a number of physical pages, each page including a number of memory cells 404. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 404, in other examples, the memory array 402 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 404 may be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, an access line 406, a first data line 410, or one or more select gates, source lines, etc.

[0063] The memory control unit 430 may control the memory operation of the memory device 400 according to one or more signals or instructions received on the control line 432 (e.g., including one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.)) or address signals (A0 to AX) received on the one or more address lines 416. One or more devices external to the memory device 400 may control the value of the control signal on the control line 432 or the address signal on the address line 416. Examples of devices external to the memory device 400 may include, but are not limited to, Figure 4 A host, a memory controller, a processor, or one or more circuits or components not described in the specification.

[0064] The memory device 400 may use the access lines 406 and the first data lines 410 to transfer (e.g., write or erase) data to or transfer (e.g., read) data from one or more of the memory cells 404. The row decoders 412 and column decoders 414 may receive and decode address signals (A0 through AX) from the address lines 416, may determine which of the memory cells 404 should be accessed, and may provide signals to one or more of the access lines 406 (e.g., one or more of a plurality of word lines (WL0 through WLm)) or the first data lines 410 (e.g., one or more of a plurality of bit lines (BL0 through BLn)), such as described above.

[0065] The memory device 400 may include sensing circuitry, such as sense amplifiers 420, configured to determine the value of data on the memory cell 404 (e.g., read) or determine the value of data written to the memory cell 404 using the first data line 410. For example, in a selected string of memory cells 404, one or more of the sense amplifiers 420 may read the logic level of the selected memory cell 404 in response to a read current flowing into the memory array 402, through the selected string, and to the data line 410.

[0066] One or more devices external to memory device 400 may communicate with memory device 400 using I / O lines (DQ0 to DQN) 408, address lines 416 (A0 to AX), or control lines 432. Input / output (I / O) circuitry 426 may use I / O lines 408 to cause data values ​​to be transferred into or out of memory device 400, such as into or out of page buffer 422 or memory array 402, according to, for example, control lines 432 and address lines 416. Page buffer 422 may store data received from one or more devices external to memory device 400 before the data is programmed into associated portions of memory array 402, or may store data read from memory array 402 before the data is transmitted to one or more devices external to memory device 400.

[0067] The column decoder 414 may receive the address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSELn). The selector 424 (e.g., a selection circuit) may receive the column select signals (CSEL1 to CSELn) and select data in the page buffer 422 representing the value of the data read from or programmed into the memory cell 404. The selected data may be transferred between the page buffer 422 and the I / O circuit 426 using the second data line 418.

[0068] The memory control unit 430 may receive positive and negative supply signals, such as a supply voltage (Vcc) 434 and a negative supply (Vss) 436 (e.g., ground potential) from an external source or supply, such as an internal or external battery, an AC to DC converter, etc. In some examples, the memory control unit 430 may include a regulator 428 that internally provides the positive or negative supply signals.

[0069] ECC and other technologies have significantly improved the reliability of NAND devices. However, there are specific situations where additional protection from data loss is desired. For example, Figure 5 As shown in FIG. 5 , a write operation with a programming failure when programming page row X 510 can damage many pages within that plane. Figure 5 , all pages in a plane (e.g., plane 1) have been corrupted due to a programming failure in page row X510. Figure 6 , an asynchronous power loss (power loss to the NAND devices without warning) during programming of the first page row X 607 can also damage a different page row Z 605.

[0070] As used herein, a page row is a logical construct that identifies a group of pages that includes pages at the same location in each plane in the plane group. Thus, for example, the first page in planes 0 to 3 is identified by page row 0. A page is made up of memory cells that belong to the same word line. A block is a group of pages, i.e., all NAND strings that share the same word line group (a NAND string is a group of NAND cells connected in series). In some NAND configurations, a block is the smallest erasable unit. A page is the smallest addressable unit for reading and writing. A plane is a group of physical blocks on a single NAND die that is configured for operation such that physical blocks from each of multiple planes can be erased in parallel (i.e., during a given time interval, physical blocks can be erased substantially simultaneously or overlapping each other), but only a single physical block in any individual plane can be erased at any one time. There can be multiple planes per NAND die. As Figures 5 to 8 , 10, and 12-14, a plane is represented by a single physical block (selected from the list of physical blocks for that plane), so, for example, in Figure 5, a flat depiction of a list of pages in the selected physical block is shown, but there are additional physical blocks that are not shown for clarity.

[0071] In some examples, improvements to NAND devices are disclosed that allow Figure 5 and Figure 6 The improved NAND data placement pattern for failure case recovery described in the present invention provides additional data protection. The present invention stripes data portions across page rows and planes to ensure that a power failure or programming error that affects an entire page row or plane does not damage the entire data item and at most damages a single portion of the data item. In some examples, parity information can be calculated and stored until programming is complete. This parity information can be used to recover from corruption of a portion of a data item.

[0072] For example, a NAND may receive a data item from a host device. This data item may be divided into several parts. For the purposes of this description, an example will be utilized in which the received data item is divided into four parts. It should be readily apparent to a person skilled in the art who would benefit from the present invention that the received data item may be divided into fewer or more parts. The first part may be programmed at a first position in the NAND, the second part at a second position, the third part at a third position, and the fourth part at a fourth position. The first position, the second position, the third position, and the fourth position may be selected so that the first part, the second part, the third part, and the fourth part are stored in memory cells on different page rows and different planes relative to each other. The different positions of the first, second, third, and fourth parts may include different planes, pages, dies, blocks, and the like. In some examples, the first, second, third, and fourth parts may be stored on the same die. The first, second, third, and fourth parts may be coupled to one or more other parts in various relationships. For example, in some examples, the first and second parts may be stored adjacent to each other (e.g., such as being stored in adjacent page rows and adjacent planes) in accordance with being stored in adjacent page rows and adjacent planes. Figure 7 As used herein, "adjacent" means the next page row and / or plane in sequence. In some examples, the second and third portions may be stored adjacent to each other by virtue of being stored in adjacent page rows and adjacent planes. In some examples, the third and fourth portions may be stored adjacent to each other by virtue of being stored in adjacent page rows and adjacent planes. See, e.g. Figure 7 710, 715, 720, and 725 in (discussed in more detail below). Thus, portions of data are stored such that damage on a single plane or single word line damages at most a single portion of the data. This enables the NAND to reconstruct the damaged portion using parity data. In some examples, each of the first, second, and third portions may be a lower page, an additional page, and an upper page, respectively, relative to each other. In these examples, the fourth portion may be a copy of one of the first, second, and third portions.

[0073] Figure 7and 8 An improved NAND data placement pattern of data according to some examples of the present disclosure is shown on a TLC NAND array 700 having four planes and 216 page rows (page rows 24-203 are not shown for clarity). Figure 8 It is the display page line 204 to 215 Figure 7 In some examples, TLC NAND array 700 may be on a single die having four planes. Figure 7 In FIG. 1 , the page rows of NAND are represented by rows, and the planes of NAND are represented by columns. The data items to be programmed (denoted by P n ) is divided into several parts: the first P n 、Second P n 、Third P n and the fourth P n , where n denotes different data items. For example, a first data item received by the host may be divided into several parts: first P1, second P1, third P1 and fourth P1. A data item may be a page, a word, a block or any other data unit sent by the host.

[0074] The example portion may include a lower page, an upper page, and additional pages of a TLC programming page corresponding to the data item. In some examples, for pages 0 to 3, the first P n Can be the next page, second page n It can be an extra page, and the third P n The fourth page may be the upper page, thus corresponding to the programming order of TLC memory. n Can be the first P n A copy of the fourth P n can be written the same as writing to the first P n For QLC NAND, the fourth P n It can be the fourth programming page. Figure 7 In one example improved NAND data placement pattern, the portion is diagonally striped so that a particular data item P x Each portion of is on a different plane and on a different page relative to the other portions. In some examples, data item P x Each portion of may be placed in a page row and on a plane that is one greater than the previous portion. Thus, the first portion may be placed at location (page row X, plane Y), the second portion may be placed at location (page row X+1, plane Y+1), the third portion may be placed at location (page row X+2, plane Y+2), and the fourth portion may be placed at location (page row X+3, plane Y+3). It should be appreciated that the "first," "second," "third," and "fourth" portions are merely convenient descriptors for different portions of the data.

[0075] When the part is placed, the plane can be folded back to the first plane. Figure 7 , the first portion of P3 is placed in plane 2 (page 0), the second portion can be placed in plane 3 (page 1), and the third portion can be folded back and placed in plane 0 (page 2), and the fourth portion can be placed in plane 1 (page 3). This data placement scheme ensures Figure 5 and Figure 6 The error condition shown in the example affects at most data item P. n As shown, portions such as the first portion (e.g., at 725) may be repeated.

[0076] In some examples, data is written to the NAND in groups of four data items P1 to P4 across four page rows (page rows 0 to 3) and four plane rows (planes 0 to 3). It should be understood that each page row (denoted as Figure 7 and 8 In the example, each plane may store a different portion of different data items (e.g., the first portion of data items P1, P2, P3, P4 is written in page 0 in plane 0, plane 1, plane 2, and plane 3, respectively). It should be understood that each plane may store a different portion of different data items, that is, each plane stores the first portion, the second portion, the third portion, and the fourth portion, but each portion belongs to a different P1, P2, P3, and P4. x For each successive next page row, a different portion of the data item is written and the data item is right shifted by 1 bit (with a wraparound process) to prevent the second portion of the same data item from being written to the same plane, thus, page row 1 may store the second portion of data items P1, P2, P3, and P4, but written to a plane that is +1 higher than the previous page, thus, written to plane 1, plane 2, plane 3, and plane 0, respectively.

[0077] In some instances, a first portion (e.g., first P1, first P2, first P3, first P4) of the four data items of the first group may correspond to a lower page of the SLC NAND, a second portion (second P1, second P2, second P3, second P4) may correspond to an additional page, a third portion (third P1, third P2, third P3, third P4) may correspond to an upper page, and a fourth portion (fourth P1, fourth P2, fourth P3, fourth P4) may correspond (in TLC NAND) to a copy of the first portion (lower page).

[0078] In some examples, the mapping between pages and portions shown in the figure may be the same for all groups of data items. Figure 7 Indicated by the dashed box and in Figure 7, includes a group of four data items. For example, for Group 2 (page rows 4-7), the first portion may be the lower page, the second portion may be the upper page, the third portion may be an additional page, and the fourth portion may be a copy of the lower page. It should be appreciated that larger or smaller group sizes may be utilized. Thus, a group may include 8 data items P1-P8 and may span 8 planes and 8 pages.

[0079] In other examples, instead of the first portion of all groups storing the lower page, the second portion storing the extra page, the third portion storing the upper page, and the fourth portion storing a copy of the first portion, the portions stored by each group may be shifted. For example, for Group 2 (page rows 4 to 7), the mapping between portions and pages may be changed so that the first portion may store the extra page, the second portion may store the upper page, the third portion may store the lower page, and the fourth portion may be a copy of the first portion (the extra page). For Group 3 (pages 8 to 11), the mapping between portions and pages may be shifted again so that the first portion may be the upper page, the second portion may be the lower page, the third portion may be the extra page, and the fourth portion may be the same as the first portion (the upper page). For Group 4 (pages 12 to 15), the programming pages assigned to the various portions may be shifted again to be the same as the programming pages in pages 0 to 3, and so on. Thus, the loop is:

[0080] Page line Flat (0…3) 0 Down 1 additional 2 superior 3 Down 4 additional 5 superior 6 Down 7 additional 8 superior 9 Down 10 additional 11 superior … …

[0081] In addition to the diagonal part placement scheme, the parity page can be calculated from the data item portion. For example, the parity page can be the XOR of the data in the first part, the second part, the third part, and the fourth part. For example:

[0082]

[0083] in is the XOR operator.

[0084] Parity values ​​may be calculated and temporarily stored in volatile memory such as RAM, and then periodically stored in non-volatile storage in a NAND block separate from user data. The diagonal placement of portions of the page data ensures that the remaining data is recoverable when a programming defect or asynchronous power loss erases an entire page or plane, since at most only one portion of a data item will be lost, and it is recoverable due to the XOR parity data.

[0085] Fig. 9 The logical placement of parity pages in a volatile memory or other component of a NAND of a controller according to some examples of the present invention is illustrated. Fig. 9 The parity page shown in the Figure 7 and 8 P nWhen programming a data item to Figure 7 When the NAND in the memory is used, the parity can be calculated and stored in a volatile memory (such as a random access memory). At a first time T0, the data items P1 to P 12 The portions of the data items are written to page rows 0 to 11 and planes 0 to 3 of die 700. At the same time, parity values ​​902 to 924 for these data items may be calculated and stored in a volatile storage device such as a RAM, such as Fig. 9 Displayed in.

[0086] At time T1, the data item P 13 To P 24 The portion of is written to page rows 12 to 23 and the corresponding parity bits are calculated and stored in RAM, such as Fig. 9 . In some examples, parity values ​​902-924 are overwritten by parity values ​​926-948. In some examples, parity values ​​902-924 may be written to the NAND, for example, to a reliable SLC block, before they are overwritten. Similarly, at time T2, parity values ​​for pages 25-36 may be calculated and stored as these pages are written.

[0087] Fig.10 A schematic diagram of a parity page storage 1000 for storing parity pages in a non-volatile NAND is shown. Fig.10 In the example of FIG. 1 , parity page storage 1000 may be configured as an SLC block to improve reliability. Fig.10 The parity page storage 1000 shown in FIG. 1 may be located at a location (eg, from a source) corresponding to the user data from which the parity page is generated. Figure 7 700). In other examples, parity pages may be stored on the same die as the user data from which the parity pages are generated. Parity pages 1-12 are stored at time T0. A cleared page row count (FPC) indicates the number of page rows of programmed user data (e.g., on die 700). Parity pages 13-24 are stored at time T1, and so on, until parity pages 205-216 are stored at time T17.

[0088] Parity data stored in RAM or SLC 1000 can be used to recover user data pages. Figure 7 , if plane 1 is damaged (such as Figure 5 ), then P nOnly individual portions of the data item may be damaged due to a failure on plane 1. The system can recover these portions using parity data. Individual portions of the user data may be recovered by applying an XOR operation to the remaining pages and the parity page. For example, if plane 1 is damaged, the second portion 715 of the P1 data item may be damaged. This portion may be recovered by applying an XOR operation to the first portion 710 of P1, the third portion 720 of P1, the fourth portion of P1, and the parity 902 of P1. Similarly, if a page row such as Figure 6 , only a single portion of the user data page will be lost. For example, if Figure 7 If only one of page rows 0 to 3 of P1 is damaged, only a single portion of a particular user page will be lost. For example, if a page on page row 1 is damaged, then the second portion 715 of P1 is damaged, but the first, second, and fourth portions are not damaged and thus the third portion can be reconstructed using the parity value. For example, by:

[0089]

[0090]

[0091] Therefore, both horizontal corruption across a plane on the same page row and vertical corruption affecting all page rows of a plane can be recovered due to the position rotation of portions of the user data.

[0092] Fig.11 A flow chart showing a method 1100 for applying an improved NAND data placement pattern to store data on a NAND die of a NAND device according to some examples of the present invention. A host device may send a data item written to the NAND. This data item may be programmed into the following portions of the NAND: a first portion, a second portion, a third portion, and a fourth portion. The example portions may correspond to the upper page, lower page, and additional page of a TLC NAND. In other examples, the data item may be divided into only two portions (corresponding to the lower page and upper page of an MLC NAND) or four portions (corresponding to the lower page, upper page, middle page, and additional page of a QLC NAND). In other examples, the portions may not correspond to the programming phase of the NAND, but may be divided in other ways (e.g., most significant bit, least significant bit, and the like). In some examples, the programming pages of the NAND corresponding to the portions may be shifted based on the grouping of the data items. Thus, in the first grouping of the data items, the lower page is written on the first page row of the group, and on the next grouping of the data items, the additional page may be written on the first page row of the group, and so on.

[0093] In operation 1102, the controller may program a first portion of the received data to a first page row and a first plane in a NAND array. In operation 1104, the controller may program a second portion of the received data to a second page row and a second plane in a NAND array. In operation 1106, the controller may program a third portion of the received data to a third page row and a third plane in a NAND array. In operation 1107, the controller may program a fourth portion of the received data to a fourth page row and a fourth plane in a NAND array. In some examples, the fourth portion may be a copy of one of the first, second, third, or fourth portions. For example, the fourth portion may be a copy of a portion (e.g., the first portion) that is first written to a group. The first page row, the second page row, the third page row, the fourth page row, the first plane, the second plane, the third plane, and the fourth plane may be selected so that the first portion, the second portion, the third portion, and the fourth portion of a particular data item are programmed into memory cells on different page rows and different planes relative to each other. In some examples, all locations are on the same die. The NAND memory device may calculate a parity value for the data item using the first, second, and third portions at operation 1108. This parity value may be stored in volatile or non-volatile memory.

[0094] While the above data placement pattern minimizes data loss by strategically placing data and using parity values, once the NAND block to which the parity corresponds is programmed, the parity values ​​can be discarded. While this saves the overhead of storing parity data, this parity data can be used with the same data placement pattern to recover from uncorrectable error correction code (UECC) situations where the NAND cannot recover data with traditional ECC. For example, if Fig.12 As shown in the figure, plane 1, page rows Z to Z+5 may have unrecoverable ECC errors.

[0095] By storing data in the improved NAND data placement pattern described above, a lost single portion of the data can be recovered with a parity value. This cost may be high in terms of the additional overhead for storing the parity values. In some examples, methods, systems, memory devices, and machine-readable media for cluster parity storage of NAND devices utilizing the improved data placement pattern disclosed above are disclosed. Instead of storing each parity value, an XOR operation may be used to combine parity values ​​from multiple data items and store them in compressed form to reduce the reserved space for saving parity values. The compressed parity value may be a merge of multiple parity values, for example, an XOR combination of two or more parity values.

[0096] For example, Fig.13 An SLC NAND block 1300 is shown storing multiple parity values ​​arranged into multiple clusters. Fig.13 , they are arranged into 16 clusters of 54 page rows of four planes per cluster. Thus, each cluster contains 216 parity values. Each parity value corresponds to a data item (e.g., Fig.10 ). The first compressed parity value can be created by XORing the parity values ​​in the same position from each different cluster. For example, the compressed parity values ​​can be created from the XOR of parity value 1, parity value 217, and so on all the way to parity value 3241. Fig.13 The second compressed parity value may be created by performing an XOR operation on the second parity value in each cluster (e.g., parity 2, parity 218, and so on up to parity value 3242). Clusters 2 to 14 included in the XOR calculation are not shown for brevity and clarity.

[0097] More generally, a set of compressed parity values ​​may be created. Each parity value in each cluster may be referenced using a relative position in the cluster using the following notation: (cluster, page, plane). For example, Fig.13 Parity value 1 in may be (0,0,0), indicating that this parity value is in cluster 0, page 0, and plane 0. Page values ​​may be relative to clusters, i.e., parity 3241 may be addressed by (15,0,0) because it is in the first page and first plane of cluster 15, even though it is in page row 810 overall. Compressed parity values ​​may be calculated by XORing parity values ​​of the same relative position for all clusters. For example:

[0098]

[0099] like Fig.13 As shown in , the values ​​of X are in the range of 0 to 53, and the values ​​of Y are in the range of 0 to 3.

[0100] like Fig.14 These compressed parity values ​​can be stored in NAND and can be labeled PARITYX a In some examples, compressed parity values ​​and / or uncompressed parity values ​​may be stored in the original NAND block before closing the original block. The uncompressed values ​​may then be deleted and the space freed for other values ​​(e.g., compressed parity values). The data item P used to calculate the parity value used to calculate the compressed parity value n The group of compressed parity data items G n For example, if Fig.13 Display corresponds to Figure 7 Data item P nIf the parity value of the first compressed parity value is 1, then all portions of the data items that make up the parity values ​​(e.g., parity 1, parity 217, and so on through parity 3241) used to generate the first compressed parity value may be part of the compressed parity data item group G1. For parity value 1, the portion of the data item may include Figure 7 The first P1, the second P1, the third P1 and the fourth P1.

[0101] If an uncorrectable ECC error occurs (e.g. Fig.12 ), then the NAND device can use the compressed parity value to reconstruct the portion of the lost data item. n The damaged part of the data item can be restored by performing an XOR operation on the value of the data item part (excluding the damaged part of course). Figure 7 ) is unrecoverable, the system may perform an XOR operation on the compressed parity value PARITYX1 and the data portion in group G1 (including the second, third and fourth portions of the data item P1) except the first portion of the data item P1 to recover the data item P1.

[0102] Fig.15 Flowchart illustrating a method of clustering parity values ​​according to some examples of the present invention. At operation 1502, incoming data may be stored according to the disclosed improved NAND data placement pattern. For example, a received data item is stored in memory cells of a NAND array such that a first portion, a second portion, a third portion, and a fourth portion of the data item are stored in memory cells on different page rows and different planes in the array relative to each other, such as Figure 7 . In operation 1504, a parity value for the received data item may be calculated and stored in a volatile or non-volatile storage device. As mentioned, the parity value may be an XOR of a portion of the data item. In operation 1506, the NAND device may assign the parity value calculated in operation 1504 to a location of a parity cluster (for example, a first location of the parity cluster). In operation 1508, a compressed parity value may be calculated using the same location of each of the clusters, for example, by applying an XOR operator to the parity values ​​in the same location in each parity value cluster.

[0103] This compressed parity value can be used to recover the data portion as previously described.For example, the damaged data portion can be recovered by performing an XOR operation on the data portion (except the damaged data portion) in the compressed parity data item group and the compressed parity.

[0104] For example, if there is the following data item P belonging to the first parity value in each parity value cluster (eg, the first page row and the first plane): n :

[0105] <![CDATA[P n ]]> Part I Part 2 Part 3 Part 4 <![CDATA[Parity n ]]> 1 010 111 000 010 111 54 101 001 110 101 111 810 000 110 010 000 100

[0106] Next, P in the table n The compressed parity of the group (G1) of data items is the XOR of 111, 111, and 100, which is 100. To recover the lost data portion, for example, P 54 In the second part of the example, the system calculates the XOR of 010, 111, 000, 010, 101, 110, 101, 000, 110, 010, 000, and 100 (which is the compressed parity). The result is: 001, which is the correction value. It should be noted that the example table and the above examples are simplified by having only three P values ​​(1, 54, and 810) and leaving P to be in group G1. 108 The value of can be simplified, such as Fig.13 Displayed in.

[0107] Fig.16 16 is a schematic diagram illustrating a memory controller 1615 according to some examples of the present invention. The memory controller 1615 is an example of the memory controller 115, the memory manager 1625 is an example of the memory manager 125, and the management table 1630 can be an example of the management table 130. The controller 1635 and the ECC 1640 can be Figure 1 1635 and an example of the controller 135 and ECC 140. The controller 1635 includes a mode controller 1642 that can determine the location of a portion of a stored data item. In some examples, the positioning is according to a NAND data placement pattern disclosed herein. For example, a first portion of a received data item is placed at a first page row of multiple page rows and a first plane of multiple planes of a NAND in an array; a second portion of the received data item is programmed to a second page row of multiple page rows in the array and a second plane of multiple planes; a third portion of the received data item is programmed to a third page row of multiple page rows in the array and a third plane of multiple planes; a parity value of the data item is calculated using the first portion, the second portion, and the third portion; and wherein the first page row, the second page row, the third page row, the first plane, the second plane, and the third plane are selected so that the first portion, the second portion, and the third portion are stored in memory cells on different page rows and different planes relative to each other. For example, the mode controller 1642 can position data in a NAND, such as Figure 7 and 8 Displayed in.

[0108] In some examples, mode controller 1642 may also calculate one or more parity values. In some examples, the parity values ​​may be calculated by a hardware XOR processor.

[0109] Mode controller 1642 may allocate and assign parity values ​​to volatile memory locations (eg, Fig. 9 ), non-volatile memory locations (such as Fig.10 ) and the like. The mode controller 1642 may assign parity values ​​to clusters and create compressed parity values ​​using parity values ​​from each cluster, and may store the compressed parity values. The parity values ​​used from each cluster may be selected based on a formula or other pattern. For example, each parity value may be assigned to a relative position in each cluster (e.g., a first parity value, a second parity value, etc. in the cluster), and the same position in each cluster may be used to create the compressed parity value. The mode controller 1642 may store the compressed parity values ​​in a volatile or non-volatile memory (e.g., such as Fig.14 ). The mode controller 1642 may implement Fig.11 and Fig.15 method.

[0110] Fig.17 A block diagram of an example machine 1700 on which any one or more of the techniques (e.g., methods) discussed herein may be executed is described. In alternative embodiments, the machine 1700 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 1700 may act as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 1700 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1700 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network device, an IoT device, an automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions taken by the machine. In addition, although only a single machine is described, the term "machine" should also be deemed to include any collection of machines that individually or jointly execute one (or more) instruction sets to perform any one or more of the methods discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0111] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by logic, components, devices, packages, or mechanisms. A circuit system is a collection of circuits (e.g., a circuit group) implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may change flexibly over time and with basic hardware variability. The circuit system includes members that can perform specific tasks individually or in combination when operating. In an example, the hardware of the circuit system may be immutably designed to implement specific operations (e.g., hard wiring). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetic, electrical, removable placement of constant mass particles, etc.) to encode instructions for specific operations. When connecting physical components, the basic electrical properties of the hardware composition (e.g.,) change from an insulator to a conductor, or vice versa. The instructions enable participating hardware (e.g., execution units or load mechanisms) to create members of the circuit system in hardware via variable connections to implement parts of specific tasks in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any of the physical components can be used in more than one member of more than one circuit system. For example, under operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system or a third circuit in the second circuit system at a different time.

[0112] The machine (e.g., computer system) 1700 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 1702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as memory controller 115, etc.), a main memory 1704, and a static memory 1706, some or all of which may communicate with each other via an interconnect (e.g., a bus) 1708. The machine 1700 may further include a display unit 1710, an alphanumeric input device 1712 (e.g., a keyboard), and a user interface (UI) navigation device 1714 (e.g., a mouse). In an example, the display unit 1710, the input device 1712, and the UI navigation device 1714 may be a touch screen display. In addition, the machine 1700 may include a storage device (e.g., a drive unit) 1716, a signal generating device 1718 (e.g., a speaker), a network interface device 1720, and one or more sensors 1716, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1700 may include an output controller 1728, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0113] The storage device 1716 may include a machine-readable medium 1722 on which is stored one or more sets of data structures or instructions 1724 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 1724 may also reside, completely or at least partially, within the main memory 1704, within the static memory 1706, or within the hardware processor 1702 during execution thereof by the machine 1700. In an example, one or any combination of the hardware processor 1702, the main memory 1704, the static memory 1706, or the storage device 1716 may constitute the machine-readable medium 1722.

[0114] Although the machine-readable medium 1722 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (such as a centralized or distributed database or associated caches and servers) configured to store one or more instructions 1724.

[0115] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions executed by the machine 1700 and causing the machine 1700 to perform any one or more of the techniques of the present invention or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples may include solid-state memory and optical and magnetic media. In an example, a massed machine-readable medium includes a machine-readable medium having a plurality of particles with a constant (e.g., stationary) mass. Thus, a massed machine-readable medium is not a transient propagating signal. Specific examples of massed machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0116] Instructions 1724 (e.g., software, programs, operating systems (OS), etc.) or other data are stored on storage device 1721 and can be accessed by memory 1704 for use by processor 1702. Memory 1704 (e.g., DRAM) is typically faster but volatile, and is therefore a different type of storage than storage device 1721 (e.g., SSD), which is suitable for long-term storage (including under "cut-off" conditions). Instructions 1724 or data used by a user or machine 1700 are typically loaded into memory 1704 for use by processor 1702. When memory 1704 is full, virtual space from storage device 1721 can be allocated to supplement memory 1704; however, because storage device 1721 is typically slower than memory 1704 and write speeds are typically at least 2 times slower than read speeds, using virtual memory can significantly reduce the user experience due to storage device latency (compared to memory 1704, such as DRAM). Furthermore, using the storage device 1721 for virtual storage can significantly reduce the available lifespan of the storage device 1721 .

[0117] Compared to virtual memory, virtual memory compression (e.g. The kernel feature "ZRAM") uses portions of memory as compressed block storage to avoid paging to storage 1721. Paging occurs in compressed blocks until the data needs to be written to storage 1721. Virtual memory compression increases the available size of memory 1704 while reducing wear and tear on storage 1721.

[0118] Storage devices optimized for mobile electronic devices or mobile storage devices typically include MMC solid-state storage devices (such as micro Secure Digital (microSD TM ) card, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are usually removable and separable components from the host device. In contrast, eMMC TM The device is attached to the circuit board and is considered a component of the host device, which has a comparable Serial ATA-based TM The read speed of SSD devices based on Serial AT (Advanced Technology) Attachment or SATA (Serial AT (Advanced Technology) Attachment). However, the performance requirements of mobile devices continue to increase, such as fully enabling virtual or augmented reality devices, taking advantage of increasing network speeds, etc. In response to this requirement, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) use a low voltage differential signaling (LVDS) serial interface with dedicated read / write paths to communicate with host devices, further improving read / write speeds.

[0119] The instructions 1724 may further be transmitted or received over a communication network 1726 using a transmission medium via a network interface device 1720 utilizing any of a number of transmission protocols, such as frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network such as the Internet, a mobile telephone network such as a cellular network, a plain old telephone (POTS) network, and a wireless data network such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards (known as ), IEEE 802.16 series of standards (called ), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc.). In an example, the network interface device 1720 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 1726. In an example, the network interface device 1720 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be taken to include any intangible media capable of storing, encoding, or carrying instructions executed by the machine 1700, and includes digital or analog communication signals or other intangible media that facilitate such software communication.

[0120] The above detailed description includes references to the accompanying drawings that form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than the elements shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) using any combination or arrangement of elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0121] In the present invention, as is common in patent archives, the term "a / an" is used to include one or more, independent of any other examples or uses of "at least one" or "one or more". In the present invention, the term "or" is used to refer to "non-exclusive or", so that "A or B" may include "A but not B", "B but not A" and "A and B", unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the common English equivalents of the corresponding terms "including" and "wherein". Moreover, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles or processes that include elements other than the elements listed after this term in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first", "second" and "third", etc. are used only as labels, and it is not intended to impose numerical requirements on their objects.

[0122] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit (including a group of processors or a multi-core device).

[0123] The term "horizontal" as used in the present invention is defined as a plane parallel to the conventional plane or surface of the substrate (such as the plane below the wafer or die), which is independent of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal defined above. Prepositions such as "on", "above", and "below" are defined relative to a conventional plane or surface on the top or exposed surface of the substrate, which is independent of the orientation of the substrate; while "on" is intended to indicate direct contact of one structure relative to another structure that is "above" the structure (in the absence of an explicit indication to the contrary); the terms "above" and "below" explicitly intend to identify the relative placement of structures (or layers, features, etc.), which explicitly include (but are not limited to) direct contact between the identified structures unless explicitly identified themselves. Similarly, the terms "above" and "below" are not limited to horizontal orientations, because if a structure is the outermost part of the construction being discussed at a certain point in time, it can be "above" a reference structure, even if such structure extends vertically relative to the reference structure, rather than extending in a horizontal orientation.

[0124] The terms "wafer" and "substrate" are generally used herein to refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit fabrication. The following detailed description should therefore not be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full range of equivalents to which such claims are entitled.

[0125] Various embodiments in accordance with the present invention and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, directional adjectives will be considered relative to the surface of the substrate on which the memory cells are formed (i.e., the vertical structure will be considered to extend away from the substrate surface, the bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and the top end of the vertical structure will be considered to be the end farthest from the substrate surface).

[0126] As used herein, directional adjectives (e.g., horizontal, vertical, normal, parallel, etc.) may refer to relative orientations, and are not intended to require strict adherence to specific geometric properties unless otherwise specified. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of a substrate, but may be substantially perpendicular to the surface of a substrate, and may form an acute angle (e.g., between 60 degrees and 120 degrees, etc.) with the surface of the substrate.

[0127] In some embodiments described herein, different doping configurations may be applied to a source side select gate (SGS), a control gate (CG), and a drain side select gate (SGD), each of which in this example may be formed of or at least include polysilicon, such that these layers (e.g., polysilicon, etc.) may have different etch rates when exposed to an etching solution. For example, during the formation of a monomer pillar in a 3D semiconductor device, the SGS and CG may form a recess, while the SGD may remain less recessed or even not recessed. Thus, these doping configurations enable selective etching of different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device by using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0128] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming," and may include both writing to or erasing from a memory cell (e.g., a memory cell may be programmed to an erased state).

[0129] According to one or more embodiments of the present invention, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a number of wear cycles or a wear state (e.g., recording wear cycles, counting operations of a memory device when they occur, tracking operations of a memory device from which they originate, evaluating memory device characteristics corresponding to a wear state, etc.).

[0130] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0131] It should be understood that when an element is referred to as being "on," "connected to," or "coupled with" another element, it may be directly on, directly connected to, or directly coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to," there are no intervening elements or layers. If two elements are shown in a drawing with a line connecting them, the two elements may be coupled or directly coupled unless otherwise indicated.

[0132] The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (such as optical disks and digital video disks), cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, and the like.

[0133] The above description is intended to illustrate rather than limit. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. For example, a person of ordinary skill in the art may use other embodiments after reviewing the above description. It should be understood when submitting that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features may be grouped together to simplify the present invention. This should not be interpreted as wishing that the disclosed features that are not claimed are essential to any claim. More specifically, the subject matter of the present invention may not have all the features of a specific disclosed embodiment. Therefore, the attached claims are hereby incorporated into the specific embodiments, wherein each claim itself is a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the embodiment should be determined with reference to the full range of equivalents authorized by the attached claims and this claim.

[0134] Other notes and examples

[0135] Example 1 is a NAND memory device comprising: an array of NAND memory cells organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations including: programming a first portion of a received data item to a first page row of the multiple page rows in the array and a first plane of the multiple planes; programming a second portion of the received data item to a second page row of the multiple page rows in the array and a second plane of the multiple planes; and programming a third portion of the received data item to a third page row of the multiple page rows in the array and a third plane of the multiple planes.

[0136] In example 2, according to the subject matter of example 1, wherein the operation includes storing a parity value by applying an XOR operator to the first portion, the second portion, and the third portion.

[0137] In example 3, the subject matter of example 2, wherein the operation further comprises storing the parity value in the NAND memory cell array.

[0138] In Example 4, the subject matter of Example 3, wherein the parity value is stored in a location of the NAND memory cell array configured as single level cell (SLC) memory cells.

[0139] In Example 5, the subject matter of any of Examples 3-4, wherein the first portion, the second portion, and the third portion are programmed into locations of the NAND memory cell array configured as three-level cell (TLC) memory cells.

[0140] In Example 6, the subject matter of any of Examples 2 to 5, wherein the operation comprises: determining that one of the first portion, the second portion, or the third portion is corrupted; and recovering the one of the first portion, the second portion, or the third portion by utilizing the parity value.

[0141] In Example 7, the subject matter of any of Examples 2 to 6 includes a volatile memory in communication with the controller; and wherein the operation further comprises: first storing the parity value in the volatile memory; and moving the parity value to the NAND memory cell array.

[0142] In Example 8, the subject matter of any of Examples 1-7, wherein the operation further comprises programming a fourth portion of the received data item to the array at a fourth page row of the plurality of page rows and a fourth plane of the plurality of planes.

[0143] In Example 9, the subject matter of any of Examples 1-8, wherein the first portion, the second portion, and the third portion comprise individual bits within the received data.

[0144] In Example 10, the subject matter of any of Examples 1-9, wherein the third page row and third plane are larger than the second page row and second plane, and the second page row and second plane are larger than the first page row and first plane.

[0145] Example 11 is a method of storing data on a NAND device, the NAND device including an array of NAND memory cells organized into multiple planes and addressable by multiple page rows, the method comprising: programming a first portion of a received data item to a first page row of the multiple page rows in the array and a first plane of the multiple planes; programming a second portion of the received data item to a second page row of the multiple page rows in the array and a second plane of the multiple planes; and programming a third portion of the received data item to a third page row of the multiple page rows in the array and a third plane of the multiple planes.

[0146] In example 12, according to the subject matter of example 11, comprising storing a parity value by applying an XOR operator to the first portion, the second portion, and the third portion.

[0147] In Example 13, the subject matter of Example 12 includes storing the parity value in the NAND memory cell array.

[0148] In Example 14, the subject matter of Example 13, wherein the parity value is stored in a location of the NAND memory cell array configured as single level cell (SLC) memory cells.

[0149] In Example 15, the subject matter of any of Examples 13-14, wherein the first portion, the second portion, and the third portion are programmed into locations of the NAND memory cell array configured as three-level cell (TLC) memory cells.

[0150] In Example 16, the subject matter of any of Examples 12-15, comprising: determining that one of the first portion, the second portion, or the third portion is corrupted; and recovering the one of the first portion, the second portion, or the third portion by utilizing the parity value.

[0151] In Example 17, the subject matter of any of Examples 12-16 includes: first storing the parity value in a volatile memory; and moving the parity value to the NAND memory cell array.

[0152] In Example 18, the subject matter of any of Examples 11-17 includes programming a fourth portion of the received data item to the array at a fourth page row of the plurality of page rows and a fourth plane of the plurality of planes.

[0153] In Example 19, the subject matter of any of Examples 11-18, wherein the first portion, the second portion, and the third portion comprise individual bits within the received data.

[0154] In Example 20, the subject matter of any of Examples 11-19, wherein the third page rows and third planes are larger than the second page rows and second planes, and the second page rows and second planes are larger than the first page rows and first planes.

[0155] Example 21 is a machine-readable medium comprising instructions that, when executed by a machine, cause the machine to perform operations comprising: programming a first portion of a received data item to a first page row of a plurality of page rows and a first plane of a plurality of planes of the NAND array in a NAND array; programming a second portion of the received data item to a second page row of the plurality of page rows and a second plane of the plurality of planes in the array; and programming a third portion of the received data item to a third page row of the plurality of page rows and a third plane of the plurality of planes in the array.

[0156] In Example 22, according to the subject matter of Example 21, wherein the operation includes storing a parity value by applying an XOR operator to the first portion, the second portion, and the third portion.

[0157] In Example 23, the subject matter of Example 22, wherein the operation further comprises storing the parity value in the NAND memory cell array.

[0158] In Example 24, the subject matter of Example 23, wherein the parity value is stored in a location of the NAND memory cell array configured as single level cell (SLC) memory cells.

[0159] In Example 25, the subject matter of any of Examples 23-24, wherein the first portion, the second portion, and the third portion are programmed into locations of the NAND memory cell array configured as three-level cell (TLC) memory cells.

[0160] In Example 26, the subject matter of any of Examples 22 to 25, wherein the operation comprises: determining that one of the first portion, the second portion, or the third portion is corrupted; and recovering the one of the first portion, the second portion, or the third portion by utilizing the parity value.

[0161] In Example 27, the subject matter of any of Examples 22 to 26 includes a volatile memory in communication with the controller; and wherein the operation further comprises: first storing the parity value in the volatile memory; and moving the parity value to the NAND memory cell array.

[0162] In Example 28, the subject matter of any of Examples 21-27, wherein the operation further comprises programming a fourth portion of the received data item to the array at a fourth page row of the plurality of page rows and a fourth plane of the plurality of planes.

[0163] In Example 29, the subject matter of any of Examples 21-28, wherein the first portion, the second portion, and the third portion comprise individual bits within the received data.

[0164] In Example 30, the subject matter of any of Examples 21-29, wherein the third page row and third plane are larger than the second page row and second plane, and the second page row and second plane are larger than the first page row and first plane.

[0165] Example 31 is a NAND memory device comprising: a NAND memory cell array organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations, the controller including means for programming a first portion of a received data item to a first page row of the multiple page rows in the array and a first plane of the multiple planes, means for programming a second portion of the received data item to a second page row of the multiple page rows in the array and a second plane of the multiple planes, and means for programming a third portion of the received data item to a third page row of the multiple page rows in the array and a third plane of the multiple planes.

[0166] In example 32, according to the subject matter of example 31, comprising means for storing a parity value by applying an XOR operator to the first portion, the second portion, and the third portion.

[0167] In Example 33, the subject matter of Example 32 includes means for storing the parity value in the NAND memory cell array.

[0168] In Example 34, the subject matter of Example 33, wherein the parity value is stored in a location of the NAND memory cell array configured as single level cell (SLC) memory cells.

[0169] In Example 35, the subject matter of any of Examples 33-34, wherein the first portion, the second portion, and the third portion are programmed into locations of the NAND memory cell array configured as three-level cell (TLC) memory cells.

[0170] In Example 36, the subject matter of any of Examples 32 to 35 includes means for determining that one of the first part, the second part, or the third part is corrupted and means for recovering the one of the first part, the second part, or the third part by utilizing the parity value.

[0171] In Example 37, the subject matter of any of Examples 32-36 includes means for first storing the parity value in a volatile memory and means for moving the parity value to the NAND memory cell array.

[0172] In Example 38, the subject matter of any of Examples 31-37 includes means for programming a fourth portion of the received data item to the array at a fourth page row of the plurality of page rows and a fourth plane of the plurality of planes.

[0173] In Example 39, the subject matter of any of Examples 31-38, wherein the first portion, the second portion, and the third portion comprise individual bits within the received data.

[0174] In Example 40, the subject matter of any of Examples 31-39, wherein the third page rows and third planes are larger than the second page rows and second planes, and the second page rows and second planes are larger than the first page rows and first planes.

[0175] Example 41 is a NAND memory device comprising: an array of NAND memory cells organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations including the following: storing a received data item in memory cells of the NAND array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells in the array that are on different page rows and different planes relative to each other; calculating a parity value for the received data item using the first portion, the second portion, and the third portion; assigning the parity value of the received data item to a first position of a parity cluster among a plurality of parity clusters; and calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster among the plurality of parity clusters.

[0176] In Example 42, according to the subject matter of Example 41, the operation of calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster includes selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches the relative position of the parity value in the first parity cluster.

[0177] In Example 43, the subject matter of any of Examples 41-42, wherein the parity value is stored in a block of the NAND memory cells.

[0178] In Example 44, the subject matter of any of Examples 42-43, wherein the operation comprises storing the compressed parity value in a block of the NAND memory cells.

[0179] In Example 45, the subject matter of any of Examples 43-44, wherein the operation comprises overwriting the parity value with the compressed parity value.

[0180] In Example 46, the subject matter of any of Examples 41 to 45, wherein the operations include: calculating the second parity value based on first, second, and third portions of a second data item; receiving an indication that a first portion of the data item read from the NAND memory cell array did not pass an error correction code check; and recovering the first portion using the compressed parity value, the second and third portions of the data item, and the first, second, and third portions of the second data item.

[0181] In Example 47, according to the subject matter of any of Examples 41-46, wherein the operation of calculating the compressed parity value comprises applying an XOR operation to the parity value and the second parity value.

[0182] In Example 48, according to the subject matter of any of Examples 41 to 47, the operation of calculating the parity value of the received data item using the first portion, the second portion, and the third portion includes applying an XOR operator to the first portion, the second portion, and the third portion.

[0183] Example 49 is a machine-readable medium comprising instructions that, when executed by a machine, cause the machine to perform operations comprising: storing a received data item in memory cells of a NAND array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells of the array that are on different page rows and different planes relative to each other; calculating a parity value for the received data item using the first portion, the second portion, and the third portion; assigning the parity value for the received data item to a first position of a parity cluster among a plurality of parity clusters; and calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster among the plurality of parity clusters.

[0184] In Example 50, according to the subject matter of Example 49, the operation of calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster includes selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches the relative position of the parity value in the first parity cluster.

[0185] In Example 51, the subject matter of any of Examples 49-50, wherein the parity value is stored in a block of the NAND memory cells.

[0186] In Example 52, the subject matter of any of Examples 50-51, wherein the operation further comprises storing the compressed parity value in the block of NAND memory cells.

[0187] In Example 53, the subject matter of any of Examples 51-52, wherein the operation further comprises overwriting the parity value with the compressed parity value.

[0188] In Example 54, the subject matter of any of Examples 49 to 53, wherein the operation further includes: calculating the second parity value based on the first, second, and third parts of the second data item; receiving an indication that the first part of the data item read from the NAND memory cell array did not pass an error correction code check; and recovering the first part using the compressed parity value, the second and third parts of the data item, and the first, second, and third parts of the second data item.

[0189] In Example 55, the subject matter of any of Examples 49-54, wherein the operation of calculating the compressed parity value comprises applying an XOR operation to the parity value and the second parity value.

[0190] In Example 56, according to the subject matter of any of Examples 49 to 55, the operation of calculating the parity value of the received data item using the first portion, the second portion, and the third portion includes applying an XOR operator to the first portion, the second portion, and the third portion.

[0191] Example 57 is a method of storing data on a NAND device, the NAND device including an array of NAND memory cells organized into multiple planes and addressable by multiple page rows, the method comprising: storing a received data item in memory cells of the NAND array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells of the array on different page rows and different planes relative to each other; calculating a parity value of the received data item using the first portion, the second portion, and the third portion; assigning the parity value of the received data item to a first position of a parity cluster among a plurality of parity clusters; and calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster among the plurality of parity clusters.

[0192] In Example 58, according to the subject matter of Example 57, calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster includes selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches the relative position of the parity value in the first parity cluster.

[0193] In Example 59, the subject matter of any of Examples 57-58, wherein the parity value is stored in a block of the NAND memory cells.

[0194] In Example 60, the subject matter of any of Examples 58-59 includes storing the compressed parity value in a block of the NAND memory cells.

[0195] In Example 61, the subject matter of any of Examples 59-60 includes overwriting the parity value with the compressed parity value.

[0196] In Example 62, the subject matter described in any of Examples 57 to 61 includes: calculating the second parity value based on first, second, and third parts of a second data item; receiving an indication that a first part of the data item read from the NAND memory cell array did not pass an error correction code check; and recovering the first part using the compressed parity value, the second and third parts of the data item, and the first, second, and third parts of the second data item.

[0197] In Example 63, according to the subject matter of any of Examples 57-62, wherein calculating the compressed parity value comprises applying an XOR operation to the parity value and the second parity value.

[0198] In Example 64, according to the subject matter of any of Examples 57 to 63, wherein calculating the parity value of the received data item using the first portion, the second portion, and the third portion includes applying an XOR operator to the first portion, the second portion, and the third portion.

[0199] Example 65 is a NAND memory device comprising: an array of NAND memory cells organized into multiple planes and addressable by multiple page rows; and a controller configured to perform operations, the controller including means for storing a received data item in memory cells of the NAND array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells in the array on different page rows and different planes relative to each other, means for calculating a parity value of the received data item using the first portion, the second portion, and the third portion, means for assigning the parity value of the received data item to a first position of a parity cluster in a plurality of parity clusters, and means for calculating a compressed parity value based on the parity value and a second parity value of a second parity cluster in the plurality of parity clusters.

[0200] In Example 66, according to the subject matter of Example 65, the means for calculating the compressed parity value based on the parity value and the second parity value of the second parity cluster includes means for selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches the relative position of the parity value in the first parity cluster.

[0201] In Example 67, the subject matter of any of Examples 65-66, wherein the parity value is stored in a block of the NAND memory cells.

[0202] In Example 68, the subject matter of any of Examples 66-67, comprising means for storing the compressed parity value in the block of NAND memory cells.

[0203] In Example 69, the subject matter of any of Examples 67-68, comprising means for overwriting the parity value with the compressed parity value.

[0204] In Example 70, the subject matter of any of Examples 65 to 69 includes means for calculating the second parity value based on first, second, and third portions of a second data item, means for receiving an indication that a first portion of the data item read from the NAND memory cell array did not pass an error correction code check, and means for recovering the first portion using the compressed parity value, the second and third portions of the data item, and the first, second, and third portions of the second data item.

[0205] In Example 71, the subject matter of any of Examples 65-70, wherein the means for calculating the compressed parity value comprises means for applying an XOR operation to the parity value and the second parity value.

[0206] In Example 72, the subject matter of any of Examples 65 to 71, wherein the means for calculating the parity value of the received data item using the first portion, the second portion, and the third portion includes means for applying an XOR operator to the first portion, the second portion, and the third portion.

[0207] Example 73 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-72.

[0208] Example 74 is an apparatus comprising means for implementing any of Examples 1-72.

[0209] Example 75 is a system for implementing any of Examples 1-72.

[0210] Example 76 is a method for implementing any of Examples 1-72.

Claims

1. A NAND memory device, comprising: An array of NAND memory cells organized into multiple planes and addressable by multiple page rows; and A controller configured to perform operations including: storing the received data item in memory cells of the NAND memory cell array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells in the NAND memory cell array that are on different page rows and different planes relative to each other; calculating a parity value of the received data item using the first part, the second part, and the third part; assigning the parity value of the received data item to a first position of a first parity cluster of a plurality of parity clusters; and A third parity value is calculated based on the parity value and a second parity value of a second parity cluster of the plurality of parity clusters.

2. The NAND memory device of claim 1 , wherein the operation of calculating the third parity value based on the parity value and the second parity value of the second parity cluster comprises: The second parity value is selected from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches a relative position of the parity value in the first parity cluster.

3. The NAND memory device of claim 1, wherein the parity values ​​are stored in blocks of the NAND memory cell array.

4. The NAND memory device of claim 2, wherein the operation comprises storing the third parity value in a block of the NAND memory cell array.

5. The NAND memory device of claim 3, wherein the operation comprises overwriting the parity value with the third parity value.

6. The NAND memory device of claim 1, wherein the operations comprise: calculating the second parity value based on the first, second and third parts of the second data item; receiving an indication that a first portion of the data item read from the NAND memory cell array failed an error correction code check; The first portion is recovered using the third parity value, the second and third portions of the data item, and the first, second and third portions of the second data item.

7. The NAND memory device of claim 1, wherein the operation of calculating the third parity value comprises applying an XOR operation to the parity value and the second parity value.

8. The NAND memory device of claim 1, wherein the operation of calculating the parity value of the received data item using the first portion, the second portion, and the third portion comprises applying an XOR operator to the first portion, the second portion, and the third portion.

9. A machine-readable medium comprising instructions that, when executed by a machine, cause the machine to perform operations comprising: storing the received data item in memory cells of a NAND memory cell array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells on different page rows and different planes of the NAND memory cell array relative to each other; calculating a parity value of the received data item using the first part, the second part, and the third part; assigning the parity value of the received data item to a first position of a first parity cluster of a plurality of parity clusters; and A third parity value is calculated based on the parity value and a second parity value of a second parity cluster of the plurality of parity clusters.

10. The machine-readable medium of claim 9, wherein the operation of calculating the third parity value based on the parity value and the second parity value of the second parity cluster comprises selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches the relative position of the parity value in the first parity cluster.

11. The machine-readable medium of claim 9, wherein the parity values ​​are stored in a block of the NAND memory cell array.

12. The machine-readable medium of claim 10, wherein the operations further comprise storing the third parity value in a block of the NAND memory cell array.

13. The machine-readable medium of claim 11, wherein the operations further comprise overwriting the parity value with the third parity value.

14. The machine-readable medium of claim 9, wherein the operations further comprise: calculating the second parity value based on the first, second and third parts of the second data item; receiving an indication that a first portion of the data item read from the NAND memory cell array failed an error correction code check; The first portion is recovered using the third parity value, the second and third portions of the data item, and the first, second and third portions of the second data item.

15. The machine-readable medium of claim 9, wherein the operation of calculating the third parity value comprises applying an XOR operation to the parity value and the second parity value.

16. The machine-readable medium of claim 9, wherein the operation of calculating the parity value of the received data item using the first portion, the second portion, and the third portion comprises applying an XOR operator to the first portion, the second portion, and the third portion.

17. A method of storing data on a NAND device, the NAND device comprising an array of NAND memory cells organized into a plurality of planes and addressable by a plurality of page rows, the method comprising: storing the received data item in memory cells of the NAND memory cell array such that a first portion, a second portion, and a third portion of the data item are stored in memory cells on different page rows and different planes in the NAND memory cell array relative to each other; calculating a parity value of the received data item using the first part, the second part, and the third part; assigning the parity value of the received data item to a first position of a first parity cluster of a plurality of parity clusters; and A third parity value is calculated based on the parity value and a second parity value of a second parity cluster of the plurality of parity clusters.

18. The method of claim 17, wherein calculating the third parity value based on the parity value and the second parity value of the second parity cluster comprises selecting the second parity value from the second parity cluster based on a relative position of the second parity value in the second parity cluster that matches the relative position of the parity value in the first parity cluster.

19. The method of claim 17, wherein the parity values ​​are stored in blocks of the NAND memory cell array.

20. The method of claim 18, further comprising storing the third parity value in a block of the NAND memory cell array.

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