Method for manufacturing semiconductor device, semiconductor manufacturing apparatus and semiconductor device

Abstract

A method for manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and a semiconductor device are provided. The method includes: forming an etch target layer on a substrate; forming thermally decomposable patterns spaced apart from each other on the etch target layer; forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns; and removing the thermally decomposable patterns by a heating method to expose the sidewalls of the first mask pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2019-0070864 filed on June 14, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept relate to a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and / or a semiconductor device. Background Art

[0004] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that have the functions of both semiconductor memory devices and semiconductor logic devices. Semiconductor devices have become highly integrated, and the structures of semiconductor devices are becoming increasingly complex. Summary of the Invention

[0005] In one aspect, a method for manufacturing a semiconductor device may include: forming an etch target layer on a substrate; forming thermally decomposable patterns spaced apart from each other on the etch target layer; forming a first mask pattern covering sidewalls of the thermally decomposable patterns; and removing the thermally decomposable patterns by a heating method to expose the sidewalls of the first mask pattern.

[0006] In one aspect, a method for manufacturing a semiconductor device may include: forming conductive patterns spaced apart from each other on a substrate; forming a thermally decomposable layer filling a space between the conductive patterns and covering the conductive patterns; forming a thermally decomposable pattern by removing an upper portion of the thermally decomposable layer, the thermally decomposable pattern partially filling the space between the conductive patterns and exposing an upper sidewall of the conductive pattern; conformally forming a first covering layer covering the conductive patterns and the thermally decomposable pattern; removing the thermally decomposable pattern to form a first gap region exposing a lower sidewall of the conductive pattern; and forming a second covering layer on the first covering layer.

[0007] In one aspect, a semiconductor manufacturing apparatus may include: a transfer chamber; at least one thermally decomposable layer deposition chamber, the at least one thermally decomposable layer deposition chamber being connected to the transfer chamber and configured to deposit a thermally decomposable layer formed of a polymer by supplying a first monomer and a second monomer; at least one annealing chamber being connected to the transfer chamber and configured to decompose the thermally decomposable layer; and at least one covering layer deposition chamber being connected to the transfer chamber and configured to deposit a covering layer.

[0008] In one aspect, a semiconductor device may include: a first conductive pattern and a second conductive pattern adjacent to each other on a substrate, the first conductive pattern having a first upper sidewall adjacent to the second conductive pattern, the second conductive pattern having a second upper sidewall adjacent to the first upper sidewall; a first covering layer, the first covering layer contacting the first upper sidewall and the second upper sidewall and connecting the first upper sidewall and the second upper sidewall to provide a gap area between the first conductive pattern and the second conductive pattern, the first covering layer defining a recessed area thereon; and a second covering layer filling the recessed area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The inventive concept will become more apparent in view of the accompanying drawings and accompanying detailed description.

[0010] Figures 1A to 1I are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0011] Figure 2 are views illustrating a deposition process and a decomposition process of a thermally decomposable layer according to some embodiments of the inventive concept.

[0012] Figure 3 are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0013] Figures 4A to 4I are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0014] Figures 5A to 5G are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 6 is a top view illustrating a semiconductor manufacturing apparatus according to some embodiments of the inventive concept.

[0016] Figure 7 is a cross-sectional view of a thermally decomposable layer deposition chamber.

[0017] Figure 8 is a top view illustrating a semiconductor manufacturing apparatus according to some embodiments of the inventive concept.

[0018] Figure 9 is a top view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0019] Figure 10 It is along Figure 9 A cross-sectional view taken along lines AA' and BB'.

[0020] Figures 11A to 11M is a diagram illustrating the manufacturing of a device having a Figure 10 A cross-sectional view of a semiconductor device of the method of the cross section.

[0021] 12A to 12C is a diagram illustrating the manufacturing of a device having a Figure 10 A cross-sectional view of a semiconductor device of the method of the cross section. DETAILED DESCRIPTION

[0022] It will be understood that although the terms first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be restricted by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the example embodiments of the present invention, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. The phrase "at least one" has the same meaning as "and / or".

[0023] For ease of description, spatial relative terms such as "below" and "above" may be used herein to describe the relationship between an element or feature as shown in the figure and other elements or features. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the element described as being below other elements or features will subsequently be oriented to be above the other elements or features. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used in this article are interpreted accordingly. In addition, when an element is referred to as being "between" two elements, the element can be the only element between the two elements, or there can be one or more other intermediate elements.

[0024] When an element is referred to as being “on,” “connected to,” or “in contact with” another element, the element may be directly on, directly connected to, or directly in contact with the other element, or one or more other intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element, there are no intervening elements present.

[0025] Hereinafter, embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

[0026] Figures 1A to 1Iare cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Figure 2 are views illustrating a deposition process and a decomposition process of a thermally decomposable layer according to some embodiments of the inventive concept. Figure 3 are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0027] Reference Figure 1A , an etching target layer 3, a first mask layer 5, a second mask layer 7, a third mask layer 9, and a fourth mask layer 11 may be sequentially stacked on a substrate 1. A fifth mask pattern 13 may be formed on the fourth mask layer 11. Although not shown in the drawings, an interlayer insulating layer, an interconnect structure, and a transistor may be located between the substrate 1 and the etching target layer 3. The substrate 1 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. Each of the etching target layer 3, the first to fourth mask layers 5, 7, 9, and 11, and the fifth mask pattern 13 may include a material having etching selectivity at least relative to the material of other layers adjacent thereto. For example, the etching target layer 3 may include a metal such as tungsten. The first mask layer 5 may include, for example, an amorphous carbon layer (ACL). The second mask layer 7 may include, for example, an amorphous silicon layer. The third mask layer 9 may include, for example, a thermally decomposable layer.

[0028] Reference Figure 2 During the process of forming the third mask layer 9, vapor of a first monomer M1 and vapor of a second monomer M2 may be supplied onto the second mask layer 7. The first monomer M1 may be the same as or different from the second monomer M2. The first monomer M1 and the second monomer M2 may be deposited on the second mask layer 7 and may react and cross-link with each other to form a thermally decomposable polymer layer PL. In this specification, the polymer layer PL may be referred to as a thermally decomposable layer. The polymer layer PL may include carbon and hydrogen. The polymer layer PL may also include at least one of oxygen or nitrogen. The polymer layer PL may be, for example, polystyrene. In this case, the first monomer M1 and the second monomer M2 may be the same and may be, for example, styrene. The polymer layer PL may be thermally decomposed at a first temperature. For example, the first temperature may range from 250°C to 800°C. The process of depositing the third mask layer 9 (e.g., the polymer layer PL) may be performed at a second temperature lower than the first temperature. For example, the second temperature may range from 50°C to 200°C. The process of depositing the third mask layer 9 (e.g., the polymer layer PL) may be performed at a pressure ranging from, for example, 0 Torr to ambient pressure. The fourth mask layer 11 may include, for example, a silicon oxynitride layer or a silicon nitride layer. The fifth mask pattern 13 may be, for example, a photoresist pattern.

[0029] Reference Figure 1B and Figure 1C, the fourth mask layer 11 may be anisotropically etched using the fifth mask pattern 13 as an etching mask to form a fourth mask pattern 11 a partially exposing the third mask layer 9. The third mask layer 9 may be etched using the fourth mask pattern 11 a as an etching mask to form a third mask pattern 9 a partially exposing the second mask layer 7. The third mask pattern 9 a may be referred to as a thermally decomposable pattern.

[0030] Reference Figure 1D , a sixth mask layer 15 can be formed on the third mask pattern 9a. The sixth mask layer 15 can cover the top surface of the third mask pattern 9a and can fill the space between the third mask patterns 9a. The sixth mask layer 15 can be, for example, a spin-on hard mask (SOH) layer. The carbon-containing composite can be formed by a spin coating method, and then a baking process can be performed on the carbon-containing composite to form the SOH layer. The carbon-containing composite can include an organic compound and a solvent. The carbon-containing composite can also include additives selected from the group including a cross-linking agent, a free radical stabilizer, a surfactant, a pH regulator, and a combination thereof. The organic compound can include a hydrocarbon compound or a derivative thereof, and the hydrocarbon compound or its derivative includes an aromatic ring such as phenyl, benzene, or naphthalene. For example, the solvent can include at least one of propylene glycol methyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), cyclohexanone, or ethyl lactate. The solvent contained in the carbon-containing composite can be evaporated by a baking process.

[0031] Reference Figure 1E and Figure 2 , the third mask pattern 9a can be removed to form a gap region GP in the sixth mask layer 15. The inner sidewall of the sixth mask layer 15 can be exposed through the gap region GP. The removal of the third mask pattern 9a can be performed by an annealing process. The annealing process can be performed at a temperature equal to or higher than the thermal decomposition temperature (e.g., the first temperature) of the material (e.g., polymer layer PL) of the third mask pattern 9a.

[0032] The polymer layer PL can be decomposed into the first monomer M1 and the second monomer M2 through the annealing process. The first monomer M1 and the second monomer M2 can pass through the sixth mask layer 15 in a vapor state and can be released to the outside. In the annealing process, at least one gas of nitrogen, hydrogen, helium, or argon can be supplied as, for example, a carrier gas. Hydrogen can react with carbon of the thermally decomposable pattern (e.g., the third mask pattern 9a) to form a low molecular weight hydrocarbon compound (e.g., methane), thereby increasing the thermal decomposition rate.

[0033] According to example embodiments, an annealing process may be performed to remove the third mask pattern 9a. Alternatively, the third mask pattern 9a may be thermally decomposed and thus removed when a baking process is performed to form the sixth mask layer 15. In this case, the process may be simplified.

[0034] Reference Figure 1F , you can Figure 1E An anisotropic etching process is performed on the sixth mask layer 15 to remove the sixth mask layer 15 located on the gap region GP, ​​thereby opening the gap region GP and forming sixth mask patterns 15a. The sixth mask patterns 15a may be spaced apart from each other.

[0035] Or, as Figure 3 As shown, it is possible to Figure 1D An anisotropic etching process is performed on the sixth mask layer 15 to remove the sixth mask layer 15 located on the third mask patterns 9a, so that a sixth mask pattern 15a can be formed between the third mask patterns 9a. Thereafter, an annealing process can be performed to remove the sixth mask layer 15 located on the third mask patterns 9a. Figure 1E The third mask pattern 9 a is removed as described, and thus, the sidewalls of the sixth mask pattern 15 a may be exposed.

[0036] Then, refer to Figures 1G to 1I , the second mask layer 7 can be etched using the sixth mask pattern 15a as an etch mask to form a second mask pattern 7a that partially exposes the top surface of the first mask layer 5. The first mask layer 5 can be etched using the second mask pattern 7a as an etch mask to form a first mask pattern 5a that partially exposes the etch target layer 3. The etch target layer 3 can be etched using the first mask pattern 5a as an etch mask to form a desired target pattern 3a.

[0037] According to the reference Figures 1A to 1I 、 Figure 2 and Figure 3In the described example embodiment, the third mask pattern 9a can be formed from a thermally decomposable material, and only the third mask pattern 9a can be decomposed by the annealing process without damaging surrounding structures. If the third mask pattern 9a is not formed from a thermally decomposable material, an additional etching process should be performed to remove the third mask pattern 9a. If the etching process is performed anisotropically, the sixth mask pattern 15a may be damaged by the etching process. In other words, the upper portion of the sixth mask pattern 15a may also be removed by the etching process, and the thickness of the sixth mask pattern 15a may be less than the desired thickness. In this case, it may be difficult to accurately form the second mask pattern 7a. If the etching process is performed isotropically, the etchant may penetrate between the second mask layer 7 and the sixth mask pattern 15a, causing the sixth mask pattern 15a to peel off. In this case, it may also be difficult to accurately form the second mask pattern 7a. However, according to embodiments, the third mask pattern 9a can be formed from a thermally decomposable material, thereby reducing etching damage or preventing or minimizing peeling of the mask pattern. Therefore, the pattern profile after etching can be accurately formed. As a result, in the process of manufacturing semiconductor devices, process failures can be reduced and the yield can be improved.

[0038] Figures 4A to 4I are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0039] Reference Figure 4A , an etching target layer 23, a first mask layer 25, a second mask layer 27, and a third mask layer 29 may be sequentially stacked on the substrate 21. A fourth mask pattern 31 may be formed on the third mask layer 29. The substrate 21 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. Each of the etching target layer 23, the first to third mask layers 25, 27, and 29, and the fourth mask pattern 31 may include a material having an etching selectivity relative to at least the material of other layers adjacent thereto. For example, the etching target layer 23 may include a metal such as tungsten. For example, the first mask layer 25 may include an amorphous carbon layer (ACL), a spin-on hard mask (SOH) layer, a silicon nitride layer, or a silicon oxynitride layer.

[0040] The second mask layer 27 may include, for example, a thermally decomposable layer. The process of forming the second mask layer 27 may be the same as that of the reference Figure 2 The processes described above are the same or similar. The third mask layer 29 may include, for example, a silicon nitride layer or a silicon oxynitride layer. The fourth mask patterns 31 may be photoresist patterns. Each fourth mask pattern 31 may have a first width W1. The distance between the fourth mask patterns 31 may be a first distance D1. For example, the ratio of the first width W1 to the first distance D1 may be approximately 3:5.

[0041] Reference Figure 4B, a first spacer layer may be conformally formed on the entire surface of the substrate 21, and then an anisotropic etching process may be performed on the first spacer layer to form first spacers 33 that respectively cover the sidewalls of the fourth mask pattern 31. The first spacers 33 may be formed of a material having an etching selectivity with respect to the third mask layer 29. For example, the first spacers 33 may be formed of silicon oxide. Each first spacer 33 may have a second width W2. For example, the second width W2 may correspond to Figure 4A The second distance D2 between the adjacent first spacers 33 may be equal to Figure 4A The first width W1.

[0042] Reference Figure 4C and Figure 4D , the fourth mask pattern 31 may be removed to expose the sidewalls of the first spacers 33. The distance between the first spacers 33 may be constant at the second distance D2. The third mask layer 29 may be etched using the first spacers 33 as an etching mask to form a third mask pattern 29a. Most of the first spacers 33 may be removed by the etching process, and the remaining portion of the first spacers 33 may remain on the third mask pattern 29a.

[0043] Reference Figure 4E , the second mask layer 27 may be etched using the third mask pattern 29a as an etching mask to form second mask patterns 27a. The second mask patterns 27a may be referred to as thermally decomposable patterns. Each second mask pattern 27a may have a second width W2. The distance between the second mask patterns 27a may be equal to the second distance D2.

[0044] Reference Figure 4F , a second spacer layer may be conformally formed on the entire surface of the substrate 21, and then an anisotropic etching process may be performed on the second spacer layer to form second spacers 35 that respectively cover the sidewalls of the second mask pattern 27a. The second spacers 35 may be formed of a material having an etching selectivity relative to the first mask layer 25. For example, the second spacers 35 may be formed of silicon oxide. Each second spacer 35 may have a third width W3. The third width W3 may be equal to Figure 4B The third distance D3 between the adjacent second spacers 35 may be equal to the third width W3. The width of the upper portion of the second spacer 35 is smaller than the width of the lower portion thereof.

[0045] Reference Figure 4G , the second mask pattern 27a may be removed to expose the sidewalls of the second spacers 35. The second mask pattern 27a may be removed by an annealing process. The thermally decomposable layer of the second mask pattern 27a may be removed as described with reference to FIG. Figure 2 Decomposed thermally as described.

[0046] Reference Figure 4H and Figure 4I , the first mask layer 25 may be anisotropically etched using the second spacer 35 as an etching mask to form a first mask pattern 25a. The etching target layer 23 may be etched using the first mask pattern 25a as an etching mask to form a target pattern 23a. At this time, each target pattern 23a may have Figure 4F The distance between the target patterns 23a may correspond to Figure 4F The third width W3 may be equal to the third distance D3.

[0047] According to the reference Figures 4A to 4I In the exemplary embodiment described above, the second mask pattern 27a can be formed of a thermally decomposable material, and only the second mask pattern 27a can be decomposed by the annealing process without damaging surrounding structures. Therefore, as described above, etching damage can be reduced or peeling of the mask pattern can be resolved. Therefore, the pattern profile after etching can be precisely formed. As a result, process failures can be reduced and the yield rate can be improved in the process of manufacturing semiconductor devices.

[0048] Figures 5A to 5G are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0049] Reference Figure 5A , conductive patterns spaced apart from each other can be formed on the substrate 41. The conductive patterns can be referred to as first interconnect patterns 43. Even though not shown in the drawings, an interlayer insulating layer, a transistor, and an interconnect structure can be located between the substrate 41 and the first interconnect patterns 43. The substrate 41 can be a semiconductor substrate or an SOI substrate. The first interconnect patterns 43 may include a metal such as tungsten, copper, and / or aluminum. Even though not shown in the drawings, each first interconnect pattern 43 may further include a diffusion barrier layer including a metal nitride layer such as a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer.

[0050] Reference Figure 5B , a thermally decomposable layer 45 may be formed on the first interconnection pattern 43. Figure 2 The thermally decomposable layer 45 may fill the spaces between the first interconnection patterns 43.

[0051] Reference Figure 5C, the upper portion of the thermally decomposable layer 45 may be removed by performing a first annealing process, thereby exposing the upper portions of the first interconnection patterns 43 and forming thermally decomposable patterns 45a between the first interconnection patterns 43. The thermally decomposable patterns 45a may be spaced apart from each other. The time, temperature, and / or pressure of the first annealing process may be adjusted so that the thermally decomposable layer 45 is not completely removed but the thermally decomposable patterns 45a remain.

[0052] Reference Figure 5D , a first capping layer 47 may be conformally formed on the entire surface of the substrate 41. The first capping layer 47 may have a single-layer or multi-layer structure including at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous insulating layer. The first capping layer 47 may have an appropriate thickness so as not to fill the space on the thermally decomposable pattern 45a between the first interconnect patterns 43. Therefore, the cross-section of the first capping layer 47 may have an uneven structure, and the first capping layer 47 may have a recessed region R on the thermally decomposable pattern 45a.

[0053] Reference Figure 5E , a second annealing process may be performed to remove the thermally decomposable pattern 45a, thereby forming a first gap region GP1 between the first interconnection patterns 43. The first gap region GP1 may expose the sidewall of the lower portion of the first interconnection pattern 43, the bottom surface of the first capping layer 47, and the top surface of the substrate 41. The thermally decomposable pattern 45a may be thermally decomposed into Figure 2 The first monomer M1 and Figure 2 The first monomer and the second monomer M2 in the vapor state may be released to the outside through the first covering layer 47 .

[0054] Reference Figure 5F , a second capping layer 49 may be formed on the first capping layer 47. The second capping layer 49 may have a single-layer or multi-layer structure including at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous insulating layer. The second capping layer 49 may be thicker than the first capping layer 47. The second capping layer 49 may fill the space (e.g., the recessed region R) between the first interconnection patterns 43 on the first capping layer 47 located on the first gap region GP1.

[0055] In an alternative embodiment, the first capping layer 47 and the second capping layer 49 can be removed from the first interconnection pattern 43, thereby exposing the top surface of the first interconnection pattern 43. The exposed area of ​​the first interconnection pattern 43 can be further processed to form an upper conductive pattern. The upper conductive pattern (not shown) can contact the first interconnection pattern 43.

[0056] Reference Figure 5G, a second interconnection pattern 53, a third capping layer 57, a second gap region GP2, and a fourth capping layer 59 may be formed on the second capping layer 49. The third capping layer 57 may be formed by the same or similar process as the first capping layer 47. The second gap region GP2 may be formed by the same or similar process as the first gap region GP1. The fourth capping layer 59 may be formed by the same or similar process as the second capping layer 49.

[0057] The density of the first cover layer 47 and the third cover layer 57 may be lower than that of the second cover layer 49 and the fourth cover layer 59, respectively. The porosity of the first cover layer 47 and the third cover layer 57 may be higher than that of the second cover layer 49 and the fourth cover layer 59, respectively. Therefore, when forming the first gap region GP1 and the second gap region GP2, vapor can easily pass through the first cover layer 47 and the third cover layer 57. The second cover layer 49 and the fourth cover layer 59 can support the first interconnection pattern 43 and the second interconnection pattern 53, respectively.

[0058] exist Figure 5G In a semiconductor device, a first capping layer 47 may cover the top surface of the first interconnect pattern 43 and the sidewalls of the upper portion of the first interconnect pattern 43. The first capping layer 47 may connect the sidewalls of the upper portion of the first interconnect pattern 43. A first gap region GP1 may be formed between the sidewalls of the lower portion of the first interconnect pattern 43. The first capping layer 47 may have a recessed region R on the first gap region GP1. The recessed region R may be filled with a second capping layer 49. The second capping layer 49 can serve as a support for the second interconnect pattern 53. In the semiconductor device, the first gap region GP1 may exist between the first interconnect patterns 43, and the second gap region GP2 may exist between the second interconnect patterns 53. Therefore, signal interference between the first interconnect patterns 43 and between the second interconnect patterns 53 can be reduced. As a result, signal transmission speed can be improved.

[0059] Figure 6 is a top view illustrating a semiconductor manufacturing apparatus according to some embodiments of the inventive concept. Figure 7 is a cross-sectional view of a thermally decomposable layer deposition chamber.

[0060] Reference Figure 6 and Figure 7 , a semiconductor manufacturing apparatus 200 according to some embodiments of the present inventive concept may include a first transfer chamber 110. At least one first robot arm 112 may be in the first transfer chamber 110. At least one thermally decomposable layer deposition chamber 120 may be connected to the first transfer chamber 110. The thermally decomposable layer deposition chamber 120 may have a structure of a plasma enhanced chemical vapor deposition (PECVD) apparatus, a small batch-type apparatus, or a thermal deposition apparatus.

[0061] In some embodiments, the thermally decomposable layer deposition chamber 120 may include a chamber wall 125, a wafer receiving unit 121 on which a wafer W is received, and a shower head 123 disposed above the wafer receiving unit 121. The wafer receiving unit 121 may be rotatable. A discharge pipe 127 may be located at a side of the wafer receiving unit 121 and below the wafer accommodating unit 121. A first monomer storage container 122a and a second monomer storage container 122b may be connected to the shower head 123 of the thermally decomposable layer deposition chamber 120. A first evaporator 124a may be located between the first monomer storage container 122a and the shower head 123. A second evaporator 124b may be located between the second monomer storage container 122b and the shower head 123. Figure 2 The first monomer M1 described above may be stored in the first monomer storage container 122a. Figure 2 The depicted second monomer M2 may be stored in the second monomer storage container 122 b .

[0062] The first monomer M1 and the second monomer M2 can be evaporated by the first evaporator 124a and the second evaporator 124b, respectively, so that the first monomer M1 and the second monomer M2 in a vapor state can be supplied to the nozzle 123. The first monomer M1 and the second monomer M2 injected through the nozzle 123 can be supplied to the wafer W located on the wafer receiving unit 121, and can be referred to Figure 2 The first and second monomers M1 and M2 react and cross-link with each other as described to deposit the thermally decomposable layer PL. Unreacted first and second monomers M1 and M2 may be exhausted to the outside through the exhaust pipe 127.

[0063] A heater may be located in or near the chamber wall 125 and the wafer receiving unit 121 to maintain the temperature of the chamber wall 125 and the wafer receiving unit 121 at a process temperature for depositing the thermally decomposable layer. When the temperature at which the thermally decomposable layer PL is thermally decomposed is defined as a first temperature, a second temperature corresponding to the process temperature in the thermally decomposable layer deposition chamber 120 may be lower than the first temperature. For example, the second temperature may range from 50° C. to 200° C. For example, the pressure in the thermally decomposable layer deposition chamber 120 may range from 0 Torr to ambient pressure. Even though not shown in the drawings, the thermally decomposable layer deposition chamber 120 may further include a device for generating plasma (e.g., a coil or an electrode).

[0064] At least one annealing chamber 130 may be connected to the first transfer chamber 110. A pipe for supplying a carrier gas (e.g., hydrogen, nitrogen, argon, and / or helium) may be additionally connected to the annealing chamber 130. The annealing chamber 130 may decompose the thermally decomposable layer deposited in the thermally decomposable layer deposition chamber 120, thereby removing a portion or the entire thermally decomposable layer. The third temperature corresponding to the process temperature of the annealing chamber 130 may be higher than the first temperature. In some embodiments, the pressure in the annealing chamber 130 may be less than the vapor pressure of the material of the thermally decomposable layer at the first temperature.

[0065] At least one capping layer deposition chamber 140 may be connected to the first transfer chamber 110. The capping layer deposition chamber 140 may have a structure of a plasma enhanced chemical vapor deposition (PECVD) apparatus, a small batch apparatus, or a thermal deposition apparatus. The capping layer deposition chamber 140 may deposit a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous insulating layer.

[0066] The second transfer chamber 160 may be connected to the first transfer chamber 110. At least one second robot 105 may be in the second transfer chamber 160. A station chamber 150 may be between the first transfer chamber 110 and the second transfer chamber 160. A plurality of wafer cassettes 170 may be mounted to the second transfer chamber 160.

[0067] The semiconductor manufacturing apparatus 200 may be used to perform Figures 5A to 5F This will be described in detail below.

[0068] The wafers in the wafer box 170 may be transferred to the station chamber 150 by the second robot arm 105. Figure 5A The first interconnect pattern 43. The first robot 112 can transfer the wafer located in the station chamber 150 to the thermally decomposable layer deposition chamber 120. In the thermally decomposable layer deposition chamber 120, a thermally decomposable layer 45 can be formed, as shown in FIG. Figure 5B The first robot 112 may unload the wafer having the thermally decomposable layer 45 from the thermally decomposable layer deposition chamber 120, and then may load the wafer into the annealing chamber 130. In the annealing chamber 130, the upper portion of the thermally decomposable layer 45 may be thermally decomposed and removed to form a thermally decomposable pattern 45a, as described with reference to FIG. Figure 5C The first robot arm 112 can unload the wafer from the annealing chamber 130 and then load the wafer into the capping layer deposition chamber 140. In the capping layer deposition chamber 140, a first capping layer 47 can be formed, as shown in FIG. Figure 5DThe first robot arm 112 may unload the wafer from the capping layer deposition chamber 140 and then may load the wafer into the annealing chamber 130. In the annealing chamber 130, the thermally decomposable pattern 45a may be thermally decomposed and removed to form the first gap region GP1, as described with reference to FIG. Figure 5E The first robot arm 112 can unload the wafer from the annealing chamber 130 and then load the wafer into the capping layer deposition chamber 140. In the capping layer deposition chamber 140, the second capping layer 49 can be formed, as shown in FIG. Figure 5F The wafer having the second cover layer 49 formed thereon may be transferred to the station chamber 150 by the first robot 112 and may be cooled to room temperature in the station chamber 150. Next, the wafer may be transferred to the wafer cassette 170 by the second robot 105.

[0069] The semiconductor manufacturing apparatus 200 according to an embodiment of the present inventive concept may include the thermally decomposable layer deposition chamber 120, the annealing chamber 130, and the capping layer deposition chamber 140 as a single group, thereby simplifying the process and eliminating vacuum break (e.g., the time required to create a vacuum). As a result, the total processing time can be reduced.

[0070] Figure 8 is a top view illustrating a semiconductor manufacturing apparatus according to some embodiments of the inventive concept.

[0071] Reference Figure 8 , the semiconductor manufacturing apparatus 201 according to some embodiments of the present invention may include a first transfer chamber 110. At least one thermally decomposable layer deposition chamber 120 may be connected to the first transfer chamber 110. The thermally decomposable layer deposition chamber 120 may be connected to the first transfer chamber 110. Figure 6 and Figure 7 The first annealing chamber 130a, the first capping layer deposition chamber 140a, the second annealing chamber 130b and the second capping layer deposition chamber 140b may be connected to the first transfer chamber 110. The first annealing chamber 130a and the second annealing chamber 130b may be connected to the first transfer chamber 110. Figure 6 The annealing chamber 130 is the same as or similar to the annealing chamber 130 described above. The first capping layer deposition chamber 140a and the second capping layer deposition chamber 140b may be the same as those described above. Figure 6 The blanket layer deposition chamber 140 is the same or similar as described.

[0072] The first annealing chamber 130a can be used as Figure 5C In this way, the upper portion of the thermally decomposable layer 45 is removed (or the upper portion of the thermally decomposable layer 45 is recessed). The first capping layer deposition chamber 140a may be used to deposit Figure 5D The second annealing chamber 130b can be used as Figure 5EThe second capping layer deposition chamber 140b may be used to deposit Figure 5F The other components and operations of the semiconductor manufacturing apparatus 201 may be the same as those in the reference Figure 6 Same or similar description.

[0073] Although not shown, the semiconductor manufacturing apparatuses 200 and 201 may further include an electronic controller and a memory connected via a bus. The memory may be a non-volatile memory such as a flash memory, a phase change random access memory (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM), or a volatile memory such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM). The electronic controller may be a central processing unit (CPU), a processor, an application specific integrated circuit (ASIC), or other suitable hardware processing unit, which, when executing instructions stored in the memory, configures the controller as a dedicated controller for controlling the semiconductor manufacturing apparatuses 200 and 201 to perform the above-mentioned operations. Figure 6 and Figure 8 One or more of the above-described manufacturing processes described in connection with the semiconductor manufacturing apparatuses 200 and 201 , the thermally decomposable layer deposition chamber 120 , the annealing chamber 130 , the capping layer deposition chamber 140 , and the robot arms 105 and 112 .

[0074] Figure 9 is a top view illustrating a semiconductor device according to some embodiments of the inventive concept. Figure 10 It is along Figure 9 A cross-sectional view taken along lines AA' and BB'.

[0075] Reference Figure 9 and Figure 10 , the device isolation pattern 302 may be in the substrate 301 to define an active portion ACT. When viewed in a top view, each active portion ACT may have an isolated shape. When viewed in a top view, each active portion ACT may have a bar shape extending in the first direction X1. Each active portion ACT may correspond to a portion of the substrate 301, which is surrounded by the device isolation pattern 302 when viewed in a top view. The substrate 301 may include a semiconductor material. For example, the substrate 301 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The device isolation pattern 302 may include at least one of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a nitride oxide (e.g., silicon oxynitride). The active portions ACT may be parallel to each other in the first direction X1 and may be arranged so that the end of each active portion ACT is adjacent to the central portion of another active portion ACT adjacent thereto.

[0076] The word lines WL may intersect the active portion ACT. The word lines WL may be located in grooves formed in the device isolation pattern 302 and the active portion ACT. The word lines WL may be parallel to a second direction X2 that intersects the first direction X1. The word lines WL may be formed of a conductive material. A gate dielectric layer 107 may be between each word line WL and the inner surface of each groove. Although not shown in the drawings, the bottom of the groove may be relatively deep in the device isolation pattern 302 and relatively shallow in the active portion ACT. The gate dielectric layer 107 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. The bottom surface of the word lines WL may be rounded.

[0077] The first doped region 312a may be in each active portion ACT between a pair of word lines WL, and a pair of second doped regions 312b may be respectively in two edge regions of each active portion ACT. The first doped region 312a and the second doped region 312b may be doped with, for example, an N-type dopant. The first doped region 312a may correspond to a common drain region, and the second doped region 312b may correspond to a source region. Each word line WL and the first doped region 312a and the second doped region 312b adjacent thereto may constitute a transistor. Since the word line WL is in a groove, the channel length of the channel region below the word line WL can be increased in a limited plane area. Therefore, the short channel effect can be minimized.

[0078] The top surface of the word line WL may be lower than the top surface of the active portion ACT. A word line capping pattern 310 may be provided on each word line WL. The word line capping pattern 310 may have a linear shape extending in the longitudinal direction of the word line WL and may completely cover the top surface of the word line WL. The word line capping pattern 310 may fill the groove on the word line WL. The word line capping pattern 310 may be formed of, for example, silicon nitride.

[0079] The interlayer insulating pattern 305 may be on the substrate 301. The interlayer insulating pattern 305 may be formed of a single layer or multiple layers including at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In a top view, the interlayer insulating pattern 305 may have an island shape spaced apart from each other. The interlayer insulating pattern 305 may cover the ends of two adjacent active portions ACT.

[0080] The upper portion of the word line capping pattern 310, the substrate 301, and the device isolation pattern 302 may be partially recessed to form a first recessed region R1. Figure 9 In a top view of FIG, the first recessed region R1 may be mesh-shaped. Sidewalls of the first recessed region R1 may be aligned with sidewalls of the interlayer insulating pattern 305 .

[0081] The bit line BL may be on the interlayer insulating pattern 305. The bit line BL may intersect the word line capping pattern 310 and the word line WL. Figure 9 As shown, the bit lines BL may be parallel to a third direction X3 that intersects the first direction X1 and the second direction X2. Each bit line BL may include a bit line polysilicon pattern 330, a bit line ohmic pattern 331, and a bit line metal-containing pattern 332 stacked sequentially. The bit line polysilicon pattern 330 may include polysilicon doped or undoped with a dopant. The bit line ohmic pattern 331 may include a metal silicide layer. The bit line metal-containing pattern 332 may include at least one of a metal (e.g., tungsten, titanium, or tantalum) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride). A bit line capping pattern 337 may be on each bit line BL. The bit line capping pattern 337 may be formed of an insulating material. For example, the bit line capping pattern 337 may include at least one of a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride).

[0082] The bit line contact DC may be in the first recessed region R1 intersecting the bit line BL. The bit line contact DC may include polysilicon doped or undoped with a dopant. Figure 10 In the BB' cross section of FIG, the sidewall of the bit line contact DC may be in contact with the sidewall of the interlayer insulating pattern 305. Figure 9 In a top view of FIG, a sidewall of the bit line contact DC contacting the interlayer insulating pattern 305 may be concave. The bit line contact DC may electrically connect the first doping region 312a to the bit line BL.

[0083] The lower filling insulating pattern 341 may be in the first recess region R1 where the bit line contact DC is not disposed. The lower filling insulating pattern 341 may be formed of a single layer or multiple layers including at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0084] A storage node contact (or contact plug) BC may be provided between a pair of adjacent bit lines BL. The storage node contacts BC may be spaced apart from each other. The storage node contacts BC may include polysilicon doped or undoped with a dopant. The top surface of the storage node contact BC may be concave. An insulating pattern (not shown) may be provided between the storage node contacts BC between the bit lines BL.

[0085] A bit line spacer SP may be provided between the bit line BL and the storage node contact BC. The bit line spacer SP may include a first subspacer 321 and a second subspacer 325 separated from each other by a gap region GP. The gap region GP may be referred to as an air gap region. The first subspacer 321 may cover the sidewalls of the bit line BL and the sidewalls of the bit line capping pattern 337. The second subspacer 325 may be adjacent to the storage node contact BC. The first subspacer 321 and the second subspacer 325 may include the same material. For example, the first subspacer 321 and the second subspacer 325 may include silicon nitride.

[0086] The bottom surface of the second subspacer 325 may be lower than the bottom surface of the first subspacer 321. The height of the top of the second subspacer 325 may be lower than the height of the top of the first subspacer 321. Therefore, the margin of the subsequent process of forming the positioning pad (landing pad) LP can be increased. As a result, the disconnection between the positioning pad LP and the storage node contact BC can be prevented. The first subspacer 321 can extend to cover the sidewalls of the bit line contact DC and the sidewalls and bottom surface of the first recessed region R1. In other words, the first subspacer 321 can be between the bit line contact DC and the lower fill insulating pattern 341, between the word line cover pattern 310 and the lower fill insulating pattern 341, between the substrate 301 and the lower fill insulating pattern 341, and between the device isolation pattern 302 and the lower fill insulating pattern 341.

[0087] The storage node ohmic layer 309 may be formed on the storage node contact BC. The storage node ohmic layer 309 may include a metal silicide. A diffusion barrier pattern 311a may conformally cover the storage node ohmic layer 309, the first subspacer 321, the second subspacer 325, and the bit line capping pattern 337. The diffusion barrier pattern 311a may include a metal nitride such as titanium nitride or tantalum nitride. A positioning pad LP may be formed on the diffusion barrier pattern 311a. The positioning pad LP may be formed of a metal-containing material such as tungsten and may be referred to as a conductive pattern. The upper portion of the positioning pad LP may cover the top surface of the bit line capping pattern 337 and may have a width greater than that of the storage node contact BC. The center of the positioning pad LP may be offset from the center of the storage node contact BC in the second direction X2. A portion of the bit line BL may vertically overlap the positioning pad LP. One upper sidewall of the bit line capping pattern 337 may overlap the positioning pad LP and may be covered by the third subspacer 327. The second recess region R2 may be formed at the other upper sidewall of the bit line capping pattern 337 .

[0088] The positioning pad LP may include a first positioning pad LP1 and a second positioning pad LP2 adjacent to each other. The first positioning pad LP1 may have a first upper sidewall sw1 adjacent to the second positioning pad LP2. The second positioning pad LP2 may have a second upper sidewall sw2 adjacent to the first upper sidewall sw1. The first covering pattern 358a may cover the first and second upper sidewalls sw1 and sw2 and may connect the first and second upper sidewalls sw1 and sw2. The first covering pattern 358a may have a substantially uniform thickness. The first covering pattern 358a may have or define a third recessed region R3 between the first and second positioning pads LP1 and LP2. The third recessed region R3 may be filled with a second covering pattern 360a. The first covering pattern 358a and the second covering pattern 360a may each independently include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The porosity of the first covering pattern 358a may be greater than the porosity of the second covering pattern 360a. Top surfaces of the first capping pattern 358 a and the second capping pattern 360 a may be coplanar with the top surface of the capture pad LP.

[0089] A gap region GP between the first subspacer 321 and the second subspacer 325 may extend between the first positioning pad LP1 and the second positioning pad LP2. The bottom surface of the first capping pattern 358a may be exposed through the gap region GP. The gap region GP may extend toward the diffusion barrier pattern 311a. In other words, the sidewalls of the diffusion barrier pattern 311a between the second positioning pad LP2 and the bit line capping pattern 337 may be recessed. The top surface of the bit line capping pattern 337 and the bottom surface of the second positioning pad LP2 may be partially exposed through the gap region GP.

[0090] The data storage pattern DS may be on the positioning pad LP. The data storage pattern DS may be a lower electrode of a capacitor, or may be a phase change material pattern, a variable resistance material pattern, or a magnetic tunnel junction pattern.

[0091] In a semiconductor device according to an embodiment of the present inventive concept, the gap region GP may not be closed at the top ends of the first subspacer 321 and the second subspacer 325, but may extend between the capture pads LP. Therefore, the space of the gap region GP between the first subspacer 321 and the second subspacer 325 can be stably secured. The dielectric constant of the air, gas, or vacuum in the gap region GP can be lower than that of silicon oxide, thereby reducing the parasitic capacitance between the bit line BL and the storage node contact BC. Furthermore, the parasitic capacitance between the capture pads LP can be reduced. As a result, the reliability of the semiconductor device can be improved.

[0092] Figures 11A to 11M is a diagram illustrating the manufacturing of a device having a Figure 10 A cross-sectional view of a semiconductor device of the method of the cross section.

[0093] Reference Figure 11A , a device isolation pattern 302 may be formed in the substrate 301 to define an active portion ACT. A device isolation trench may be formed in the substrate 301, and the device isolation pattern 302 may fill the device isolation trench. The active portion ACT and the device isolation pattern 302 may be patterned to form a recess. At this time, the etching recipes for the substrate 301 and the device isolation pattern 302 may be adjusted so that the device isolation pattern 302 is etched more than the substrate 301. As a result, the bottom surface of the recess may be uneven.

[0094] Word lines WL may be formed in the grooves, respectively. A pair of word lines WL may intersect each active portion ACT. Figure 9 As shown, each active portion ACT may be divided into a first source / drain region SDR1 and a pair of second source / drain regions SDR2 by a pair of word lines WL. The first source / drain region SDR1 may be defined between the pair of word lines WL, and the pair of second source / drain regions SDR2 may be defined in two edge regions of each active portion ACT.

[0095] A gate dielectric layer 107 may be formed on the inner surface of the groove before forming the word line WL. The gate dielectric layer 107 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, and / or an atomic layer deposition (ALD) process. A gate conductive layer may be formed to fill the groove, and an etch-back process may be performed on the gate conductive layer to form the word line WL. The top surface of the word line WL may be recessed to be lower than the top surface of the active portion ACT. An insulating layer (e.g., a silicon nitride layer) may be formed on the substrate 301 to fill the groove, and then the insulating layer may be etched to form word line capping patterns 310 on the word lines WL, respectively.

[0096] Reference Figure 11B , dopants may be implanted into the active portion ACT using the word line capping pattern 310 and the device isolation pattern 320 as masks, thereby forming a first doping region 312a and a second doping region 312b. The first doping region 312a and the second doping region 312b may be formed at Figure 11AThe first source / drain region SDR1 and the second source / drain region SDR2 are formed in the substrate 301. An insulating layer and a first polysilicon layer may be sequentially stacked on the entire surface of the substrate 301. The first polysilicon layer may be patterned to form a polysilicon mask pattern 330a. The polysilicon mask pattern 330a may be used as an etching mask to etch the insulating layer, the device isolation pattern 302, the substrate 301, and the word line capping pattern 310 to simultaneously form a first recessed region R1 and an interlayer insulating pattern 305. The interlayer insulating pattern 305 may have a plurality of island shapes spaced apart from each other. The interlayer insulating pattern 305 may cover the ends of two active portions ACT adjacent to each other. When viewed in a top view, the first recessed region R1 may have a mesh shape. The first recessed region R1 may expose the first doped region 312a.

[0097] Reference Figure 11C A second polysilicon layer 329 may be formed over the entire surface of the substrate 301 to fill the first recessed region R1. A planarization etching process may be performed on the second polysilicon layer 329 to remove the second polysilicon layer 329 on the polysilicon mask pattern 330a and expose the top surface of the polysilicon mask pattern 330a. A bitline ohmic layer 331a, a bitline metal-containing layer 332a, and a bitline capping layer 337a may be sequentially stacked on the polysilicon mask pattern 330a and the second polysilicon layer 329. The bitline ohmic layer 331a may be formed of a metal silicide, such as cobalt silicide. A metal layer may be deposited on the polysilicon mask pattern 330a and the second polysilicon layer 329, and then a heat treatment process may be performed to react the metal layer with the polysilicon of the polysilicon mask pattern 330a and the second polysilicon layer 329, thereby forming a metal silicide. Thereafter, the unreacted metal layer may be removed to form the bitline ohmic layer 331a.

[0098] A first mask pattern 339 defining a planar shape of the bit line BL may be formed on the bit line capping layer 337a. The first mask pattern 339 may be formed by referring to Figures 4A to 4H The first mask pattern 339 may be formed by the method described above. The first mask pattern 339 may be formed of a material having an etching selectivity relative to the bit line cap layer 337a (e.g., an amorphous carbon layer (ACL), a silicon oxide layer, or a photoresist layer). The first mask pattern 339 may extend in a third direction X3 intersecting the first direction X1 and the second direction X2.

[0099] Reference Figure 11D, the bit line capping layer 337a, the bit line metal-containing layer 332a, the bit line ohmic layer 331a, the polysilicon mask pattern 330a, and the second polysilicon layer 329 can be sequentially etched using the first mask pattern 339 as an etching mask to form a bit line BL, a bit line contact DC, and a bit line capping pattern 337. Each bit line BL may include a bit line polysilicon pattern 330, a bit line ohmic pattern 331, and a bit line metal-containing pattern 332. In addition, the top surface of the interlayer insulating pattern 305 and the inner sidewalls and bottom surface of the first recessed region R1 may be partially exposed. The first mask pattern 339 may be removed.

[0100] Reference Figure 11E , a first sub-spacer layer can be conformally formed on the entire surface of the substrate 301. The first sub-spacer layer can conformally cover the bottom surface and inner sidewalls of the first recessed region R1. The first sub-spacer layer can be, for example, a silicon nitride layer. An insulating layer (for example, a silicon nitride layer) can be formed on the entire surface of the substrate 301 to fill the first recessed region R1, and then an anisotropic etching process can be performed on the insulating layer to form a lower filling insulating pattern 341 in the first recessed region R1. At this time, the first sub-spacer layer can also be etched by an anisotropic etching process, so that a first sub-spacer 321 can be formed. In addition, the top surface of the interlayer insulating pattern 305 can be exposed. A sacrificial spacer layer can be conformally stacked on the entire surface of the substrate 301, and then an anisotropic etching process can be performed on the sacrificial spacer layer to form a sacrificial spacer 323 covering the sidewalls of the first sub-spacer 321. The sacrificial spacer 323 may include a material having an etching selectivity relative to the first sub-spacer 321. The sacrificial spacer 323 can be made of, for example, a material having an etching selectivity relative to the first sub-spacer 321. Figure 2 The heat decomposable layer described above is formed. The second sub-spacer 325 may be formed to cover the sidewalls of the sacrificial spacer 323. The second sub-spacer 325 may be formed of, for example, a silicon nitride layer. The top surface of the interlayer insulating pattern 305 may be exposed after the second sub-spacer 325 is formed.

[0101] Reference Figure 11E and Figure 11F, a polysilicon layer can be stacked on the entire surface of the substrate 301 to fill the space between the bit lines BL. The polysilicon layer can be etched to form a preliminary storage node contact 350 and expose the upper portions of the first subspacer 321, the sacrificial spacer 323, and the second subspacer 325. The upper portions of the sacrificial spacer 323 and the second subspacer 325 can be removed so that the height of the top ends of the sacrificial spacer 323 and the second subspacer 325 is similar to the height of the top surface of the preliminary storage node contact 350. Therefore, the upper sidewall of the first subspacer 321 can be exposed. These processes can increase the process margin of the subsequent process of forming the positioning pad. When the upper portions of the sacrificial spacer 323 and the second subspacer 325 are removed, the upper portion of the first subspacer 321 can also be partially removed, so that the width of the upper portion of the first subspacer 321 can be reduced.

[0102] Reference Figure 11F and Figure 11G A third subspacer layer may be conformally formed over the entire surface of substrate 301 and anisotropically etched to form third subspacers 327 covering the exposed upper sidewalls of first subspacers 321. The lower portion of third subspacers 327 may cover the exposed top ends of sacrificial spacers 323. Preliminary storage node contacts 350 may be etched to expose the upper sidewalls of second subspacers 325 and form storage node contacts BC. Third subspacers 327 can compensate for damaged upper portions of first subspacers 321 and cover sacrificial spacers 323, preventing the etchant used in the process of forming storage node contacts BC and the cleaning solution from the subsequent cleaning process from penetrating into bit lines BL. This prevents damage to bit lines BL. A cleaning process may be performed to clean the top surfaces of storage node contacts BC. A metal silicide process may be performed on the top surfaces of storage node contacts BC to form storage node ohmic layers 309. A diffusion barrier layer 311 may be conformally formed over the entire surface of substrate 301. Afterwards, a positioning pad layer 352 may be formed on the entire surface of the substrate 301 to fill the space between the bit line capping patterns 337. The positioning pad layer 352 may include, for example, tungsten. A second mask pattern 340 may be formed on the positioning pad layer 352. The second mask pattern 340 may be formed using a reference pattern. Figures 1A to 1H or Figure 3 The second mask pattern 340 may be formed by the method described above. The second mask pattern 340 may be formed of, for example, an amorphous carbon layer (ACL). The second mask pattern 340 may define the position of the positioning pad. The second mask pattern 340 may vertically overlap with the storage node contact BC. The second mask pattern 340 may have an island shape spaced apart from each other.

[0103] Reference Figure 11HAn anisotropic etching process of removing a portion of the positioning pad layer 352 may be performed using the second mask pattern 340 as an etching mask to simultaneously form the positioning pad LP and the opening 354 exposing the diffusion barrier layer 311 .

[0104] Reference Figure 11I , the diffusion barrier layer 311 exposed through the opening 354 may be removed by an isotropic etching process to form diffusion barrier patterns 311 a separated from each other and expose a portion of the top surfaces of the bit line capping pattern 337 and the third subspacer 327. At this time, the diffusion barrier pattern 311 a may be over-etched by the isotropic etching process so that the bottom surface of the positioning pad LP may be partially exposed.

[0105] Reference Figure 11I and Figure 11J An anisotropic etching process may be performed to remove the bit line capping pattern 337 and portions of the third subspacer 327 exposed by the opening 354, thereby exposing the sacrificial spacer 323. At this time, a second recess region R2 may be formed on the bit line capping pattern 337.

[0106] Reference Figure 11K , the second mask pattern 340 can be removed. Figure 2 The thermal decomposable layer 356 may be formed to fill the opening 354 and the second recessed region R2 by the method described above. The thermal decomposable layer 356 may also be formed on the positioning pad LP. The thermal decomposable layer 356 may be in contact with the sacrificial spacer 323. The thermal decomposable layer 356 may be formed in the manner described above. Figures 6 to 8 The semiconductor manufacturing apparatus 200 or 201 is formed in the thermally decomposable layer deposition chamber 120 .

[0107] Reference Figure 11L , a first annealing process may be performed to remove the upper portion of the thermally decomposable layer 356, thereby exposing the top surface and upper sidewalls of the positioning pad LP and forming thermally decomposable patterns 356a spaced apart from each other. A first capping layer 358 may be conformally formed on the thermally decomposable patterns 356a and the positioning pad LP. Figure 6 in the annealing chamber 130 or Figure 8 The first annealing process is performed in the first annealing chamber 130a. Figure 6 The capping layer deposition chamber 140 or Figure 8 The first capping layer 358 is deposited in the first capping layer deposition chamber 140 a.

[0108] Reference Figure 11M , a second annealing process may be performed to remove the thermally decomposable pattern 356a and the sacrificial spacer 323 and form a gap region GP. Figure 6 Annealing chamber 130 or Figure 8A second annealing process is performed in the second annealing chamber 130b. Next, a second capping layer 360 may be formed on the first capping layer 358. Figure 6 The capping layer deposition chamber 140 or Figure 8 The second capping layer 360 is deposited in the second capping layer deposition chamber 140b. Figure 10 An etch-back process or a chemical mechanical polishing (CMP) process may be performed to remove the first capping layer 358 and the second capping layer 360 on the positioning pad LP, thereby exposing the positioning pad LP. Next, a data storage pattern DS connected to the positioning pad LP may be formed.

[0109] 12A to 12C is a diagram illustrating the manufacturing of a device having a Figure 10 A cross-sectional view of a semiconductor device of the method of the cross section.

[0110] Reference Figure 12A , the sacrificial spacer 323c may be a sacrificial material other than a thermally decomposable polymer. The sacrificial spacer 323c may be formed of, for example, a silicon oxide layer. Figure 11J As described, an anisotropic etching process may be performed to expose top surfaces of the sacrificial spacers 323 c .

[0111] Reference Figure 12B and Figure 12C , the sacrificial spacer 323c exposed by the opening 354 may be removed to form a second gap region GP2 between the first sub-spacer 321 and the second sub-spacer 325. Thereafter, a thermally decomposable layer 356 may be formed on the positioning pad LP. The thermally decomposable layer 356 may not fill the second gap region GP2 between the first sub-spacer 321 and the second sub-spacer 325. Subsequently, a reference may be performed. Figure 11L and Figure 11M The process described above. In other words, a thermally decomposable pattern 356a may be formed between the positioning pads LP. Subsequently, a first capping layer 358 may be formed, and then the thermally decomposable pattern 356a may be removed to form a gap region GP between the positioning pads LP. The gap region GP between the positioning pads LP may be connected to the second gap region GP2 between the first subspacer 321 and the second subspacer 325.

[0112] The method for manufacturing a semiconductor device according to the present invention can use a thermally decomposable layer, thereby reducing process failures. In addition, the semiconductor manufacturing apparatus according to the present invention can reduce the total process time. In addition, the semiconductor device according to the present invention can have improved reliability.

[0113] Although the present invention has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are illustrative rather than restrictive. Therefore, the scope of the present invention is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be limited or defined by the foregoing description.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming an etching target layer on a substrate; forming thermally decomposable patterns spaced apart from each other on the etch target layer; forming a first mask layer filling spaces between the thermally decomposable patterns and covering top surfaces of the thermally decomposable patterns; removing the thermally decomposable pattern by heating; as well as An upper portion of the first mask layer is removed after removing the thermally decomposable pattern to form a first mask pattern.

2. The method according to claim 1, wherein Forming the first mask layer includes: coating the thermally decomposable pattern with a spin-on hard mask composite; and baking the spin-on hard mask composite, wherein the thermally decomposable pattern is removed during the baking of the spin-on hard mask composite.

3. The method according to claim 1, further comprising: before forming the thermally decomposable pattern, forming a second mask layer on the etching target layer, Wherein, removing the thermally decomposable pattern includes exposing a top surface of the second mask layer.

4. The method according to claim 3, further comprising: etching the second mask layer using the first mask pattern as a first etch mask to form a second mask pattern; and The etch target layer is etched using the second mask pattern as a second etch mask.

5. The method according to claim 1, wherein Forming the thermally decomposable pattern comprises: forming a thermally decomposable layer by reacting a first monomer and a second monomer on the etch target layer; forming a second mask pattern on the thermally decomposable layer; and The thermally decomposable layer is etched using the second mask pattern as an etch mask.

6. A method for manufacturing a semiconductor device, the method comprising: forming an etching target layer on a substrate; forming thermally decomposable patterns spaced apart from each other on the etch target layer; forming a first mask layer covering the thermally decomposable pattern; removing an upper portion of the first mask layer to form a first mask pattern covering a sidewall of the thermally decomposable pattern; and The thermally decomposable pattern is removed by a heating method to expose sidewalls of the first mask pattern.

7. The method according to claim 6, further comprising: before forming the thermally decomposable pattern, forming a second mask layer on the etching target layer, Wherein, removing the thermally decomposable pattern includes exposing a top surface of the second mask layer.

8. The method according to claim 7, further comprising: etching the second mask layer using the first mask pattern as a first etch mask to form a second mask pattern; and The etch target layer is etched using the second mask pattern as a second etch mask.

9. The method according to claim 6, wherein: The first mask layer conformally covers the thermally decomposable pattern, and removing an upper portion of the first mask layer is performed by performing an anisotropic etching process on the first mask layer, The width of the upper portion of the first mask pattern is smaller than the width of the lower portion of the first mask pattern.

10. The method according to claim 6, wherein: Forming the thermally decomposable pattern comprises: forming a thermally decomposable layer by reacting a first monomer and a second monomer on the etch target layer; forming a second mask pattern on the thermally decomposable layer; and The thermally decomposable layer is etched using the second mask pattern as an etch mask.

11. A method for manufacturing a semiconductor device, the method comprising: forming conductive patterns spaced apart from each other on a substrate; forming a thermally decomposable layer filling spaces between the conductive patterns and covering the conductive patterns; forming a thermally decomposable pattern by removing an upper portion of the thermally decomposable layer, the thermally decomposable pattern partially filling a space between the conductive patterns and exposing upper sidewalls of the conductive patterns; conformally forming a first covering layer covering the conductive pattern and the thermally decomposable pattern; removing the thermally decomposable pattern to form a first gap region exposing a lower sidewall of the conductive pattern; and A second covering layer is formed on the first covering layer.

12. The method according to claim 11, wherein The first cover layer is thinner than the second cover layer.

13. The method according to claim 11, further comprising: removing the first covering layer and the second covering layer on the conductive pattern to expose a top surface of the conductive pattern; and An upper conductive pattern is formed to contact the conductive pattern.

14. The method according to claim 11, before forming the conductive pattern, further comprising: forming word lines extending in a first direction and parallel to each other in the substrate; forming a first doping region and a second doping region spaced apart from each other in the substrate between the word lines; forming a bit line on the substrate, the bit line being electrically connected to the first doped region and extending in a second direction intersecting the first direction; and Contact plugs are formed between the bit lines to electrically connect the second doped regions to the conductive patterns.

15. The method according to claim 14, further comprising: Before forming the contact plug, forming a bit line covering pattern on the bit line; After forming the contact plug and before forming the conductive pattern, forming a diffusion barrier layer covering a top surface of the contact plug and the bit line covering pattern; and after forming the conductive pattern and before forming the thermally decomposable pattern, removing the diffusion barrier layer that does not overlap with the conductive pattern, The removing of the diffusion barrier layer includes exposing a portion of a bottom surface of the conductive pattern on the bit line capping pattern.

16. The method according to claim 14, further comprising: Before forming the conductive pattern, forming a bit line spacer covering a sidewall of the bit line and including a sacrificial spacer; and After forming the conductive pattern and before forming the thermally decomposable pattern, upper portions of the sacrificial spacers are exposed.

17. The method according to claim 16, further comprising: before forming the thermally decomposable pattern, removing the sacrificial spacer to form a second gap region, wherein the top end of the second gap region is closed when the thermally decomposable pattern is formed, and Wherein, when the thermally decomposable pattern is removed to form the first gap region, the first gap region and the second gap region are connected to each other.

18. The method according to claim 16, wherein The sacrificial spacer comprises a thermally decomposable material, When forming the thermally decomposable pattern, the thermally decomposable pattern is in contact with the sacrificial spacer, and When the thermally decomposable pattern is removed, the sacrificial spacers are simultaneously removed.

19. The method according to claim 11, wherein The formation of the thermally decomposable layer comprises: reacting the first monomer and the second monomer with each other to form a polymer, wherein removing the upper portion of the thermally decomposable layer is performed by a first annealing process, and Wherein, removing the thermally decomposable pattern is performed through a second annealing process.

20. A semiconductor manufacturing apparatus comprising: transfer room; at least one thermally decomposable layer deposition chamber connected to the transfer chamber and configured to deposit a thermally decomposable layer formed of a polymer by supplying a first monomer and a second monomer; at least one annealing chamber connected to the transfer chamber and configured to decompose the thermally decomposable layer; and At least one capping layer deposition chamber is connected to the transfer chamber and configured to deposit a capping layer.

21. The semiconductor manufacturing apparatus according to claim 20, further comprising: a first monomer storage container connected to the thermally decomposable layer deposition chamber and configured to store the first monomer; a first evaporator configured to evaporate the first monomer; a second monomer storage container connected to the thermally decomposable layer deposition chamber and configured to store the second monomer; and A second evaporator is configured to evaporate the second monomer.

22. The semiconductor manufacturing apparatus according to claim 20, wherein: The at least one annealing chamber is configured to decompose the thermally decomposable layer at a first temperature, and the at least one blanket layer deposition chamber being configured to maintain a second temperature, The second temperature is lower than the first temperature.

23. The semiconductor manufacturing apparatus according to claim 20, wherein: The at least one annealing chamber is configured to decompose the thermally decomposable layer at a first temperature, and the at least one thermally decomposable layer deposition chamber being configured to maintain a second temperature, The second temperature is lower than the first temperature.

24. The semiconductor manufacturing apparatus according to claim 20, wherein The at least one annealing chamber is configured to decompose the thermally decomposable layer at a first temperature, and the at least one annealing chamber being configured to maintain a second temperature, The second temperature is higher than the first temperature.

25. A semiconductor device comprising: A first conductive pattern and a second conductive pattern adjacent to each other on a substrate, wherein the first conductive pattern has a first upper sidewall adjacent to the second conductive pattern, and the second conductive pattern has a second upper sidewall adjacent to the first upper sidewall; a first cover layer contacting the first upper sidewall and the second upper sidewall and connecting the first upper sidewall and the second upper sidewall to provide a gap region between the first conductive pattern and the second conductive pattern, the first cover layer defining a recessed region thereon; and A second covering layer fills the recessed area.

26. The semiconductor device according to claim 25, wherein Top surfaces of the first and second cover layers are coplanar with top surfaces of the first and second conductive patterns.

27. The semiconductor device according to claim 25, further comprising: a bit line capping pattern located between the substrate and the second conductive pattern; and a diffusion barrier pattern located between the bit line capping pattern and the second conductive pattern, The gap region extends to the diffusion barrier pattern to expose a portion of a bottom surface of the second conductive pattern and a portion of a top surface of the bit line capping pattern at a side of the diffusion barrier pattern.

28. The semiconductor device according to claim 27, further comprising: a bit line located between the bit line capping pattern and the substrate; a contact plug located between the first conductive pattern and the substrate; and a bit line spacer located between the contact plug and the bit line, Wherein, the bit line spacer comprises: a first subspacer in contact with the bit line; and a second sub-spacer in contact with the contact plug, The gap region extends between the first sub-spacer and the second sub-spacer.

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