Semiconductor device including air spacer and method of manufacturing the same

Abstract

A semiconductor device is provided that includes a substrate that includes a trench. A first conductive pattern is disposed within the trench. The first conductive pattern has a width that is less than a width of the trench. A first spacer extends along at least a portion of a side surface of the first conductive pattern and the trench. A second spacer at least partially fills the trench adjacent to the first spacer. An air spacer is provided that includes a first portion between the first spacer and the second spacer, and a second portion disposed on the second spacer and the first portion. A width of the second portion of the air spacer is greater than a width of the first portion of the air spacer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0070413, filed on June 14, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including an air spacer and a method for manufacturing the same. Background Technology

[0004] As the integration of semiconductor devices continues to increase, discrete circuit patterns are further miniaturized to realize more semiconductor devices in the same area, thereby increasing density.

[0005] As the integration density of semiconductor memory devices increases, parasitic capacitance and leakage current may increasingly degrade performance. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a semiconductor device including a substrate having trenches is provided. A first conductive pattern is disposed within the trenches. The first conductive pattern has a width smaller than the width of the trenches. A first spacer extends along at least a portion of a side surface of the first conductive pattern and the trenches. A second spacer at least partially fills the trenches adjacent to the first spacer. An air spacer is provided, comprising a first portion located between the first spacer and the second spacer, and a second portion disposed on the second spacer and the first portion. The width of the second portion of the air spacer is greater than the width of the first portion of the air spacer.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device including a substrate having trenches is provided. A conductive pattern is disposed within the trenches. The conductive pattern has a width smaller than the width of the trench. A first spacer extends along at least a portion of a side surface of the conductive pattern and the trench. A second spacer at least partially fills the trench and is disposed on the first spacer. An air spacer is provided, comprising a first portion located between the first spacer and the second spacer, and a second portion disposed on the second spacer and the first portion. The first spacer includes a lower spacer located between the conductive pattern and the first portion of the air spacer, and an upper spacer located between the conductive pattern and the second portion of the air spacer. The width of the upper spacer of the first spacer is smaller than the width of the lower spacer of the first spacer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device comprising a substrate having trenches is provided. A conductive pattern is disposed within the trenches. The conductive pattern has a width smaller than the width of the trench. A first spacer extends along at least a portion of a side surface of the conductive pattern and the trench. An air spacer is displaced from the conductive pattern by the first spacer, the air spacer extending along at least a portion of the first spacer. The air spacer has a T-shaped cross-section, and a portion of the air spacer is formed within the trench. Attached Figure Description

[0009] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention;

[0011] Figure 2 It is along the exemplary embodiment of the concept of the present invention. Figure 1 A cross-sectional view taken from line A-A';

[0012] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This illustrates an exemplary embodiment of the concept according to the present invention. Figure 2 Various magnified views of the R1 region;

[0013] Figure 4 It is along the exemplary embodiment of the concept of the present invention. Figure 1 A cross-sectional view taken from line B-B'; and

[0014] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 This is a cross-sectional view illustrating various stages of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0015] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0016] Figure 2 is a cross-sectional view taken along line A-A' of the exemplary embodiment according to the inventive concept. Figure 1 Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are various enlarged views of the R1 region of Figure 2 Figure 4 is a cross-sectional view taken along line B-B' of the exemplary embodiment according to the inventive concept. Figure 1

[0017] Referring to Figure 1 , Figure 2 , FIG. 3, and Figure 4 , a semiconductor device according to an exemplary embodiment of the inventive concept includes a substrate 100, a device isolation film 110, a base insulating film 120, a bit line structure 130, a word line structure 160, a spacer structure 140, a direct contact DC, a contact structure 150, an interlayer insulating film 180, and a capacitor structure 190.

[0018] The substrate 100 can include a base substrate and an epitaxial layer, one of which is stacked on top of the other, but the inventive concept is not limited thereto. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor-on-insulator (SOI) substrate. For example, the substrate 100 as described below can be a silicon substrate.

[0019] The substrate 100 can include active regions AR. As the design rule of a semiconductor device decreases, the active regions AR can be formed in a diagonal bar shape. For example, as shown in Figure 1 , the active regions AR can be bars extending in a direction different from the first direction (e.g., the X direction) and the second direction (e.g., the Y direction) (e.g., a diagonal direction) on a plane extending in the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).

[0020] The active regions AR can be a plurality of bars extending in parallel to each other in a horizontal direction. In addition, a center of one of the plurality of active regions AR can be disposed adjacent to an end portion of another active region AR. For example, the end portions of the adjacent active regions AR can overlap in the first direction (e.g., the X direction) and can be staggered with respect to each other.

[0021] ​​​The active region AR can function as a source region and a drain region by including an impurity. According to an exemplary embodiment of the inventive concept, a center of the active region AR can be in contact with the bit line structure 130 through the direct contact DC, and both ends of the active region AR can be in contact with the capacitor structure 190 through the contact structure 150.

[0022] The device isolation film 110 can define a plurality of active regions AR. Although a side surface of the device isolation film 110 is shown as having a slope in FIGS. 1A and 1B, the inventive concept is not limited thereto. Figure 2 and Figure 4 Although a side surface of the device isolation film 110 is shown as having a slope in FIGS. 1A and 1B, the inventive concept is not limited thereto.

[0023] The device isolation film 110 can include silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto. The device isolation film 110 can be a single layer film formed of one type of insulating material or a multi-layer film formed of a combination of various types of insulating materials.

[0024] The base insulating film 120 can be formed on the substrate 100 and the device isolation film 110. According to an exemplary embodiment of the inventive concept, the base insulating film 120 can extend along an upper surface of the substrate 100 and an upper surface of the device isolation film 110 in regions where the direct contact DC and the buried contact BC are not formed.

[0025] The base insulating film 120 can be a single layer film, but can also be a multi-layer film as shown. For example, the base insulating film 120 can include a first insulating film 122, a second insulating film 124, and a third insulating film 126 stacked in sequence on the substrate 100.

[0026] For example, the first insulating film 122 can include silicon oxide. The second insulating film 124 can include a material having an etching selectivity different from that of the first insulating film 122. For example, the second insulating film 124 can include silicon nitride. The third insulating film 126 can include a material having a dielectric constant smaller than that of the second insulating film 124. For example, the third insulating film 126 can include silicon oxide.

[0027] The bit line structure 130 can be formed on the substrate 100, the device isolation film 110, and the base insulating film 120. The bit line structure 130 can extend longitudinally across the active region AR and the word line structure 160 in a second direction (e.g., Y direction). For example, the bit line structure 130 can obliquely traverse the active region AR, and orthogonally traverse the word line structure 160. A plurality of bit line structures 130 can be spaced apart in a first direction (e.g., X direction). For example, a plurality of bit line structures 130 can be formed spaced apart at the same pitch.

[0028] According to exemplary embodiments of the inventive concept, the first conductive pattern can include a bit line structure 130 and a direct contact DC. The bit line structure 130 can include at least two conductive films 132, 134, and 136 and a first cap pattern 138 sequentially stacked on the substrate 100.

[0029] The conductive films 132, 134, and 136 can be single-layer films, but can also be multi-layer films, as shown. For example, the conductive films of the bit line structure 130 can include a first conductive film 132, a second conductive film 134, and a third conductive film 136 sequentially stacked on the substrate 100.

[0030] The first conductive film 132, the second conductive film 134, and the third conductive film 136 can each include, for example, polysilicon, titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten, tungsten silicide, or a combination thereof, but the inventive concept is not limited thereto. For example, the first conductive film 132 can include polysilicon, the second conductive film 134 can include TiSiN, and the third conductive film 136 can include tungsten.

[0031] The first cap pattern 138 can be formed on the first to third conductive films 132, 134, and 136. For example, the first cap pattern 138 can be formed on the third conductive film 136. The first cap pattern 138 can include silicon nitride, but the inventive concept is not limited thereto.

[0032] The direct contact DC can connect the active region AR of the substrate 100 with the bit line structure 130 by penetrating the base insulating film 120. For example, the second conductive film 134 and the third conductive film 136 of the corresponding bit line structure 130 can be disposed on an upper surface of the direct contact DC, while the direct contact DC penetrates the first conductive film 132 and the first conductive film 132 surrounds a sidewall of the direct contact DC. The substrate 100 can include a first trench T1. The first trench T1 can expose at least a portion of the active region AR by penetrating the base insulating film 120. The direct contact DC can be formed in the first trench T1 and can connect the active region AR of the substrate 100 with the first to third conductive films 132, 134, and 136. For example, the direct contact DC can have a lower surface disposed below the lowermost first insulating film 122 and exposed to the active region AR. The direct contact DC can extend from a bottom of the first trench T1 to a lower surface of the second conductive film 134 in a thickness direction orthogonal to a plane of an upper surface of the substrate 100.

[0033] According to exemplary embodiments of the inventive concept, as Figure 1As shown, the first trench T1 can expose a center of the active region AR. Accordingly, the direct contact DC can be in contact with the center of the active region AR. For example, in a plan view, the center of the active region AR can have a staggered arrangement with respect to each other. According to an exemplary embodiment of the inventive concept, a portion of the first trench T1 can overlap a portion of the device isolation film 110. Accordingly, the first trench T1 can expose a portion of the device isolation film 110 as well as a portion of the substrate 100.

[0034] The direct contact DC can include an electrically conductive material. Accordingly, the first to third electrically conductive films 132, 134, and 136 of the bit line structure 130 can be in electrical contact with the active region AR of the substrate 100. The active region AR of the substrate 100 in contact with the first to third electrically conductive films 132, 134, and 136 and the direct contact DC can function as a source region and a drain region.

[0035] According to an exemplary embodiment of the inventive concept, the direct contact DC can include the same material as that of the first electrically conductive film 132. For example, the direct contact DC can include polysilicon. However, the inventive concept is not limited thereto. According to a manufacturing process, the direct contact DC can include a different material from that of the first electrically conductive film 132.

[0036] According to an exemplary embodiment of the inventive concept, in a first direction (e.g., an X direction), a width of the direct contact DC can be less than a width of the first trench T1. For example, as shown in FIG. 1A, the direct contact DC can have a width WDC in the first direction (e.g., the X direction) that is less than a width WT1 of the first trench T1 in the first direction (e.g., the X direction). Figure 2 As shown, the direct contact DC can overlap only a portion of the substrate 100 exposed by the first trench T1. According to an exemplary embodiment of the inventive concept, a width of the bit line structure 130 can also be less than a width (e.g., a diameter) of the first trench T1. For example, as shown in FIG. 1A, the bit line structure 130 can have a width WBL in the first direction (e.g., the X direction) that is less than the width WT1 of the first trench T1 in the first direction (e.g., the X direction). Figure 2 As shown, in a first direction (e.g., an X direction), a width of the bit line structure 130 can be substantially the same as a width of the direct contact DC.

[0037] The word line structure 160 can cross the active region AR and the bit line structure 130 and extend along a first direction (e.g., an X direction). For example, as shown in FIG. 1A, the word line structure 160 can cross the active region AR obliquely and the bit line structure 130 orthogonally. Figure 1 As shown, the word line structure 160 can cross the active region AR obliquely and the bit line structure 130 orthogonally. A plurality of word line structures 160 can be spaced apart from each other in a second direction (e.g., a Y direction). For example, a plurality of word line structures 160 can be formed to be spaced apart at the same pitch.

[0038] According to an exemplary embodiment of the inventive concept, as shown in FIG. 1A, the word line structure 160 can include a gate dielectric film 162, a second conductive pattern, and a second cap pattern 168. Figure 4 As shown, in a first direction (e.g., an X direction), a width of the bit line structure 130 can be substantially the same as a width of the direct contact DC.

[0039] The second conductive pattern can be a single layer film, but can also be a multi-layer film, as shown. For example, the second conductive pattern can include a fourth conductive film 164 and a fifth conductive film 166 sequentially stacked on the substrate 100. The fourth conductive film 164 and the fifth conductive film 166 can each include, for example, a metal, polysilicon, or a combination thereof, but the inventive concept is not limited thereto.

[0040] A gate dielectric film 162 can be disposed between the second conductive pattern and the substrate 100. For example, the gate dielectric film 162 can include silicon oxide, silicon oxynitride, silicon nitride, and / or a high-k dielectric material having a dielectric constant greater than that of silicon oxide. However, the inventive concept is not limited thereto.

[0041] A second cap pattern 168 can be formed on the second conductive pattern. The second cap pattern 168 can include silicon nitride, but the inventive concept is not limited thereto.

[0042] According to an exemplary embodiment of the inventive concept, the word line structure 160 can be buried within the substrate 100. For example, the substrate 100 can include a fourth trench T4 extending in the first direction (e.g., the X direction). The gate dielectric film 162 can extend along the profile of the fourth trench T4. The fourth conductive film 164 and the fifth conductive film 166 can fill a portion of the fourth trench T4 above the gate dielectric film 162. For example, the fourth conductive film 164 can have a substantially "U"-shaped cross-section and can line a lowermost portion of the fourth trench T4, and the fifth conductive film 166 can fill an interior of the "U"-shaped fourth conductive film 164 and can have an upper surface substantially coplanar therewith. The second cap pattern 168 can fill another portion of the fourth trench T4 above the second conductive pattern. For example, the second cap pattern 168 can have a substantially rectangular shape having a lower surface disposed on the planarized upper surface of the second conductive pattern, an upper surface disposed on the first insulating film 122, and parallel side surfaces disposed on the device insulating film 110 and on a lower portion of the direct contact DC.

[0043] A spacer structure 140 can be formed on a side surface of the bit line structure 130. Further, the spacer structure 140 can extend along the side surface of the bit line structure 130. As shown, the spacer structure 140 can extend longitudinally in the second direction Y. Figure 1

[0044] ​According to an exemplary embodiment of the present inventive concept, a portion of the spacer structure 140 can be in contact with the substrate 100 and the device isolation film 110. For example, in a region where the first trench T1 is formed, a lower portion of the spacer structure 140 can fill the first trench T1. However, in a region where the first trench T1 is not formed, the spacer structure 140 can be formed on the base insulating film 120. According to an exemplary embodiment of the present inventive concept, the spacer structure 140 can have a flat lowermost portion connected to parallel curved side surfaces. The flat lowermost portion can contact the exposed direct contact DC connected to the substrate 100, and the parallel curved side surfaces can contact the corresponding device isolation film 110, an upper surface of which contacts a lower portion of the contact structure 150.

[0045] The spacer structure 140 can include an air spacer 140A. The air spacer 140A can be formed as air or a void. The air spacer 140A can have a dielectric constant less than that of silicon oxide, and can effectively reduce the parasitic capacitance of the semiconductor device according to an exemplary embodiment of the present inventive concept.

[0046] The air spacer 140A can extend along at least a portion of a side surface of the bit line structure 130. In a region where the first trench T1 is not formed, the air spacer 140A can be formed on the base insulating film 120. In a region where the first trench T1 is formed, the air spacer 140A can extend along a side surface of the bit line structure 130 and a side surface of the direct contact DC. For example, as shown in FIG. 1B, the air spacer 140A can include a first portion 140AL and a second portion 140AU. For example, the air spacer 140A can extend in a thickness direction (e.g., a direction orthogonal to a plane of an upper surface of the substrate 100) from a lower portion of the first trench T1, and in a second direction (e.g., the Y direction). Figure 3A

[0047] ​The first portion 140AL of the air spacer 140A can be formed within the first trench T1. For example, the first portion 140AL of the air spacer 140A can extend along a side surface of the direct contact DC. Since the first trench T1 can be formed within the substrate 100, a lowermost surface of the air spacer 140A including the first portion 140AL can be formed lower than an upper surface of the base insulating film 120. According to an exemplary embodiment of the present inventive concept, the first portion 140AL of the air spacer 140A can not extend along the first trench T1. The second portion 140AU of the air spacer 140A can be formed on the first portion 140AL and can include, for example, a stepped interface. The second portion 140AU of the air spacer 140A can extend along a side surface of the bit line structure 130. The second portion 140AU of the air spacer 140A can be connected with the first portion 140AL of the air spacer 140A. In other words, the second portion 140AU of the air spacer 140A can be integrally formed with the first portion 140AL of the air spacer 140A.

[0048] According to an exemplary embodiment of the present inventive concept, as shown in FIG. 1, a width W1U of the second portion 140AU of the air spacer 140A can be greater than a width W1L of the first portion 140AL of the air spacer 140A. Figure 3A

[0049] According to an exemplary embodiment of the present inventive concept, the width W1L of the first portion 140AL of the air spacer 140A can be equal to or greater than about 1 nm and less than about 10 nm. When the width W1L of the first portion 140AL of the air spacer 140A is less than about 1 nm, it can be difficult to form a void within the first portion 140AL of the air spacer 140A in an etching process. For example, the width W1L of the first portion 140AL of the air spacer 140A can be about 0.5 nm to about 1 nm. When the width W1U of the second portion 140AU of the air spacer 140A is greater than about 10 nm, a distance between the direct contact DC and the bit line structure 130 can be increased. For example, the width W1U of the second portion 140AU of the air spacer 140A can be about 10 nm to about 20 nm. and the width W1U of the second portion 140AU of the air spacer 140A can be about 10 nm to about 20 nm. Preferably, the width W1L of the first portion 140AL of the air spacer 140A can be about 1 nm to about 5 nm and the width W1U of the second portion 140AU of the air spacer 140A can be about 5 nm to about 10 nm. Preferably, the width W1L of the first portion 140AL of the air spacer 140A can be about 1 nm to about 5 nm and the width W1U of the second portion 140AU of the air spacer 140A can be about 5 nm to about 10 nm.

[0050] ​​​​​According to exemplary embodiments of the inventive concept, the spacer structure 140 can be a multi-layer film formed in a combination of various types of insulating materials. For example, the spacer structure 140 can further include a first spacer 141, a second spacer 142, a third spacer 143, and a fourth spacer 144.

[0051] The first spacer 141 can extend along at least a portion of a side surface of the bit line structure 130. The first spacer 141 can represent an innermost layer of the spacer structure 140 closest to the direct contact DC and the bit line structure 130, and can at least partially surround a sidewall of the direct contact DC and the bit line structure 130 in a thickness direction. For example, the first spacer 141 can cover a curved sidewall of the first trench T1 and a vertical sidewall of the direct contact DC and the bit line structure 130. In other words, as the first spacer 141 traces around an area occupied by the direct contact DC and the bit line structure 130, the first spacer 141 can line a resulting shape of the first trench T1. In an area where the first trench T1 is not formed, the first spacer 141 can extend along a side surface of the bit line structure 130 and an upper surface of the base insulating film 120. In an area where the first trench T1 is formed, the first spacer 141 can extend along a side surface of the bit line structure 130, a side surface of the direct contact DC, and the first trench T1. For example, as shown, the first spacer 141 can include a lower spacer 141L and an upper spacer 141U. Figure 3A

[0052] The lower spacer 141L can be formed within the first trench T1. For example, the lower spacer 141L can extend along a side surface of the direct contact DC and the first trench T1. The upper spacer 141U can be formed on the lower spacer 141L. For example, the upper spacer 141U can extend along a side surface of the bit line structure 130. The upper spacer 141U can be connected with the lower spacer 141L. That is, the upper spacer 141U can be integrally formed with the lower spacer 141L.

[0053] The first spacer 141 can be disposed between the bit line structure 130, the direct contact DC, and the air spacer 140A. According to exemplary embodiments of the inventive concept, the first spacer 141 can be in contact with the bit line structure 130 and the direct contact DC.

[0054] The first spacer 141 can include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, but the inventive concept is not limited thereto. The following will be exemplarily described below based on an assumption that the first spacer 141 includes silicon nitride.

[0055] ​A second spacer 142 can be formed on the first spacer 141 within the first trench T1. For example, the second spacer 142 can extend along the curved sidewall of the first trench T1, overlap the lower spacer 141L of the first spacer 141, and opposite end portions of the second spacer 142 contact the contact structure 150 and the sidewall of the first portion 140AL of the air spacer 140A. According to an example embodiment of the inventive concept, the second spacer 142 can not extend vertically along the side surface of the direct contact DC.

[0056] According to an example embodiment of the inventive concept, the second spacer 142 can define a lower portion of the air spacer 140A. For example, as shown in FIG. 1B, the second spacer 142 can define a lower portion of the first portion 140AL of the air spacer 140A. Figure 3A

[0057] According to an example embodiment of the inventive concept, a lowermost surface of the second spacer 142 can be disposed on the same plane as a lowermost surface of the air spacer 140A. For example, a lowermost surface of the second spacer 142 can be disposed on the same plane as a lower surface of the first portion 140AL of the air spacer 140A.

[0058] The second spacer 142 can include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, although the inventive concept is not limited thereto. According to an example embodiment of the inventive concept, the second spacer 142 can include a material different from that of the first spacer 141. For example, the second spacer 142 can include a material having a dielectric constant greater than that of the first spacer 141. Alternatively, the second spacer 142 can include a material having an etch selectivity different from that of the first spacer 141. The following will be exemplarily described below based on the assumption that the second spacer 142 includes silicon oxide. A third spacer 143 can fill a portion of the first trench T1. The third spacer 143 can be spaced apart from the first spacer 141 by the air spacer 140A. For example, as shown in FIG. 1B, the first portion 140AL of the air spacer 140A can be disposed between the lower spacer 141L and the third spacer 143. The third spacer 143 can occupy a space defined by the second spacer 142, the first portion 140AL, and a fourth spacer 144. Figure 3A

[0059] According to an example embodiment of the inventive concept, an uppermost surface of the third spacer 143 can be disposed on the same plane as an uppermost surface of the lower spacer 141L and an uppermost surface of the first portion 140AL.

[0060] ​​The third spacer 143 can include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, although the inventive concepts are not limited thereto. According to an exemplary embodiment of the inventive concepts, the third spacer 143 can include a material different from that of the second spacer 142. For example, the third spacer 143 can include a material having an etch selectivity different from that of the second spacer 142. The following will be exemplarily described below based on the assumption that the third spacer 143 includes silicon nitride.

[0061] The fourth spacer 144 can be formed on the third spacer 143. A first sidewall of the fourth spacer 144 can extend along at least a portion of a side surface of the bit line structure 130 and the direct contact DC. A second sidewall opposite the first sidewall can be disposed on the contact structure 150. A lower portion of the fourth spacer 144 can be curved and extend below the stepped portion of the air spacer 140A. A gap between the first sidewall of the lowermost portion of the fourth spacer 144 and the first portion 140AL extending from the stepped portion can be occupied by the vertical segment of the third spacer 143. For example, the third spacer 143 can have a shape defined by the lower portion of the fourth spacer 144, the first portion 140AL, and the second spacer 142. In addition, the fourth spacer 144 can be spaced apart from the first spacer 141 by the air spacer 140A. For example, as shown, the second portion 140AU of the air spacer 140A can be disposed between the upper spacer 141U and the fourth spacer 144. According to an exemplary embodiment of the inventive concepts, a lower surface of the fourth spacer 144 can be formed lower than an uppermost surface of the third spacer 143. In other words, the lower surface of the fourth spacer 144 can be formed lower than a lower surface of the second portion 140AU of the air spacer 140A. For example, the lower portion of the fourth spacer 144 can have a form buried within the third spacer 143. Figure 3A

[0062] According to an exemplary embodiment of the inventive concepts, the fourth spacer 144 can extend along at least a portion of a side surface of the contact structure 150. For example, the fourth spacer 144 can be disposed between the air spacer 140A and the contact structure 150. According to an exemplary embodiment of the inventive concepts, the fourth spacer 144 can be in contact with the contact structure 150.

[0063] The fourth spacer 144 can include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, although the inventive concepts are not limited thereto. According to an exemplary embodiment of the inventive concepts, the fourth spacer 144 can include a material different from that of the second spacer 142. For example, the fourth spacer 144 can include a material having an etch selectivity different from that of the second spacer 142. The following will be exemplarily described below based on the assumption that the fourth spacer 144 includes silicon nitride.​

[0064] According to exemplary embodiments of the inventive concept, the first spacer 141, the third spacer 143, and the fourth spacer 144 can define the air spacer 140A. For example, the first spacer 141 and the third spacer 143 can define a first portion 140AL of the air spacer 140A, and the first spacer 141 and the fourth spacer 144 can define a second portion 140AU of the air spacer 140A.

[0065] For example, as shown in FIG. 1A, the lower spacer 141L can include a first side surface 141SL opposite the third spacer 143, and the upper spacer 141U can include a second side surface 141SU opposite the fourth spacer 144. In addition, the third spacer 143 can include a third side surface 143S opposite the lower spacer 141L, and the fourth spacer 144 can include a fourth side surface 144S opposite the upper spacer 141U. The first side surface 141SL can define one side of the first portion 140AL of the air spacer 140A, and the third side surface 143S can define the other side of the first portion 140AL of the air spacer 140A. In addition, the second side surface 141SU can define one side of the second portion 140AU of the air spacer 140A, and the fourth side surface 144S can define the other side of the second portion 140AU of the air spacer 140A. Figure 3A According to exemplary embodiments of the inventive concept, a width W3U of the upper spacer 141U can be less than a width W3L of the lower spacer 141L. For example, the second side surface 141SU can be disposed closer to the side surface of the first conductive pattern than the first side surface 141SL.

[0066] According to exemplary embodiments of the inventive concept, the width W3U of the upper spacer 141U can be equal to or less than about 10 µm.

[0067] When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm. When the width W3U of the upper spacer 141U is greater than about 10 µm, it can be difficult to secure a space for subsequently forming a spacer (e.g., the air spacer 140A or the fourth spacer 144) due to insufficient manufacturing margin. For example, the width W3U of the upper spacer 141U can be about 10 µm to about 20 µm.

[0068] According to an exemplary embodiment of the inventive concept, the air spacer 140A can have a T-shaped shape in a cross-section. For example, the first side surface 141SL can be spaced apart from the side surface of the first conductive pattern in the first direction (e.g., the X direction) by a distance greater than a distance by which the second side surface 141SU is spaced apart from the side surface of the first conductive pattern in the first direction (e.g., the X direction), and the third side surface 143S can be spaced apart from the side surface of the first conductive pattern in the first direction (e.g., the X direction) by a distance smaller than a distance by which the fourth side surface 144S is spaced apart from the side surface of the first conductive pattern in the first direction (e.g., the X direction). Accordingly, the air spacer 140A can have a T-shaped shape in a cross-section intersecting the second direction (e.g., the Y direction).

[0069] According to an exemplary embodiment of the inventive concept, a displacement distance W2a from the first side surface 141SL to the second side surface 141SU in the first direction (e.g., the X direction) can be different from a displacement distance W2b from the third side surface 143S to the fourth side surface 144S in the first direction (e.g., the X direction). For example, as shown in FIG. 2B, the displacement distance W2a from the first side surface 141SL to the second side surface 141SU can be smaller than the displacement distance W2b from the third side surface 143S to the fourth side surface 144S. Figure 3A

[0070] According to an exemplary embodiment of the inventive concept, the width W4 of the second spacer 142 can be substantially the same as the width W1L of the first portion 140AL of the air spacer 140A. For example, the width W4 can represent a height in a normal direction perpendicular to the curved side surface of the first trench T1. For example, the width W4 of the second spacer 142 and the width W1L of the first portion 140AL of the air spacer 140A can be about 1 µm to about 5 µm.

[0071] According to an exemplary embodiment of the inventive concept, the first portion 140AL of the air spacer 140A can extend in the thickness direction by the width W4, across the second spacer 142, to the lower upper surface of the lower spacer 141L of the first spacer 141.

[0072] Again, referring back to Figure 1 and Figure 2 ​​The contact structure 150 can be formed on the substrate 100 and the device isolation film 110. The contact structure 150 can penetrate the base insulating film 120 and connect the active region AR of the substrate 100 and the capacitor structure 190. The contact structure 150 can be formed on a side surface of the bit line structure 130. The contact structure 150 can be spaced apart from the bit line structure 130 by the spacer structure 140. In other words, the spacer structure 140 can electrically insulate the bit line structure 130 from the contact structure 150.

[0073] According to an exemplary embodiment of the inventive concept, the contact structure 150 can include a buried contact BC and a landing pad LP sequentially stacked on the substrate 100.

[0074] The buried contact BC can be formed on the substrate 100 between the plurality of bit line structures 130. According to an exemplary embodiment of the inventive concept, an upper surface of the buried contact BC can be lower than an upper surface of the bit line structure 130. For example, the upper surface of the buried contact BC can be further from an upper surface of the substrate 100 in a thickness direction than an upper surface of the third conductive film 136, but can be lower than an upper surface of the first cap pattern 138. As shown, the buried contact BC can be disposed on an area defined by the word line structure 160 and between adjacent bit line structures 130. In addition, the buried contact BC can form a plurality of isolation regions spaced apart from each other. Figure 1

[0075] The buried contact BC can penetrate the base insulating film 120 and connect the active region AR of the substrate 100 and the landing pad LP. For example, the substrate 100 can include a second trench T2 within the active region AR. The second trench T2 can expose a portion of the active region AR by penetrating the base insulating film 120. The buried contact BC can be formed within the second trench T2 and can connect the active region AR of the substrate 100 and the landing pad LP.

[0076] According to an exemplary embodiment of the inventive concept, the second trench T2 can expose both ends of the active region AR. Accordingly, as shown, the buried contact BC can be in contact with both ends of the active region AR. A portion of the second trench T2 can overlap a portion of the device isolation film 110. Accordingly, the second trench T2 can expose a portion of the device isolation film 110 as well as a portion of the substrate 100. Figure 1

[0077] The buried contact BC can include a conductive material. Accordingly, the buried contact BC can be in electrical contact with the active region AR of the substrate 100. The active region AR of the substrate 100 in contact with the buried contact BC can function as a source region and a drain region. For example, the buried contact BC can include polysilicon, but the inventive concept is not limited thereto. ​​

[0078] The landing pad LP can be formed on the buried contact BC. Also, the landing pad LP can be in contact with an upper surface of the buried contact BC. According to an exemplary embodiment of the inventive concept, an upper surface of the landing pad LP can be higher than an upper surface of the bit line structure 130. For example, the landing pad LP can cover a portion of the upper surface of the bit line structure 130.

[0079] The landing pad LP can form a plurality of isolation regions spaced apart from each other. Figure 1 It is illustrated that each landing pad LP has a circular shape; however, the inventive concept is not limited thereto. Also, Figure 1 It is illustrated that a plurality of landing pads LP are arranged in a honeycomb structure; however, the inventive concept is not limited thereto.

[0080] The plurality of landing pads LP can be in contact with the buried contact BC forming the plurality of isolation regions. For example, each landing pad LP can be isolated by a third trench T3.

[0081] The landing pad LP can include a conductive material. Accordingly, the capacitor structure 190 can be electrically contacted with the active region AR of the substrate 100 through the contact structure 150. For example, the landing pad LP can include tungsten, but is not limited thereto.

[0082] According to an exemplary embodiment of the inventive concept, a portion of the third trench T3 can expose a portion of the bit line structure 130. For example, the third trench T3 can be disposed between adjacent landing pads LP and can extend from an upper surface of the landing pad LP to below an upper surface of the bit line structure 130 in a thickness direction. Accordingly, the plurality of landing pads LP can be isolated from each other by the bit line structure 130 and the third trench T3. According to an exemplary embodiment of the inventive concept, a lower surface of the third trench T3 can be formed to be higher than a lower surface of the first capping pattern 138. Accordingly, the third trench T3 can expose a portion of the first capping pattern 138. For example, the third trench T3 can expose an upper corner portion and a sidewall of the first capping pattern 138.

[0083] Since the air spacer 140A can be disposed between the bit line structure 130 and the contact structure 150, the third trench T3 can expose at least a portion of an upper surface of the air spacer 140A. For example, a portion of the third trench T3 can define the upper surface of the air spacer 140A. According to an exemplary embodiment of the inventive concept, the third trench T3 can also expose an upper surface of the first spacer 141 and an upper surface of the fourth spacer 144.

[0084] Interlayer insulating film 180 can be formed on a portion of the upper surface of the landing pad LP and a portion of the bit line structure 130. Furthermore, interlayer insulating film 180 can define areas of the landing pad LP where multiple isolation regions are formed. For example, interlayer insulating film 180 can fill a third trench T3. Therefore, interlayer insulating film 180 can isolate multiple landing pads LP from each other in a first direction (e.g., the X direction). Additionally, interlayer insulating film 180 can be patterned to expose a portion of the upper surface of each landing pad LP.

[0085] Interlayer insulating film 180 may include insulating material to electrically isolate the plurality of landing pads LP from each other. For example, interlayer insulating film 180 may include silicon oxide, silicon oxynitride, silicon nitride, and / or a low-k dielectric material with a dielectric constant less than that of silicon oxide, but the inventive concept is not limited thereto.

[0086] Capacitor structure 190 can be disposed on interlayer insulating film 180 and landing pad LP. Capacitor structure 190 can contact a portion of the upper surface of landing pad LP exposed through interlayer insulating film 180. As a result, capacitor structure 190 can make electrical contact with the source and drain regions that are in contact with contact structure 150. Therefore, capacitor structure 190 can store charge in semiconductor memory devices, etc.

[0087] For example, such as Figure 2 and Figure 4 As shown, the capacitor structure 190 may include a lower electrode 192, a capacitor dielectric film 194, and an upper electrode 196. The capacitor structure 190 can store charge within the capacitor dielectric film 194 by utilizing the potential difference generated between the lower electrode 192 and the upper electrode 196. The lower electrode 192 may have a tuning fork-shaped cross-section. For example, the upturned side of the lower electrode 192 may have a lower edge surface that is at least partially disposed on the upper surface of the adjacent interlayer insulating film 180. The lower segment of the lower electrode 192 connecting the upturned sides may extend in the thickness direction to the upper surface of the corresponding landing pad LP. The capacitor dielectric film 194 may cover the exposed surfaces of the lower electrode 192 and the interlayer insulating film 180. The upper electrode 196 may have a shape complementary to the common shape of the lower electrode 192 and the capacitor dielectric film 194.

[0088] The lower electrode 192 and the upper electrode 196 may comprise, for example, doped polysilicon, metal, and / or metal nitride, but the inventive concept is not limited thereto. Furthermore, the capacitor dielectric film 194 may comprise, for example, silicon oxide and / or a high-k dielectric material, but the inventive concept is not limited thereto.

[0089] As semiconductor devices become more integrated, the effects of parasitic capacitance and leakage current gradually increase. For example, as the pitch between conductive patterns of a dynamic random access memory (DRAM) becomes narrower, parasitic capacitance between the conductive patterns can increase.

[0090] However, a semiconductor device according to exemplary embodiments of the inventive concept can more effectively reduce parasitic capacitance of the semiconductor device by using the air spacer 140A, and thus can provide a semiconductor device having enhanced operating characteristics.

[0091] For example, in a semiconductor device according to exemplary embodiments of the inventive concept, the air spacer 140A can include a first portion 140AL formed within the first trench T1. As the first portion 140AL of the air spacer 140A can extend to a lower portion (e.g., a direct contact DC) of the conductive pattern formed within the first trench T1, parasitic capacitance between the conductive patterns can be effectively reduced. For example, the air spacer 140A can effectively reduce parasitic capacitance between the direct contact DC and the buried contact BC.

[0092] Further, in a semiconductor device according to exemplary embodiments of the inventive concept, a first spacer 141 defining an inner sidewall of the air spacer 140A adjacent to the direct contact DC can include an upper spacer 141U having a width W3U smaller than a width W3L of a lower spacer 141L. In other words, the upper spacer 141U can provide additional space in order to form a second portion 140AU of the air spacer 140A. Thus, the upper spacer 141U can define adjacent sidewalls of the second portion 140AU of the air spacer 140A, and the second portion 140AU can thus have a greater width and sidewalls that protrude more toward the direct contact DC in the first direction (e.g., the X direction) than corresponding sidewalls of the first portion 140AL.

[0093] Further, in a semiconductor device according to exemplary embodiments of the inventive concept, the air spacer 140A can have a T-shape. The air spacer 140A having a T-shape can be easily formed. For example, in an etching process of forming the air spacer 140A, as the second portion 140AU can have a shape of a gap widening from both sides of the first portion 140AL, it is easy to form the gap within the first portion 140AL. Thus, as the air spacer 140A can extend toward a lower portion (e.g., a direct contact DC) of the conductive pattern formed within the first trench T1, parasitic capacitance between the conductive patterns can be effectively reduced.

[0094] Reference will now be made to Figure 3BIn the semiconductor device according to the exemplary embodiment of the present inventive concept, a displacement distance W2a from the first side surface 141SL to the second side surface 141SU in the first direction (e.g., the X direction) can be greater than a displacement distance W2b from the third side surface 143S to the fourth side surface 144S.

[0095] Referring to Figure 3C In the semiconductor device according to the exemplary embodiment of the present inventive concept, the second spacer 142 can extend along a portion of the side surface of the direct contact DC and the curved side wall of the first trench T1 over the first spacer 141. For example, the second spacer 142 can include an inner portion 142i and an outer portion 142o.

[0096] The inner portion 142i of the second spacer 142 can extend in the thickness direction over the first spacer 141 along a portion of the side surface of the direct contact DC. The outer portion 142o of the second spacer 142 can be connected to (e.g., integrally formed with) the inner portion 142i and can extend over the first spacer 141 along the curved side wall of the first trench T1.

[0097] According to the exemplary embodiment of the present inventive concept, the second spacer 142 can define a lower portion of the air spacer 140A. For example, as shown in FIG. 1A, an upper surface of the inner portion 142i of the second spacer 142 can define a lower surface of the first portion 140AL of the air spacer 140A. In addition, as described above, a lowermost surface of the second spacer 142 (e.g., a lower surface of the inner portion 142i) can be formed lower than a lowermost surface of the air spacer 140A. Figure 3C

[0098] According to the exemplary embodiment of the present inventive concept, a width W4i of the inner portion 142i of the second spacer 142 can be the same as a width W1L of the first portion 140AL of the air spacer 140A. According to the exemplary embodiment of the present inventive concept, a width W4o of the outer portion 142o of the second spacer 142 can be the same as the width W4i of the inner portion 142i of the second spacer 142. For example, the width W4i of the inner portion 142i of the second spacer 142, the width W4o of the outer portion 142o of the second spacer 142, and the width W1L of the first portion 140AL of the air spacer 140A can be about 1 µm to about 5 µm.

[0099] Referring to Figure 3D ​​In the semiconductor device according to the exemplary embodiments of the present inventive concept, the air spacer 140A can further extend along a portion of the first trench T1. For example, a first portion 140AL of the air spacer 140A can further extend along a portion of the curved sidewall of the first trench T1 over the first spacer 141 and can be connected to a first end of the second spacer 142. A second end of the second spacer 142 opposite the first end can be disposed on the buried contact BC.

[0100] According to the exemplary embodiments of the present inventive concept, the second spacer 142 can define a lower portion of the air spacer 140A. For example, as shown in FIG. 1A, a lower surface of the second spacer 142 can define an upper surface of the air spacer 140A extending along the first trench T1. Accordingly, a lowermost surface of the second spacer 142 can be higher than a lowermost surface of the air spacer 140A. Figure 3D

[0101] According to the exemplary embodiments of the present inventive concept, a width W1Lo of the air spacer 140A extending along the first trench T1 can be the same as a width W1Li of the air spacer 140A extending along the side surface of the direct contact DC. According to the exemplary embodiments of the present inventive concept, the width W1Lo of the air spacer 140A extending along the first trench T1 can be the same as a width W4 of the second spacer 142. For example, the width W1Lo of the air spacer 140A extending along the first trench T1, the width W1Li of the air spacer 140A extending along the side surface of the direct contact DC, and the width W4 of the second spacer 142 can be about 1 µm to about 10 µm, about 1 µm to about 5 µm, or about 1 µm to about 2 µm.

[0102] Referring to FIG. 1A, the semiconductor device 100 can include a substrate 110, a buried contact BC, a direct contact DC, a first spacer 141, a second spacer 142, and an air spacer 140A. Figure 3E In the semiconductor device according to the exemplary embodiments of the present inventive concept, the air spacer 140A can further extend along a portion of the first trench T1. For example, a first portion 140AL of the air spacer 140A can further extend along a portion of the curved sidewall of the first trench T1 over the first spacer 141 and can be connected to a first end of the second spacer 142. A second end of the second spacer 142 opposite the first end can be disposed on the buried contact BC.

[0103] According to the exemplary embodiments of the present inventive concept, a first portion 140AL of the air spacer 140A can expose a portion of the buried contact BC. For example, in an etching process to form the air spacer 140A, the second spacer 142 in the buried contact BC can be completely removed. Figure 3A

[0104] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 ​​​, Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 It is along Figure 1 The cross-sectional view taken along line A-A' illustrates an intermediate stage in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. For ease of explanation and for brevity, previously described elements and relationships may be omitted herein. (Refer to...) Figure 5 The substrate insulating film 120, the first conductive film to the third conductive film 132, 134, 136, the direct contact DC and the first capping pattern 138 can be formed on the substrate 100 and the device isolation film 110.

[0105] For example, the first to third insulating films 122, 124, 126 and the first conductive film 132 can be sequentially formed on the substrate 100 and the device isolation film 110. Subsequently, an exposure can be formed within the substrate 100. Figure 1 A first trench T1 is formed in part of the active region AR. According to an exemplary embodiment of the present invention, the first trench T1 may expose the center of the active region AR. Next, a direct contact DC may be formed to fill the first trench T1. Subsequently, a second conductive film 134, a third conductive film 136, and a first capping pattern 138 may be sequentially formed on the first conductive film 132 and the direct contact DC.

[0106] Reference Figure 6 The first conductive film to the third conductive films 132, 134 and 136, the direct contact DC and the first cover pattern 138 can be patterned.

[0107] Therefore, it is possible to form such as Figure 1 The bit line structure 130 shown extends longitudinally along a second direction (e.g., the Y direction) while traversing the active region AR and the word line structure 160. According to an exemplary embodiment of the invention, the width of the direct contact DC and the width of the bit line structure 130 stacked thereon can be formed to be smaller than the width of the first trench T1. In other words, the patterned direct contact DC and the patterned bit line structure 130 stacked thereon may not completely fill the first trench T1. The upper surface of the first conductive pattern and the upper surface of the adjacent bit line structure 130 that does not contain the direct contact DC can be coplanar.

[0108] Reference Figure 7 The first spacer 141 can be formed in Figure 6on a resultant object of the first spacer 141 and the second spacer 142. For example, the first spacer 141 can be disposed on the first trench T1, the patterned bit line structure 130, and an exposed surface of the patterned direct contact DC.

[0109] According to an exemplary embodiment of the inventive concept, the first spacer 141 can be conformally formed. For example, the first spacer 141 can extend along a side surface and an upper surface of the bit line structure 130, a side surface of the direct contact DC, a side surface and an upper surface of the base insulating film 120, and a profile of the first trench T1.

[0110] The first spacer 141 can include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, but the inventive concept is not limited thereto. Hereinafter, the following will be exemplarily described based on an assumption that the first spacer 141 includes silicon nitride.

[0111] Referring to Figure 8 , the second spacer 142 can be formed on the first spacer 141.

[0112] According to an exemplary embodiment of the inventive concept, the second spacer 142 can be conformally formed on the first spacer 141. For example, the second spacer 142 can extend along a profile of the first spacer 141.

[0113] According to an exemplary embodiment of the inventive concept, the second spacer 142 can include a material different from that of the first spacer 141. For example, the second spacer 142 can include a material having a dielectric constant greater than that of the first spacer 141. Alternatively, for example, the second spacer 142 can include a material having a different etch selectivity with respect to the etch selectivity of the first spacer 141. Hereinafter, the following will be exemplarily described based on an assumption that the second spacer 142 includes silicon oxide.

[0114] Referring to Figure 9 , the third spacer 143 can be formed within the first trench T1. The third spacer 143 can be formed within the first trench T1 on the second spacer 142. The third spacer 143 can fill a region of the first trench T1 remaining after deposition of the first spacer 141 and the second spacer 142. For example, an upper surface of the third spacer 143 can be coplanar with an upper surface of the second spacer 142.

[0115] For example, a spacer film can be formed on the second spacer 142. Subsequently, a portion of the spacer film can be removed by using the second spacer 142 as an etch stop film. Accordingly, the third spacer 143 can be formed to fill the first trench T1. For example, the removing of the portion of the spacer film can be performed by using a wet etching process using H3PO4, but the inventive concept is not limited thereto.

[0116] According to an exemplary embodiment of the inventive concept, the third spacer 143 can include a material different from that of the second spacer 142. For example, the third spacer 143 can include a material having a different etching selectivity with respect to the etching selectivity of the second spacer 142. The following will be exemplarily described based on the assumption that the third spacer 143 includes silicon nitride.

[0117] Referring to Figure 10 and Figure 11 , a portion of the second spacer 142 can be removed, and a thickness of a portion of the first spacer 141 can be reduced. For reference, Figure 11 is an enlarged view of an R2 region of Figure 10 .

[0118] For example, a portion of the second spacer 142 extending along the side surface and the upper surface of the bit line structure 130 and the upper surface of the base insulating film 120 can be removed. For example, the removal of the second spacer 142 can be performed by using a wet etching process using HF, but the inventive concept is not limited thereto.

[0119] According to an exemplary embodiment of the inventive concept, the second spacer 142 formed within the first trench T1 can not be removed. For example, the second spacer 142 within the first trench T1 can extend on the first spacer 141 along the profile of the first trench T1. The upper surface of the third spacer 143 can be etched to be coplanar with the uppermost end of the patterned second spacer 142 and the upper surface of the first spacer 141 extending along the base insulating film 120 in the first direction (e.g., the X direction).

[0120] Subsequently, the thickness of the first spacer 141 exposed by the removed second spacer 142 can be reduced. For example, the thickness of the first spacer 141 extending along the side surface and the upper surface of the bit line structure 130 can be reduced. For example, the reduction of the thickness of the first spacer 141 can be performed by using a wet etching process using HF, but the inventive concept is not limited thereto. Thus, as Figure 11 shown, the thickness W3U of the upper spacer 141U can be less than the thickness W3L of the lower spacer 141L.

[0121] According to an exemplary embodiment of the inventive concept, the width W3U of the upper spacer 141U can be equal to or less than about For example, the width W3U of the upper spacer 141U can be about to about and the width W3L of the lower spacer 141L can be about to about Preferably, the width W3U of the upper spacer 141U can be about to about and the width W3L of the lower spacer 141L can be about to

[0122] The removing of the portion of the second spacer 142 and the reducing of the thickness of the portion of the first spacer 141 can be performed in situ, but the inventive concept is not limited thereto.

[0123] Referring to Figure 12 , the sacrificial spacer 140P can be formed on the result object of Figure 10 and Figure 11 According to an exemplary embodiment of the inventive concept, the sacrificial spacer 140P can be conformally formed on the exposed etched surface of the first spacer 141. For example, the sacrificial spacer 140P can extend along the side surface and the upper surface of the first spacer 141, the exposed end portion of the second spacer 142, and the upper surface of the third spacer 143.

[0124] According to an exemplary embodiment of the inventive concept, the thickness of the sacrificial spacer 140P can be greater than the thickness of the second spacer 142.

[0125] According to an exemplary embodiment of the inventive concept, the sacrificial spacer 140P can include a material different from the materials of the first spacer 141 and the third spacer 143. For example, the sacrificial spacer 140P can include a material having a different etch selectivity with respect to the etch selectivity of the first spacer 141 and the third spacer 143. According to an exemplary embodiment of the inventive concept, the sacrificial spacer 140P can include the same material as the material of the second spacer 142. The following will be exemplarily described based on the assumption that the sacrificial spacer 140P includes silicon oxide.

[0126] Referring to Figure 13 , the fifth trench T5 can be formed between the plurality of bit line structures 130.

[0127] According to an exemplary embodiment of the inventive concept, a lower surface of the fifth trench T5 can be formed lower than the uppermost surface of the third spacer 143. For example, the fifth trench T5 can be formed within the base insulating film 120. According to an exemplary embodiment of the inventive concept, the fifth trench T5 can expose the upper surface of the substrate 100.

[0128] In the process of forming the fifth trench T5, a portion of the sacrificial spacer 140P can be removed. For example, the sacrificial spacer 140P on the upper surface of the bit line structure 130 can be removed. The horizontal segment of the sacrificial spacer 140P extending in the first direction (e.g., the X direction) between the bit line structures 130 can be removed, and in addition, a portion of the first spacer 141, the second spacer 142, the third spacer 143, and the base insulating film 120 thereunder can also be removed.

[0129] Referring to Figure 14 , the fourth spacer 144 can be formed on the result object of Figure 13 .

[0130] According to an example embodiment of the present inventive concept, the fourth spacer 144 can be conformally formed on the exposed surfaces of the substrate 100, the bit line structure 130, the first spacer 141, the second spacer 142, the third spacer 143, and the base insulating film 120. For example, the fourth spacer 144 can extend along the side surface of the sacrificial spacer 140P and the profile of the fifth trench T5.

[0131] According to an example embodiment of the present inventive concept, the fourth spacer 144 can include a material different from that of the second spacer 142 and the sacrificial spacer 140P. For example, the fourth spacer 144 can include a material having a different etching selectivity with respect to the etching selectivity of the second spacer 142 and the sacrificial spacer 140P. The following will be exemplarily described based on the assumption that the fourth spacer 144 includes silicon nitride.

[0132] Referring to Figure 15 , the second trench T2 can be formed between the plurality of bit line structures 130. The second trench T2 can extend in the thickness direction from the fifth trench T5 toward the substrate 100 and can be narrower in the first direction (e.g., the X direction). For example, the second trench T2 can be formed to pass through a flat lowermost portion of the fourth spacer 144 disposed in the fifth trench T5 between vertical portions of the fourth spacer 144 covering the sidewalls of adjacent bit line structures 130.

[0133] According to an example embodiment of the present inventive concept, a lower surface of the second trench T2 can be formed lower than an upper surface of the substrate 100. For example, the second trench T2 can be formed within the active region AR of the substrate 100. Figure 1 According to an example embodiment of the present inventive concept, the second trench T2 can expose both ends of the active region AR.

[0134] In the process of forming the second trench T2, a portion of the fourth spacer 144 may be removed. For example, the fourth spacer 144 may be removed from the upper surface of the bit line structure 130. (Refer to...) Figure 16 The contact structure 150 can be formed within the second groove T2. For example, it can be... Figure 15 A conductive film is formed on the resulting object. Subsequently, an etching process can be performed so that the upper surface of the conductive film is lower than the upper surface of the bit line structure 130. Therefore, buried contacts BC forming multiple isolation regions can be formed in the second trench T2. The buried contacts BC may include polysilicon, but the inventive concept is not limited thereto.

[0135] Subsequently, a landing pad LP can be formed on the buried contact BC. According to an exemplary embodiment of the present invention, the upper surface of the landing pad LP can be formed above the upper surface of the bit line structure 130. For example, the landing pad LP may include tungsten, but the present invention is not limited thereto.

[0136] Reference Figure 17 A third trench T3 can be formed within the landing pad LP. In other words, the landing pad LP can be patterned using the third trench T3. Therefore, multiple isolation areas can be formed using the patterned landing pad LP. According to an exemplary embodiment of the present invention, the third trench T3 can be formed to arrange multiple landing pads LP in a honeycomb structure. Therefore, as... Figure 1 As shown, multiple landing pads (LPs) can be formed in a honeycomb structure.

[0137] According to an exemplary embodiment of the present invention, the third trench T3 may be formed to overlap with the sacrificial spacer 140P. Therefore, the upper portion of the sacrificial spacer 140P may be exposed by the third trench T3.

[0138] According to an exemplary embodiment of the present invention, in a first direction (e.g., the X direction), the second groove T2 may be offset relative to the third groove T3.

[0139] Reference Figure 18 and Figure 19 At least a portion of the second spacer 142 and the sacrificial spacer 140P can be removed to form an air spacer 140A. For reference, Figure 19 yes Figure 18 A magnified view of the R3 region.

[0140] For example, an etching process can be performed to remove the sacrificial spacer 140P exposed by the third trench T3. This etching process may include, for example, a plasma dry cleaning (PDC) process, but the inventive concept is not limited thereto.

[0141] Reference Figure 18After removing the sacrificial spacer 140P, the upper part of the second spacer 142 can be exposed. Subsequently, in the process of removing the sacrificial spacer 140P, at least a portion of the exposed second spacer 142 (e.g., the vertical portion overlapping the sidewall of the direct contact member DC) can also be removed.

[0142] According to an exemplary embodiment of the present invention, when the thickness of the sacrificial spacer 140P is formed to be thicker than the thickness of the second spacer 142, the second spacer 142 and the sacrificial spacer 140P may have a T-shaped form. Therefore, in the process of removing the sacrificial spacer 140P, the exposed second spacer 142 can be removed more easily.

[0143] Therefore, as Figure 19 As shown, at least a portion of the second spacer 142 and the sacrificial spacer 140P can be replaced by an air spacer 140A comprising a first portion 140AL and a second portion 140AU. According to an exemplary embodiment of the present invention, since the thickness of the sacrificial spacer 140P can be greater than the thickness of the second spacer 142, the width W1U of the second portion 140AU of the air spacer 140A can be greater than the width W1L of the first portion 140AL of the air spacer 140A.

[0144] Reference Figure 20 An interlayer insulating film 180 can be formed on the landing pad LP. The interlayer insulating film 180 can be formed to fill the third trench T3. Therefore, the landing pad LP can form a plurality of isolation regions spaced apart from each other by the interlayer insulating film 180. In addition, the interlayer insulating film 180 can be patterned to expose a portion of the upper surface of each landing pad LP.

[0145] Subsequently, referring to Figures 1-4 , can Figure 20 A capacitor structure 190 is formed on the resulting object. For example, a lower electrode 192 can be formed that contacts the landing pad LP and is exposed through the interlayer insulating film 180. Then, a capacitor dielectric film 194 and an upper electrode 196 can be sequentially formed on the lower electrode 192. Therefore, a method for manufacturing a semiconductor device with enhanced operating characteristics according to an exemplary embodiment of the present invention can be provided.

[0146] Although exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, which includes trenches; A first conductive pattern is disposed within the trench, wherein the width of the first conductive pattern is smaller than the width of the trench. A first spacer extends along at least a portion of the side surface of the first conductive pattern and the trench. A second spacer, which at least partially fills the groove adjacent to the first spacer; as well as An air gap member, comprising a first portion located between a first gap member and a second gap member, and a second portion disposed on the second gap member and the first portion. Wherein, the width of the second portion of the air spacer is greater than the width of the first portion of the air spacer. The first spacer includes a lower spacer located between the first conductive pattern and the first portion of the air spacer, and an upper spacer located between the first conductive pattern and the second portion of the air spacer. Wherein, the width of the upper spacer of the first spacer is smaller than the width of the lower spacer of the first spacer.

2. The semiconductor device according to claim 1, wherein, The width of the upper spacer of the first spacer is Or smaller.

3. The semiconductor device according to claim 1, wherein, The width of the first portion of the air gap is Or larger.

4. The semiconductor device of claim 1, further comprising a third spacer, the third spacer being spaced apart from the first spacer by the second portion of the air spacer.

5. The semiconductor device according to claim 4, wherein, The side surface of the second spacer adjacent to the first spacer is closer to the first conductive pattern than the side surface of the third spacer adjacent to the first spacer.

6. The semiconductor device according to claim 4, wherein, In the direction toward the substrate, the lower surface of the third spacer is lower than the lower surface of the second portion of the air spacer.

7. The semiconductor device according to claim 1, wherein, The substrate includes an active region and a means isolation film defining the active region, and The first conductive pattern is in contact with the active region.

8. The semiconductor device of claim 7, further comprising a second conductive pattern that extends through the active region and extends within the substrate in a first direction. in, The first conductive pattern traverses the active region and extends in a second direction intersecting the first direction.

9. The semiconductor device according to claim 1, wherein, The first spacer and the second spacer comprise silicon nitride.

10. The semiconductor device of claim 1, further comprising: A contact structure that contacts the substrate and is spaced apart from the first conductive pattern by the first spacer, the air spacer, and the second spacer; and A capacitor structure that contacts the contact structure.

11. A semiconductor device, comprising: A substrate, which includes trenches; A conductive pattern is disposed within the trench, wherein the width of the conductive pattern is smaller than the width of the trench; A first spacer extends along at least a portion of the side surface of the conductive pattern and the trench; A second spacer, which at least partially fills the groove and is disposed on the first spacer; as well as An air gap member, comprising a first portion located between a first gap member and a second gap member, and a second portion disposed on the second gap member and the first portion. The first spacer includes a lower spacer located between the conductive pattern and the first portion of the air spacer, and an upper spacer located between the conductive pattern and the second portion of the air spacer. Wherein, the width of the upper spacer of the first spacer is smaller than the width of the lower spacer of the first spacer.

12. The semiconductor device according to claim 11, wherein, The width of the second portion of the air spacer is greater than the width of the first portion of the air spacer.

13. The semiconductor device of claim 11, further comprising a third spacer spaced apart from the first spacer by a second portion of the air spacer located on the second spacer.

14. The semiconductor device according to claim 13, wherein, The distance from the side surface of the upper spacer opposite to the third spacer to the side surface of the lower spacer opposite to the second spacer is different from the distance from the side surface of the third spacer opposite to the upper spacer to the side surface of the second spacer opposite to the lower spacer.

15. The semiconductor device according to claim 11, wherein, The bit line structure of the conductive pattern extends in a first direction, and The air gap has a T-shaped cross-section intersecting the first direction.

16. A semiconductor device, comprising: Substrate, which includes trenches; A conductive pattern is disposed within the trench, wherein the width of the conductive pattern is smaller than the width of the trench; A first spacer extends along at least a portion of the side surface of the conductive pattern and the trench; as well as An air spacer, displaced from the conductive pattern by the first spacer, the air spacer extending along at least a portion of the first spacer. The air gap has a T-shaped cross-section, and A portion of the air gap is formed within the groove.

17. The semiconductor device of claim 16, further comprising a contact structure that contacts the substrate and is spaced apart from the bit line structure of the conductive pattern by the first spacer and the air spacer.

18. The semiconductor device according to claim 17, wherein, The contact structure includes an embedded contact and a landing pad disposed on the embedded contact. The buried contact element contacts the substrate and includes an upper surface lower than the upper surface of the bit line structure. The landing pad has an upper surface that is higher than the upper surface of the bit line structure.

19. The semiconductor device of claim 18, further comprising a capacitor structure that contacts the landing pad on the bit line structure.

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