Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is provided, including a plurality of first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and a memory cell located at an intersection between the first conductive line and the second conductive line. The plurality of first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each memory cell includes a horizontally arranged variable resistance element and a switching element. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode located between the first variable resistance pattern and the first conductive line, a second electrode located between the second variable resistance pattern and the second conductive line, and a third electrode located between the first variable resistance pattern and the second variable resistance pattern.

Description

[0001] The entirety of Korean patent application No. 10-2019-0069618, filed with the Korean Intellectual Property Office on June 12, 2019, entitled “Three Dimensional Semiconductor Memory Devices,” is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure relate to three-dimensional semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices including variable resistance memory cells. Background Technology

[0003] Semiconductor devices are highly integrated to meet the demands for high performance and low cost. For example, the integration level of two-dimensional (2D) or planar semiconductor devices is primarily determined by the area used for a single memory cell. Therefore, the integration level of 2D or planar semiconductor devices depends on the technology used for fine patterning. However, such fine patterning in 2D or planar semiconductor manufacturing processes requires expensive equipment, limiting the increase in integration level of 2D or planar semiconductor devices. Three-dimensional semiconductor memory devices, including memory cells arranged in three dimensions, have been developed to overcome these limitations.

[0004] In addition, based on the demand for high-capacity and low-power memory devices, non-volatile and non-refreshable next-generation memory devices, such as phase-change random access memory (PRAM), nano-floating gate memory, polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FRAM), or resistive RAM (RRAM), have been investigated. Summary of the Invention

[0005] According to an example embodiment, a three-dimensional semiconductor memory device may include: a substrate; a plurality of first wires extending in a first direction parallel to an upper surface of the substrate and spaced apart from each other in a second direction intersecting the first direction and parallel to the upper surface of the substrate; a second wire extending upward in a third direction perpendicular to the first and second directions; and a plurality of memory cells disposed at intersections between the plurality of first and second wires, each of the plurality of memory cells including a variable resistor element and a switching element arranged horizontally in the second direction. The variable resistor element may include: a first variable resistor pattern and a second variable resistor pattern arranged in the second direction; a first electrode located between the first variable resistor pattern and the first wire; a second electrode located between the second variable resistor pattern and the second wire; and a third electrode located between the first variable resistor pattern and the second variable resistor pattern. The first electrode, the second electrode, and the third electrode may have different resistivities.

[0006] According to an example embodiment, a three-dimensional semiconductor memory device may include: a substrate; a first conductor extending in a first direction parallel to an upper surface of the substrate; a second conductor extending in a second direction perpendicular to the upper surface of the substrate and intersecting the first conductor; and a plurality of memory cells disposed between the first conductor and the second conductor. Each of the plurality of memory cells may include a first variable resistor pattern and a second variable resistor pattern arranged in a third direction intersecting the first and second directions and parallel to the upper surface of the substrate. Each of the first variable resistor pattern and the second variable resistor pattern may include: a sidewall portion adjacent to a sidewall of the first conductor; and a plurality of horizontal portions extending in a third direction from opposite ends of the sidewall portion.

[0007] According to an example embodiment, a three-dimensional semiconductor memory device may include: a substrate; a plurality of stacked structures and a plurality of buried insulating patterns alternately arranged on the substrate in a first direction parallel to the upper surface of the substrate, each of the plurality of stacked structures including a plurality of memory cells and a plurality of insulating layers alternately stacked on top of each other in a second direction perpendicular to the upper surface of the substrate; a plurality of first wires extending in the first direction, located at a first side of the plurality of memory cells and stacked in the second direction; and a plurality of second wires disposed between corresponding buried insulating patterns in the plurality of buried insulating patterns, located at a second side of the plurality of memory cells, the second side of the plurality of memory cells being opposite to the first side of the plurality of memory cells. Each of the plurality of memory cells may include a plurality of variable resistance patterns and a plurality of electrodes located between corresponding variable resistance patterns in the plurality of variable resistance patterns. The plurality of electrodes may have different resistivities. Attached Figure Description

[0008] The features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0009] Figure 1 A schematic perspective view of a three-dimensional semiconductor memory device according to an example embodiment is shown.

[0010] Figure 2 A plan view of a three-dimensional semiconductor memory device according to an example embodiment is shown.

[0011] Figure 3A and Figure 3B The following are shown respectively along Figure 2 The sectional view taken from lines I-I' and II-II'.

[0012] Figure 4 It shows Figure 3A A magnified view of part A.

[0013] Figure 5A schematic perspective view of a three-dimensional semiconductor memory device according to an example embodiment is shown.

[0014] Figure 6 It shows along Figure 5 The sectional view taken from line III-III'.

[0015] Figure 7 It shows Figure 6 A magnified view of part B.

[0016] Figure 8 A plan view of a three-dimensional semiconductor memory device according to an example embodiment is shown.

[0017] Figure 9A and Figure 9B The following are shown respectively along Figure 8 A sectional view taken from lines IV-IV' and V-V'.

[0018] Figure 10A , Figure 10B , Figure 10C and Figure 10D It shows Figure 9A A magnified view of part C.

[0019] Figure 11 A plan view of a three-dimensional semiconductor memory device according to an example embodiment is shown.

[0020] Figure 12A and Figure 12B The following are shown respectively along Figure 11 A sectional view taken from lines VI-VI' and VII-VII'.

[0021] Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16 , Figure 17 and Figure 18 A cross-sectional view is shown of a stage in a method for manufacturing a three-dimensional semiconductor memory device according to an example embodiment. Figure 13A , Figure 14A , Figure 15A , Figure 16 , Figure 17 and Figure 18 It is along Figure 2 A cross-sectional view taken by line I-I'. Figure 13B , Figure 14B and Figure 15B It is along Figure 2 The sectional view taken from line II-II'.

[0022] Figure 19, Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 A cross-sectional view is shown of a stage in a method for manufacturing a three-dimensional semiconductor memory device, and is along... Figure 2 A sectional view taken from line I-I'. Detailed Implementation

[0023] Various exemplary embodiments will now be described more fully below with reference to the accompanying drawings. Throughout this application, the same reference numerals may denote the same elements.

[0024] Figure 1 This is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to an example embodiment.

[0025] Reference Figure 1 A three-dimensional (3D) semiconductor memory device may include a cross-point memory cell array, the cross-point memory cell array including memory cells MC1 and MC2 arranged three-dimensionally on a substrate 100. The cross-point memory cell array may include: word lines WL1 and WL2; a bit line BL, intersecting word lines WL1 and WL2; and memory cells MC1 and MC2, arranged at the intersection of word lines WL1 and WL2 and bit line BL.

[0026] Word lines WL1 and WL2 may include: a first word line WL1 located on a first side of bit line BL; and a second word line WL2 located on a second side of bit line BL, the second side of the bit line being opposite to the first side of bit line BL. The first word line WL1 and the second word line WL2 may extend along a first direction D1 parallel to the upper surface of the substrate 100. The first word line WL1 may be stacked on a third direction D3 perpendicular to the upper surface of the substrate 100. The second word line WL2 may be stacked on the third direction D3. The second word line WL2 may be spaced apart from the first word line WL1 in a second direction D2, and the bit line BL is located between the second word line WL2 and the first word line WL1. The second direction D2 may be parallel to the upper surface of the substrate 100 and may intersect the first direction D1.

[0027] Bit lines BL may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. Although bit lines BL are shown exemplarily extending in the third direction D3 in the figures, embodiments are not limited thereto. In some embodiments, bit lines BL may extend in the first direction D1, and word lines WL1 and WL2 may extend in the third direction D3.

[0028] The memory cells MC1 and MC2 may include: a first memory cell MC1, located at the intersection of bit line BL and first word line WL1; and a second memory cell MC2, located at the intersection of bit line BL and second word line WL2.

[0029] Any memory cell in the first memory cell MC1 and the second memory cell MC2 can be selected by choosing the corresponding word line in the first word line WL1 and the second word line WL2, and the corresponding bit line in the bit line BL. Adjacent memory cells in the first memory cell MC1 and the second memory cell MC2 in the second direction D2 can share the corresponding bit line BL. Each of the first memory cell MC1 and the second memory cell MC2 may include a variable resistor element VR and a switching element SW connected in series. The variable resistor element VR and the switching element SW may be arranged horizontally along the second direction D2. Each of the first memory cell MC1 and the second memory cell MC2 may also include an electrode located between the variable resistor element VR and the switching element SW.

[0030] The switching element SW can be a diode or a device based on a threshold switching phenomenon with a nonlinear (e.g., S-shaped) IV curve. For example, the switching element SW can be a bidirectional threshold switch (OTS) element with bidirectional characteristics.

[0031] A variable resistance element (VR) can include materials capable of storing information based on changes in resistance. A variable resistance element (VR) can also include materials capable of changing to multiple states with different resistance values.

[0032] In some embodiments, the variable resistance element VR may include a phase change material capable of reversibly changing between a crystalline and amorphous state depending on temperature. Depending on temperature, the phase change material may have an amorphous state with relatively high resistance and a crystalline state with relatively low resistance. For example, the phase change material may include a compound / mixture composed of at least one of a chalcogenide material (such as a material formed by combining Te or Se with at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C). The phase change material may include at least one of, for example, GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe.

[0033] In some embodiments, the variable resistance element VR may have a superlattice structure in which layers including Ge and non-Ge layers are repeated and alternately stacked. The variable resistance element VR may have a structure in which GeTe layers and SbTe layers are repeated and alternately stacked.

[0034] In some embodiments, the variable resistance element VR may comprise a material whose resistance value can be varied by the formation and disappearance of filaments and / or bridges. The variable resistance element VR may comprise, for example, perovskite compounds or transition metal oxides.

[0035] In some embodiments, the variable resistance element VR may include a magnetic tunnel junction in which the resistance value can be changed according to the magnetization direction between the free layer and the pinned layer.

[0036] In each of the first memory cell MC1 and the second memory cell MC2, the variable resistance element VR may include at least two variable resistance patterns and electrodes in contact with the respective variable resistance patterns.

[0037] Each first memory cell MC1 may be symmetrical to a corresponding second memory cell MC2 about a corresponding bit line BL in the bit lines BL. In some embodiments, the variable resistor element VR of the first memory cell MC1 and the second memory cell MC2 may be jointly connected to the corresponding bit line BL in the bit lines BL. The switching element SW of the first memory cell MC1 may be connected to the first word line WL1. The switching element SW of the second memory cell MC2 may be connected to the second word line WL2. In some embodiments, the switching elements SW of the first memory cell MC1 and the second memory cell MC2 may be jointly connected to the corresponding bit line BL in the bit lines BL, and the variable resistor element VR of the first memory cell MC1 and the second memory cell MC2 may be connected to the corresponding word lines in the first word lines WL1 and the second word lines WL2.

[0038] Figure 2 This is a plan view illustrating a three-dimensional semiconductor memory device according to an example embodiment. Figure 3A and Figure 3B They are along Figure 2 The sectional view taken from lines I-I' and II-II'. Figure 4 yes Figure 3A A magnified view of part A.

[0039] Reference Figure 2 , Figure 3A and Figure 3B The stacked structure SS can be disposed on the substrate 100. The substrate 100 may include a semiconductor substrate. The substrate 100 may also include a thin layer disposed on the semiconductor substrate, but the embodiments are not limited thereto. The stacked structure SS may extend in the first direction D1.

[0040] Separating insulating patterns (hereinafter also referred to as first separating insulating patterns) 130 may be disposed on opposite sides of the stacked structures SS. Separating insulating patterns 130 may respectively cover opposite sidewalls of the stacked structures SS. Separating insulating patterns 130 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2, with the stacked structures SS located between the separating insulating patterns 130. The stacked structures SS may be spaced apart from adjacent stacked structures SS, and each separating insulating pattern 130 is located between a stacked structure SS and an adjacent stacked structure SS. Each of the separating insulating patterns 130 may include, for example, oxides, nitrides, and / or oxynitrides.

[0041] The stacked structure SS may include insulating layers 110 and first conductors (i.e., word lines WL1 and WL2) that are alternately and repeatedly stacked on a third direction D3. The first conductors may include first word lines WL1 and second word lines WL2. The first word lines WL1 and second word lines WL2 may extend in a first direction D1. The first word lines WL1 and second word lines WL2 may be spaced apart from each other in a second direction D2, may be located on corresponding insulating layers 110, and may be positioned between adjacent insulating layers 110 in the third direction D3. The first word lines WL1 may be stacked vertically and may be spaced apart from each other, with each insulating layer 110 located between the first word lines WL1. The second word lines WL2 may be stacked vertically and may be spaced apart from each other, with each insulating layer 110 located between the second word lines WL2. The lowermost insulating layer 110 of the insulating layer 110 may be placed between the lowermost first word line WL1 of the first word line WL1 and the lowermost second word line WL2 of the second word line WL2 and the substrate 100, but the embodiments are not limited thereto.

[0042] One of the insulating patterns 130 may cover the sidewall of the first letter WL1 and the sidewall of the insulating layer 110 located between the first letter WL1. Another insulating pattern 130 may cover the sidewall of the second letter WL2 and the sidewall of the insulating layer 110 located between the second letter WL2.

[0043] The stacked structure SS may include a second conductor (i.e., a bit line BL) between the first word line WL1 and the second word line WL2. The bit lines BL may extend from the upper surface of the substrate 100 in a third direction D3 and may be spaced apart from each other in a first direction D1. The bit lines BL may intersect the first word line WL1 and the second word line WL2. Each of the bit lines BL may pass through the insulating layer 110. The first word line WL1, the second word line WL2, and the bit line BL may include metals (e.g., copper, tungsten, or aluminum) and / or metal nitrides (e.g., tantalum nitride, titanium nitride, or tungsten nitride). The insulating layer 110 may include, for example, silicon nitride.

[0044] The stacked structure SS may include a buried insulating pattern 120 between the first word line WL1 and the second word line WL2. The buried insulating pattern 120 may extend from the upper surface of the substrate 100 in a third direction D3 and may be spaced apart from each other in a first direction D1.

[0045] In the first direction D1, each bit line BL can be positioned between adjacent buried insulation patterns 120 in the buried insulation pattern 120.

[0046] Each of the buried insulating patterns 120 may extend in the second direction D2 to contact the sidewalls of the first word line WL1 and the second word line WL2. Each of the buried insulating patterns 120 may penetrate the insulating layer 110. The buried insulating patterns 120 may include, for example, oxides, nitrides, and / or oxynitrides.

[0047] The stacked structure SS may include memory cells MC1 and MC2 located at the intersection of the first word line WL1 and the second word line WL2 with the bit line BL. Memory cells MC1 and MC2 may include: a first memory cell MC1 located at the intersection of the first word line WL1 and the bit line BL; and a second memory cell MC2 located at the intersection of the second word line WL2 and the bit line BL.

[0048] First memory cells MC1 can be spaced apart from each other in a first direction D1 and a third direction D3 between a first word line WL1 and a bit line BL. First memory cells MC1 located at the same horizontal level can be connected to the corresponding bit line BL and can be collectively connected to a corresponding first word line WL1 within the first word line WL1. First memory cells MC1 located at the same horizontal level can be separated from each other in the first direction D1 by corresponding buried insulating patterns 120. First memory cells MC1 spaced apart from each other in the third direction D3 can be connected to the corresponding first word line WL1 and can be collectively connected to a corresponding bit line BL within the bit line BL. First memory cells MC1 spaced apart from each other in the third direction D3 can be separated from each other by corresponding insulating layers 110.

[0049] The second memory cells MC2 can be spaced apart from each other in the first direction D1 and the third direction D3 between the second word line WL2 and the bit line BL. Second memory cells MC2 located at the same horizontal level can be connected to the corresponding bit line BL, and can also be connected to a corresponding second word line WL2. Second memory cells MC2 located at the same horizontal level can be separated from each other by corresponding buried insulating patterns 120. Second memory cells MC2 spaced apart from each other in the third direction D3 can be connected to the corresponding second word line WL2, and can also be connected to a corresponding bit line BL. Second memory cells MC2 spaced apart from each other in the third direction D3 can be separated from each other by corresponding insulating layers 110. The second memory cells MC2 can be spaced apart from the first memory cell MC1 along the second direction D2.

[0050] Each of the first memory unit MC1 and the second memory unit MC2 may include, as referenced Figure 1 The variable resistor element VR and the switching element SW are described. Each of the first memory cell MC1 and the second memory cell MC2 may be partially disposed between a pair of buried insulating patterns 120 adjacent to each other in the first direction D1 and between a pair of insulating layers 110 adjacent to each other in the third direction D3.

[0051] The first memory cell MC1 can be arranged symmetrically with respect to the second memory cell MC2 about the bit line BL between them. For example, the variable resistor elements VR of the first memory cell MC1 and the second memory cell MC2 that are adjacent to each other in the second direction D2 can be connected together to a corresponding bit line BL, and the switching elements SW of the first memory cell MC1 and the second memory cell MC2 that are adjacent to each other in the second direction D2 can be connected to the first word line WL1 and the second word line WL2, respectively. Optionally, the switching elements SW of the first memory cell MC1 and the second memory cell MC2 that are adjacent to each other in the second direction D2 can be connected together to a corresponding bit line BL, and the variable resistor elements VR of the first memory cell MC1 and the second memory cell MC2 that are adjacent to each other in the second direction D2 can be connected to the first word line WL1 and the second word line WL2, respectively.

[0052] More specifically, refer to Figure 3A and Figure 4 Each of the first memory cell MC1 and the second memory cell MC2 may include: a switching element SW; an intermediate electrode EP located between the switching element SW and the first word line WL1 or the second word line WL2; and a variable resistor element VR located between the switching element SW and each bit line BL.

[0053] The variable resistor element VR may include: a first variable resistor pattern RP1 and a second variable resistor pattern RP2, arranged in a second direction D2; a first electrode EL1, located between the first variable resistor pattern RP1 and each bit line BL; a second electrode EL2, located between the first variable resistor pattern RP1 and the second variable resistor pattern RP2; and a third electrode EL3, located between the second variable resistor pattern RP2 and the switching element SW.

[0054] The first variable resistance pattern RP1 and the second variable resistance pattern RP2 may include at least one of materials having information storage properties. When the 3D semiconductor memory device according to the example embodiment is a phase-change memory device, the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may include materials capable of reversibly transitioning between a crystalline and an amorphous state depending on temperature. In some embodiments, the phase transition temperature between the crystalline and amorphous states in the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may be between about 250°C and 350°C.

[0055] The first variable resistance pattern RP1 and the second variable resistance pattern RP2 may comprise phase change materials having the same chemical composition. In some embodiments, the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may comprise phase change materials with different chemical compositions. In this case, the phase transition temperatures of the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may be different from each other.

[0056] Each of the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may include a compound / mixture composed of at least one of a chalcogenide material (such as a material formed by combining Te or Se with at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C). Each of the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may include, for example, at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe.

[0057] In some embodiments, each of the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may have a superlattice structure in which layers including Ge and non-Ge layers are repeated and alternately stacked. For example, each of the first variable resistance pattern RP1 and the second variable resistance pattern RP2 may include a structure in which GeTe layers and SbTe layers are repeated and alternately stacked.

[0058] The first electrode EL1, the second electrode EL2, and the third electrode EL3 may comprise conductive materials with different resistivities. For example, the resistivity r1 of the first electrode EL1 may be greater than the resistivity of each of the second electrode EL2 and the third electrode EL3, the resistivity r3 of the second electrode EL2 may be less than the resistivity of each of the first electrode EL1 and the third electrode EL3, and the resistivity r2 of the third electrode EL3 may be less than the resistivity of the first electrode EL1 and greater than the resistivity of the second electrode EL2 (r1>r2>r3). In some embodiments, the resistivity of the second electrode EL2 may be greater than the resistivity of each of the first electrode EL1 and the third electrode EL3, and the resistivity of the first electrode EL1 may be less than the resistivity of each of the second electrode EL2 and the third electrode EL3.

[0059] In some embodiments, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include a conductive material doped with impurities. The impurity concentrations in the conductive materials of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be different. The impurities doped in the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include at least one of, for example, boron (B), phosphorus (P), silicon (Si), germanium (Ge), and carbon (C).

[0060] In some embodiments, the impurity concentration in the first electrode EL1 may be greater than the impurity concentration in each of the second electrode EL2 and the third electrode EL3, and the impurity concentration in the second electrode EL2 may be less than the impurity concentration in each of the first electrode EL1 and the third electrode EL3. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include TiSiN, and the silicon concentrations in the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be different from each other. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be a polycrystalline silicon pattern doped with impurities such as boron (B), phosphorus (P), silicon (Si), germanium (Ge), or carbon (C).

[0061] The switching element SW in each of the first memory cell MC1 and the second memory cell MC2 can be a bidirectional threshold switch (OTS) element with bidirectional characteristics. For example, the switching element SW can be an element based on a threshold switching phenomenon with a nonlinear (e.g., S-shaped) IV curve. The switching element SW can have a phase transition temperature higher than the phase transition temperature of each variable resistance pattern between a crystalline and amorphous state. For example, the phase transition temperature of the switching element SW can be between about 350°C and about 450°C. Therefore, during operation of the variable resistance memory device according to the example embodiment, the phase of the variable resistance pattern can reversibly change between a crystalline and amorphous state according to the operating voltage, while the switching element SW can remain substantially amorphous without undergoing a phase transition.

[0062] As used herein, substantially amorphous (or amorphous phase) does not preclude the presence of grain boundaries or locally crystalline portions within a part of the object. The switching element SW may comprise a compound / mixture of at least one of a chalcogenide material (such as a material formed by combining Te or Se with at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P). In addition to the aforementioned elements, the switching element SW may also comprise a thermally stabilizing element. The thermally stabilizing element may comprise at least one of C, N, and O. For example, the switching element SW may include at least one of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsSeGeC, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, AsTeGeSiSeNS, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe.

[0063] In some embodiments, the switching element SW of each of the first memory cell MC1 and the second memory cell MC2 may be a diode. In this case, the switching element SW may include patterns with different conductivity types. For example, the switching element SW may be a silicon diode or an oxide diode with rectification characteristics. The switching element SW may have a structure in which an n-type impurity-doped semiconductor pattern is bonded to a p-type impurity-doped semiconductor pattern. Optionally, the switching element SW may be a P-NiO... x With N-TiO x Bonding or P-CuO x With N-TiO xJunction oxide diode.

[0064] The intermediate electrode EP between the switching element SW and the first word line WL1 or the second word line WL2 may include at least one of, for example, W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0065] When programming current flows in the first memory cell MC1 or the second memory cell MC2 between the bit line BL and the first word line WL1 or the second word line WL2, Joule heating can be generated at the interface between the first variable resistor pattern RP1 and the second variable resistor pattern RP2 and the first electrode EL1, the second electrode EL2, and the third electrode EL3. Joule heating can transform the portion of the first variable resistor pattern RP1 or the second variable resistor pattern RP2 adjacent to the first electrode EL1, the second electrode EL2, and the third electrode EL3 into an amorphous or crystalline state.

[0066] Because the first electrode EL1, the second electrode EL2, and the third electrode EL3 are formed of materials with different resistivities, the volumes of the phase transition portions P1, P2, and P3 can be different when the programming current flows in the variable resistive element VR. Based on the programming current, the variable resistive element VR can have any of the four resistance levels.

[0067] As an example, when a first programming current flows in the variable resistor element VR, the portion P1 of the first variable resistor pattern RP1 adjacent to the first electrode EL1, which has the highest resistivity, can undergo a phase transition. Subsequently, when a second programming current with a current intensity greater than the first programming current flows in the variable resistor element VR, the portion P2 of the second variable resistor pattern RP2 adjacent to the third electrode EL3 can undergo a phase transition. Simultaneously, the volume of the phase-transition portion P1 in the first variable resistor pattern RP1 can increase. Subsequently, when a third programming current with a current intensity greater than the second programming current flows in the variable resistor element VR, the portions P3 of the first and second variable resistor patterns RP1 and RP2 adjacent to the second electrode EL2, which has the lowest resistivity, can undergo a phase transition. Simultaneously, the volumes of the phase-transition portions P1 in the first variable resistor pattern RP1 and P2 in the second variable resistor pattern RP2 can increase.

[0068] Figure 5 This is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to an example embodiment. Figure 6 It is along Figure 5 The cross-sectional view taken by line III-III' shows a three-dimensional semiconductor memory device according to an example embodiment. Figure 7 yes Figure 6 A magnified view of part B.

[0069] For ease of explanation, the references and comparisons are omitted. Figure 2 , Figure 3A and Figure 3B The described technical structure is the same as the technical structure described.

[0070] Reference Figure 5 and Figure 6 As described above, the corresponding first memory cell MC1 can be symmetrical with respect to the corresponding second memory cell MC2 about the corresponding bit line BL.

[0071] As an example, the variable resistor element VR of the first memory cell MC1 and the second memory cell MC2 can be connected together to the corresponding bit line BL in the bit line BL. The switching element SW of the first memory cell MC1 can be connected to the first word line WL1. The switching element SW of the second memory cell MC2 can be connected to the second word line WL2.

[0072] In each of the first memory cell MC1 and the second memory cell MC2, the variable resistance element VR may include at least three variable resistance patterns and electrodes in contact with the respective variable resistance patterns.

[0073] Specifically, each of the first memory cell MC1 and the second memory cell MC2 may include: a switching element SW; an intermediate electrode EP located between the switching element SW and the first word line WL1 or the second word line WL2; and a variable resistor element VR located between the switching element SW and the bit line BL. Here, the variable resistor element VR may include: a first variable resistor pattern RP1, a second variable resistor pattern RP2, a third variable resistor pattern RP3, and a fourth variable resistor pattern RP4, arranged sequentially in the second direction D2; a first electrode EL1 located between the first variable resistor pattern RP1 and the bit line BL; a second electrode EL2 located between the first variable resistor pattern RP1 and the second variable resistor pattern RP2; a third electrode EL3 located between the second variable resistor pattern RP2 and the third variable resistor pattern RP3; a fourth electrode EL4 located between the third variable resistor pattern RP3 and the fourth variable resistor pattern RP4; and a fifth electrode EL5 located between the fourth variable resistor pattern RP4 and the switching element SW.

[0074] The first electrodes EL1 to the fifth electrodes EL5 can comprise conductive materials with different resistivities. Therefore, when a programming current flows in the variable resistive element VR, the sequence of phase transitions can be changed according to the resistivity of the first electrodes EL1 to the fifth electrodes EL5.

[0075] As an example, the resistivity r1 of the first electrode EL1 can be greater than the resistivity of each of the second electrodes EL2 through the fifth electrode EL5. The resistivity r5 of the second electrode EL2 can be less than the resistivity of each of the first electrode EL1, the third electrode EL3, the fourth electrode EL4, and the fifth electrode EL5. The resistivity r3 of the third electrode EL3 can be less than the resistivity of the first electrode EL1 and greater than the resistivity of the second electrode EL2. The resistivity r2 of the fourth electrode EL4 can be less than the resistivity of the first electrode EL1 and greater than the resistivity of the third electrode EL3. The resistivity r4 of the fifth electrode EL5 can be less than the resistivity of the third electrode EL3 and greater than the resistivity of the second electrode EL2 (r1>r2>r3>r4>r5).

[0076] In this case, as the programmed current flowing in the variable resistor element VR increases sequentially, phase transitions occur in the first variable resistor pattern RP1 to the fourth variable resistor pattern RP4 in the order of adjacent to the first electrode EL1, adjacent to the fourth electrode EL4, adjacent to the third electrode EL3, adjacent to the fifth electrode EL5, and adjacent to the second electrode EL2.

[0077] Figure 8 This is a plan view illustrating a three-dimensional semiconductor memory device according to an example embodiment. Figure 9A and Figure 9B They are along Figure 8 The cross-sectional views taken by lines IV-IV' and V-V' illustrate a three-dimensional semiconductor memory device according to an exemplary embodiment. Figure 10A , Figure 10B , Figure 10C and Figure 10D yes Figure 9A A magnified view of part C.

[0078] For ease of explanation, the references and comparisons are omitted. Figure 2 , Figure 3A and Figure 3B The described technical structure is the same as the technical structure described.

[0079] Reference Figure 8 , Figure 9A and Figure 9B The bit line BL can be located between the first word line WL1 and the second word line WL2. The first memory cell MC1 can be located at the intersection of the first word line WL1 and the bit line BL. The second memory cell MC2 can be located at the intersection of the second word line WL2 and the bit line BL.

[0080] Each of the first memory cell MC1 and the second memory cell MC2 may include: a switching element SW; a first intermediate electrode EP1 located between the switching element SW and the first word line WL1 or the second word line WL2; a variable resistor element VR located between the switching element SW and the bit line BL; and a second intermediate electrode EP2 located between the variable resistor element VR and the switching element SW.

[0081] The switching element SW can be positioned between the variable resistor element VR and either the first word line WL1 or the second word line WL2. The variable resistor element VR can be positioned between the bit line BL and the switching element SW. The variable resistor element VR can include multiple variable resistor patterns. The sidewalls of the variable resistor patterns can collectively contact a corresponding bit line BL.

[0082] Specifically, refer to Figures 10A to 10D The variable resistor element VR may include a first variable resistor pattern RP1 to a fourth variable resistor pattern RP4 arranged sequentially in the second direction D2. As an example, the first variable resistor pattern RP1 may be adjacent to the switching element SW (or adjacent to the first word line WL1 or the second word line WL2).

[0083] Each of the first variable resistor patterns RP1 to the third variable resistor patterns RP3 may include: a sidewall portion VP adjacent to the sidewall of the first word line WL1 or the second word line WL2; and a horizontal portion HP extending from opposite ends of the sidewall portion VP in a second direction D2. As an example, the sidewall portions VP of the first variable resistor patterns RP1 to the third variable resistor patterns RP3 may extend parallel to the third direction D3. The sidewall portion VP of the first variable resistor pattern RP1 may contact the second intermediate electrode EP2 between the switching element SW and the variable resistor element VR. Furthermore, as... Figure 9B As shown, the horizontal portion HP of each of the first variable resistor patterns RP1 to the third variable resistor patterns RP3 may include: a first horizontal portion parallel to the upper surface of the corresponding insulating layer 110 and the lower surface of the corresponding insulating layer 110 in the insulating layer 110; and a second horizontal portion parallel to the sidewall of the corresponding buried insulating pattern 120 in the buried insulating pattern 120.

[0084] The fourth variable resistor pattern RP4 may fill the space defined by the sidewall portion VP and the horizontal portion HP of the third variable resistor pattern RP3. Optionally, similar to the first to third variable resistor patterns RP1, the fourth variable resistor pattern RP4 may include the sidewall portion VP and the horizontal portion HP.

[0085] One sidewall of the horizontal portion HP of the first variable resistor pattern RP1 to the fourth variable resistor pattern RP4 can be vertically aligned. As an example, one sidewall of the horizontal portion HP of the first variable resistor pattern RP1 to the fourth variable resistor pattern RP4 can contact the bit line BL.

[0086] As an example, refer to Figure 10A In each of the first to third variable resistor patterns RP1 to RP3, the thickness a of the sidewall portion VP in the second direction D2 (i.e., the horizontal direction) can be substantially the same as the thickness b of each of the horizontal portions HP in the third direction D3 (i.e., the vertical direction). In some embodiments, reference is made to... Figure 10B The thickness 'a' of the sidewall portion VP can be different from the thickness 'b' of each of the horizontal portions HP. For example, the thickness 'a' of the sidewall portion VP can be greater than the thickness 'b' of each of the horizontal portions HP.

[0087] Reference Figure 10A and Figure 10B The variable resistor element VR may include a first electrode EL1, a second electrode EL2, and a third electrode EL3 located between corresponding variable resistor patterns in a first variable resistor pattern RP1 to a fourth variable resistor pattern RP4 arranged sequentially. In this case, the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include conductive materials with different resistivities. As described above, the resistivity r1 of the first electrode EL1 may be greater than the resistivity of each of the second electrode EL2 and the third electrode EL3, and the resistivity r3 of the second electrode EL2 may be less than the resistivity of each of the first electrode EL1 and the third electrode EL3. The resistivity r2 of the third electrode EL3 may be less than the resistivity of the first electrode EL1 and greater than the resistivity of the second electrode EL2.

[0088] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include: a first portion PO1, contacting the horizontal portion HP of a corresponding variable resistance pattern among the first variable resistance patterns RP1 to the third variable resistance patterns RP3; and a second portion PO2, extending from the first portion PO1 and contacting the sidewall portion VP. Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have a substantially uniform thickness in the first portion PO1 and the second portion PO2. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have... to The thickness.

[0089] One sidewall of the first portion PO1 of the first electrode EL1, the second electrode EL2, and the third electrode EL3 can be vertically aligned. For example, one sidewall of the first portion PO1 of the first electrode EL1, the second electrode EL2, and the third electrode EL3 can contact one sidewall of the bit line BL.

[0090] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may comprise a conductive material having anisotropic current characteristics. When a predetermined voltage is applied to each of the first electrode EL1, the second electrode EL2, and the third electrode EL3, its current characteristics in the second direction D2 may differ from its current characteristics in the third direction D3. For example, in each of the first electrode EL1, the second electrode EL2, and the third electrode EL3, the amount of current flowing in the second direction D2 may be greater than the amount of current flowing in the third direction D3.

[0091] Therefore, when the programming current flows in the variable resistor element VR, a phase transition can occur in the sidewall portions VP of the first to fourth variable resistor patterns RP1 to RP4. That is, during programming operation, each of the sidewall portions VP of the first to fourth variable resistor patterns RP1 to RP4 may include a phase transition portion. As an example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include a material having anisotropic resistivity depending on the direction of the current. That is, in each of the first electrode EL1, the second electrode EL2, and the third electrode EL3, the first portion PO1 and the second portion PO2 may have different resistivities. For example, the larger of the resistivity of the first portion PO1 and the resistivity of the second portion PO2 may be greater than about 5 times the smaller of the resistivity of the first portion PO1 and the resistivity of the second portion PO2. Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have a resistivity of at least 20 μΩ·cm. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have a resistivity of 20 μΩ·cm to 20 mΩ·cm. In some embodiments, the crystal size of each of the first portion PO1 and the crystal size of each of the second portion PO2 in each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be different. Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may comprise a conductive polymer material having anisotropic resistivity, and may comprise, for example, TiO2.

[0092] In some embodiments, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include a conductive material doped with impurities. The impurity concentrations in the conductive materials of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be different.

[0093] Reference Figure 10C The first variable resistor pattern RP1 to the fourth variable resistor pattern RP4 may include different phase change materials. For example, the first variable resistor pattern RP1 may include a first phase change material, the second variable resistor pattern RP2 may include a second phase change material, the third variable resistor pattern RP3 may include a third phase change material, and the fourth variable resistor pattern RP4 may include a fourth phase change material.

[0094] As an example, the first variable resistance pattern RP1 to the fourth variable resistance pattern RP4 may include chalcogenide materials with different compositions. The phase transition temperatures at which the first to fourth phase change materials transform into an amorphous or crystalline state may be different.

[0095] Reference Figure 10D The first variable resistance pattern RP1 to the fourth variable resistance pattern RP4 may include different phase change materials, and the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be respectively placed between the first variable resistance pattern RP1 to the fourth variable resistance pattern RP4. In this case, the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include conductive materials with different resistivities.

[0096] Figure 11 This is a plan view illustrating a three-dimensional semiconductor memory device according to an example embodiment. Figure 12A and Figure 12B They are along Figure 11 The cross-sectional views taken by lines VI-VI' and VII-VII' show a three-dimensional semiconductor memory device according to an example embodiment.

[0097] For ease of explanation, the references and comparisons are omitted. Figure 2 , Figure 3A and Figure 3B The described technical structure is the same as the technical structure described.

[0098] Reference Figure 11 , Figure 12A and Figure 12B The first word line WL1 and the second word line WL2 can be positioned between a pair of first separating insulating patterns 130. A pair of bit lines BL can be positioned between the first word line WL1 and the second word line WL2.

[0099] The first line BL1 can be arranged spaced apart from each other in the first direction D1. The second line BL2 can be arranged spaced apart from each other in the first direction D1. The first line BL1 can be separated from the second line BL2 by the second separating insulating pattern 140 in the second direction D2.

[0100] The first line BL1 can extend from the third line to D3. The second line BL2 can extend from the third line to D3.

[0101] The second insulating pattern 140 can extend in the first direction D1 and can be disposed between the first bit line BL1 and the second bit line BL2.

[0102] Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16 , Figure 17 and Figure 18 This is a cross-sectional view illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an example embodiment. Figure 13A , Figure 14A , Figure 15A , Figure 16 , Figure 17 and Figure 18 It is along Figure 2 A cross-sectional view taken by line I-I'. Figure 13B , Figure 14B and Figure 15B It is along Figure 2 The sectional view taken from line II-II'.

[0103] Reference Figure 2 , Figure 13A and Figure 13B A thin structure TS can be formed on the substrate 100. The thin structure TS may include an insulating layer 110 and a sacrificial layer 115 stacked on the upper surface of the substrate 100. The insulating layer 110 and the sacrificial layer 115 may be stacked alternately and repeatedly on a third direction D3. The lowermost insulating layer 110 may be placed between the lowermost sacrificial layer 115 and the substrate 100, but the embodiments are not limited thereto.

[0104] The insulating layer 110 may include, for example, silicon nitride or silicon oxide. The sacrificial layer 115 may include a material that has etch selectivity relative to the insulating layer 110. For example, the sacrificial layer 115 may include impurity-doped silicon or impurity-doped metal oxide. In some embodiments, the sacrificial layer 115 may include a chalcogenide material. The sacrificial layer 115 may include a compound / mixture of at least one of chalcogenide materials (such as materials formed by combining Te or Se with at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P). The sacrificial layer 115 may include impurities (e.g., at least one of C, N, B, and O).

[0105] An embedded insulating pattern 120 can be formed in a thin structure TS. The embedded insulating patterns 120 can be spaced apart from each other in a first direction D1 and can extend in a second direction D2 in the thin structure TS. Each of the embedded insulating patterns 120 can pass through the thin structure TS to contact the upper surface of the substrate 100.

[0106] The buried insulating pattern 120 can be formed by, for example, the following steps: forming vias through the thin structure TS; forming a buried insulating layer on the thin structure TS to fill the vias; and planarizing the buried insulating layer until the upper surface of the thin structure TS is exposed. The vias can be formed by, for example, the following steps: forming a mask pattern on the thin structure TS to define the area in which the buried insulating pattern 120 will be formed; and using the mask pattern as an etching mask to etch the thin structure TS. The vias can be spaced apart from each other in a first direction D1. Each of the vias can have a linear shape extending in a second direction D2 and can expose the upper surface of the substrate 100. When the buried insulating layer is planarized, the buried insulating pattern 120 can be locally formed in the vias. The buried insulating pattern 120 can include, for example, oxides, nitrides, and / or oxynitrides.

[0107] Reference Figure 2 , Figure 14A and Figure 14B A pair of trenches 130T can be formed to penetrate the thin structure TS. The pair of trenches 130T can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. The pair of trenches 130T can be spaced apart from each other in the second direction D2, and a buried insulating pattern 120 is located between the pair of trenches 130T. Each of the pair of trenches 130T can expose the sidewalls of the insulating layer 110 and the sacrificial layer 115 of the thin structure TS, and can expose the surface of the substrate 100. The trenches 130T can be formed by, for example, the following steps: forming a mask pattern on the thin structure TS to define the area in which the trenches 130T will be formed; and using the mask pattern as an etching mask to etch the thin structure TS.

[0108] Subsequently, each exposed portion of the sacrificial layer 115 in the trench 130T can be removed, so that a first recessed region R1 can be formed between the insulating layers 110.

[0109] The first recessed region R1 can be formed by etching the sacrificial layer 115, for example, by etching a process with etch selectivity relative to the insulating layer 110, the buried insulating pattern 120, and the substrate 100. The first recessed region R1 can extend horizontally from each of the trenches 130T. The first recessed regions R1 can extend in a first direction D1 and can be spaced apart from each other in a third direction D3. Each of the first recessed regions R1 can be formed between a pair of insulating layers 110 adjacent to each other along the third direction D3. Each of the first recessed regions R1 can extend in the first direction D1 and can expose the sidewalls of the buried insulating pattern 120 and the sidewalls of the sacrificial layer 115 between the buried insulating patterns 120.

[0110] Reference Figure 2 , Figure 15A and Figure 15B A first word line WL1 and a second word line WL2 can be formed in each of the first recessed regions R1. The first word line WL1 and the second word line WL2 can be formed by, for example, the following steps: forming a first conductive layer on a thin structure TS to fill at least a portion of each of the first recessed regions R1 and trenches 130T; and removing the first conductive layer from the trenches 130T. The first conductive layer may include a metal (e.g., copper, tungsten, or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride). Removal of the first conductive layer may include etching the first conductive layer until the upper surface of the thin structure TS and the inner surface of each of the trenches 130T are exposed. When the first conductive layer is etched, the first word line WL1 and the second word line WL2 can be locally formed in the first recessed region R1. The first word line WL1 and the second word line WL2 may extend in a first direction D1 and may contact the sidewalls of the buried insulating pattern 120 and the sidewalls of the sacrificial layer 115 between the buried insulating patterns 120.

[0111] After forming the first word line WL1 and the second word line WL2, a separator insulating pattern 130 can be formed in the trench 130T. The separator insulating pattern 130 can be formed by, for example, the following steps: forming a separator insulating layer on a thin structure TS to fill the trench 130T; and planarizing the separator insulating layer until the upper surface of the thin structure TS is exposed. The separator insulating pattern 130 can be locally formed in the trench 130T by a planarization process. The separator insulating patterns 130 can extend in a first direction D1 and can be spaced apart from each other in a second direction D2, with the first word line WL1 and the second word line WL2 located between the separator insulating patterns 130. The separator insulating pattern 130 can include oxides, nitrides, and / or oxynitrides.

[0112] Reference Figure 2 and Figure 16Vertical vias 140H can be formed to penetrate the thin structure TS. The vertical vias 140H can be spaced apart from each other in a first direction D1 between the separating insulating patterns 130. The vertical vias 140H can be arranged alternately with the buried insulating patterns 120 along the first direction D1. Each of the vertical vias 140H can expose the sidewalls of the insulating layer 110 and the sacrificial layer 115, as well as the upper surface of the substrate 100. Each of the vertical vias 140H can expose the sidewalls of a pair of buried insulating patterns 120 adjacent to each other in the first direction D1. The vertical vias 140H can be formed by, for example, the following steps: forming a mask pattern on the thin structure TS to define the area in which the vertical vias 140H will be formed; and using the mask pattern as an etching mask to etch the thin structure TS.

[0113] Subsequently, each exposed sacrificial layer 115 in the vertical hole 140H can be removed to form a second recessed region R2 between the insulating layers 110. As an example, the second recessed region R2 may expose one sidewall of the first word line WL1 and one sidewall of the second word line WL2. Alternatively, when forming the second recessed region R2, a portion of the sacrificial layer 115 may be retained between the insulating layers 110.

[0114] The second recessed region R2 can be formed by etching the sacrificial layer 115, for example, by etching a process that has etch selectivity relative to the insulating layer 110, the buried insulating pattern 120, and the substrate 100. The second recessed region R2 can extend horizontally from each of the vertical holes 140H. Each of the second recessed regions R2 can be formed between a pair of insulating layers 110 adjacent to each other along the third direction D3, and between a pair of buried insulating patterns 120 adjacent to each other along the first direction D1.

[0115] Reference Figure 2 and Figure 17 A switching element SW can be formed to partially fill the second recessed region R2. The switching element SW can be formed separately by the following steps: forming a switching layer to conformally cover the inner surface of the second recessed region R2; and removing a portion of the switching layer in a portion of the second recessed region R2 to locally form the switching element SW in the second recessed region R2.

[0116] In some embodiments, where the sacrificial layer 115 comprises a chalcogenide material, when the second recessed region R2 is formed, a portion of the sacrificial layer 115 may be retained between the insulating layers 110, and the retained portion of the sacrificial layer 115 may constitute a switching element SW.

[0117] Before forming the switching element SW, an intermediate electrode EP can be formed on one sidewall of the second recessed region R2, exposed in each of the first word lines WL1 and the second word lines WL2. The intermediate electrode EP can be formed by, for example, the following steps: forming a metal layer on the thin structure TS to fill at least a portion of each of the second recessed region R2 and the vertical hole 140H; removing the metal layer from each of the vertical holes 140H; and recessing the metal layer in each of the second recessed regions R2 until the metal layer remains at the required thickness.

[0118] After forming the switching element SW, the initial electrode PE and the variable resistor pattern RP can be alternately formed in the second recessed region R2.

[0119] The initial electrode PE can be formed individually by, for example, the following steps: forming a conductive layer on a thin structure TS to fill at least a portion of each of the second recessed region R2 and the vertical hole 140H; removing the conductive layer from each of the vertical holes 140H; and recessing the conductive layer in each of the second recessed regions R2 until the conductive layer remains at the required thickness. The conductive layer may comprise a metal or a semiconductor material.

[0120] The variable resistance pattern RP can be formed individually by, for example, the following steps: forming a variable resistance layer on a thin structure TS to fill at least a portion of each of the second recessed regions R2 and the vertical holes 140H; etching the variable resistance layer until the upper surface of the thin structure TS and the inner surface of each of the vertical holes 140H are exposed; and recessing the variable resistance layer in each of the second recessed regions R2 until the remaining required thickness of the variable resistance layer is achieved. When the variable resistance layer is recessed, the variable resistance pattern RP can be locally formed in each of the second recessed regions R2.

[0121] Subsequently, a bit line BL can be formed in the vertical aperture 140H. The bit line BL can be formed by, for example, the following steps: depositing a metal layer to partially or completely fill the vertical aperture 140H; and etching the metal layer to expose the upper surface of the uppermost layer in the insulating layer 110. Therefore, the bit line BL can be formed locally in the vertical aperture 140H alone.

[0122] Subsequently, refer to Figure 2 and Figure 18 Ion implantation processes S1, S2, and S3 can be performed on the initial electrode PE. Therefore, electrodes with different resistivity (e.g., first electrode EL1 and second electrode EL2) can be formed between the variable resistance patterns RP.

[0123] More specifically, a first ion implantation mask can be formed on the uppermost insulating layer 110. The first ion implantation mask may have an opening at a location corresponding to the initial electrode PE adjacent to the switching element SW. A first ion implantation process S1 can be performed to implant impurities at a first concentration using the first ion implantation mask. The first ion implantation mask can be removed.

[0124] A second ion implantation mask with an opening at a position corresponding to the initial electrode PE adjacent to the co-position line BL can be formed on the uppermost insulating layer 110. Then, a second ion implantation process S2 can be performed to implant impurities at a second concentration different from the first concentration using the second ion implantation mask. The second ion implantation mask can be removed.

[0125] Subsequently, a third ion implantation mask with an opening at the position corresponding to the initial electrode PE between the variable resistor pattern RP can be formed on the uppermost insulating layer 110. Then, a third ion implantation process S3 can be performed to implant impurities using the third ion implantation mask at each of the first and second concentrations. The third ion implantation mask can be removed.

[0126] In the first ion implantation process S1, the second ion implantation process S2, and the third ion implantation process S3, at least one of Si, P, C, N, B, and O can be used as an impurity.

[0127] Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a cross-sectional view illustrating a method for manufacturing a three-dimensional semiconductor memory device, and is along... Figure 2 A cross-sectional view taken along line I-I'. For ease of explanation, the description of the same technical construction as the method for manufacturing a three-dimensional semiconductor device described above can be omitted.

[0128] Reference Figure 19 In reference Figure 16 Following the described process, after the switching element SW is locally formed in the second recessed region R2, a first electrode layer L1 can be formed to conformally cover the inner surface of the second recessed region R2 and the inner sidewall of the vertical hole 140H with a uniform thickness. The first electrode layer L1 can be formed by chemical vapor deposition or atomic vapor deposition. The first electrode layer L1 may include a material having a first resistivity.

[0129] Reference Figure 20A portion of the first electrode layer L1 can be etched isotropically to form first electrodes EL1 that are vertically spaced apart from each other. When the first electrode layer L1 isotropically etched, a portion of the inner wall of the vertical hole 140H and a portion of the upper and lower surfaces of the insulating layer 110 can be exposed.

[0130] Reference Figure 21 A first variable resistance layer RL1 can be formed to conformally cover the inner surface of the second recessed region R2 with the first electrode EL1 and the inner sidewall of the vertical hole 140H with a uniform thickness.

[0131] Reference Figure 22 A portion of the first variable resistance layer RL1 can be etched isotropically to form a first variable resistance pattern RP1 that is vertically spaced apart from each other. When the first variable resistance layer RL1 isotropically etched, a portion of the inner wall of the vertical hole 140H and a portion of the upper and lower surfaces of the insulating layer 110 can be exposed.

[0132] Reference Figure 23 A second electrode layer L2 can be formed to conformally cover the inner surface of the second recessed region R2, which has a first variable resistance pattern RP1, and the inner sidewall of the vertical hole 140H with a uniform thickness. The second electrode layer L2 may include a material having a second resistivity different from the first resistivity.

[0133] Reference Figure 24 A portion of the second electrode layer L2 can be etched isotropically to form second electrodes EL2 that are vertically spaced apart from each other. When the second electrode layer L2 isotropically etched, a portion of the inner wall of the vertical hole 140H and a portion of the upper and lower surfaces of the insulating layer 110 can be exposed.

[0134] Subsequently, additional variable resistance patterns and additional electrodes can be alternately and repeatedly formed in the second recessed region R2.

[0135] Example embodiments have been disclosed herein. Although specific terminology has been used, it will be used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art from the time of filing of this application that, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a substrate; a plurality of first wires extending in a first direction parallel to an upper surface of the substrate and spaced apart from each other in a second direction crossing the first direction and parallel to the upper surface of the substrate; a second wire extending in a third direction perpendicular to the upper surface of the substrate; and a plurality of memory cells located at intersections between the plurality of first wires and the second wire, each of the plurality of memory cells including a variable resistance element and a switching element arranged horizontally in the second direction, wherein the variable resistance element includes: a first variable resistance pattern and a second variable resistance pattern arranged in the second direction; a first electrode located between the first variable resistance pattern and the first wire; a second electrode located between the second variable resistance pattern and the second wire; and a third electrode located between the first variable resistance pattern and the second variable resistance pattern, the first electrode, the second electrode, and the third electrode having different resistivities, wherein each of the first variable resistance pattern and the second variable resistance pattern includes: a sidewall portion adjacent to the first wire; and a plurality of horizontal portions extending in the second direction from opposite ends of the sidewall portion, wherein the plurality of horizontal portions of the first variable resistance pattern and the second variable resistance pattern contact the second wire. The resistivity of the third electrode is smaller than the resistivity of each of the first electrode and the second electrode.

2. The three-dimensional semiconductor memory device as claimed in claim 1, wherein, The resistivity of the first electrode is larger than the resistivity of the second electrode.

3. The three-dimensional semiconductor memory device as claimed in claim 2, wherein, Each of the first electrode, the second electrode, and the third electrode includes a conductive material doped with an impurity, and the impurity concentrations of the first electrode, the second electrode, and the third electrode are different.

4. The three-dimensional semiconductor memory device as claimed in claim 1, wherein, The variable resistance element further includes:

5. The three-dimensional semiconductor memory device as claimed in claim 1, wherein, a third variable resistance pattern and a fourth variable resistance pattern arranged in the second direction between the second electrode and the second wire; a fourth electrode located between the third variable resistance pattern and the fourth variable resistance pattern; and a fifth electrode located between the fourth variable resistance pattern and the second wire, wherein each of the fourth electrode and the fifth electrode has a resistivity different from the resistivity of each of the first electrode to the third electrode. The resistivity of the first electrode is larger than the resistivity of each of the second electrode to the fifth electrode, and the resistivity of the third electrode is smaller than the resistivity of each of the second electrode, the fourth electrode, and the fifth electrode.

6. The three-dimensional semiconductor memory device as claimed in claim 5, wherein, The resistivity of the fourth electrode is larger than the resistivity of the second electrode, and the resistivity of the fifth electrode is smaller than the resistivity of the second electrode.

7. The three-dimensional semiconductor memory device as claimed in claim 6, wherein, 8. The three-dimensional semiconductor memory device as claimed in claim 1, wherein: each of the first electrode to the third electrode includes: a first portion in contact with the sidewall portion of each of the first variable resistance pattern and the second variable resistance pattern; and a plurality of second portions extending from the first portion and in contact with the plurality of horizontal portions of each of the first variable resistance pattern and the second variable resistance pattern, and the first portion has a resistivity different from the resistivity of each of the plurality of second portions.

9. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a substrate; a first wire extending in a first direction parallel to an upper surface of the substrate; ​ a second wire extending in a second direction perpendicular to the upper surface of the base and crossing the first wire; and a plurality of memory cells between the first wire and the second wire, wherein each of the plurality of memory cells includes a first variable resistance pattern and a second variable resistance pattern arranged in a third direction crossing the first direction and the second direction and parallel to the upper surface of the base, and wherein each of the first variable resistance pattern and the second variable resistance pattern includes a side wall portion adjacent to a side wall of the first wire and a plurality of horizontal portions extending in the third direction from opposite ends of the side wall portion, wherein the plurality of horizontal portions of the first variable resistance pattern and the second variable resistance pattern contact the second wire.

10. The three-dimensional semiconductor memory device as claimed in claim 9, wherein, The side walls of the horizontal portions of the first variable resistance pattern are vertically aligned with the side walls of the horizontal portions of the second variable resistance pattern.

11. The three-dimensional semiconductor memory device as claimed in claim 9, wherein, The first variable resistance pattern and the second variable resistance pattern include chalcogenide materials having different compositions.

12. The three-dimensional semiconductor memory device as claimed in claim 9, wherein, In each of the first variable resistance pattern and the second variable resistance pattern, a thickness of the side wall portion in the third direction is different from a thickness of each of the horizontal portions in the second direction.

13. The three-dimensional semiconductor memory device of claim 9, further comprising: a first electrode between the first wire and the first variable resistance pattern; a second electrode between the first variable resistance pattern and the second variable resistance pattern; and a third electrode between the second variable resistance pattern and the second wire, wherein each of the first electrode to the third electrode includes a first portion in contact with the side wall portion of each of the first variable resistance pattern and the second variable resistance pattern and a plurality of second portions extending from the first portion and in contact with the horizontal portions of each of the first variable resistance pattern and the second variable resistance pattern. In each of the first electrode to the third electrode, a resistivity of the first portion is different from a resistivity of each of the plurality of second portions.

14. The three-dimensional semiconductor memory device as claimed in claim 13, wherein, Side walls of the plurality of second portions of the first electrode to the third electrode are vertically aligned.

15. The three-dimensional semiconductor memory device as claimed in claim 13, wherein, The first electrode to the third electrode have different resistivities.

16. The three-dimensional semiconductor memory device as claimed in claim 13, wherein, A resistivity of the second electrode is smaller than a resistivity of each of the first electrode and the third electrode, and a resistivity of the first electrode is larger than a resistivity of the third electrode.

17. The three-dimensional semiconductor memory device as claimed in claim 16, wherein, 18. A three-dimensional semiconductor memory device, comprising: a base; a plurality of stack structures and a plurality of buried insulating patterns alternately arranged on the base in a first direction parallel to an upper surface of the base, each of the plurality of stack structures including a plurality of memory cells and a plurality of insulating layers alternately stacked with each other in a second direction perpendicular to the upper surface of the base; a plurality of first wires extending in the first direction, located at a first side of the plurality of memory cells and stacked in the second direction; and a plurality of second wires located between respective ones of the plurality of buried insulating patterns, located at a second side of the plurality of memory cells opposite the first side of the plurality of memory cells, ​ wherein each of the plurality of memory cells includes a plurality of variable resistance patterns and a plurality of electrodes between respective ones of the plurality of variable resistance patterns, and wherein the plurality of electrodes have different resistivities, wherein each of the plurality of variable resistance patterns includes a sidewall portion adjacent to the first conductive line and a plurality of horizontal portions extending from opposite ends of the sidewall portion in a third direction, wherein the plurality of horizontal portions of the plurality of variable resistance patterns contact the second conductive line, and the third direction intersects the first and second directions and is parallel to the upper surface of the substrate.

19. The three-dimensional semiconductor memory device of claim 18, wherein: the plurality of variable resistance patterns includes a first variable resistance pattern and a second variable resistance pattern arranged in a third direction, the plurality of electrodes includes a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and each of the plurality of second conductive lines, and a third electrode between the first variable resistance pattern and the second variable resistance pattern, and the resistivities of the first, second, and third electrodes are different from each other.

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