Display device

Abstract

The present disclosure relates to a display device including a substrate, a first thin film transistor and a second thin film transistor provided at different distances from a top surface of the substrate. A display means is electrically connected to the first thin film transistor. The first thin film transistor includes a first semiconductor layer including polycrystalline silicon, and a first gate electrode overlapping with a channel region of the first semiconductor layer in a direction of a thickness of the substrate. The second thin film transistor includes a second semiconductor layer including an oxide semiconductor. The first gate electrode has a stacked structure including a first layer and a second layer. The second layer includes titanium, and the first layer includes a material different from the second layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0069553, filed on June 12, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] One or more embodiments relate to a display apparatus. BACKGROUND

[0004] Display apparatuses for displaying various types of electrical signal information have been rapidly developed. For example, various flat panel display apparatuses have been developed, which provide improved features such as a slim profile, a light weight, and a low power consumption. These flat panel display apparatuses can include thin film transistors (TFTs) and capacitors, etc. The TFTs can have different characteristics according to a material of a semiconductor layer included in the TFTs. A display apparatus can employ different types of TFTs to provide improved performance. SUMMARY

[0005] For example, a display apparatus can employ a first thin film transistor including a polysilicon semiconductor layer and a second thin film transistor including an oxide semiconductor layer. The first thin film transistor can have improved characteristics by reducing defects (traps) within the polysilicon semiconductor layer through a heat treatment. However, the heat treatment performed to improve the characteristics of the first thin film transistor can affect the oxide semiconductor layer, and thus the characteristics of the second thin film transistor can be changed.

[0006] One or more exemplary embodiments include a display apparatus capable of improving characteristics of a polysilicon semiconductor layer without affecting an oxide semiconductor layer.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the description, or can be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more exemplary embodiments, a display apparatus includes a substrate, a first thin film transistor and a second thin film transistor disposed on the substrate at different distances from a top surface of the substrate. A display device is electrically connected to the first thin film transistor. The first thin film transistor includes a first semiconductor layer including polysilicon, and a first gate electrode overlapping a channel region of the first semiconductor layer in a direction of a thickness of the substrate. The second thin film transistor includes a second semiconductor layer including an oxide semiconductor. The first gate electrode has a stacked structure including a first layer and a second layer. The second layer includes titanium, and the first layer includes a different material from the second layer.

[0009] The second layer can be disposed between the first layer and the first semiconductor layer.

[0010] The first gate electrode can further include a third layer disposed on the first layer and including titanium.

[0011] The display apparatus can further include a capacitor overlapping the first thin film transistor in a thickness direction of the substrate, and the first gate electrode is a first electrode of the capacitor.

[0012] The capacitor further includes a second electrode overlapping the first electrode in the thickness direction of the substrate, and the display apparatus can further include: a first insulating layer disposed between the first semiconductor layer and the first gate electrode; a second insulating layer disposed between the first gate electrode and the second electrode; and a third insulating layer disposed on the second electrode. The second semiconductor layer can be disposed on the third insulating layer.

[0013] The display apparatus can further include a light blocking layer overlapping the second semiconductor layer in the thickness direction of the substrate, disposed between the second insulating layer and the third insulating layer, and having an electric conductivity.

[0014] The first semiconductor layer can further include a drain region and a source region respectively arranged on both sides of the channel region. The channel region, the source region, and the drain region can be doped with the same impurity. A doping concentration of the impurity of the channel region can be less than each of respective doping concentrations of the impurities of the source region and the drain region.

[0015] The doping concentration of the impurity of the channel region can be 1×e 11 / cm 2 to 1×e 13 / cm 2 .

[0016] The impurity can be boron (B).

[0017] The hydrogen concentration of the second semiconductor layer can be greater than the hydrogen concentration of the first semiconductor layer.

[0018] These and / or other aspects will become apparent and more readily appreciated from the following description of embodiments, taken in conjunction with the accompanying drawings in which: BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other aspects, features and advantages of certain exemplary embodiments of the present inventive concept will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a top view of a display apparatus according to an exemplary embodiment of the present inventive concept;

[0021] Figure 2 is an equivalent circuit diagram of a (sub)pixel of a display apparatus according to an exemplary embodiment of the present inventive concept;

[0022] Figure 3 is a cross-sectional view taken along line I-I' of the thin film transistor of Figure 1

[0023] Figure 4 is a cross-sectional view of another exemplary embodiment of the first thin film transistor of Figure 3

[0024] Figure 5 is a graph showing the magnitude of the threshold voltage of the first thin film transistor of Figure 4

[0025] Figure 6 is a cross-sectional view of another exemplary embodiment of the first thin film transistor of Figure 3

[0026] Figure 7 is a cross-sectional view of another exemplary embodiment of the first thin film transistor of Figure 3

[0027] Figure 8 is a cross-sectional view of another exemplary embodiment of the first thin film transistor of Figure 3 DETAILED DESCRIPTION

[0028] Because the present disclosure allows various changes and numerous embodiments, specific exemplary embodiments will be shown in the drawings and described in detail in the written description below. In the following, the effects and features of the present disclosure and methods of achieving them will be more fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are illustrated. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein.

[0029] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0030] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0031] It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0032] ​​​​​​It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. For example, intervening layers, regions or components can be present.

[0033] For ease of explanation, the size of elements in the drawings can be exaggerated. In other words, the size and thickness of components in the drawings are arbitrarily shown for ease of explanation.

[0034] When a certain example embodiment can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially concurrently or in the reverse order of the described order.

[0035] One or more example embodiments of the inventive concept will hereinafter be described in greater detail with reference to the accompanying drawings. Like or corresponding components are denoted by the same reference numerals, regardless of whether they are shown in different drawings. Embodiments of the inventive concept will be described with reference to the accompanying drawings, in which:

[0036] Figure 1 is a plan view of a display apparatus 100 according to an example embodiment of the inventive concept. Figure 2 is an equivalent circuit diagram of one (sub) pixel PX of the display apparatus 100 according to an example embodiment of the inventive concept. Figure 3 is a cross-sectional view taken along line I-I' of Figure 1 .

[0037] Although an organic light emitting display apparatus will now be shown and described as the display apparatus 100 according to an example embodiment of the inventive concept, example embodiments of the inventive concept are not limited thereto. For example, in other example embodiments, the display apparatus 100 can be various different types of display apparatuses, such as inorganic light emitting displays, quantum dot light emitting displays, etc.

[0038] Referring to Figure 1 , the display apparatus 100 includes a substrate 110. The display apparatus 100 includes a display area DA in which an image is displayed and a peripheral area PA located outside the display area DA. For example, in the example embodiment shown in Figure 1 , the peripheral area PA is disposed along a periphery of the display area DA in the X and / or Y direction. Accordingly, the substrate 110 has the display area DA and the peripheral area PA.

[0039] A plurality of pixels PX can be arranged on the display area DA. Each of the plurality of pixels PX can emit light such as red light, green light, blue light, or white light by including a display device such as an organic light emitting diode (OLED).

[0040] Figure 2An exemplary embodiment of an equivalent circuit of each pixel PX is shown. Reference is made to Figure 2 Each pixel PX can include a display device and a pixel circuit driving the display device. In an exemplary embodiment, the display device can be an organic light emitting diode OLED. However, exemplary embodiments of the inventive concept are not limited thereto. For ease of explanation, an exemplary pixel PX including an organic light emitting diode OLED as a display device will be shown and described herein.

[0041] Although each pixel PX includes a signal line, an initialization voltage line 141 and a power voltage line 161 in Figure 2 , exemplary embodiments of the inventive concept are not limited thereto. According to another exemplary embodiment, at least one of the signal line, the initialization voltage line 141 or / and the power voltage line 161 can be shared by adjacent pixels PX.

[0042] The signal line includes a first scan line 131 transmitting a first scan signal GWP, a second scan line 151 transmitting a second scan signal GWN, a third scan line 153 transmitting a third scan signal GI, a light emission control line 133 transmitting a light emission control signal EM and a data line 171 intersecting the first scan line 131 and transmitting a data signal DATA.

[0043] The power voltage line 161 transmits a first power voltage ELVDD to the first thin film transistor T1, and the initialization voltage line 141 transmits an initialization voltage VINT initializing the first thin film transistor T1 and a pixel electrode of the organic light emitting diode OLED.

[0044] The pixel circuit of the pixel PX can include a plurality of thin film transistors. For example, in the exemplary embodiment shown in Figure 2 , the pixel circuit includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7 and a capacitor Cst. The first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 include Figure 2 a first electrode E11, E21, E31, E41, E51, E61, E71 and a second electrode E12, E22, E32, E42, E52, E62, E72. According to the type (p-type or n-type) and / or the working condition of the thin film transistors T1 to T7, the first electrodes E11 to E71 and the second electrodes E12 to E72 can be a source electrode (source region) or a drain electrode (drain region), respectively. The capacitor Cst includes a first electrode 41 and a second electrode 43.

[0045] The first thin film transistor T1 includes a first gate electrode G1 connected to the first electrode 41 of the capacitor Cst, a first electrode E11 connected to the power supply voltage line 161 via the fifth thin film transistor T5, and a second electrode E12 electrically connected to the pixel electrode of the organic light emitting diode OLED via the sixth thin film transistor T6. The first thin film transistor T1 functions as a drive transistor, and receives the data signal DATA and supplies the current loled to the organic light emitting diode OLED according to the switching operation of the second thin film transistor T2.

[0046] The second thin film transistor T2 includes a second gate electrode G2 connected to the first scan line 131, a first electrode E21 connected to the data line 171, and a second electrode E22 connected to the first electrode E11 of the first thin film transistor T1. The second thin film transistor T2 is turned on according to the first scan signal GWP received via the first scan line 131, and performs a switching operation of transferring the data signal DATA received from the data line 171 to the first electrode E11 of the first thin film transistor T1.

[0047] The third thin film transistor T3 includes a third gate electrode G3 connected to the second scan line 151, a first electrode E31 connected to the second electrode E12 of the first thin film transistor T1, and a second electrode E32 connected to the first electrode 41 of the capacitor Cst, the second electrode E42 of the fourth thin film transistor T4, and the first gate electrode G1 of the first thin film transistor T1. The first electrode E31 of the third thin film transistor T3 is also connected to the pixel electrode of the organic light emitting diode OLED via the sixth thin film transistor T6. The third thin film transistor T3 is turned on according to the second scan signal GWN received via the second scan line 151, and diode- connects the first thin film transistor T1.

[0048] The fourth thin film transistor T4 includes a fourth gate electrode G4 connected to the third scan line 153, a first electrode E41 connected to the initialization voltage line 141, and a second electrode E42 connected to the first electrode 41 of the capacitor Cst, the second electrode E32 of the third thin film transistor T3, and the first gate electrode G1 of the first thin film transistor T1. The fourth thin film transistor T4 is turned on according to the third scan signal GI received via the third scan line 153, and transfers the initialization voltage VINT to the node N and the first gate electrode G1 of the first thin film transistor T1 to thereby initialize the gate voltage of the first thin film transistor T1.

[0049] The fifth thin film transistor T5 includes a fifth gate electrode G5 connected to the light emission control line 133, a first electrode E51 connected to the power supply voltage line 161, and a second electrode E52 connected to the first electrode E11 of the first thin film transistor T1 and the second electrode E22 of the second thin film transistor T2.

[0050] The sixth thin film transistor T6 includes a sixth gate electrode G6 connected to the light emission control line 133, a first electrode E61 connected to the second electrode E12 of the first thin film transistor T1 and the first electrode E31 of the third thin film transistor T3, and a second electrode E62 connected to the pixel electrode of the organic light emitting diode OLED. The fifth thin film transistor T5 and the sixth thin film transistor T6 are simultaneously turned on according to the light emission control signal EM received via the light emission control line 133 to allow current to flow in the organic light emitting diode OLED.

[0051] The seventh thin film transistor T7 includes a seventh gate electrode G7 connected to the first scan line 131, a first electrode E71 connected to the second electrode E62 of the sixth thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second electrode E72 connected to the initialization voltage line 141. The seventh thin film transistor T7 is turned on according to the first scan signal GWP received via the first scan line 131 and initializes the voltage of the pixel electrode of the organic light emitting diode OLED.

[0052] The capacitor Cst includes a first electrode 41 connected to the first gate electrode G1 of the first thin film transistor T1 and a second electrode 43 connected to the power voltage line 161. The first electrode 41 of the capacitor Cst is also connected to the second electrode E32 of the third thin film transistor T3 and the second electrode E42 of the fourth thin film transistor T4.

[0053] The organic light emitting diode OLED can include a pixel electrode and a common electrode opposite the pixel electrode. The common electrode can receive the second power voltage ELVSS. The organic light emitting diode OLED can display an image by receiving current from the first thin film transistor T1 and emitting light.

[0054] At least some of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 can include different types of semiconductor layers. For example, the first thin film transistor T1 acting as a driving transistor can include a semiconductor layer including polysilicon, and at least some of the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 acting as switching transistors can include an oxide semiconductor layer.

[0055] Polysilicon is excellent in terms of electron mobility and reliability. Since the first thin film transistor T1 directly affecting the brightness of the organic light emitting diode OLED includes a semiconductor layer including polysilicon, the display device 100 can have high resolution.

[0056] A thin film transistor including an oxide semiconductor layer has a low off-state current and can operate at a low frequency. Thus, in an example embodiment, at least one of the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 includes an oxide semiconductor layer. Thus, power consumption of the display device 100 can be reduced.

[0057] Figure 3 is a cross-sectional view illustrating a portion of the display device 100. For ease of explanation, Figure 3 Only the first thin film transistor Tl, the second thin film transistor T2, the capacitor Cst, and the organic light emitting diode OLED among the components of the pixel PX as described above are illustrated.

[0058] Referring to Figure 3 A buffer layer 11 can be provided over the substrate 110. For example, as illustrated in Figure 3 In an example embodiment, as illustrated in

[0059] The substrate 110 can include one or more of various materials such as glass, metal, and a polymer resin. When the substrate 110 includes metal, the substrate 110 can include iron (Fe), chromium (Cr), manganese (Mn), nickel (Ni), titanium (Ti), molybdenum (Mo), stainless steel (SUS), Invar alloy, Inconel alloy, and Kovar alloy. The substrate 110 can include a polymer resin such as polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0060] The buffer layer 11 can planarize the upper surface of the substrate 110 and block foreign matter or the like from entering via the substrate 110. For example, the buffer layer 11 can include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, or the like, or an organic material such as polyimide, polyester, acrylic, or the like, and can be formed as a single layer or a plurality of layers.

[0061] The first thin film transistor Tl is provided over the buffer layer 11. For example, as illustrated in Figure 3In the example embodiment shown in FIG. 1, the first thin film transistor T1 can be disposed directly on the buffer layer 11 (e.g., in the Z-direction). The first thin film transistor T1 includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Since the first thin film transistor T1 functions as a driver transistor, the first semiconductor layer A1 can include polysilicon.

[0062] The first gate electrode G1 is disposed on the first semiconductor layer A1, and the first source electrode S1 and the first drain electrode D1 are electrically connected to each other in response to a signal applied to the first gate electrode G1.

[0063] For example, the first gate electrode G1 can include at least one material among aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). However, the example embodiments of the inventive concept are not limited thereto.

[0064] A first insulating layer 12 including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride can be disposed between the first semiconductor layer A1 and the first gate electrode G1. For example, as shown in FIG. 1, the first insulating layer 12 can be disposed directly on the first semiconductor layer A1 (e.g., in the Z-direction), and the first gate electrode G1 can be disposed directly on the first insulating layer 12 (e.g., in the Z-direction). The first insulating layer 12 provides insulation between the first semiconductor layer A1 and the first gate electrode G1. Figure 3

[0065] The capacitor Cst can be disposed on and overlap the first gate electrode G1 (e.g., in the Z-direction). The capacitor Cst can include a first electrode 41 and a second electrode 43. A second insulating layer 13 including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride can be disposed between the first electrode 41 and the second electrode 43. The first gate electrode G1 can also function as the first electrode 41 of the capacitor Cst. For example, the first gate electrode G1 and the first electrode 41 can be formed in one body. As shown in FIG. 1, the second insulating layer 13 can be disposed directly on the first electrode 41 of the capacitor Cst (e.g., in the Z-direction), and the second electrode 43 of the capacitor Cst can be disposed directly on the second insulating layer 13 (e.g., in the Z-direction). Figure 3

[0066] The second electrode 43 of the capacitor Cst can be disposed on the second insulating layer 13 such that the second electrode 43 at least partially overlaps the first electrode 41 of the capacitor Cst (e.g., in the Z-direction). The second electrode 43 can be electrically connected to a signal line 20 that transmits a driving voltage.​​Figure 2 a power supply voltage line 161.

[0067] A third insulating layer 14 including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride can be provided over the second electrode 43. For example, as shown in the exemplary embodiment of FIG. 1 IB, the third insulating layer 14 can be provided directly (e.g., in the Z-direction) over the second electrode 43. A second thin-film transistor T2 can be provided over the third insulating layer 14, e.g., the second thin-film transistor T2 can be provided directly (e.g., in the Z-direction) over the third insulating layer 14. A distance (e.g., a length in the Z-direction) from a bottom surface of the second thin-film transistor T2 to a top surface of the substrate 110 is different from a distance (e.g., a length in the Z-direction) from a bottom surface of the first thin-film transistor Tl to the top surface of the substrate 110. For example, as shown in the exemplary embodiment of FIG. 1 IB, the distance from the bottom surface of the second thin-film transistor T2 to the top surface of the substrate 110 is greater than the distance from the bottom surface of the first thin-film transistor Tl to the top surface of the substrate 110. Figure 3 Figure 3

[0068] The second thin-film transistor T2 includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. Since the second thin-film transistor T2 functions as a switching transistor, the second semiconductor layer A2 can include an oxide semiconductor. In exemplary embodiments, the oxide semiconductor can include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or the like. In some exemplary embodiments, the oxide semiconductor can include a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or the like and an oxide of the metal. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in some exemplary embodiments, the oxide semiconductor can be a zinc-oxide-based material, and can include zinc oxide, In-Zn oxide, Ga-In-Zn oxide, or the like. According to some exemplary embodiments, the oxide semiconductor can be an In-Ga-Zn-O (IGZO) semiconductor containing a metal such as In and Ga in zinc oxide. It will be understood that the first electrodes El l, E21 and the second electrodes E12, E22 of the first thin-film transistor Tl and the second thin-film transistor T2 in the exemplary embodiments shown in Figure 2 Figure 3

[0069] ​​​​In an exemplary embodiment, at least one of the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 of the pixel circuit, such as the second thin-film transistor T2, can include an oxide semiconductor layer. According to an exemplary embodiment of the present inventive concept, the driving transistor includes a semiconductor layer having a polysilicon semiconductor with excellent reliability, and at least one thin-film transistor (e.g., a switching transistor) includes a semiconductor layer having an oxide semiconductor with a lower off current. Accordingly, the display apparatus 100 can provide high reliability and low power consumption.

[0070] The second gate electrode G2 can be disposed on the second semiconductor layer A2. The fourth insulating layer 15 can be disposed between the second gate electrode G2 and the second semiconductor layer A2. For example, the fourth insulating layer 15 can be disposed directly (e.g., in the Z direction) on the second semiconductor layer A2, and the second gate electrode G2 can be disposed directly (e.g., in the Z direction) on the fourth insulating layer 15. As shown in Figure 3 As shown in an exemplary embodiment of FIG. 2A, the fourth insulating layer 15 can extend only between the second semiconductor layer A2 and the second gate electrode G2. For example, as shown in Figure 3 As shown in an exemplary embodiment of FIG. 2A, the fourth insulating layer 15 can extend only between the second semiconductor layer A2 and the second gate electrode G2. For example, as shown in

[0071] In an exemplary embodiment, the second gate electrode G2 can include at least one material of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can have a single layer or a multi-layer structure. The fourth insulating layer 15 can include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0072] The light-blocking layer BML can be further arranged to overlap with the second semiconductor layer A2 (e.g., in the Z direction). For example, the light-blocking layer BML can be disposed between the second insulating layer 13 and the third insulating layer 14. Figure 3 In the exemplary embodiment, the bottom of the light-blocking layer BML (e.g., in the Z direction) directly contacts the top of the second insulating layer 13, and the top of the light-blocking layer BML directly contacts a portion of the third insulating layer 14. The light-blocking layer BML prevents light from incident on the second thin-film transistor T2. Light incident on the second semiconductor layer A2 of the second thin-film transistor T2 induces a photocurrent, causing a deterioration in the characteristics of the second thin-film transistor T2. Therefore, including the light-blocking layer BML can prevent this deterioration. The light-blocking layer BML can be conductive and can be electrically connected to the second source electrode S2 of the second thin-film transistor T2, thereby improving the characteristics of the second thin-film transistor T2.

[0073] The fifth insulating layer 16 may be disposed on the second gate electrode G2 and may comprise an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride to have a single-layer or multi-layer structure. For example, as in Figure 3 In the exemplary embodiment, the fifth insulating layer 16 can be directly disposed on the second gate electrode G2 and can cover the top surface and side edges of the second gate electrode G2.

[0074] The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 are disposed on the fifth insulating layer 16. For example, as in Figure 3 In the exemplary embodiment shown, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can be (e.g., in the Z direction) directly disposed on the fifth insulating layer 16.

[0075] The first source electrode S1 and the first drain electrode D1 can be electrically connected to the first semiconductor layer A1 via contact holes. For example, in an embodiment where the fourth insulating layer 15 extends only between the second semiconductor layer A2 and the second gate electrode G2, contact holes formed in the first insulating layer 12, the second insulating layer 13, the third insulating layer 14, and the fifth insulating layer 16 can electrically connect the first source electrode S1 and the first drain electrode D1 to the first semiconductor layer A1. The second source electrode S2 and the second drain electrode D2 can be electrically connected to the second semiconductor layer A2 via contact holes formed in the fifth insulating layer 16, as in... Figure 3 As shown in the exemplary embodiment. In the exemplary embodiment in which the fourth insulating layer 15 is formed to correspond to the entire area of ​​the substrate 110, the second source electrode S2 and the second drain electrode D2 can be electrically connected to the second semiconductor layer A2 via contact holes formed in the fourth insulating layer 15 and the fifth insulating layer 16.

[0076] In an exemplary embodiment, the first source electrode Sl, the first drain electrode Dl, the second source electrode S2, and the second drain electrode D2 can include at least one material among aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can have a single layer or a multi-layer structure in consideration of conductivity or the like.

[0077] The sixth insulating layer 17 can be disposed on the first thin film transistor T1 and the second thin film transistor T2 having the above-described structure, respectively. For example, as shown in Figure 3 when the organic light emitting diode OLED is disposed at a higher position than the first thin film transistor T1 and the second thin film transistor T2 (e.g., in the Z direction), the sixth insulating layer 17 can cover the first thin film transistor T1 and the second thin film transistor T2 to planarize unevenness caused by the first thin film transistor T1 and the second thin film transistor T2. In an exemplary embodiment, the sixth insulating layer 17 can include an organic material such as acrylic, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). However, exemplary embodiments of the inventive concept are not limited thereto.

[0078] The conductive layer 140 can be disposed on the sixth insulating layer 17. For example, as shown in Figure 3 an exemplary embodiment of , the conductive layer 140 can be disposed directly on the sixth insulating layer 17. The conductive layer 140 can be a connection electrode that electrically connects one electrode of the capacitor Cst of the pixel PX and one electrode of one of the plurality of transistors (including the first thin film transistor T1 and the second thin film transistor T2) to the pixel electrode 210.

[0079] The seventh insulating layer 18 including an organic material such as acrylic, BCB, or HMDSO can be disposed on the conductive layer 140, and the organic light emitting diode OLED can be disposed on the seventh insulating layer 18. For example, as shown in Figure 3 an exemplary embodiment of , the seventh insulating layer 18 is disposed directly on the conductive layer 140 (e.g., in the Z direction), and the organic light emitting diode OLED is disposed directly on the seventh insulating layer 18.

[0080] The organic light emitting diode OLED includes the pixel electrode 210, the counter electrode 230, and the intermediate layer 220 disposed between the pixel electrode 210 and the counter electrode 230 and including an emission layer.

[0081] The pixel electrode 210 can be electrically connected to the conductive layer 140 through a contact hole formed in the seventh insulating layer 18. In an exemplary embodiment, the pixel electrode 210 can be a transparent (or semi-transparent) electrode or a reflective electrode. In an embodiment in which the pixel electrode 210 is a transparent (or semi-transparent) electrode, the pixel electrode 210 can include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In an embodiment in which the pixel electrode 210 is a reflective electrode, the pixel electrode 210 can include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a layer including ITO, IZO, ZnO, In2O3, IGO, or AZO. However, exemplary embodiments of the inventive concept are not limited thereto, and the pixel electrode 210 can include any one of various other materials, and can have any one of various structures, such as a single layer or a multi-layer structure.

[0082] An eighth insulating layer 19 can be disposed on the seventh insulating layer 18. For example, as shown in an exemplary embodiment of FIG. 2B, the eighth insulating layer 19 can be disposed (e.g., in the Z direction) directly on the seventh insulating layer 18. The eighth insulating layer 19 defines an emission area by including an opening through which at least a central portion of the pixel electrode 210 is exposed. In this embodiment, as shown in FIG. 2B, the eighth insulating layer 19 covers the edge of the pixel electrode 210, and thus increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 disposed thereon, to thereby prevent an arc or the like from occurring on the edge of the pixel electrode 210. Figure 3 Figure 3 In this embodiment, as shown in FIG. 2B, the eighth insulating layer 19 covers the edge of the pixel electrode 210, and thus increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 disposed thereon, to thereby prevent an arc or the like from occurring on the edge of the pixel electrode 210.

[0083] The intermediate layer 220 of the organic light emitting diode OLED includes an emission layer. The emission layer can include a low molecular or high molecular organic material that emits light of a certain color. The intermediate layer 220 can further include at least one functional layer of a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL). The functional layer can include an organic material.

[0084] ​The counter electrode 230 can be formed as a unit constituting a plurality of organic light emitting diodes OLEDs, and thus can correspond to a plurality of pixel electrodes 210. For example, the counter electrode 230 can extend in the X direction, and serve as a counter electrode for a plurality of organic light emitting diodes OLEDs. In an exemplary embodiment, the counter electrode 230 can be a transparent (or semi-transparent) electrode or a reflective electrode. In an embodiment in which the counter electrode 230 is a transparent (or semi-transparent) electrode, the counter electrode 230 can have a layer including a metal having a small work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or a compound thereof, and a transparent (or semi-transparent) conductive layer including ITO, IZO, ZnO, In2O3, or the like. However, exemplary embodiments of the inventive concept are not limited thereto. In an embodiment in which the counter electrode 230 is a reflective electrode, the counter electrode 230 can have a layer including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or a compound thereof. The configuration of the counter electrode 230 and the materials included in the counter electrode 230 are not limited to those described above, and various modifications can be made to the counter electrode 230.

[0085] A packaging layer for protecting the organic light emitting diode OLED from external moisture or oxygen, or the like, can be located on the counter electrode 230. The packaging layer can cover the display area DA and extend beyond the display area DA. The packaging layer can include an inorganic packaging layer including at least one inorganic material, and an organic packaging layer including at least one organic material. According to some exemplary embodiments, the packaging layer can have a stacked structure in which a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer are stacked on each other. Various functional layers such as a polarizing layer for reducing reflection of external light, a black matrix, a color filter, and / or a touch screen layer including a touch electrode can be arranged on the packaging layer.

[0086] As described above, the first semiconductor layer A1 of the first thin-film transistor T1 to drive the organic light emitting diode OLED can include polysilicon. Thus, defects (traps) within the first semiconductor layer A1 can be reduced via a heat treatment, and thus the threshold voltage Vth of the first thin-film transistor T1 can be reduced and the voltage margin of the threshold voltage Vth can be increased. Thus, the reliability of the first thin-film transistor T1 can be improved. However, when a heat treatment is performed to improve the reliability of the first thin-film transistor T1, the characteristics of the second thin-film transistor T2 including an oxide semiconductor layer can be changed. Thus, it is difficult to improve the reliability of the first thin-film transistor T1 via a heat treatment. On the other hand, when the reliability of the first thin-film transistor T1 is not improved, the driving margin of the first thin-film transistor T1 is too narrow, and ghosting or the like can occur on the display apparatus 100.

[0087] Accordingly, in order to improve the reliability of the first thin film transistor T1 without affecting the second thin film transistor T2, the first semiconductor layer A1 can be doped with an impurity. When the channel region of the first semiconductor layer A1 is doped with a dopant, the hysteresis characteristics of the first semiconductor layer A1 can be improved, and the voltage margin of the threshold voltage Vth can be increased. However, when the doping concentration of the impurity in the channel region of the first semiconductor layer A1 is increased, the threshold voltage Vth of the first thin film transistor T1 is shifted in the positive (+) direction. For example, when the channel region of the first semiconductor layer A1 is doped with boron (B) at a doping amount of 3 x e 11 / cm 2 , the threshold voltage Vth of the first thin film transistor T1 is shifted by about 0.6 V in the positive (+) direction. Accordingly, it would be advantageous to modify the threshold voltage value generated when the first semiconductor layer A1 is doped with an impurity to be approximately equal to the threshold voltage value before the doping. This will be described in more detail later with reference to Figure 4 to Figure 8 .

[0088] Figure 4 is a cross-sectional view of an exemplary embodiment of the first thin film transistor T1 of Figure 3 . Figure 5 is a graph showing the hydrogen concentration in the buffer layer 11, the first semiconductor layer A1, and the first insulating layer 12 of Figure 4 according to an exemplary embodiment. Figure 6 is a graph showing the magnitude of the threshold voltage Vth of the first thin film transistor T1 of Figure 3 according to an exemplary embodiment.

[0089] For ease of explanation, Figure 4 only the first semiconductor layer A1 and the first gate electrode G1 of the first thin film transistor T1 are shown.

[0090] As shown in Figure 4 , the first semiconductor layer A1 includes a channel region AS that overlaps (e.g., in the Z direction) the first gate electrode G1, and a source region SS and a drain region DS that are respectively arranged (e.g., in the X direction) on both sides of the channel region AS. By doping the channel region AS with an impurity, the characteristics of the first thin film transistor T1 can be improved even when no heat treatment is performed.

[0091] For example, the first thin film transistor T1 can be a P-channel thin film transistor, and the source region SS, the drain region DS, and the channel region AS can be doped with a P-type impurity. The impurity can be, for example, boron (B). However, in other exemplary embodiments, the impurity can be one or more other compounds.

[0092] In an example embodiment, the first semiconductor layer Al can be formed by forming an amorphous silicon layer on the buffer layer 11, applying an excimer laser to the amorphous silicon layer, and crystallizing the amorphous silicon layer. In one example embodiment, impurities are injected into the amorphous silicon layer before crystallization, and then the amorphous silicon layer can be crystallized. Alternatively, the amorphous silicon layer can be first crystallized and the first semiconductor layer Al can be formed, and then impurities can be injected into the first semiconductor layer Al.

[0093] Then, the first gate electrode Gl can be formed on the first insulating layer 12, and impurities can be secondarily injected into the source region SS and the drain region DS by using the first gate electrode Gl as a mask. Accordingly, the impurity doping concentration of the source region SS and the drain region DS can be greater than the impurity doping concentration of the channel region AS, respectively.

[0094] For example, in an example embodiment, the doping concentration of the channel region AS can be 1 x e 11 / cm 2 to 1 x e 13 / cm 2 When the doping concentration of the channel region AS is greater than 1 x e 13 / cm 2 , the threshold voltage Vth of the first thin film transistor Tl is shifted in the positive (+) direction by a value that is too large, and thus, as will be described later, it can be difficult to restore the shifted threshold voltage to an original value even when hydrogen diffusion into the channel region AS is prevented. On the other hand, when the doping concentration of the channel region AS is less than 1 x e 11 / cm 2 , it is difficult to improve the characteristics of the first thin film transistor Tl.

[0095] Each of the doping concentrations of the source region SS and the drain region DS can be greater than the doping concentration of the channel region AS. For example, in an example embodiment, each of the doping concentrations of the source region SS and the drain region DS can be approximately 1 x e 15 / cm 2 .

[0096] During the manufacturing of the first thin film transistor Tl and the like, hydrogen included in an inorganic layer such as the first insulating layer 12 can diffuse into the channel region AS. The hydrogen that diffuses into the channel region AS can affect the doping concentration of the channel region AS. In other words, when hydrogen diffuses into the channel region AS doped with boron (B), the threshold voltage Vth of the first thin film transistor Tl is shifted in the positive (+) direction by a value that can increase, and it can be difficult to restore the shifted threshold voltage to an original value. Accordingly, hydrogen diffusion into the channel region AS should be prevented.

[0097] As in the above-described example embodiment, the first semiconductor layer Al can be formed by forming an amorphous silicon layer on the buffer layer 11, applying an excimer laser to the amorphous silicon layer, and crystallizing the amorphous silicon layer. In one example embodiment, impurities are injected into the amorphous silicon layer before crystallization, and then the amorphous silicon layer can be crystallized. Alternatively, the amorphous silicon layer can be first crystallized and the first semiconductor layer Al can be formed, and then impurities can be injected into the first semiconductor layer Al. Figure 4In an exemplary embodiment, the first gate electrode G1 may have a stacked structure comprising a first layer M1 containing molybdenum (Mo) and a second layer M2 containing titanium (Ti). For example, the first gate electrode G1 may include (e.g., in the Z direction) a second layer M2 containing titanium (Ti) directly disposed on the first layer M1 containing molybdenum (Mo). Figure 4 In the exemplary embodiment shown, the second layer M2 can be disposed directly on top of the first layer M1. The top surface of the first layer M1 can directly contact the bottom surface of the second layer M2. The titanium (Ti) of the second layer M2 can collect hydrogen and thus prevent hydrogen from diffusing into the channel region AS. Although the first layer M1 in the exemplary embodiment contains molybdenum (Mo), the first layer M1 can contain a different material than the material of the second layer M2.

[0098] Figure 5 The results of hydrogen concentration measurements based on the depth from the first insulating layer 12 to the buffer layer 11 are shown. Figure 5 The hydrogen concentration in the first semiconductor layer A1 refers to the hydrogen concentration in the channel region AS of the first semiconductor layer A1. Figure 5 (5A) represents the hydrogen concentration when the first gate electrode G1 consists only of a first layer M1 containing molybdenum (Mo), and Figure 5 (5B) represents the hydrogen concentration when the first gate electrode G1 comprises a stacked structure having a first layer M1 containing molybdenum (Mo) and a second layer M2 containing titanium (Ti). As from... Figure 5 It can be seen that, compared with case (5A), the hydrogen concentration in the first semiconductor layer A1 is significantly reduced in case (5B). Compared with the first gate electrode G1, Figure 3 The second gate electrode G2 of the second thin-film transistor T2 does not have a structure capable of collecting hydrogen. Therefore, in Figure 3 The hydrogen concentration in the second semiconductor layer A2 may be greater than the hydrogen concentration in the first semiconductor layer A1.

[0099] Figure 6 The threshold voltage Vth of the first thin-film transistor T1 is shown. (Compared to...) Figure 5 Similar to (5A), Figure 6 (6A) can represent the reference threshold voltage of the first thin-film transistor T1 when the first gate electrode G1 comprises only a first layer M1 containing molybdenum (Mo). In this embodiment, the channel region AS is not boron-doped, and hydrogen has diffused into the channel region AS during the fabrication of the first thin-film transistor T1.

[0100] Figure 6 (6B) represents the threshold voltage Vth of the first thin-film transistor T1 when the channel region AS is boron-doped and the first gate electrode G1 includes a second layer M2 in addition to the first layer M1. Figure 6(6C) represents the threshold voltage Vth of the first thin-film transistor T1 when the channel region AS is doped with boron and the first gate electrode G1 consists only of the first layer M1.

[0101] In Figure 6 When comparing (6A) and (6C), the threshold voltage Vth of the first thin-film transistor T1 changes in the positive (+) direction due to boron doping. However, in case (6B), even with boron doping similar to that in case (6C), the threshold voltage Vth of the first thin-film transistor T1 is very similar to that in case (6A). This is because preventing hydrogen diffusion into the channel region AS during the fabrication of the first thin-film transistor T1 prevents further change in the positive (+) direction of the threshold voltage Vth of the first thin-film transistor T1 due to hydrogen diffusion.

[0102] Therefore, according to an exemplary embodiment of the present invention, doping boron in the channel region AS can improve the characteristics of the first thin-film transistor T1 without affecting the performance of the transistor. Figure 3 The second thin-film transistor T2, and the inclusion of a second titanium-containing layer M2 in the first gate electrode G1, can prevent the threshold voltage Vth of the first thin-film transistor T1 from changing due to boron doping. In this exemplary embodiment, when boron is doped in the channel region AS and hydrogen diffusion is prevented, the boron doping concentration in the channel region AS can be 1×e 11 / cm 2 up to 1×e 13 / cm 2 The threshold voltage Vth of the first thin-film transistor T1 can have the same value as the reference threshold voltage (Vth). Figure 6 (6A) is approximately the same value.

[0103] Figure 7 and Figure 8 This is a cross-sectional view of another exemplary embodiment of the first thin-film transistor T1.

[0104] Figure 7 The first thin-film transistor T1 includes a first gate electrode G1, which comprises both a first layer M1 and a second layer M2 containing titanium (Ti), and thus prevents or minimizes the diffusion of hydrogen from the buffer layer 11 and the first insulating layer 12 into the first semiconductor layer A1 as described above. However, in Figure 7 In an exemplary embodiment, the first gate electrode G1 includes a second layer M2 comprising titanium disposed beneath the first layer M1. For example, the top surface of the second layer M2 directly contacts the bottom surface of the first layer M1. The second layer M2 may be located between the first layer M1 and the first semiconductor layer A1 to effectively prevent hydrogen diffusion into the first semiconductor layer A1. The first layer M1 may comprise a different material than the material of the second layer M2. For example, the first layer M1 may not contain titanium.

[0105] As shown in the exemplary embodiments of Figure 8 As shown in the exemplary embodiments of

[0106] According to the exemplary embodiments of the present inventive concept, a display apparatus employing different types of thin film transistors can prevent a decrease in image quality by including thin film transistors having improved characteristics.

[0107] Although the present disclosure has been particularly shown and described with reference to exemplary embodiments of the present inventive concept, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, wherein, The display device includes: Base; A first thin-film transistor and a second thin-film transistor are disposed on the substrate, the first thin-film transistor and the second thin-film transistor being arranged at different distances from the top surface of the substrate; and A display device electrically connected to the first thin-film transistor. The first thin-film transistor includes: a first semiconductor layer comprising polycrystalline silicon; and a first gate electrode that overlaps with the channel region of the first semiconductor layer in the thickness direction of the substrate. The second thin-film transistor includes a second semiconductor layer comprising an oxide semiconductor, and The first gate electrode has a stacked structure comprising a first layer and a second layer, wherein the second layer comprises titanium, and the first layer comprises a material different from the second layer. The hydrogen concentration in the second semiconductor layer is greater than that in the first semiconductor layer.

2. The display device according to claim 1, wherein, The second layer is disposed between the first layer and the first semiconductor layer.

3. The display device according to claim 2, wherein, The first gate electrode further includes a third layer disposed on the first layer and comprising titanium.

4. The display device according to claim 1, wherein, The display device further includes: The capacitor overlaps with the first thin-film transistor in the direction of the thickness of the substrate. The first gate electrode is the first electrode of the capacitor.

5. The display device according to claim 4, wherein: The capacitor further includes a second electrode that overlaps with the first electrode in the direction of the thickness of the substrate. The display device further includes: a first insulating layer disposed between the first semiconductor layer and the first gate electrode; a second insulating layer disposed between the first gate electrode and the second electrode; and a third insulating layer disposed on the second electrode. The second semiconductor layer is disposed on the third insulating layer.

6. The display device according to claim 5, wherein, The display device further includes: A light-blocking layer overlaps with the second semiconductor layer in the direction of the thickness of the substrate and is disposed between the second insulating layer and the third insulating layer.

7. The display device according to claim 1, wherein: The first semiconductor layer further includes a drain region and a source region respectively disposed on both sides of the channel region. The channel region, the source region, and the drain region are doped with the same impurities, and The doping concentration of the impurities in the channel region is less than the doping concentration of the impurities in the drain region and the source region.

8. The display device according to claim 7, wherein, The doping concentration of the impurity in the channel region is 1×e 11 / cm 2 up to 1×e 13 / cm 2 Within the range.

9. The display device according to claim 7, wherein, The impurity is boron.

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