Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes an insulating layer on a substrate, channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other, a gate electrode crossing the channel semiconductor patterns, source / drain regions at both sides of the gate electrode, respectively, and connected to each other through the channel semiconductor patterns, the source / drain regions having a concave bottom surface, and an air gap between the insulating layer and the bottom surface of the source / drain regions.

Description

[0001] Korean patent application No. 10-2019-0070028, entitled "Semiconductor Device", filed with the Korean Intellectual Property Office on June 13, 2019, is incorporated herein by reference in its entirety. Technical Field

[0002] Several embodiments relate to a semiconductor device. Background Technology

[0003] Semiconductor devices can include integrated circuits with metal-oxide-semiconductor field-effect transistors (MOS-FETs). To meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOS-FETs can be miniaturized. Summary of the Invention

[0004] An embodiment can be implemented by providing a semiconductor device comprising: an insulating layer on a substrate; a channel semiconductor pattern stacked on the insulating layer and vertically spaced apart from each other; a gate electrode intersecting the channel semiconductor pattern; source / drain regions located on opposite sides of the gate electrode and connected to each other via the channel semiconductor pattern, the source / drain regions having recessed bottom surfaces; and an air gap located between the insulating layer and the bottom surfaces of the source / drain regions.

[0005] An embodiment can be implemented by providing a semiconductor device comprising: an insulating layer on a substrate; a first channel semiconductor pattern on the insulating layer at a first vertical level; a second channel semiconductor pattern stacked on the first channel semiconductor pattern at a second vertical level higher than the first vertical level; a gate electrode intersecting the first and second channel semiconductor patterns; and source / drain regions located on a side surface of the gate electrode and connected to the first and second channel semiconductor patterns, wherein the source / drain regions comprise: a first semiconductor pattern covering the side surfaces of the first and second channel semiconductor patterns; and a second semiconductor pattern on the first semiconductor pattern, wherein the width of the first semiconductor pattern at the first vertical level is greater than the width of the first semiconductor pattern at the second vertical level.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: an insulating layer on a substrate; a first channel stack on the insulating layer; a second channel stack on the insulating layer and spaced apart from the first channel stack along a first direction, each of the first and second channel stacks including channel semiconductor patterns stacked and vertically spaced apart from each other; and a source / drain region located between the first and second channel stacks, wherein the source / drain region includes: a pair of first semiconductor patterns covering side surfaces of the channel region and spaced apart from each other along the first direction; and a second semiconductor pattern located on the first semiconductor patterns and connecting the pair of first semiconductor patterns to each other. Attached Figure Description

[0007] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0008] Figure 1 A plan view of a semiconductor device according to an embodiment is shown.

[0009] Figures 2A to 2C They show the following along Figure 1 A sectional view taken from lines A-A', B-B', and C-C'.

[0010] Figure 3 A portion of a semiconductor device according to an embodiment is shown (e.g., Figure 2A Enlarged sectional view of AA).

[0011] Figure 4 and Figure 5 A portion of a semiconductor device according to an embodiment is shown (e.g., Figure 2A Enlarged sectional view of AA).

[0012] Figure 6 , Figure 7 , Figure 8A and Figure 8B The semiconductor device according to the embodiment is shown along Figure 1 A sectional view taken by line C-C'.

[0013] Figure 9 , Figure 11 , Figure 13 , Figure 18 and Figure 20 A plan view of the stages in a method for manufacturing a semiconductor device according to an embodiment is shown.

[0014] Figure 10A , Figure 12A , Figure 14A , Figure 19A and Figure 21A They show the following along Figure 9 , Figure 11 , Figure 13 , Figure 18 and Figure 20 A sectional view taken by line A-A'.

[0015] Figure 10B , Figure 12B , Figure 14B , Figure 19B and Figure 21B They show the following along Figure 9 , Figure 11 , Figure 13 , Figure 18 and Figure 20 The sectional view taken by line B-B'.

[0016] Figure 14C , Figure 19C and Figure 21C They show the following along Figure 13 , Figure 18 and Figure 20 A sectional view taken by line C-C'.

[0017] Figures 15 to 17 The following is shown according to the embodiment. Figure 13 A cross-sectional view of a stage in the method of forming source / drain patterns, taken by line A-A'. Detailed Implementation

[0018] Figure 1 A plan view of a semiconductor device according to an embodiment is shown. Figures 2A to 2C They show the following along Figure 1 A sectional view taken from lines A-A', B-B', and C-C'.

[0019] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C The insulating layer 105 may be located on the substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate or a germanium substrate. The insulating layer 105 may include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. As used herein, the term "or" is not an exclusive term; for example, "A or B" will include A, B, or A and B. In embodiments, the substrate 100 and the insulating layer 105 may be part of a silicon-on-insulator (SOI) wafer. For example, the substrate 100 may be an operating substrate of an SOI wafer, and the insulating layer 105 may be an insulator of the SOI wafer.

[0020] The channel stack CS may be located on the insulating layer 105. The channel stack CS may be arranged two-dimensionally (e.g., spaced apart from each other) along a first direction D1 and a second direction D2 (e.g., perpendicular to the first direction D1). The channel stack CS may be located below the gate electrode GE (e.g., the distance from the substrate 100 to the channel stack CS along a third direction D3 perpendicular to the first direction D1 and the second direction D2 may be less than the distance from the substrate 100 to the gate electrode GE), as will be described below. In an embodiment, the channel stack CS may be located between a pair of source / drain regions SD. Each of the channel stack CS may include a plurality of channel semiconductor patterns CH1, CH2, and CH3 stacked vertically (e.g., along the third direction D3). The channel semiconductor patterns CH1, CH2, and CH3 included in each channel stack CS may differ from each other depending on their distance from the insulating layer 105 along the third direction D3. In an embodiment, the channel semiconductor patterns CH1, CH2, and CH3 may be vertically spaced apart from each other (e.g., along the third direction D3). Each of the channel semiconductor patterns CH1, CH2, and CH3 can be formed in the form of cuboid nanosheets. Each of the channel semiconductor patterns CH1, CH2, and CH3 may include a semiconductor material that can be used as a channel region for a field-effect transistor. In embodiments, the channel semiconductor patterns CH1, CH2, and CH3 may be formed of, for example, Si, SiGe, or Ge, or may include Si, SiGe, or Ge. The channel semiconductor patterns CH1, CH2, and CH3 may be doped with n-type or p-type impurities. In embodiments, such as Figures 2A to 2C As shown, the channel stack CS may include three stacked channel semiconductor patterns CH1, CH2, and CH3. In an embodiment, the semiconductor device may include a suitable number of channel semiconductor patterns in the channel stack CS.

[0021] Gate electrodes GE may be located on insulating layer 105. Gate electrodes GE may be arranged along a first direction D1 (e.g., spaced apart). Each of the gate electrodes GE may extend along a second direction D2 (e.g., longitudinally) to intersect at least one of the channel stacks CS. For example, each of the gate electrodes GE may extend along the second direction D2 to intersect a plurality of channel stacks CS arranged along the second direction D2 (e.g., spaced apart).

[0022] The gate insulating pattern GI may extend along the side surface (e.g., the surface facing the first direction D1 or the second direction D2) and bottom surface (e.g., the surface facing the substrate 100) of the gate electrode GE. In an embodiment, the gate overlay pattern GP may cover the gate electrode GE and the gate insulating pattern GI. The top surface of the gate insulating pattern GI and the gate electrode GE (e.g., the surface facing away from the substrate 100 along the third direction D3) may contact the bottom surface of the gate overlay pattern GP. The gate electrode GE and the gate insulating pattern GI may fill the space between vertically adjacent channel semiconductor patterns CH1, CH2, and CH3, and the space between the lowermost channel semiconductor pattern CH1 (e.g., the channel semiconductor pattern CH1 closest to the substrate 100 along the third direction D3) and the insulating layer 105. For example, the gate electrode GE and the gate insulating pattern GI may surround the outer peripheral surface of each of the channel semiconductor patterns CH1, CH2, and CH3. In an embodiment, each of the channel semiconductor patterns CH1, CH2, and CH3 may penetrate the gate electrode GE along the first direction D1. Each of the channel semiconductor patterns CH1, CH2 and CH3 may have opposite ends protruding from opposite side surfaces of the gate electrode GE, respectively.

[0023] The gate electrode GE can be formed or comprise, for example, a doped semiconductor material, a conductive metal nitride, or a metal material. In embodiments, the gate electrode GE can be formed or comprise, for example, a metal nitride (e.g., TiN, WN, or TaN) or a metal material (e.g., Ti, W, or Ta). The gate insulating pattern GI can be formed or comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. The high-k dielectric material can include materials whose dielectric constant is higher than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)). The gate overlay pattern GP can be formed or comprise, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0024] The gate spacer GS may be located on the side surface of the gate electrode GE. The gate spacer GS may extend along the side surface of the gate electrode GE and in the second direction D2. The gate spacer GS may be a single-layer structure or a multi-layer structure. In an embodiment, the gate spacer GS may include, for example, a silicon nitride layer, a silicon oxynitride layer, or a silicon carbide nitride layer.

[0025] The source / drain regions SD can be located on either side of the gate electrode GE. An adjacent pair of source / drain regions SD can be directly connected to the channel stack CS located between them. For example, the channel semiconductor patterns CH1, CH2, and CH3 included in each channel stack CS can connect adjacent pairs of source / drain regions SD to each other. The source / drain regions SD can be epitaxial patterns formed using the channel semiconductor patterns CH1, CH2, and CH3 as seed layers.

[0026] The source / drain region SD can apply strain to the channel semiconductor patterns CH1, CH2, and CH3. The source / drain region SD can be configured as, for example, a PMOSFET, and can include materials that apply compressive strain to the channel semiconductor patterns CH1, CH2, and CH3. For example, the channel semiconductor patterns CH1, CH2, and CH3 can include a first semiconductor element, and the source / drain region SD can include a second semiconductor element. The lattice constant of the crystal formed by the second semiconductor element can be greater than the lattice constant of the crystal formed by the first semiconductor element. In an embodiment, the first semiconductor element can be, for example, silicon (Si). In an embodiment, the second semiconductor element can be, for example, germanium (Ge). The source / drain region SD can include both the first and second semiconductor elements. In an embodiment, when the channel semiconductor patterns CH1, CH2, and CH3 include silicon, the source / drain region SD can be formed of or include a SiGe layer whose lattice constant is greater than that of silicon. In an embodiment, the conductivity type of the source / drain region SD can be p-type.

[0027] In the implementation method, such as Figure 2CAs shown, the side surfaces of the source / drain regions SD that are opposite each other along the second direction D2 may have a laterally sharp wedge shape. For example, each of the source / drain regions SD may include a lower side surface and an upper side surface, the horizontal distance between the lower side surfaces (e.g., the distance along the second direction D2) increasing with the distance to the top surface of the insulating layer 105 (e.g., the distance along the third direction D3), and the horizontal distance between the upper side surfaces decreasing with the distance to the top surface of the insulating layer 105. The bottom surface of the source / drain region SD (e.g., the surface facing the substrate 100) may have a recessed shape. In one embodiment, the lowest or bottommost surface of the source / drain region SD (e.g., the portion of the source / drain region SD closest to the substrate 100 along the third direction D3) may be located at a level no lower than the highest or topmost surface of the insulating layer 105 (e.g., the portion of the insulating layer 105 furthest from the substrate 100 along the third direction D3) (e.g., the distance from the substrate 100 along the third direction D3 of the insulating layer 105). In another embodiment, the adjacent facing side surfaces of the source / drain region SD along the second direction D2 may be spaced apart from each other. In yet another embodiment, the adjacent facing side surfaces of the source / drain region SD may be connected to each other.

[0028] An air gap AG may be located between the insulating layer 105 and the source / drain region SD. The air gap AG may be an area not filled with solid material and may be substantially empty. The air gap AG may be defined by the top surface of the insulating layer 105 and the recessed bottom surface of the source / drain region SD. Further reference... Figure 3 The topmost point AGt of the air gap AG can be located at a level lower than the level of the bottom surface CH1L of the first channel semiconductor pattern CH1 (e.g., the topmost point AGt of the air gap AG is closer to the substrate 100 than the bottom surface CH1L of the first channel semiconductor pattern CH1 along the third direction D3). The first channel semiconductor pattern CH1 is the closest (e.g., closest along the third direction D3) insulating layer 105 among the vertically stacked channel semiconductor patterns CH1, CH2, and CH3. For example, the strain applied to the first channel semiconductor pattern CH1 may not be reduced by the air gap AG. The bottommost point AGb of the air gap AG can be located at a level lower than the topmost surface 105t of the insulating layer 105 (e.g., closer to the substrate 100 along the third direction D3).

[0029] The source / drain region SD may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 formed sequentially.

[0030] The first semiconductor pattern SP1 may be a buffer layer and may be located (e.g., along the first direction D1) between the channel stack CS and the second semiconductor pattern SP2. The germanium (Ge) content in the first semiconductor pattern SP1 may be relatively low. In an embodiment, the germanium (Ge) content in the first semiconductor pattern SP1 may be, for example, 5 at% to 15 at%. The germanium (Ge) content in the second semiconductor pattern SP2 may be higher than that in the first semiconductor pattern SP1. In an embodiment, the germanium (Ge) content in the second semiconductor pattern SP2 may be, for example, 20 at% to 60 at%.

[0031] In one embodiment, the third semiconductor pattern SP3 may be a capping layer for protecting the second semiconductor pattern SP2. The third semiconductor pattern SP3 may include the same semiconductor elements as the substrate 100. In another embodiment, the third semiconductor pattern SP3 may include single-crystal silicon (Si). The concentration of silicon (Si) in the third semiconductor pattern SP3 may be, for example, from about 90 at% to about 100 at%.

[0032] In an implementation, the second semiconductor pattern SP2, which is one of the semiconductor patterns of the source / drain region SD, may have the highest germanium concentration and the largest volume (e.g., the largest volume among the semiconductor patterns of the source / drain region SD). For example, the source / drain region SD may apply strong strain to the channel stack CS located on its side surface.

[0033] Figure 3 A portion of a semiconductor device according to an embodiment is shown (e.g., Figure 2A Enlarged sectional view of AA).

[0034] For example, refer to Figure 3The source / drain region SD can be located between a first channel stack CS1 and a second channel stack CS2 spaced apart from each other along a first direction D1. Each of the first channel stack CS1 and the second channel stack CS2 can include a first channel semiconductor pattern CH1, a second channel semiconductor pattern CH2, and a third channel semiconductor pattern CH3 stacked and vertically spaced apart from each other. The first channel semiconductor pattern CH1, the second channel semiconductor pattern CH2, and the third channel semiconductor pattern CH3 can be located at a first vertical level LV1, a second vertical level LV2, and a third vertical level LV3, respectively. The source / drain region SD can cover the side surfaces of the first channel semiconductor pattern CH1, the second channel semiconductor pattern CH2, and the third channel semiconductor pattern CH3. The topmost region SDt of the source / drain region SD can be located at a level higher than the top surface of the third channel semiconductor pattern CH3 (e.g., the distance from the substrate 100 to the topmost region SDt of the source / drain region SD along a third direction D3 can be greater than the distance from the substrate 100 to the top surface of the third channel semiconductor pattern CH3 along a third direction D3). The bottom SP1b of the source / drain region SD can be located at a level below the bottom surface CH1L of the first channel semiconductor pattern CH1 but not below the top surface 105t of the insulating layer 105 (for example, the distance from the substrate 100 to the bottom SP1b of the source / drain region SD along the third direction D3 can be less than the distance from the substrate 100 to the bottom surface CH1L of the first channel semiconductor pattern CH1 along the third direction D3, and can be greater than the distance from the substrate 100 to the top surface 105t of the insulating layer 105 along the third direction D3).

[0035] A pair of first semiconductor patterns SP1 may cover the side surfaces of a first channel stack CS1 and a second channel stack CS2. The pair of first semiconductor patterns SP1 may have a shape symmetrical to each other along a first direction D1 (e.g., a shape symmetrical about a line or plane bisecting the source / drain region SD along a third direction D3). Each of the pair of first semiconductor patterns SP1 may include an upper SP1U and a lower SP1L. The width of the lower SP1L along the first direction D1 may be greater than the width of the upper SP1U along the first direction D1. The width of the upper SP1U of the first semiconductor pattern SP1, measured along the first direction D1, may increase as the distance from the lower SP1L decreases (e.g., closer to the lower SP1L). Each of the lower SP1L of the first semiconductor pattern SP1 may include a protrusion PS projecting toward the other first semiconductor pattern SP1 adjacent to it. The width of the lower part SP1L of the first semiconductor pattern SP1, measured along the first direction D1, can decrease as the vertical horizontal distance from the protrusion PS increases (for example, the lower part SP1L of the first semiconductor pattern SP1 can have a maximum width along the first direction at its protrusion PS).

[0036] The first semiconductor pattern SP1 may have a first width w1 (e.g., along the first direction D1) at a first vertical horizontal LV1 where the first channel semiconductor pattern CH1 is located. The first semiconductor pattern SP1 may have a second width w2 (e.g., along the first direction D1) at a second vertical horizontal LV2 where the second channel semiconductor pattern CH2 is located. The first semiconductor pattern SP1 may have a third width w3 (e.g., along the first direction D1) at a third vertical horizontal LV3 where the third channel semiconductor pattern CH3 is located. The first width w1 may be greater than the second width w2, and the second width w2 may be greater than the third width w3.

[0037] A second semiconductor pattern SP2 may be located on a pair of first semiconductor patterns SP1 to connect the pair of first semiconductor patterns SP1 to each other. The bottom surface of the second semiconductor pattern SP2 may be located at a level lower than the level of the protrusion PS of the first semiconductor pattern SP1. The second semiconductor pattern SP2 may define an air gap AG together with the first semiconductor pattern SP1 and the insulating layer 105 (and, for example, the lower semiconductor layer 107 described below). The topmost point AGt of the air gap AG may be defined by the bottom surface of the second semiconductor pattern SP2. The topmost point AGt of the air gap AG may be located at a level lower than the level of the bottom surface CH1L of the first channel semiconductor pattern CH1.

[0038] The second semiconductor pattern SP2 may include a first sub-semiconductor pattern SP2a, a second sub-semiconductor pattern SP2b, and a third sub-semiconductor pattern SP2c formed sequentially. The second sub-semiconductor pattern SP2b may cover the surface of the first sub-semiconductor pattern SP2a. The third sub-semiconductor pattern SP2c may cover the surface of the second sub-semiconductor pattern SP2b. In an embodiment, the germanium (Ge) content in the first sub-semiconductor pattern SP2a may be, for example, 20 at% to 30 at, the germanium (Ge) content in the second sub-semiconductor pattern SP2b may be, for example, 35 at% to 45 at, and the germanium (Ge) content in the third sub-semiconductor pattern SP2c may be, for example, 50 at% to 60 at. The third semiconductor pattern SP3 may cover the surface of the third sub-semiconductor pattern SP2c.

[0039] The first interlayer insulating layer 110 may be located on the top surface of the substrate 100. The first interlayer insulating layer 110 may cover the insulating layer 105, the gate spacer GS, and the source / drain region SD. The first interlayer insulating layer 110 may have a top surface that is substantially coplanar with the top surface of the gate overlay pattern GP. The second interlayer insulating layer 120 may be located on the first interlayer insulating layer 110. In embodiments, the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may be formed of, for example, a silicon oxide layer or a silicon oxynitride layer, or may include a silicon oxide layer or a silicon oxynitride layer.

[0040] The active contact AC can penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and can be connected to the source / drain region SD. In an embodiment, the active contact AC can be formed of or comprise a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0041] Figure 4 and Figure 5 A portion of a semiconductor device according to an embodiment is shown (e.g., Figure 2A Enlarged sectional view of AA).

[0042] Reference Figure 4 The lower part of the first semiconductor pattern SP1 may protrude in a raised manner toward the air gap AG, for example, the air gap AG may have a recessed upper surface. The bottommost part of the first semiconductor pattern SP1 (e.g., the bottommost part of the source / drain region SD, SP1b) may be located at a level lower than the level of the topmost surface 105t of the insulating layer 105.

[0043] Reference Figure 5 The aforementioned pair of first semiconductor patterns SP1 can be connected to each other to form a single object or structure. The connecting portion CR can connect a portion of the first semiconductor pattern SP1 located on the side surface of the first channel stack CS1 to another portion of the first semiconductor pattern SP1 located on the side surface of the second channel stack CS2. For example, the first semiconductor pattern SP1 can cover the side surfaces of the first channel stack CS1 and the second channel stack CS2, and the bottom and top surfaces of the first semiconductor pattern SP1 can have recessed shapes. The uppermost AGt of the air gap AG can be defined by the bottom surface of the first semiconductor pattern SP1.

[0044] Figure 6 , Figure 7 , Figure 8A and Figure 8B The semiconductor device according to the embodiment is shown along Figure 1 A sectional view taken by line C-C'.

[0045] Reference Figure 6 The source / drain region SD can be spaced apart from the insulating layer 105. In an embodiment, the region between the source / drain region SD and the insulating layer 105 can be filled with a first interlayer insulating layer 110. For example, the bottom surface of the source / drain region SD can be covered by the first interlayer insulating layer 110. The first interlayer insulating layer 110 can contact the bottom surface of the second semiconductor pattern SP2.

[0046] Reference Figure 7The source / drain region SD can be spaced apart from the insulating layer 105, and the third semiconductor pattern SP3 can surround the second semiconductor pattern SP2. For example, the bottom surface of the second semiconductor pattern SP2 can be covered by the third semiconductor pattern SP3, so the bottom surface of the second semiconductor pattern SP2 is not exposed (e.g., not exposed to the first interlayer insulating layer 110).

[0047] Combination Figure 5 Reference Figure 8A and Figure 8B The first semiconductor pattern SP1 on the first channel stack CS1 and the first semiconductor pattern SP1 on the second channel stack CS2 can be connected to each other to form a single object or structure. For example, a portion of the surface of the first semiconductor pattern SP1 can be covered by the second semiconductor pattern SP2. In an embodiment, as... Figure 8A As shown, another portion of the surface of the first semiconductor pattern SP1 (e.g., the bottom surface) may be covered by the first interlayer insulating layer 110. In an embodiment, as... Figure 8B As shown, the bottom surface of the first semiconductor pattern SP1 and the bottom surface of the second semiconductor pattern SP2 can be covered by the third semiconductor pattern SP3.

[0048] In the following, a method for manufacturing a semiconductor device according to an embodiment will be described in more detail with reference to the accompanying drawings.

[0049] Figure 9 , Figure 11 , Figure 13 , Figure 18 and Figure 20 A plan view of the stages in a method for manufacturing a semiconductor device according to an embodiment is shown. Figure 10A , Figure 12A , Figure 14A , Figure 19A and Figure 21A They show the following along Figure 9 , Figure 11 , Figure 13 , Figure 18 and Figure 20 A sectional view taken by line A-A'. Figure 10B , Figure 12B , Figure 14B , Figure 19B and Figure 21B They show the following along Figure 9 , Figure 11 , Figure 13 , Figure 18 and Figure 20 The sectional view taken by line B-B'. Figure 14C , Figure 19C and Figure 21C They show the following along Figure 13 , Figure 18 and Figure 20 A sectional view taken by line C-C'. Figures 15 to 17 The following is shown according to the embodiment. Figure 13 The cross-sectional view taken along line A-A' shows the method for forming the source / drain pattern.

[0050] Reference Figure 9 , Figure 10A and Figure 10B An SOI wafer can be prepared. The SOI wafer may include a substrate 100 and an insulating layer 105 located on the substrate 100. A lower semiconductor layer 107 may be formed on the SOI wafer. The lower semiconductor layer 107 may be a seed layer for growing a sacrificial layer SAC and a channel semiconductor layer CHL on its top surface. Thereafter, the sacrificial layer SAC and the channel semiconductor layer CHL may be stacked alternately and repeatedly on the lower semiconductor layer 107. The sacrificial layer SAC may include a material that has etch selectivity relative to the channel semiconductor layer CHL. For example, the sacrificial layer SAC may be formed of a material selected to minimize the etching of the channel semiconductor layer CHL in a process of etching the sacrificial layer SAC using a predetermined etch formulation. This etch selectivity may be quantitatively expressed as the ratio of the etch rate of the sacrificial layer SAC to the etch rate of the channel semiconductor layer CHL. In one embodiment, the sacrificial layer SAC may be formed of or comprise a material selected to have an etch rate ratio of 1:10 to 1:200 relative to the channel semiconductor layer CHL. In another embodiment, the sacrificial layer SAC may be formed of or comprise, for example, SiGe, Si, or Ge, and the channel semiconductor layer CHL may be formed of or comprise, for example, another of SiGe, Si, or Ge.

[0051] The sacrificial layer SAC can be formed by an epitaxial growth process, wherein the lower semiconductor layer 107 or the channel semiconductor layer CHL is used as a seed layer. The channel semiconductor layer CHL can also be formed by an epitaxial growth process, wherein the sacrificial layer SAC is used as a seed layer. For example, the epitaxial growth process can be a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The sacrificial layer SAC and the channel semiconductor layer CHL can be formed continuously in the same chamber. The sacrificial layer SAC and the channel semiconductor layer CHL can be conformally grown from the entire top surface of the substrate 100 (e.g., not in a selective epitaxial growth manner). In an embodiment, the sacrificial layer SAC and the channel semiconductor layer CHL can be formed to have substantially the same thickness.

[0052] Next, the sacrificial layer SAC and the channel semiconductor layer CHL can be patterned to form a preliminary channel stack pCS. The preliminary channel stack pCS can have a line shape or strip shape extending along a first direction D1 (e.g., lateral) and can be spaced apart from each other along a second direction D2. The patterning process can be an anisotropic etching process performed using a mask pattern. In an embodiment, when the sacrificial layer SAC and the channel semiconductor layer CHL are patterned, the lower semiconductor layer 107 can also be patterned. In an embodiment, with Figure 10B As shown, the lower semiconductor layer 107 can be partially retained in the region below the sacrificial layer SAC and the channel semiconductor layer CHL.

[0053] Reference Figure 11 , Figure 12A and Figure 12B The sacrificial gate pattern PP can be formed to intersect with the initial channel stack pCS. The sacrificial gate pattern PP can be formed to have a line shape or strip shape extending along a second direction D2 (e.g., longitudinal). Forming the sacrificial gate pattern PP can include: forming a sacrificial layer on a substrate 100; forming a mask pattern MP on the sacrificial layer; and using the mask pattern MP as an etching mask to etch the sacrificial layer. The sacrificial layer can be formed of, for example, polysilicon or include polysilicon. The mask pattern MP can be formed of, for example, silicon oxide, silicon nitride, or silicon oxynitride or include silicon oxide, silicon nitride, or silicon oxynitride. A pair of gate spacers GS can be formed on opposite side surfaces of each of the sacrificial gate patterns PP. Forming the gate spacers GS can include: forming a spacer layer on the substrate 100 using a deposition process (e.g., CVD or ALD process); and performing an anisotropic etching process on the spacer layer. In embodiments, the gate spacers GS can be formed of, for example, SiCN, SiCON, or SiN or include SiCN, SiCON, or SiN.

[0054] Reference Figure 13 as well as Figures 14A to 14C The channel stack CS can be formed by removing a portion of the initial channel stack pCS. A portion of the channel semiconductor layer CHL can be removed to form a first channel semiconductor pattern CH1, a second channel semiconductor pattern CH2, and a third channel semiconductor pattern CH3 that are vertically spaced and stacked. A portion of the sacrificial layer SAC can be removed to form a sacrificial pattern SAP. The sacrificial pattern SAP and the channel semiconductor patterns CH1, CH2, and CH3 can be stacked alternately.

[0055] For example, further reference Figure 15The mask pattern MP and gate spacer GS can be used as etching masks to remove the portions of the first preliminary channel stack pCS located between the sacrificial gate patterns PP. An anisotropic etching process can be used to perform the removal of these portions of the preliminary channel stack pCS. In one embodiment, an anisotropic etching process can be performed to expose the top surface of the insulating layer 105. As a result, each of the preliminary channel stack pCS can be cut along a first direction D1 to form channel stacks CS spaced apart from each other and arranged along both the first direction D1 and the second direction D2. Furthermore, recessed regions RS can be formed between the channel stacks CS that are adjacent to each other along the first direction D1. Each of the recessed regions RS can be formed with a "U"-shaped cross-section. For example, when measured along the first direction D1 in a cross-sectional view, the recessed region RS can have its maximum width at its middle level. The bottom surface of the recessed region RS can be located at a level not higher than the top surface of the insulating layer 105, and in this case, the preliminary channel stack pCS can be divided into a plurality of channel stacks CS by the recessed regions RS. For example, the bottom surface of the recessed region RS can be located at a level lower than the level of the top surface of the insulating layer 105.

[0056] Subsequently, source / drain regions SD can be formed in the recessed region RS. The source / drain regions SD may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 formed sequentially.

[0057] Reference Figure 16 A preliminary first semiconductor pattern pSP1 can be formed using a selective epitaxial growth process, wherein the channel semiconductor patterns CH1, CH2, and CH3 exposed through the recessed region RS are used as seed layers. The preliminary first semiconductor pattern pSP1 may contain a low concentration of a second semiconductor element. The first semiconductor pattern SP1 can be lightly doped with impurities in situ. For example, the preliminary first semiconductor pattern pSP1 may include a silicon-germanium (SiGe) layer in situ doped with boron. The germanium (Ge) content in the first semiconductor pattern SP1 may be, for example, from 5 at% to 15 at%.

[0058] The first selective epitaxial growth process can be performed under higher pressure conditions than those in the second and third selective epitaxial growth processes described below. In an embodiment, the first selective epitaxial growth process can be performed under pressures ranging from 50 Torr to 300 Torr.

[0059] Reference Figure 16 and Figure 17A reflow process can be performed on the preliminary first semiconductor pattern pSP1 to form the first semiconductor pattern SP1. The reflow process can be performed in a hydrogen environment (e.g., in a hydrogen atmosphere). The reflow process can be performed under pressure conditions lower than those used for the first selective epitaxial growth process. For example, the reflow process can be performed at a pressure of approximately 30 Torr. The reflow process can be performed at a temperature of, for example, 500°C to 700°C. During the reflow process, the width of the upper portion of the preliminary first semiconductor pattern pSP1 along the first direction D1 can be reduced, and the width of the lower portion of the preliminary first semiconductor pattern pSP1 along the first direction D1 can be increased. For example, the side surface of the sacrificial pattern SAP located most adjacent to the insulating layer 105 can be thickly covered by the first semiconductor pattern SP1, which prevents the lower portion of the source / drain region SD from being damaged by the subsequent process of removing the sacrificial pattern SAP.

[0060] Return to reference Figure 13 as well as Figures 14A to 14C A second semiconductor pattern SP2 can be formed using a second selective epitaxial growth process, wherein a first semiconductor pattern SP1 is used as a seed layer. The second semiconductor pattern SP2 can be formed to have a higher content of the second semiconductor element than the first semiconductor pattern SP1. The second semiconductor pattern SP2 can be heavily doped with impurities in situ. The second selective epitaxial growth process can be repeated while increasing the concentration of the second semiconductor element and reducing the pressure. For example, a first sub-semiconductor pattern SP2a, a second sub-semiconductor pattern SP2b, and a third sub-semiconductor pattern SP2c can be formed. In an embodiment, each of the first sub-semiconductor pattern SP2a, the second sub-semiconductor pattern SP2b, and the third sub-semiconductor pattern SP2c can be formed by, for example, a boron-doped silicon-germanium (SiGe) layer or include a boron-doped silicon-germanium (SiGe) layer. The germanium (Ge) content in the second semiconductor pattern SP2 can be, for example, from 20 at% to 60 at%.

[0061] A third semiconductor pattern SP3 can be formed using a third selective epitaxial growth process, wherein a second semiconductor pattern SP2 is used as a seed layer. The third semiconductor pattern SP3 may contain the same semiconductor elements as the semiconductor elements (e.g., the first semiconductor elements) of the substrate 100. For example, the third semiconductor pattern SP3 may include single-crystal silicon (Si). The first selective epitaxial growth process, the second selective epitaxial growth process, and the third selective epitaxial growth process described above can be performed sequentially in the same chamber.

[0062] During the formation of the second semiconductor pattern SP2 and the third semiconductor pattern SP3, an air gap AG can be formed between the source / drain region SD and the insulating layer 105.

[0063] Reference Figure 18 as well as Figures 19A to 19C A first interlayer insulating layer 110 can be formed on substrate 100. The first interlayer insulating layer 110 can then be planarized to expose the top surface of the sacrificial gate pattern PP. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. All mask patterns MP can be removed during the planarization process. For example, the top surface of the first interlayer insulating layer 110 can be coplanar with the top surfaces of the sacrificial gate pattern PP and the gate spacer GS. Subsequently, the exposed sacrificial gate pattern PP and sacrificial pattern SAP can be selectively removed.

[0064] In the implementation method, such as Figures 6 to 8B As shown, when the source / drain region SD is formed to be spaced apart from the insulating layer 105, the first interlayer insulating layer 110 can be formed to fill the air gap AG.

[0065] Reference Figure 20 as well as Figures 21A to 21C The gate dielectric pattern GI, gate electrode GE, and gate overlay pattern GP can be formed in the empty spaces from which the sacrificial gate pattern PP and sacrificial pattern SAP are removed. The gate dielectric pattern GI can be conformally formed to partially fill the empty spaces. The gate dielectric pattern GI can be formed by atomic layer deposition (ALD) or chemical oxidation processes. As an example, the gate dielectric pattern GI can be formed of or include a high-k dielectric material. High-k dielectric materials can include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0066] The gate electrode GE can be formed by forming a gate electrode layer that completely fills the remaining area of ​​the empty space and then planarizing the gate electrode layer. As an example, the gate electrode layer can be formed of or include a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0067] Next, the upper portion of the gate electrode GE can be recessed. A gate cover pattern GP can be formed on the gate electrode GE. The gate cover pattern GP can be formed to completely fill the recessed portion of the gate electrode GE. The gate cover pattern GP can be formed of, for example, SiON, SiCN, SiCON, or SiN, or include, for example, SiON, SiCN, SiCON, or SiN.

[0068] Return to reference Figure 1 as well as Figures 2A to 2CA second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110 and the gate overlay pattern GP. The second interlayer insulating layer 120 can be formed of, for example, silicon oxide or a low-k oxide material, or include, for example, silicon oxide or a low-k oxide material. For example, the low-k oxide material can include carbon-doped silicon oxide (e.g., SiCOH). The second interlayer insulating layer 120 can be formed by a CVD process.

[0069] Contact holes can be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and expose the source / drain region SD. In an embodiment, the contact hole can be a self-aligned contact hole that is self-aligned by the gate overlay pattern GP and the gate spacer GS. Active contacts AC can be formed in the contact hole and can be electrically connected to the source / drain region SD.

[0070] In summary and review, the miniaturization of MOS-FETs leads to a degradation in the operating characteristics of semiconductor devices. Various studies are underway to overcome the technical limitations associated with the miniaturization of semiconductor devices and to achieve high-performance semiconductor devices.

[0071] One or more embodiments may provide a semiconductor device including a field-effect transistor and a method of manufacturing the semiconductor device.

[0072] One or more embodiments may provide a semiconductor device with improved electrical characteristics and improved reliability.

[0073] According to embodiments, the lower portion of the source / drain regions can have a stable structure, enabling the realization of a semiconductor device with improved reliability. Furthermore, according to embodiments, the strain applied to the semiconductor channel pattern can be increased, thereby achieving a semiconductor device with improved electrical characteristics.

[0074] Example embodiments have been disclosed herein, and although specific terminology has been used, it will be used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art from the date of filing of this application that, unless specifically instructed otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device comprising: an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode intersecting the channel semiconductor patterns; source / drain regions at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source / drain regions having a concave bottom surface; and an air gap between the insulating layer and the bottom surface of the source / drain regions.

2. The semiconductor device of claim 1, wherein, a topmost portion of the air gap is located at a level lower than a level of a bottom surface of a bottommost channel semiconductor pattern of the channel semiconductor patterns closest to the insulating layer.

3. The semiconductor device of claim 1, wherein, a bottommost portion of the air gap is located at a level lower than a level of a topmost surface of the insulating layer.

4. The semiconductor device according to claim 1, wherein: the source / drain regions are spaced apart from each other in a first direction, each of the source / drain regions includes a pair of first semiconductor patterns spaced apart from each other in the first direction, and the first semiconductor patterns have a lower portion and an upper portion, a width of the lower portion in the first direction being greater than a width of the upper portion in the first direction.

5. The semiconductor device according to claim 1, wherein: the source / drain regions are spaced apart from each other in a first direction, and each of the source / drain regions includes a pair of first semiconductor patterns spaced apart from each other in the first direction, and a second semiconductor pattern on the pair of first semiconductor patterns and connecting the pair of first semiconductor patterns.

6. The semiconductor device according to claim 5, wherein: the channel semiconductor patterns include a first semiconductor element, each of the first semiconductor patterns and the second semiconductor patterns includes a second semiconductor element, a crystal lattice constant of a crystal constituted by the second semiconductor element being greater than a crystal lattice constant of a crystal constituted by the first semiconductor element, and a content of the second semiconductor element in the second semiconductor pattern is higher than a content of the second semiconductor element in each of the first semiconductor patterns.

7. The semiconductor device of claim 5, wherein, a topmost portion of the air gap is defined by a bottom surface of each of the second semiconductor patterns.

8. The semiconductor device according to claim 1, wherein: the channel semiconductor patterns include a first semiconductor element, the source / drain regions include the first semiconductor element and a second semiconductor element, a crystal lattice constant of a crystal constituted by the second semiconductor element being greater than a crystal lattice constant of a crystal constituted by the first semiconductor element, and a content of the second semiconductor element in the source / drain regions decreases as a distance from the insulating layer decreases.

9. The semiconductor device according to claim 1, wherein: the source / drain regions are spaced apart from each other in a first direction, each of the source / drain regions includes a pair of first semiconductor patterns spaced apart from each other in the first direction, and a bottommost portion of the first semiconductor patterns is located at a level lower than a level of a topmost surface of the insulating layer.

10. The semiconductor device according to claim 1, wherein: the source / drain regions include first semiconductor patterns covering side surfaces of the channel semiconductor patterns, and second semiconductor patterns on the first semiconductor patterns, and the air gap is defined by a bottom surface of the first semiconductor patterns, a bottom surface of the second semiconductor patterns, and a top surface of the insulating layer.

11. A semiconductor device comprising: an insulating layer on a substrate; a first channel semiconductor pattern located on the insulating layer and at a first vertical level; a second channel semiconductor pattern stacked on the first channel semiconductor pattern and located at a second vertical level higher than the first vertical level; a gate electrode intersecting the first channel semiconductor pattern and the second channel semiconductor pattern; and a source / drain region located on a side surface of the gate electrode and connected to the first channel semiconductor pattern and the second channel semiconductor pattern, wherein: the source / drain region includes a first semiconductor pattern covering side surfaces of the first channel semiconductor pattern and the second channel semiconductor pattern, and a second semiconductor pattern located on the first semiconductor pattern, and a width of the first semiconductor pattern at the first vertical level is greater than a width of the first semiconductor pattern at the second vertical level.

12. The semiconductor device according to claim 11, wherein: each of the first channel semiconductor pattern and the second channel semiconductor pattern includes a first semiconductor element and a second semiconductor element, a crystal of the second semiconductor element has a lattice constant greater than a crystal of the first semiconductor element, and a content of the second semiconductor element in the second semiconductor pattern is higher than a content of the second semiconductor element in the first semiconductor pattern. a bottommost portion of the first semiconductor pattern is located at a level lower than a level of a topmost surface of the insulating layer.

13. The semiconductor device of claim 11, wherein, 14. The semiconductor device according to claim 11, further comprising an air gap between a bottom surface of the source / drain region and a top surface of the insulating layer. a topmost portion of the air gap is located at a level lower than a level of a bottom surface of the first channel semiconductor pattern.

15. The semiconductor device of claim 14, wherein, 16. A semiconductor device comprising: an insulating layer located on a substrate; a first channel stack located on the insulating layer; a second channel stack located on the insulating layer and spaced apart from the first channel stack in a first direction, each of the first channel stack and the second channel stack including channel semiconductor patterns stacked vertically spaced apart from each other; a source / drain region located between the first channel stack and the second channel stack, wherein the source / drain region includes a pair of first semiconductor patterns covering side surfaces of the channel semiconductor patterns of the first channel stack and the channel semiconductor patterns of the second channel stack and spaced apart from each other in the first direction, and a second semiconductor pattern located on the pair of first semiconductor patterns and connecting the pair of first semiconductor patterns to each other. the pair of first semiconductor patterns include protrusions, the protrusion of one first semiconductor pattern protruding toward the protrusion of the other first semiconductor pattern.

18. The semiconductor device according to claim 16, further comprising an air gap between a bottom surface of the source / drain region and a top surface of the insulating layer.

17. The semiconductor device of claim 16, wherein, a topmost portion of the air gap is located at a level lower than a level of a bottom surface of a lowermost channel semiconductor pattern of the channel semiconductor patterns. a bottommost portion of the air gap is located at a level lower than a level of a topmost surface of the insulating layer.

19. The semiconductor device of claim 18, wherein, ​ 20. The semiconductor device of claim 18, wherein, ​

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