Unified address space for storage devices

Abstract

A unified address space for storage devices is disclosed. The provided method for processing I / O commands includes: obtaining a read command indicating a logical address; querying an FTL table using the logical address to obtain a unified address; calculating a physical address based on the unified address; and using the physical address to access the storage medium to obtain the data to be accessed by the read command.

Description

Technical Field

[0001] The present application relates to a storage device, and in particular, to using a unified address space based on a small block structure in a storage device. Background Art

[0002] Figure 1 The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MR AM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor (CPU) or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The FTL table and / or the data of the cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0009] A chunk contains physical blocks from each of multiple logical units (LUNs), also called logical unit groups. Each logical unit can provide one physical block for a chunk. For example, Figure 2In the schematic diagram of the block shown, the block is constructed on every 16 logical units (LUNs). Each block includes 16 physical blocks from the 16 logical units (LUNs). Figure 2 In the example of , chunk 0 includes physical chunk 0 from each of the 16 logical units (LUNs), and chunk 1 includes physical chunk 1 from each logical unit (LUN). Chunks may also be structured in a variety of other ways.

[0010] For example, page stripes are constructed in large blocks, and physical pages with the same physical address in each logical unit (LUN) constitute a "page stripe". Figure 2 In , physical pages P0-0, P0-1, ... and P0-x constitute page stripe 0, wherein physical pages P0-0, P0-1, ... and P0-14 are used to store user data, and physical pages P0-x are used to store check data calculated based on all user data in the stripe. Similarly, Figure 2 In the embodiment, physical page P2-0, physical page P2-1, ... and physical page P2-x constitute page stripe 2. The physical page for storing the check data can be located at any position in the page stripe. As another example, in the Chinese patent application with application number 201710752321.0, Figure 3A and its instructions Figure 3A In the related description, another construction method of large blocks is provided.

[0011] In the storage device, the FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address.

[0012] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is an important metadata in a solid-state storage device. The FTL table includes multiple FTL table entries (or table items). In one case, each FTL table entry records the correspondence between a logical page address and a physical page. In another case, each FTL table entry records the correspondence between a plurality of continuous logical page addresses and a plurality of continuous physical pages. In yet another case, each FTL table entry records the correspondence between a logical block address and a physical block address. In still yet another case, the FTL table records the mapping relationship between a logical block address and a physical block address, and / or the mapping relationship between a logical page address and a physical page address.

[0013] When processing a read command from the host, the solid-state storage device uses the logical address carried in the read command to obtain the corresponding physical address from the FTL table, and sends a read request to the NVM chip based on the physical address, and receives the data output by the NVM chip in response to the read request. When processing a write command from the host, the solid-state storage device assigns a physical address to the write command, records the correspondence between the logical address of the write command and the assigned physical address in the FTL table, and sends a write request to the NVM chip based on the assigned physical address.

[0014] There are many storage protocols (also called storage interface protocols) according to which storage devices are accessed. For example, the SCSI (Small Computer System Interface) protocol and the NVMe (NVM Express) protocol. In the SCSI protocol and the NVMe protocol, the storage device exposes a linear logical address space to the electronic device (such as a host) coupled thereto. The host uses the logical address to access the storage device.

[0015] There is also an OCSSD (OpenChannel Solid State Drive) storage protocol ("OpenChannel Solid Drive Specification" Revision 2.0, January 29, 2018, available from http: / / lightnvm.io / docs / OCSSD-2_0-20180129.pdf), which exposes more physical information related to the NVM storage medium to the electronic device coupled with the storage device, so that the host uses the addressing method defined by OCSSD to access the storage medium of the storage device. The addressing method defined by the OCSSD protocol can be used in the NVMe protocol. Summary of the invention

[0016] There are a variety of available control components, NVM chips, memories, etc. for constructing storage devices. The composition of the storage cells of the NVM chip varies with the generation and / or specifications of the product. The configuration of the storage cell includes, for example, the number of logical cells, the number of physical blocks, the storage capacity of the physical blocks, the number of word lines, the number of physical pages in the word lines, the number of physical pages, the storage capacity of the physical pages, the number of bits stored in each storage cell (referred to as the type of storage cell), etc. The control component of the storage device is also coupled to multiple NVM chips in a variety of ways, in which the number of channels used, the number of chips coupled to the channels, and the number of chip select signals (CE) may be different. These changes lead to diversity in the physical address space of the storage device.

[0017] In order to adapt to changes in control components, NVM chips, memories, etc., it is necessary to change or redevelop the software (or firmware) running in the processor of the control component, which prolongs the development cycle of the storage device, increases the development cost, and introduces more defects during the development process.

[0018] It is desirable to provide a unified physical address space that does not change frequently, so that the FTL of the storage device does not need to be changed between multiple storage devices. The unified physical address space also helps to provide OCSSD, so that the host can manage multiple storage devices when providing FTL without adapting or providing drivers for each storage device. Conversion is required between the unified physical address space and the physical address accepted by the NVM chip. This conversion should be simple, such as resolvable, so that it can be completed by storage devices with insufficient computing / memory resources, thereby hiding the physical address space changes caused by different configurations of its storage units from the host accessing the storage device.

[0019] According to the first aspect of the present application, a first method for processing IO commands according to the first aspect of the present application is provided, including: obtaining a read command indicating a logical address; using the logical address to query the FTL table to obtain a unified address; calculating a physical address based on the unified address; using the physical address to access a storage medium to obtain data to be accessed by the read command.

[0020] According to the second method of processing IO commands in the first aspect of the present application, the method includes: obtaining a write command indicating a logical address; assigning a unified address that indexes data units to which data has not yet been written; calculating a physical address based on the unified address; and using the physical address to access a storage medium to write the data to be written by the write command.

[0021] According to the third method for processing IO commands in the first aspect of the present application, the method includes: obtaining a read command indicating a unified address; calculating a physical address based on the unified address; and using the physical address to access a storage medium to obtain data to be accessed by the read command.

[0022] According to one of the first to third methods of processing IO commands according to the first aspect of the present application, a fourth method of processing IO commands according to the first aspect of the present application is provided, wherein the unified address is an element of a unified address space, the unified address space is composed of storage space provided by multiple small blocks, and the number of the small block has a linear relationship with the unified address of the small block in the unified address space.

[0023] According to the fourth method for processing IO commands according to the first aspect of the present application, a fifth method for processing IO commands according to the first aspect of the present application is provided, wherein the small block includes multiple data units from each of multiple logical units, and the number of the data unit has a linear relationship with the address of the data unit in the unified address space.

[0024] According to the fifth method for processing IO commands according to the first aspect of the present application, a sixth method for processing IO commands according to the first aspect of the present application is provided, wherein multiple data units in small blocks from different logical units have the same physical address.

[0025] According to one of the fourth to sixth methods of processing IO commands according to the first aspect of the present application, a seventh method of processing IO commands according to the first aspect of the present application is provided, wherein the numbers of the small blocks correspond one-to-one to the word lines of the storage medium, and the numbers of the small blocks serve as part of the unified address of the small blocks.

[0026] According to one of the fourth to seventh methods of processing IO commands of the first aspect of the present application, an eighth method of processing IO commands according to the first aspect of the present application is provided, wherein the physical address includes bits describing word lines and bits describing physical page indexes, wherein the bits describing word lines and the bits describing physical page indexes jointly address physical pages of the storage medium; the unified address includes a small block number and a data unit number, wherein the data unit number indicates a data unit within the small block represented by the small block number; the bits describing word lines and the bits describing physical page indexes are isolated in the physical address by bits describing parallel units; and the bits describing parallel units of the physical address come from specified high bits of the data unit number of the unified address corresponding to the physical address.

[0027] According to the eighth method for processing IO commands according to the first aspect of the present application, a ninth method for processing IO commands according to the first aspect of the present application is provided, wherein multiple data units provided by one or more physical pages indicated by a physical address accessed by a single programming command have continuous unified addresses in a unified address space corresponding to the physical address.

[0028] According to the eighth or ninth method for processing IO commands according to the first aspect of the present application, a tenth method for processing IO commands according to the first aspect of the present application is provided, wherein the bits describing the word lines of the physical address come from the small block number of the unified address corresponding to the physical address.

[0029] According to the tenth method for processing IO commands according to the first aspect of the present application, there is provided an eleventh method for processing IO commands according to the first aspect of the present application, wherein the bits describing the word line of the physical address also include specified high bits of the data unit number from the unified address corresponding to the physical address.

[0030] According to one of the fourth to eleventh methods of processing IO commands according to the first aspect of the present application, a twelfth method of processing IO commands according to the first aspect of the present application is provided, wherein the specified high bits of the physical address are the physical block number, which comes from the specified high bits of the unified address corresponding to the physical address.

[0031] According to one of the fourth to twelfth methods for processing IO commands in the first aspect of the present application, a thirteenth method for processing IO commands in the first aspect of the present application is provided, which also includes: obtaining a physical address according to the unified address by calculation, obtaining a physical block address of the physical address according to the specified high bits of the obtained unified address, obtaining the data unit number part of the physical address according to the specified low bits of the unified address, obtaining the bits describing the parallel units of the physical address according to the specified high bits of the data unit number of the unified address, and obtaining the bits describing the word lines of the physical address according to the small block number of the unified address.

[0032] According to the thirteenth method for processing IO commands according to the first aspect of the present application, there is provided a fourteenth method for processing IO commands according to the first aspect of the present application, which also includes: obtaining bits describing the physical page index of the physical address based on the bits between the specified high bit and the specified low bit of the data unit number of the unified address, wherein the physical page index is used to describe the storage unit type and / or plane.

[0033] According to one of the first to fourteenth methods of processing IO commands according to the first aspect of the present application, a fifteenth method of processing IO commands according to the first aspect of the present application is provided, wherein the data unit indexed by the physical address corresponding to one or more unified addresses of the unified address space is a faulty data unit, and the faulty data unit is provided by a bad block of the storage medium.

[0034] According to the fifteenth method for processing IO commands according to the first aspect of the present application, a sixteenth method for processing IO commands according to the first aspect of the present application is provided, wherein the logical address of the logical address space will not be mapped to the unified address of the unified address space corresponding to the faulty data unit.

[0035] According to the fifteenth or sixteenth method for processing IO commands according to the first aspect of the present application, there is provided a seventeenth method for processing IO commands according to the first aspect of the present application, wherein a reverse mapping table is stored for data units indexed by physical addresses corresponding to one or more unified addresses of a unified address space, and the reverse mapping table records the logical addresses of data stored in small blocks including the data unit.

[0036] According to the seventeenth method for processing IO commands according to the first aspect of the present application, there is provided an eighteenth method for processing IO commands according to the first aspect of the present application, wherein the data unit storing the reverse mapping table has a specified data unit number within the small block.

[0037] According to one of the fifteenth to eighteenth methods for processing IO commands of the first aspect of the present application, a nineteenth method for processing IO commands according to the first aspect of the present application is provided, wherein a data unit indexed by a physical address corresponding to one or more unified addresses of a unified address space stores verification data, and the verification data is verification data calculated from user data of a small block including the data unit.

[0038] According to the second aspect of the present application, a first storage device according to the second aspect of the present application is provided, comprising a control component and a non-volatile storage medium, wherein the control component executes one of the first to nineteenth methods of processing IO commands according to the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0040] Figure 1 is a block diagram of a solid-state storage device in the related art;

[0041] Figure 2 A schematic diagram of the bulk is shown;

[0042] Figure 3A A unified address space constructed with small blocks according to an embodiment of the present application is shown;

[0043] Figure 3B A schematic diagram of a small block according to an embodiment of the present application is shown;

[0044] Figure 4 A schematic diagram showing mapping of small blocks to large blocks according to an embodiment of the present application is shown;

[0045] Figure 5A A schematic diagram showing mapping of small blocks to large blocks according to another embodiment of the present application is shown;

[0046] Figure 5B is a schematic diagram of mapping small blocks and large blocks according to yet another embodiment of the present application;

[0047] Figure 6 A schematic diagram showing mapping of small blocks to large blocks according to still another embodiment of the present application is shown;

[0048] Fig. 7A A schematic diagram showing conversion from a unified address to a physical address according to an embodiment of the present application is shown;

[0049] Figure 7BA flowchart of mapping a unified address to a physical address according to an embodiment of the present application is shown;

[0050] Fig. 8A A schematic diagram showing a small block according to still another embodiment of the present application;

[0051] Figure 8B A schematic diagram showing mapping of small blocks to large blocks according to still another embodiment of the present application is shown;

[0052] Fig.9A A flowchart of processing a read command according to an embodiment of the present application is shown;

[0053] Fig. 9B A flowchart of processing a write command according to an embodiment of the present application is shown; and

[0054] Fig. 9C A flowchart for processing a read command according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0055] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0056] Figure 3A A unified address space constructed with small blocks according to an embodiment of the present application is shown.

[0057] According to an embodiment of the present application, a storage device displays a logical address space to provide storage capabilities. When accessing the storage device with a logical address, the logical address is converted by the FTL into a unified address of the unified address space, and the storage device converts the unified address into a physical address describing a storage unit of the NVM chip, and uses the physical address to issue an IO command to the NVM chip.

[0058] The addresses of the logical address space are called logical addresses (denoted as LBA 0, LBA 1, ... LBAm). The logical address space is composed of, for example, continuous available logical addresses. Accessing the logical address space composed of continuous addresses is simple, and the user does not have to consider problems such as address space holes. Each logical address in the logical address space is available, and the user does not have to consider the problem of unavailable storage units in the address space. Optionally, the logical address space also includes some holes to provide intervals for partitions or other purposes. Each unit of the logical address space (the smallest continuous space described by the logical address) is, for example, 512 bytes, 2KB, 4KB or other values.

[0059] The address of the unified address space is called a unified address. The unified address space is filled with storage space provided by multiple small blocks (recorded as small block 0, small block 1, small block 2, ... small block n). Each small block has a specified size and occupies a certain position in the unified address space. Therefore, according to the number of the small block, the unified address of its unified address space can be calculated. The small block includes multiple data units (DU). A data unit (DU) is a storage space directly provided by a word line or a physical page of an NVM chip with a specified size of, for example, 4KB. Typically, a physical page includes multiple (for example, 4) data units (DU). The multiple data units included in the small block come from multiple logical units, so that the data units of the small block from different logical units can be accessed in parallel. There are holes in the unified address space, and some of the addresses indicate data units that are faulty and cannot be used. For example, the NVM chip includes bad physical blocks that cannot be used, and the data units contained in the physical pages of these physical blocks are also used to construct small blocks. The information of the bad blocks is recorded in the small block or elsewhere in the storage device to identify which data units of the small block are unavailable. In the process of mapping the logical address to the unified address through the FTL, it is avoided to map the logical address to the unified address provided by the unavailable data unit, so as to eliminate the inconvenience caused by the address hole of the unified address space to the use of the storage device.

[0060] The small blocks and data units have configurable specified sizes. For example, the size of the data unit is configured, and the number of data units contained in the small blocks is configured. However, the unified address space does not need to describe the configuration of the storage unit of the storage device (for example, the number of logical units, the number of physical blocks, the storage capacity of the physical blocks, the number of word lines, the number of physical pages in the word lines, the number of physical pages, the storage capacity of the physical pages, the number of bits stored in each storage unit (called the type of storage unit), etc.), nor does it need to describe the way in which the control component of the storage device couples the NVM chip (the number of channels used, the number of chips and chip select signals (CE) coupled on the channels, etc.), so that for different storage devices, there is no need to modify the FTL to provide a mapping from the logical address space to the unified address space. For example, storage device A uses a larger capacity NVM chip than storage device B, each physical block of which has more word lines (physical pages), and each storage unit stores a larger number of bits. In the unified address space, only the larger unified address space provided by the larger number of small blocks is presented to the FTL. Therefore, when managing the NVM chips through the FTL, there is no need to change the FTL for different configurations of the storage units and different organizations of the NVM chips in the storage device.

[0061] Continue to view Figure 3A, each address in the unified address space is directly mapped (one-to-one mapping) to the physical address space. The address of the physical address space is called the physical address, which is provided by each NVM chip and is an address acceptable to the NVM chip for accessing its physical block, word line, physical page, etc. The physical address also includes, for example, a portion for indicating the channel, chip select signal, and logic unit of the coupled NVM chip. Since the unified address space is directly mapped to the physical address space, the address of the unified address space is converted to the address of the physical address space according to the specified calculation process. Accordingly, the mapping from the unified address space to the physical address space is called resolvable, without the need to use a lookup table to obtain the physical address based on the unified address.

[0062] The physical address space is provided by the NVM chip of the storage device. For a specific storage device, the NVM chip on it provides the physical address space. There are holes in the physical address space. Some physical blocks may not be used, some channels may not be coupled to the NVM chip, and the number of channels may not be an integer power of 2. The physical addresses where the holes in the physical address space are located are also mapped to the unified address space, and the unified address space also has holes.

[0063] Figure 3B A schematic diagram of a small block according to an embodiment of the present application is shown.

[0064] Figure 3B The storage device includes n+1 small blocks, each of which includes 1024 data units (DU). The storage device also includes 8 channels (indicated by CH0, CH1, ... CH7, respectively), each channel includes 8 chip select signals (indicated by CE0, CE1, ... and CE7, respectively), and each chip select signal also indicates 2 logical units (indicated by LUN0 and LUN1, respectively), so that the storage device has a total of 128 logical units. Each storage unit of the NVM chip of the storage device stores 1 bit of information (SLC medium, SingleLevelperCe ll, 1 level per unit), and each physical page includes 4 data units (DU).

[0065] according to Figure 3B In the embodiment of the present invention, each small block includes 8 data units (DU) provided by each of the 128 logical units. As an example, the 8 data units (DU) provided by each logical unit for the same small block come from two physical pages.

[0066] Figure 3BThe mapping method of small blocks of the unified address space to the physical address space is also shown. The first 4 data units (DU, numbered 0-3) of small block 0 come from physical page P0 of LUN 0 of channel 0 and CE0, and the next 4 data units (DU, numbered 4-7) come from physical page P0 of LUN 0 of channel 1 and CE 0... Data units 508-511 of small block 0 come from physical page P0 of LUN 1 of channel 7 and CE 7. Next, data units 512-515 of the small block come from physical page P1 of LUN 0 of channel 0 and CE0, and the next 4 data units (DU, numbered 516-519) come from physical page P1 of LUN 0 of channel 1 and CE 0,... The last 4 data units (DU, numbered 1020-1023) of small block 0 come from physical page P1 of LUN 1 of channel 7 and CE 7.

[0067] The first 4 data units (DU, numbered 0-3) of small block 1 come from physical page P2 of LUN 0 of channel 0 and CE0, the next 4 data units (DU, numbered 4-7) come from physical page P2 of LUN 0 of channel 1 and CE 0... The last 4 data units (DU, numbered 1020-1023) of small block 1 come from physical page P2 of LUN 1 of channel 7 and CE 7. The first 4 data units (DU, numbered 0-3) of small block n come from physical page P2n of LUN 0 of channel 0 and CE0, the next 4 data units (DU, numbered 4-7) come from physical page P2n of LUN 0 of channel 1 and CE 0... The last 4 data units (DU, numbered 1020-1023) of small block n come from physical page P2n+1 of LUN 1 of channel 7 and CE 7.

[0068] Continue to view Figure 3B , LUN 0 of channel 1 (CH1) and CE0 of the storage device fails, so that the data units provided by the logical unit for each small block are unavailable, as indicated by the horizontal dashed line in 3B. However, this part of the data unit has a physical address, a unified address, and occupies part of the unified address space.

[0069] Each small block specifies the data unit (for example, see Figure 3B , the last data unit, numbered 1023) stores metadata such as a reverse mapping table. The metadata is used to describe the small block, for example, the reverse mapping table records the logical address of the data recorded in each data unit of the small block.

[0070] According to an embodiment of the present application, each small block occupies a specified size in a unified address space. The small block includes multiple data units, one or more of which may be unavailable. Each data unit of the small block is directly mapped to the physical address of the NVM chip in a resolvable manner. Each logical unit provides multiple data units (DU) to the small block, and these multiple data units provided to a single small block may come from one or more pages of the LUN. In an optional embodiment, the multiple data units with continuous unified addresses provided by the LUN to the small block come from the same physical page of the LUN, so that when the address of the unified address space is allocated to the data, the data is set to the same physical page through the allocated continuous address, so that in a programming operation of the physical page, the data is written to the physical page, so that the data is reliably stored in the NVM chip as soon as possible. In contrast, if the continuous multiple data units allocated to the data are provided by different physical pages, a separate programming command is required for each physical page to write data to it, so that more programming commands are required to persist the data written to these data units, and the time for the data to be written to the NVM chip is inappropriately extended.

[0071] Figure 4 A schematic diagram showing the mapping of small blocks to large blocks according to an embodiment of the present application is shown.

[0072] As an example, the storage device includes 16 logical units (respectively recorded as LUN 0, LUN 1, ..., LUN 15), each logical unit has a single plane, and each storage unit records 1 bit of information (SLC, single-level unit). Figure 4 Physical block 0 of each logical unit is shown. Physical pages of a logical unit are indicated by reference numeral Pa-b, where a indicates the logical unit number providing the physical page and b indicates the physical page address within physical block 0 providing the physical page.

[0073] The small block includes 64 data units, and each logical unit provides 4 data units with consecutive addresses for the small block. For example, the physical page P0-0 provides 4 data units (numbered 0-3) for the small block 0, the physical page P1-0 provides 4 data units (numbered 4-7) for the small block 0, and the physical page P15-0 provides 4 data units (numbered 60-63) for the small block 0.

[0074] Figure 4 In FIG. 1 , data units of physical page P0-1 are used to construct small block 1 (not shown). Data units of physical page P0-2 are used to construct small block 2. Data units of physical page Px-2 of each logical unit are used to construct small block 2.

[0075] Thus, according to an embodiment of the present application, data units with continuous uniform addresses in a small block are mapped to multiple logical units, which enables access to continuous data units of the small block to be mapped to access to multiple logical units, which can be processed in parallel, thus speeding up data access.

[0076] and, Figure 4 The way in which each logical unit provides physical pages for a small block also makes the mapping from the unified address space to the physical address space resolvable. Taking data units as units, each data unit of a small block is provided by each logical unit sorted by the logical unit number at a time, and each logical unit provides physical pages for the small block in the order of the physical page number (each physical page provides 4 data units). After each logical unit provides a physical page to a small block, the next logical unit will provide another physical page. Thus, the data units corresponding to each unified address in the unified address space are represented by Figure 4 The logical units in the are provided sequentially from left to right (increasing logical unit numbers), and within the units, from top to bottom (increasing physical page numbers).

[0077] It can be understood that for a storage device with a specified configuration of the NVM chip, the small blocks may have different sizes (including different numbers of data units). For example, each of the logical units provides 2 physical pages to the small block, so that the small block includes 128 data units; or the storage device includes 16 logical units, and each 8 logical units are used as a group to provide physical pages to the small block, and each small block includes 32 data units provided by 8 physical pages.

[0078] Figure 5A A schematic diagram showing the mapping of small blocks to large blocks according to yet another embodiment of the present application is shown.

[0079] As an example, the storage device includes 16 logical units (respectively recorded as LUN 0, LUN 1 ... LUN 15), each logical unit has a single plane, and each storage unit records 3 bits of information (TL C, Triple Level per Cell, triple level unit). Figure 5A Physical block 0 of each logical unit is shown. Physical pages of a logical unit are indicated by reference numeral Pa-b, where a indicates the logical unit number providing the physical page and b indicates the physical page address within physical block 0 providing the physical page. Figure 5A In the example, physical pages P0-0, P0-1 and P0-2 belong to the same word line, and the NVM chip accepts a One-ShotProgram command to write data to multiple physical pages P0-0, P0-1 and P0-2 of the same word line according to a single command.

[0080] The small block includes 192 data units, and each logical unit provides 12 data units with consecutive addresses belonging to 3 physical pages for the small block. As an example, physical page P0-0 provides 4 data units (numbered 0-3) for small block 0, physical page P0-1 provides 4 data units (numbered 4-7) for small block 0, and physical page P0-2 provides 4 data units (numbered 8-11) for small block 0. According to the embodiment of FIG. 5, in the process of mapping physical pages to a unified address space, multiple physical pages belonging to the same word line (or written as a whole in a complete programming command) are preferentially provided to the small block, so that in the process of writing continuous data units of the small block, all data for a complete programming command can be obtained as soon as possible, so that the data can be written into the NVM chip as soon as possible, reducing the time that the data is waiting to be written into the NVM chip.

[0081] After multiple physical pages belonging to the same word line (or written as a whole in a complete program command) of a logical unit (eg, LUN 0) are mapped to the unified address space, the physical pages obtained from the next logical unit (eg, LUN 1) are then mapped to the unified address space.

[0082] Figure 5B It is a schematic diagram of mapping small blocks and large blocks according to yet another embodiment of the present application.

[0083] Figure 5B The storage devices shown are Figure 5A The storage device shown has basically the same configuration, but its NV M chip accepts (2-8) programming commands, where the same word line provides 3 physical pages (e.g., P0-0, P0-1 and P0-2). To program the word line, two programming commands are provided to the word line in succession, the former programming command writes data to physical page P0-0, and the latter programming command writes data to physical page P0-1 and physical page P0-2.

[0084] The small block includes 192 data units, and each logical unit provides 12 data units belonging to 3 physical pages for the small block. Among the 12 data units, the first 4 data units have continuous unified addresses, and the last 8 data units have continuous unified addresses, but the unified addresses of the first 4 data units and the last 8 data units do not have to be continuous. As an example, physical page P0-0 provides 4 data units (numbered 0-3) for small block 0, and then physical page P1-0 of LUN1, which is different from the logical unit where physical page P0-0 is located, provides 4 data units (numbered 4-7) for small block 0. After each logical unit provides data units for the small block, physical page P0-1 and physical page P0-2 of LUN 0 provide 8 data units (numbered 64-67 and 68-71) for small block 0. Thus, after receiving the data to be written to data unit 0-3, the first part of the "2-8 programming command" is issued to physical page P0-0 to write data unit 0-3, and after receiving the data to be written to data unit 64-71, the second part of the "2-8 programming command" is issued to physical pages P0-1 and P0-2 to write data unit 64-71.

[0085] Figure 6 A schematic diagram showing mapping of small blocks to large blocks according to still another embodiment of the present application is shown.

[0086] For example, the storage device includes n logical units (respectively denoted as LUN 0, LUN 1, ... LUN n-1), each logical unit has two planes (respectively denoted as Plane 0 and Plane 1), and each storage unit records 3 bits of information (TLC). Figure 6 Physical block 0 of each logical unit is shown. Physical pages of logical units are indicated by reference numerals Pa-bc, where a indicates the logical unit number providing the physical page, b indicates the plane number providing the physical page, and c indicates the physical page address within physical block 0 providing the physical page. Figure 6 In the example of FIG. 1 , the NVM chip accepts a One-ShotProgram command to write data to multiple physical pages (P0-0-0, P0-1-0, P0-0-1, P0-1-1, P0-0-2, and P0-1-2) according to a single command.

[0087] The small block includes 24*n data units, and each logical unit provides 24 data units with consecutive addresses in 6 physical pages belonging to 2 planes for the small block. As an example, physical page P0-0-0 provides 4 data units (numbered 0-3) for small block 0, physical page P0-1-0 provides 4 data units (numbered 4-7) for small block 0...physical page P0-1-2 provides 4 data units (numbered 20-23) for small block 0. These 6 physical pages are written as a whole in one multi-plane complete programming command.

[0088] according to Figure 6 In an embodiment, in the process of mapping physical pages to a unified address space, multiple physical pages that can be written as a whole in a multi-plane complete programming command are preferentially provided to small blocks, so that in the process of writing continuous data units of the small blocks, all data for a multi-plane complete programming command can be obtained as soon as possible, so that the data can be written into the NVM chip as soon as possible, reducing the time that data has to wait to be written into the NVM chip.

[0089] After mapping multiple physical pages of a logical unit (e.g., LUN 0) that can be written as a whole in a multi-plane complete programming command to a unified address space, the multiple physical pages that can be written as a whole in a multi-plane complete programming command are obtained from the next logical unit (e.g., LUN 1) and mapped to the unified address space.

[0090] Fig. 7A A schematic diagram of unified address to physical address conversion according to an embodiment of the present application is shown.

[0091] For a specified storage device, its unified address has a specified width (e.g., 32 bits) for describing a unified address space. As an example, the unified address includes multiple fields, such as a data unit (DU) number, a small block number, and / or a large block number. The data unit number of the unified address is used to index a data unit (DU) within a small block. The small block number is used to index a small block of a storage device.

[0092] In one example, the unified address includes only the small block number and the data unit number. In another example, the unified address also includes the large block number in the high position. The large block number includes multiple bits, and the large block indexed by the large block number includes multiple small blocks. It can be understood that the term "large block" here refers to a group of small blocks, and its meaning can be the same as Figure 2 The same block as described can also be Figure 2 The chunks described are different.

[0093] The unified address is resolvably mapped to a physical address. The width of the physical address is the same or substantially the same as the unified address. As an example, the physical address received by the NVM chip does not need to include an index to the channel and / or CE, so that the physical address can have several bits less than the corresponding unified address, but the control component of the storage device needs these bits to address the channel and / or CE.

[0094] See also Fig. 7A As an example, the designated high bit (large block number portion) of the unified address is used as the physical block number of the physical address. After the small block number of the unified address is combined with the DU number, they are used to describe the bits of the word line (WL), LUN, CE, channel (CH), physical page index and data unit (DU) of the physical address in order from high to low. Optionally, the physical address also includes bits indicating the storage cell type and / or plane, and several bits of the unified address are used to describe the storage cell type and / or plane. Optionally, some bits of the physical page index are used to describe the plane and / or storage cell type.

[0095] The word line (WL) of the physical address can be used to describe the layer (Z-axis direction) that provides the storage unit in the 3D NAND flash memory. The storage unit type is used to describe the number of bits stored in each storage unit of the NVM chip (SLC, MLC, TLC or other). Logical units (LUNs), CEs, and / or channels (CHs) are collectively referred to as parallel units (PUs), so that the multiple bits after the small block number and DU number of the unified address are combined are used to describe the parallel units of the storage device.

[0096] According to an embodiment of the present application, in the physical address, the bits describing the word line (WL) and the bits describing the physical page index together describe the physical page of the NVM chip. For example, a physical block includes 384 or 512 physical pages, which need to be described by 9 bits. The number of physical pages may not be an integer power of 2.

[0097] Although the bits describing the word line (WL) and the bits describing the physical page index together describe the physical page of the NVM chip, the bits describing the word line and the bits describing the physical page index (and optionally the bits describing the storage cell type) are not adjacent to each other, and the bits describing the parallel unit (and optionally the bits describing the plane) are in between. This allows data units with continuous addresses to be allocated from a unified address space when allocating data units, and when writing data to small blocks of data units with continuous addresses, the distribution of physical pages carrying data can take into account the parallelism provided by multiple parallel units and allow multiple physical pages accessed by the same programming command to be filled with data as quickly as possible. The multiple physical pages accessed by the same programming command are called programming units. Some bits of the physical page index field (and optionally the bits describing the storage cell type) describe the programming unit.

[0098] A physical page includes multiple (e.g., 4) data units, and accordingly, the bits used to describe the data units in the physical address index the specified data units in the physical page. Thus, when the physical page includes 4 data units, the field used to describe the data unit (DU) in the physical address includes 2 bits (Log2(4)).

[0099] Figure 7B A flowchart of mapping a unified address to a physical address according to an embodiment of the present application is shown.

[0100] According to an embodiment of the present application, a unified address is obtained (710). The unified address comes from an IO command provided by the host, or the FTL of the storage device obtains the unified address according to the logical address provided by the host. It can still be understood that for a write command, the storage device allocates a unified address to which data is not written. The obtained unified address has a specified width (e.g., 32 bits).

[0101] The designated high bit of the unified address is used as the block number of the physical address (720). In one example, when the small block includes data units of all parallel units of the storage device, the large block number in the unified address is used as the block number of the physical address. In another example, the parallel units of the storage device are divided into two groups, and the small block includes data units provided by a group of parallel units. In this case, the large block number in the unified address is removed by one bit and used as the block number of the physical address, and the removed bit is used to describe the group of parallel units.

[0102] The other bits of the unified address are used to describe the word line, parallel unit, physical page index and data unit respectively. Specifically, the lowest n1 bits of the unified address are used as the offset within the physical page of the physical address (730) to describe the data unit within the physical page, where 2^n1 is the number of data units included in the physical page. The unified address is removed from the bits describing the large block number, and the part after the lowest n1 bits is also removed, and is recorded as R, and R%Nwl is used as the physical page index of the physical address (740), where Nwl is the number of physical pages in the word line. In some cases, the physical page address received by the NVM chip uniformly addresses the word line (WL) and the physical page index. In this case, the control unit also extracts the bit indicating the word line number and the bit indicating the physical page index from the generated physical address, and maps them to the uniformly addressed physical page.

[0103] (R / Nwl)%Np is used as the index of the parallel unit of the physical address (750), where Np is the number of parallel units of the storage device. Optionally, when the parallel units of the storage device are grouped and the small block includes data units provided by a group of parallel units, Np is the number of parallel units in each group. It can be understood that the parallel unit index includes bits for describing channels (CH), CE and / or logical units, and one or more bits of the parallel unit index are mapped to describe channels (CH), CE and / or logical units according to the configuration of the storage device. And the remaining bits of the unified address are used as bits in the physical address for describing word lines (WL) (760).

[0104] As another embodiment, in another configuration of a storage device, the large block number of the unified address is used as the block number of the physical address, and the small block number of the unified address (and optionally the specified high bit of the data unit number) is used as the word line index. The lowest n1 bits of the small block number of the unified address are used as the offset within the physical page of the physical address, which is used to describe the data unit within the physical page, where 2^n1 is the number of data units included in the physical page. The part of the data unit index of the unified address after removing the lowest n1 bits is recorded as R (if it exists, the part used as the word line index is also removed), and R%Nwl is used as the physical page index of the physical address, where Nwl is the number of physical pages in the word line. (R / Nwl)%Np is used as the index of the parallel unit of the physical address, where Np is the number of parallel units of the storage device.

[0105] As a specific example, the storage device includes 8 channels, each channel includes 2 CEs and 2 LUNs, each LUN includes 1200 physical blocks, each physical block includes 256 word lines (WLs), the storage unit type is TLC (each word line includes 3 physical pages), and each physical page provides 4 data units.

[0106] Each parallel unit provides 1 word line to a single small block, so that the small block includes 384 data units (DU), and thus 9 bits (low [8:0] bits) are used in the unified address to describe the data unit (DU) number in the small block. The unified address space includes 1200 large blocks, each large block includes 256 small blocks, so that the [16:9] bits of the unified address are the small block number, and the [27:17] bits are the large block number. Thus, the unified address has a total of 28 bits. In the unified address space, the 9 bits describing the data unit number indicate 384 data units, so that 128 address elements in this part of the space do not indicate data units and become holes, and the 11 bits of the large block number indicate 1200 physical blocks, so that 2048 elements in this part of the space indicate 1200 physical blocks, and 848 elements become holes.

[0107] To obtain a physical address from a unified address, the 11-bit large block number (bits [27:17]) of the unified address is used as the physical block number of the physical address, and the 8-bit small block number (bits [16:9]) of the unified address is used as the word line (WL) index of the physical address.

[0108] Since each physical page provides 4 data units, the lowest 2 bits of the unified address are used to describe the data unit (DU) in the physical page. The remainder of the lower [8:2] bits of the unified address divided by 3 (the type of storage unit is TLC, and the 3 bits stored in each storage unit come from 3 physical pages respectively) is used as the physical page index of the physical address (occupying 2 bits in the physical address). The remainder of the quotient of the lower [8:2] bits of the unified address divided by 3 and then divided by 32 is used as the parallel unit index of the physical address (where 1 bit describes CE, 1 bit describes LUN, and 3 bits describe channel CH).

[0109] Fig. 8A A schematic diagram of a block according to still another embodiment of the present application is shown.

[0110] Fig. 8A The storage device includes n+1 small blocks, each of which includes 1024 data units (DU). The storage device also includes 8 channels (indicated by CH0, CH1, ... CH7, respectively), each channel includes 8 chip select signals (indicated by CE0, CE1, ... and CE7, respectively), and each chip select signal also indicates 2 logical units (indicated by LUN0 and LUN1, respectively), so that the storage device has a total of 128 logical units. Each storage unit of the NVM chip of the storage device stores 1 bit of information (SLC medium), and each physical page includes 4 data units (DU). Each small block includes 8 data units (DU) provided by each of the 128 logical units. As an example, the 8 data units (DU) provided by each logical unit for the same small block come from two physical pages.

[0111] Small blocks include data units storing user data and data units storing mapping tables. Figure 3B Compared with the small block shown in FIG. 8 , the small block shown in FIG. 8 also includes a data unit for storing check data (provided by LUN1 of channels CH7 and CE7, indicated by the diagonal shadow from the upper right to the lower left). The check data of the small block is calculated based on other data stored in the small block, for example, the check data is obtained by XORing all other data stored in the small block. The data unit storing the check data is not mapped to the logical address space.

[0112] The designated data unit of each small block (for example, see FIG. 8 , the data unit numbered 1019) stores metadata such as a reverse mapping table. The metadata is used to describe the small block. For example, the reverse mapping table records the logical address of the data recorded in each data unit of the small block. The data units numbered 0-1018 of each small block are used to store user data. One or more data of the small block may be a faulty data unit.

[0113] Figure 8B A schematic diagram showing mapping of small blocks to large blocks according to still another embodiment of the present application is shown.

[0114] As an example, the storage device includes n logical units (respectively denoted as LUN 0, LUN 1, ... LUN n-1), each logical unit has two planes (respectively denoted as Plane 0 and Plane 1), and each storage unit records 3 bits of information (TLC). FIG8 shows the physical block 0 of each logical unit. The physical page of the logical unit is indicated by the reference numeral Pa-bc, where a indicates the logical unit number providing the physical page, b indicates the plane number providing the physical page, and c indicates the physical page address within the physical block 0 providing the physical page. Figure 8B In the example of FIG. 1 , the NVM chip accepts a One-ShotProgram command to write data to multiple physical pages (P0-0-0, P0-1-0, P0-0-1, P0-1-1, P0-0-2, and P0-1-2) according to a single command.

[0115] The small block includes 24*(n+1) data units, and each logical unit provides 24 data units with consecutive addresses of 6 physical pages belonging to 2 planes for the small block. As an example, physical page P0-0-0 provides 4 data units (numbered 0-3) for small block 0, physical page P0-1-0 provides 4 data units (numbered 4-7) for small block 0...physical page P0-1-2 provides 4 data units (numbered 20-23) for small block 0. These 6 physical pages are written as a whole in one multi-plane full programming command.

[0116] The 24 data units provided by LUN n for the small block are used to store the check data of the small block (the physical page with diagonal shadow provides the data unit for storing the check data for the small block). The check data for the small block is generated according to other data written to the small block.

[0117] According to an optional implementation, the check data of each small block of the storage device is stored in a data unit provided by a different LUN. For example, the small block number is modulo the number of LUNs providing data units for the small block, and the result is used as the number of the LUN where the data unit for storing the check data provided to the small block is located.

[0118] Fig.9A A flowchart for processing a read command according to an embodiment of the present application is shown.

[0119] As an example, the host provides a read command indicating a logical address to the storage device, and the storage device obtains the read command indicating the logical address (910). According to the logical address indicated by the read command, the FTL table is queried to obtain a unified address corresponding to the logical address (915). The physical address is calculated based on the unified address (920). For the specified storage device, the mapping relationship of converting the unified address to the physical address is determined and resolvable. According to the physical address, a read command is issued to the NVM chip (925), and data provided by the NVM chip in response to the read command is obtained (930) as a response to the read command indicating the logical address in step 910.

[0120] Fig. 9B A flowchart for processing a write command according to an embodiment of the present application is shown.

[0121] As an example, the host provides a write command indicating a logical address to the storage device. The storage device obtains the write command indicating the logical address (940). An available unified address is obtained (945), which indicates a data unit to which data has not yet been written. A physical address is calculated based on the obtained unified address (950). The obtained unified address is recorded in the FTL table in association with the logical address of the write command. A programming command is sent to the NVM chip based on the obtained physical address (955) to record the data of the write command obtained in step 940 in the NVM chip.

[0122] Fig. 9C A flowchart for processing a read command according to another embodiment of the present application is shown.

[0123] As an example, the host provides a read command indicating a unified address to the storage device. The storage device obtains the read command indicating the unified address (960). The physical address is calculated based on the unified address (965) without querying the FTL. For large-capacity storage devices, the size of the FTL table is huge (occupying several GB or even more storage space), and the query of the large-size FTL table is also relatively slow. Fig. 9C In the embodiment, the conversion from the unified address to the physical address is resolvable, thereby eliminating the process of querying the FTL table, and processing the read command more quickly. According to the physical address, a read command is issued to the NVM chip (970), and data provided by the NVM chip in response to the read command is obtained (975) as a response to the read command indicating the unified address in step 950.

[0124] According to an embodiment of the present application, a storage device is also provided, which includes a controller and a non-volatile memory chip, wherein the controller executes any one of the processing methods provided in the embodiments of the present application.

[0125] According to an embodiment of the present application, there is also provided a program stored on a readable medium, which, when executed by a controller of a storage device, enables the storage device to execute any one of the processing methods provided according to the embodiment of the present application.

[0126] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for processing an IO command, comprising: Obtaining a read command indicating a logical address; Use the logical address to query the FTL table to obtain a unified address; Calculate a physical address based on the unified address; Using the physical address to access the storage medium to obtain the data to be accessed by the read command; The unified address is an element of the unified address space, which is composed of storage space provided by multiple small blocks. The unified address of the small block in the unified address space can be calculated according to the number of the small block; the small block includes multiple data units, and the data unit is a storage space of a specified size provided by the word line or physical page of the NVM chip.

2. A method for processing an IO command, comprising: Get a write command indicating a logical address; Allocating a unified address that indexes a data unit to which data has not yet been written; Calculate a physical address based on the unified address; Using the physical address to access the storage medium to write the data to be written by the write command; The unified address is an element of the unified address space, which is composed of storage space provided by multiple small blocks. The unified address of the small block in the unified address space can be calculated according to the number of the small block; the small block includes multiple data units, and the data unit is a storage space of a specified size provided by the word line or physical page of the NVM chip.

3. A method for processing an IO command, comprising: Get a read command indicating a unified address; Calculate a physical address based on the unified address; Using the physical address to access the storage medium to obtain the data to be accessed by the read command; The unified address is an element of the unified address space, which is composed of storage space provided by multiple small blocks. The unified address of the small block in the unified address space can be calculated according to the number of the small block; the small block includes multiple data units, and the data unit is a storage space of a specified size provided by the word line or physical page of the NVM chip.

4. The method according to any one of claims 1 to 3, wherein: The number of a small block has a linear relationship with the unified address of the small block in the unified address space.

5. The method according to claim 4, wherein The physical address includes bits describing a word line and bits describing a physical page index, wherein the bits describing the word line and the bits describing the physical page index together address a physical page of the storage medium; The unified address includes a small block number and a data unit number, wherein the data unit number indicates a data unit within the small block represented by the small block number; The bits describing the word line are separated from the bits describing the physical page index in the physical address by the bits describing the parallel unit; and The bits describing the parallel unit of the physical address come from the designated high bits of the data unit number of the unified address corresponding to the physical address.

6. The method according to claim 5, wherein The multiple data units provided by one or more physical pages indicated by the physical address accessed by a single program command have continuous unified addresses in the unified address space corresponding to the physical address.

7. The method according to claim 6, further comprising: To calculate the physical address based on the unified address, the physical block address of the physical address is obtained according to the specified high bits of the obtained unified address, the data unit number part of the physical address is obtained according to the specified low bits of the unified address, the bits describing the parallel units of the physical address are obtained according to the specified high bits of the data unit number of the unified address, and the bits describing the word lines of the physical address are obtained according to the small block number of the unified address.

8. The method according to claim 7, further comprising: The bits describing the physical page index of the physical address are obtained according to the bits between the specified high bit and the specified low bit of the data unit number of the unified address, wherein the physical page index is used to describe the storage unit type and / or plane.

9. The method according to claim 4, wherein The data unit indexed by the physical address corresponding to one or more unified addresses in the unified address space is a faulty data unit, and the faulty data unit is provided by a bad block of the storage medium.

10. A storage device, comprising a control component and a non-volatile storage medium, wherein the control component executes one of the methods for processing IO commands according to claims 1-9.

Images