Method and apparatus for interpolation

Abstract

A method for interpolating attribute values of an image grid can include determining a root value of an attribute of a root node located at a center of the image grid, precomputing metadata for a plurality of child nodes of one or more levels based on one or more gradients of the attribute, and deriving an attribute value for each child node of each level based on a corresponding root value and the metadata of the level of each child node, wherein each child node can serve as a root node of a next level. The image grid can have a plurality of outer cells arranged radially around a center cell, and the root node can be located in the center cell.

Description

Technical Field

[0001] This disclosure relates generally to interpolation, and more specifically to methods and apparatus for efficient interpolation of nodes in a grid, such as an image grid. Background Technology

[0002] Interpolation is the process of determining the attribute values ​​of unknown data points located between known data points. For example, in image processing, interpolation can be used to find intermediate values ​​of attributes for a set of pixels that are spatially adjacent and located within primitives, which are the basic geometric units used to create larger images. Interpolators consume resources such as power and area on integrated circuits. The high cost and power consumption of traditional interpolators limit throughput or the speed at which pixels are rendered. However, displays continue to offer higher resolutions, use more primitives, and / or operate on larger image domains compared to the conventional tile domain, which is a subset of the image. Furthermore, downstream image processing devices (such as execution units) that use and / or transform data from the interpolator continue to improve. This can create a mismatch between the bandwidth of the interpolator and the bandwidth of the downstream unit, potentially leading to low utilization of the downstream unit and / or low frame rates on rendering devices. Therefore, there is a need for interpolators that can operate with higher efficiency and / or throughput. Summary of the Invention

[0003] A method for interpolating attribute values ​​of an image grid, the method comprising: determining a first-level root value of an attribute at a first-level root node located at the center of the image grid; calculating first-level metadata based on a first gradient of the attribute in a first direction and a second gradient of the attribute in a second direction; and deriving first-level sub-values ​​of attributes of two or more first-level child nodes in the image grid based on the first-level root value and the first-level metadata, wherein the two or more first-level child nodes are arranged radially around the first-level root node in the image grid. The method may further comprise: using one of the first-level child nodes and its corresponding first-level sub-value as a second-level root node and a second-level root value of a cell in the image grid, wherein the root node of the cell is located at the center of the cell; calculating second-level metadata based on the first gradient and the second gradient; and deriving second-level sub-values ​​of attributes of two or more second-level child nodes in the cell based on the second-level root value and the second-level metadata, wherein the two or more second-level child nodes are arranged radially around the second-level root node in the cell.

[0004] Each first-level child node can be offset symmetrically from the first-level root node in both the first and second directions. Each first-level child node can be offset by approximately zero or approximately the same distance from the first-level root node in both the first and second directions. The image mesh can include a 3x3 cell array with a center cell and eight outer cells. Two or more first-level child nodes can include eight first-level child nodes. The first-level root node can be located at the center of the center cell, and each first-level child node can be located at the center of one of the outer cells. First-level metadata can include incremental values ​​of the offset attribute in the first and second directions. The value of the first parameter A can be based on a first gradient, and the value of the second parameter B can be based on a second gradient. First-level metadata can include values ​​A, B, A+B, and AB. The first parameter A can be based on the first gradient, the second parameter B can be based on the second gradient, the image mesh includes a 3x3 cell array, and the first-level metadata can include values ​​3A, 3B, 3(A+B), and 3(AB), while second-level metadata can include values ​​A, B, A+B, and AB. The first-level metadata can be calculated based on plane equations. The plane equation can have the form P(x,y) = A*(x-Seed_X) + B*(y-Seed_Y) + C, where P can be parameters of a two-dimensional surface that can be interpolated at each location (x,y), where x can be the distance in the x-direction, y can be the distance in the y-direction, A can be the gradient per pixel (or other cell) in the x-direction, B can be the gradient per pixel (or other cell) in the y-direction, and C can be the value of P at location (Seed_X,Seed_Y). Deriving first-level sub-values ​​can include adding one or more first-level metadata to the first-level root value. The first-level root node and each first-level child node can correspond to a pixel. The first-level root node and each first-level child node can correspond to a sample. The method can also include rasterizing the image in response to attribute values. Attributes can include a first value indicating whether a node can be inside a primitive and a second value indicating whether a node can be outside a primitive.

[0005] A method for interpolating attribute values ​​of an image mesh may include: determining the root value of an attribute of a root node located at the center of the image mesh; pre-computing metadata of multiple child nodes in one or more levels based on one or more gradients of the attribute; and deriving the attribute value of each child node in each level based on the corresponding root value and metadata of each child node's level; wherein each child node may serve as the root node of the next level. The image mesh may have multiple outer cells arranged radially around a central cell, and the root node may be located in the central cell. The root node may be located in a first cell having one or more additional nodes, and the method may further include: determining the attribute values ​​of one or more additional nodes in the first cell; and deriving the attribute values ​​of additional child nodes corresponding to each additional node in the first cell at each level, wherein the attribute values ​​of each additional child node may be derived based on the attribute values ​​of the corresponding additional nodes in the first cell and the metadata of the corresponding level. The attribute values ​​of the additional child nodes may be derived using a separate hierarchical tree with respect to each node in the first cell. The first cell may be a pixel, and each node in the first cell may be a sample. Samples in pixels may be used for multisample anti-aliasing (MSAA).

[0006] A system for interpolating attribute values ​​of an image grid may include: a root unit configured to determine the root value of an attribute at the root node located at the center of the image grid; a metadata unit configured to pre-compute metadata for multiple child nodes at one or more levels based on one or more parameters of the attribute; and a tree of one or more logical stages, the one or more logical stages being coupled to the root unit and the metadata unit and configured to derive the attribute value of each child node at each level based on the corresponding root value and metadata of each child node's level. One or more of the logical stages may include combinational logic with two-input adders, arranged to add the root value of the attribute to the metadata of the multiple child nodes. The system may also include a redirection unit coupled between the root unit and the tree, and configured to rearrange the orientation of samples from the root unit to the tree based on an operating mode. The logical stages may be configured to process multiple samples in a multi-sample operating mode. The image grid can be a first subgrid of a larger image grid, and the system may further include: a second root cell configured to determine a second root value of a second attribute of a second root node located at the center of the second subgrid of the larger image grid; a second metadata cell configured to pre-compute second metadata of multiple second child nodes in one or more levels based on one or more parameters of the second attribute; and a second tree of one or more logical stages coupled to the second root cell and the second metadata cell, and configured to derive the second attribute value of each second child node at each level based on the corresponding second root value and second metadata of each level of the second child node. The second root cell, the second tree, and the second metadata cell may be configured to selectively use attributes of the first subgrid as second attributes of the second subgrid. The attributes of the first subgrid and the second subgrid may be used for different primitives. The system may also include one or more additional logical stages coupled between the root cell and the tree in a serial hybrid configuration, wherein the one or more additional logical stages use an interpolation technique substantially different from the tree of the one or more logical stages. The system may be implemented in hardware, software, or a combination thereof. Hardware may include integrated circuits.

[0007] An apparatus for interpolating attribute values ​​of an image mesh may include a tree of one or more logical stages configured to derive attribute values ​​of a plurality of child nodes surrounding a root node at the center of one or more levels, based on the corresponding attribute value at the root node and metadata of each of one or more levels. The apparatus may also include a metadata unit coupled to the tree of one or more logical stages and configured to pre-compute metadata of a plurality of child nodes of each of one or more levels based on one or more parameters of the attribute. The apparatus may also include a root unit coupled to the tree of one or more logical stages and configured to determine the root value of the attribute of the root node in the image mesh. One or more of the logical stages may include combinational logic having a two-input adder, arranged to add the root value of the attribute to the metadata of the plurality of child nodes. The apparatus may also include one or more additional logical stages coupled to the tree in a serial hybrid configuration, wherein the one or more additional logical stages use an interpolation technique substantially different from that of the tree of one or more logical stages. The tree of one or more logical stages may be implemented in an integrated circuit. Other and / or additional configurations are contemplated. Attached Figure Description

[0008] The accompanying drawings are not necessarily drawn to scale, and for illustrative purposes throughout the drawings, elements with similar structures or functions are generally indicated by similar reference numerals. The drawings are intended only to facilitate the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. The drawings, together with the specification, illustrate exemplary embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0009] Figure 1 This illustrates a common technique for interpolating attribute values ​​of a pixel grid.

[0010] Figure 2 An embodiment of a method for interpolating attribute values ​​of a pixel grid according to the principles of this disclosure is shown.

[0011] Figure 3 This is a flowchart of a method for interpolating the attribute values ​​of a pixel grid based on the principles of this disclosure.

[0012] Figure 4 An example embodiment of a method for interpolating attribute values ​​using planar equations, based on the principles of this disclosure, is shown.

[0013] Figure 5 An example embodiment of a method for interpolation using boundary equations for rasterization, based on the principles of this disclosure, is shown.

[0014] Figure 6 An example embodiment of a method for interpolating metadata at adjacent levels by relating it to a scaling factor is shown.

[0015] Figure 7 This is a block diagram illustrating the structure and data flow microarchitecture of an embodiment of a hierarchical interpolation system according to the principles of this disclosure.

[0016] Figure 8 This is a block diagram illustrating the microarchitecture of the structure and data flow of an embodiment of a multi-sample hierarchical interpolation system according to the principles of this disclosure.

[0017] Figures 9 to 11 An embodiment of a grid that can be subdivided according to the principles of this disclosure is shown.

[0018] Figure 12 This is a block diagram illustrating the microarchitecture of the structure and data flow of an embodiment of a multi-attribute hierarchical interpolation system according to the principles of this disclosure.

[0019] Figure 13 An embodiment of imaging device 204 is shown, and any method or apparatus described in this disclosure may be integrated into the imaging device 204.

[0020] Figure 14 This is a block diagram illustrating another microarchitecture of the structure and data flow of an embodiment of a hierarchical interpolation system according to the principles of this disclosure.

[0021] Figure 15 An embodiment of a computing system according to this disclosure is shown. Detailed Implementation

[0022] Figure 1 This illustrates a common technique for interpolating attribute values ​​across a 9-pixel by 9-pixel grid 100. The attribute value can be determined first for the bottom-left pixel at sample point 102. Then, the attribute values ​​at sample points for other pixels can be found by traversing the grid pixel-by-pixel in the x and y directions, as shown. Figure 1 As shown by the arrows in the diagram. The attribute increment value for each pixel is added to the sum of the attributes of the previous pixels. (The increment value is sometimes called the attribute's "delta".) The attribute increment value for each pixel can be based on the x and y offsets of each pixel relative to the previous pixels, as well as a function that can be used to determine the attribute value of any pixel.

[0023] However, the x and y offsets for each pixel can be variable for each row and / or each column, so attribute calculations for each node might require a 3-input adder, which can be relatively expensive to implement in hardware or software. Furthermore, the logic level for a hardware implementation of an n-pixel multiplied n-pixel grid could be 2^n. Another drawback might be implementation... Figure 1The area required for the hardware of this technology can increase geometrically with the value of n. Furthermore, the hardware implementation may result in a large fan-out, which could necessitate larger and / or more expensive drivers to avoid additional latency in the computation.

[0024] Figure 2 An embodiment of a method for interpolating attribute values ​​of an image grid according to the principles of this disclosure is shown. The image grid may initially be divided into nine cells C1, C2, ..., C9, which may be the highest level shown in grid 110A. Each cell may have corresponding nodes N1, N2, ..., N9. The central cell C5 and the central node N5 may be designated as the root cell and root node, respectively. The remaining cells C1-C4 and C6-C9, which may be arranged radially around the central cell, may be designated as child cells. The remaining nodes N1-N4 and N6-N9 may be designated as child nodes.

[0025] This method can begin by determining the attribute value (root attribute) of the root node. This can be implemented in any suitable manner. For example, if the root node N5 happens to be a known sample point, the sample value at that point can be used as the root value at the highest level. Otherwise, the root value can be calculated, for example, by interpolating from other nodes outside the image grid 110A using a general multiplier, adder, etc. The method can calculate metadata, which can include, for example, attribute increment values ​​representing the offsets between the root node N5 and its child nodes in the x and y directions. This can be achieved, for example, by using a plane equation on the attribute. The attribute values ​​for each child node N1-N4 and N6-N9 can then be derived from the root node N5 by combining the root value with the metadata, such as... Figure 2 As indicated by the arrows in the diagram. For example, the attribute value of each child node can be calculated by adding one or more metadata elements to the root value using streamlined addition processing as described below. Figure 2 The process of exporting attribute values ​​from sub-cells is called Stage 1.

[0026] Each of the nine cells at the highest level, C1, C2, ..., C9, can be subdivided into smaller sub-cells at the next level, as shown in grid 110B, which is another view of the subdivided grid 110A. For example, cell C1 can be subdivided into second-level cells or sub-cells C1-1, C1-2, ..., C1-9. Each second-level cell can have corresponding nodes N1-1, N1-2, ..., N1-9. (To avoid confusion with the accompanying drawings, in...) Figure 2While not all subdivided cells and nodes of image grid 110B are labeled, the designation of each cell is clearly visible from the standard labeling pattern. The central cell C1-5 and central node N1-5 can be designated as the second-level root cell and root node, respectively. Therefore, the first-level child node N1 can be used as the second-level root node N1-5. Similarly, the derived attribute value at the first-level child node N1 can be used as the second-level root value of the second-level root node N1-5. The remaining cells C1-1 to C1-4 and C1-6 to C1-9, which can be arranged radially along the central cell C1-5, can be designated as second-level child cells. The remaining nodes N1-1 to N1-4 and N1-6 to N1-9 can be designated as second-level child nodes.

[0027] This method can compute the metadata of second-level child nodes, which may include attribute increment values ​​representing the offsets in the x and y directions between the second-level root node N1-5 and its second-level child nodes N1-1 to N1-4 and N1-6 to N1-9. This can be accomplished, for example, using the plane equation of the attribute. Then, the attribute values ​​of each second-level child node can be derived from the second-level root values ​​of the attribute at the second-level root node N1-5 by combining the second-level root values ​​with the second-level metadata, such as... Figure 2 As shown by the arrows in the diagram. For example, the attribute value of each second-level child node can be calculated by adding one or more second-level metadata to the second-level root value using a streamlined addition process, as described below.

[0028] Similarly, each of the other first-level cells C2 through C9 can be subdivided into smaller cells, each with its own second-level node, as shown in grid 110B. In the case of the highest-level center cell C5 in the grid center, the root node N5 can be used as the second-level root node N5-5 of the second-level cell C5-5. Figure 2 The processing of exporting attribute values ​​from second-level sub-cells is called stage 2.

[0029] The process of repeatedly subdividing cells, creating child nodes, and deriving attribute values ​​at each child node can be repeated at any number of levels, thereby creating a hierarchical tree structure and a grid with increasingly finer resolutions. Therefore, interpolation can begin from the root node in the central cell of the highest level and ripple down to an increasing number of nodes at each subsequent lower level. Furthermore, the principles of this disclosure are not limited to... Figure 2 The 3×3 cell arrangement, this particular topology (which can be described as a diagonally layered 3×3 topology), can provide many benefits as described below.

[0030] Figure 3This is a flowchart of a method for interpolating attribute values ​​of an image mesh according to the principles of this disclosure. The method can begin at the starting point 112 of the highest level of the hierarchical tree. In step 114, the method determines the attribute value at the root node located at the center of the image at the highest level. In step 116, metadata can be pre-computed for multiple child nodes of one or more levels based on parameters of the attribute (such as gradients). In step 118, the method derives the attribute value of each child node of the current level based on the corresponding root value and metadata of the current level. In step 120, if the current level is not the lowest level, then in step 122, the attribute value of each child node is used as the value of the root node of the next level below it, and step 118 is repeated; otherwise, the process ends at 124.

[0031] about Figure 3 The described method can be modified and configured and adapted in a variety of ways for countless applications. For example, even though some embodiments are shown as having a 3×3 array, i.e., a geometric ratio N = 9, any number of nodes N can be used. Then, as additional levels are added, the number of nodes in the tree can be adjusted according to level 1, N, N... 2 N 3 The tree grows geometrically. However, in some embodiments, the tree may not grow with the same proportion of nodes at each level.

[0032] As another example, in addition to interpolating continuous attribute values, this method can also be used for rasterization to determine the pixel coverage of primitives via boundary estimation (i.e., point classification or point-to-line distance estimation relative to the boundary), thereby determining whether a particular sample is located inside, outside, or on the boundary of a primitive, and other applications. In such applications, attributes can be, for example, binary input / output determination, ternary input / output / online determination, etc. Cells and nodes at various levels of the hierarchy can be used to implement any combination of pixels and / or samples. For example, in some embodiments, each of the highest-level cells C1, C2, ..., C9 can be used to implement a pixel with each of the highest-level nodes N1 to N9, serving as the primary sample among the pixels. Additional nodes can then be used to implement additional sampling for oversampling, supersampling, multisample anti-aliasing (MSAA), etc. In some other embodiments, the smallest subdivision cell at the lowest level of the hierarchy can implement pixels of a relatively high-resolution image.

[0033] A grid can have any number of cells in each direction, thus providing a general n-cell by m-cell grid. This may lead to trade-offs between, for example, the cost of generating and storing pre-computed metadata, tree depth, etc. In the case of a general asymmetric n-cell by m grid (i.e., n ≠ m), the metadata that might be needed to derive the attribute values ​​of child nodes can be assumed to be expressed as n*A, m*B, n*A+m*B, n*Am*B.

[0034] Depending on the mesh topology, there may be no second-level child nodes derived from one or more top-level nodes. This can happen, for example, if the top-level root node is aligned with a line dividing two cells or the intersection of four cells, as might occur in a mesh with an even number of cells on one or both sides. Root node N5 is shown in... Figure 2 The center of grids 110A and 110B is shown, and each other node is shown at the center of its corresponding cell, but it may not be necessary to place nodes at these central locations. However, in some embodiments, it may be beneficial to place the root node or other nodes at the center in a sense that they are close enough to the center, so that child nodes and other levels of the hierarchical tree can be created and interpolated efficiently.

[0035] about Figure 2 An example application of the method shown is interpolating attribute values ​​at sample locations using a plane equation. Equation 1 is an example plane equation for the parameters P of a two-dimensional surface, which can be used to interpolate at each location (x, y) using parameters A, B, and C that define the plane:

[0036] P(x, y) = A*(x- Seed X )+B*(y- Seed Y )+C (Equation 1)

[0037] Where A is the gradient per pixel (or other cell) in the x direction, B is the gradient per pixel (or other cell) in the y direction, and C is the value of P at position (Seed_X, Seed_Y).

[0038] Figure 4 An example embodiment of a method for interpolating attribute values ​​using planar equations is shown. The description is based on the scenario where samples are implemented at each node. Figure 4 This is an example of an implementation, but the principle also applies to pixels or any other type of node. Figure 4 The embodiment uses a 3-sample-by-3-sample grid 130 of spatially adjacent samples S1 to S9 because it provides computational benefits as described below. The method uses plane equations, such as Equation 1, where the parameter P is used as the property to be interpolated. This method... Figure 4The values ​​of metadata A, B, A+B, and AB are pre-calculated for a specific cell size. The attribute values ​​at the root node can be determined in any suitable manner. For example, the attribute values ​​at the root sample can be calculated by interpolating from other samples or nodes outside the image grid 130 using a general multiplier, adder, etc.

[0039] Once the attribute value at root sample S5 is known, and the metadata values ​​A, B, A+B, and AB have been pre-calculated, the attribute values ​​at subsamples S1-S4 and S6-S9 can be derived by simply adding the following metadata values ​​to the attribute value at root sample S5: Figure 4 As shown: Sample S1: -(AB); Sample S2: B; Sample S3: A+B; Sample S4: -A; Sample S6: A; Sample S7: -(A+B); Sample S8: -B; and Sample S9: AB. The simplicity of these calculations can be achieved through topological symmetry. That is, each subsample is located at a position offset by zero or one common unit from the root sample in either x or y. In this embodiment, the common unit is equal to the size of the grid cell. For example, sample S6 has an x ​​offset of 1 unit and a y offset of 0, while sample S3 has an x ​​offset of 1 unit and a y offset of 1 unit. This arrangement of all samples with zero or one unit offset, even samples placed diagonally from the root, allows each subsample to be performed using a simple addition. This, in turn, allows the addition operation for each subsample to be implemented using a 2-input adder, and... Figure 1 This reduces cost and area compared to the 3-input adders required for traditional asymmetric difference (delta) techniques.

[0040] like Figure 5 As shown, Figure 4 The diagonal hierarchical 3×3 topology is applicable to rasterization. When used with rasterization, interpolation can be based on the edge equation instead of the plane equation. In this case, the metadata can be pre-computed as dx, dy, dx+dy, and dx-dy, where dx may be the difference in the x-direction and dy may be the difference in the y-direction. The process can begin with an estimate of the edge equation at the boundary where the root value of the tree is located, and the sample can be the pixel center. Then, the following metadata can be added to the initial value at pixel P5 to compute... Figure 5 The values ​​of the sub-pixels shown in grid 132 are: pixel P1: -(dx-dy); pixel P2: dy; pixel P3: dx+dy; pixel P4: -dx; pixel P6: dx; pixel P7: -(dx+dy); pixel P8: -dy; pixel P9: dx-dy.

[0041] Equation 1 can be adapted for use with boundary equations, for example, by replacing A with dx, B with dy, and C with “start” (the boundary estimate for the location of the boundary) in the plane equation.

[0042] Can Figure 4 and Figure 5 The method can be extended to additional levels, such as Figure 6 As shown, in this scenario, the metadata at each level can be correlated with the metadata at adjacent levels using a simple scaling factor. For example, in... Figure 6 In the embodiments, Figure 5 The 3×3 grid 132 can be used as a secondary subdivision cell of the primary grid 134A, and the pre-computed metadata dx, dy, dx+dy, and dx-dy can be used to derive secondary subpixels. (Pixels P1 to P9 can be reassigned as P1-1 to P1-9.) The pre-computed metadata for the primary grid 134A can be calculated as 3dx, 3dy, 3(dx+dy), and 3(dx-dy). These primary metadata can be used to derive primary subpixels P1 to P4 and P6 to P9 by adding them to the starting value of the root pixel P5, as follows: pixel P1: -3(dx-dy); pixel P2: 3dy; pixel P3: 3(dx+dy); pixel P4: -3dx; pixel P6: 3dx; pixel P7: -3(dx+dy); pixel P8: -3dy; pixel P9: 3(dx-dy).

[0043] The 3x factor associated with a diagonally layered 3x3 topology can be particularly easy to implement in digital logic because x³ multiplication can be implemented using a 2-input adder. For example, 3*x can be implemented as x + 2*x, and 2*x can be cheaply implemented in floating-point because 2*x can be implemented by increasing the exponent of x by 1. Similarly, if Figure 4 The 3×3 topology is extended to another level, so that the pre-computed metadata can be computed as 3A, 3B, 3(A+B) and 3(AB).

[0044] Figure 7 This is a block diagram illustrating the structure and data flow microarchitecture of an embodiment of a hierarchical interpolation system according to the principles of this disclosure. Figure 7The system can be used to implement any of the methods and processes disclosed herein, but is not limited to any implementation details described herein. System 150 includes a root unit 154 configured to compute attribute values ​​of the root node—e.g., the central sample location—at the highest level of the hierarchical tree topology. Root unit 154 can respond to input 152, which may depend on the specific application of the system, for example, by interpolation using a general multiplier, adder, etc. For example, when used to interpolate samples based on a plane equation, input 152 may include parameters from Equation 1, including parameters A, B, and C that define the plane, where A is the gradient per pixel (or other cell) in the x-direction, B is the gradient per pixel (or other cell) in the y-direction, and C is the value of P at location (Seed_X, Seed_Y). Input 152 may also include the coordinates of the root location (X_root, Y_root). Metadata unit 156 can be configured to pre-compute metadata for deriving attribute values ​​of child nodes in response to input 152, such as A, B, A+B, and AB in the case of planar equations, and dx, dy, dx+dy, and dx-dy in the case of boundary equations. Metadata unit 156 can be configured to use a metadata set for each level of the hierarchical tree. For example, if the metadata pre-computed for the lowest level includes the set M = {A, B, A+B, AB}, then the set pre-computed for the next level up could be M' = 3*M, the set pre-computed for the level after that could be M” = 9*M, and so on.

[0045] A tree 158 with one or more logical stages, having three stages 158A, 158B, and 158C in this example, can be configured to perform computations that derive the attribute values ​​of child nodes at each level of the hierarchical topology. In this embodiment, a 3×3 topology is assumed. Therefore, the first stage 158A can be constructed to accommodate 9 nodes, the second stage 158B to accommodate 81 nodes, and the third stage 158C to accommodate 729 nodes.

[0046] Output 160 can be in the form of an N-pixel multiplied by M-pixel interpolated output, but in other embodiments, the output can have an array of one or more different dimensions, node types, etc. The desired bandwidth, for example, the number of samples or pixels per clock cycle or other time unit, can be N pixels in the x-direction and M pixels in the y-direction to match the throughput with downstream processing or execution units that can use and / or transform the output data.

[0047] For the purpose of explanation, Figure 7 The embodiment is illustrated as a 3×3 topology with three levels, but other topologies and numbers of levels (stages) can be used. Therefore, the dashed line between stage 158C and output 160 indicates additional stages that can be added. Figure 7 System 150 can be implemented in hardware, software, or any combination thereof. In a hardware implementation, the tree 158 of the logic stages and the metadata unit 156 can be implemented as combinational logic with simple two-input adders, capable of interpolating the entire tree hierarchically, that is, reducing all nodes to the lowest level in a single clock cycle. This can result in reduced power and / or energy consumption and / or circuit area requirements. The root unit 154 can be implemented using combinational and synchronous logic to be integrated into the clock of a larger image processing system. In some hardware implementations, system 150 can be integrated into a graphics processing unit (GPU) on an integrated circuit (IC), where this can enable improved rendering frame rates.

[0048] In a software implementation, the methods and architectures disclosed herein can reduce the constant temporary storage space required for addition and / or subtraction operations. In some hybrid embodiments, a series of hierarchical tree stages can be implemented in hardware and fed root values ​​and / or metadata provided by software.

[0049] Figure 7 The system and other embodiments disclosed herein offer several other potential benefits, as follows. If N is the number of samples or other nodes to be interpolated per clock cycle, i.e., the number of nodes at the lowest level of the grid tree, then the logical depth of the tree can be given by the logarithm of N+1 to the base 9, i.e., log9(N+1). This can be compared with... Figure 1 Compared to traditional techniques, where the number of logic levels can increase geometrically with the value of N, diagonal layering, particularly in 3×3 implementations, can reduce the number of logic levels and / or critical paths for addition processing. Therefore, this can be advantageous for high-frequency design synthesis and for reducing latency due to propagation delays through one or more stages of the layered tree. Furthermore, this can reduce the cost per computed value because relatively fewer metadata values, such as A, B, A+B, and AB or their scaled versions, may need to be stored per level.

[0050] Figure 7 The embodiments described herein, as well as other embodiments disclosed herein, can be implemented in a serial hybrid configuration, where conventional interpolation techniques can be used to implement one or more higher levels, such as sequentially traversed x and y paths, as... Figure 1 As shown. Hybrid configurations can simplify the implementation of one or more higher levels, while still using hierarchical tree topology at lower levels, i.e., near or at the bottom leaf nodes. The cost savings of hierarchical tree topology may be greatest at lower levels. In addition, when using meshes of sizes other than 3×3, synthesis tools in electronic design automation (EDA) platforms may be able to automatically optimize unused leaf nodes.

[0051] Figure 14This is a block diagram illustrating another microarchitecture of an embodiment of a hierarchical interpolation system according to the principles of this disclosure, showing the structure and data flow. Figure 14 System 151 can be architecturally similar to Figure 7 The system 150, however, can include a generalized tree 159 with stages 159A, 159B, 159C, ..., each stage having "I" nodes, I 2 Each node, I 3 The number of nodes... can be represented by I = W * Z, where W and Z represent the number of nodes in the x and y directions, respectively. Therefore, each node can branch to I nodes in the next stage. As the tree grows from the root node to the leaf node, the number of nodes in each stage may increase according to the following pattern or series: 1, I, I 2 I 3 I 4 ...

[0052] During the design process, the numbers I, W, and Z can be selected as constants. Figure 7 The embodiments can be regarded as Figure 8 A special case of the embodiment, wherein W=3, Z=3, and therefore I=9.

[0053] Figure 14 An embodiment of this can be characterized by having a general logical level or tree depth given by O(logN), where N can be the number of nodes in the lowest level of the hierarchical tree, and O can represent a general complexity notation that may be related to asymptotic bounds. For example, in an embodiment where each node can branch to "I" nodes in the next stage, the logical level and thus the waiting time caused by the propagation delay through the stages of the tree can be given by the logarithm of N to the base I, i.e., O(logN). I N). Depending on the implementation details, this can be related to... Figure 1 Compared to conventional techniques, in which the logic level can be given by O(N) as N increases, this is advantageously contrasted with traditional techniques. Therefore, in some embodiments, having... Figure 14 The system with the general tree topology shown can reduce the logic level and / or propagation delay / interpolation delay from O(N) to O(logN).

[0054] In some embodiments, metadata can be viewed as having three general components: an X component, a Y component, and an XY component. For example, when using boundary equations, the X, Y, and XY components can be dx, dy, and dx+ / -dy, respectively. The X, Y, and XY components can be specified as META_X, META_Y, and META_X+ / -META_Y, respectively. Just as the number of nodes increases at each stage when moving from the root node to a leaf node, in the opposite direction, moving from the leaf node to the root node, the metadata can grow, such as: {META_X,META_Y,META_X+ / -META_Y,…},{W*META_X,Z*META_Y,W*META_X+ / -Z*META_Y…},{W 2 *META_X,Z 2 *META_Y,W 2 *META_X+ / -Z 2 *META_Y…},{W 3 *META_X,Z 3 *META_Y,W 3 *META_X+ / -Z 3 *META_Y…}….

[0055] Metadata unit 157 can be configured to use a metadata set for each level of the hierarchical tree. For example, if the metadata pre-computed for the lowest level includes the set M = {META_X, META_Y, META_X+META_Y, META_X-META_Y}, then the sets pre-computed for subsequent upward levels can be M' = I*M, M” = I 2 *M etc.

[0056] and Figure 7 The implementation is the same as the previous one. Figure 14 Implementations can be carried out in hardware, software, or any combination thereof. Any number of stages can be used, and any N-pixel multiplied by M-pixel interpolated output can be generated.

[0057] Figure 7 and Figure 14 The embodiments described herein, as well as other embodiments disclosed herein, can be configured for use with multi-sample anti-aliasing (MSAA), which uses multiple samples per pixel to improve image quality. A common arrangement for MSAA is to use four samples per pixel, arranged in a rotated 2×2 grid within the pixel. This can be referred to as 4× or 4 to 1 MSAA, but other variations of 2×, 8×, and MSAA can be used.

[0058] For example, to work with MSAA, the structure can be modified by copying or branching. Figure 7An embodiment is provided to enable it to process additional samples for each pixel, such as Figure 8 As shown. Figure 8 System 170 can be broadly similar to Figure 7 The system 150 is modified, but a redirection unit 162 is added. This redirection unit 162 can operate in response to a mode selection input 164 to rearrange the way samples are directed from the root unit 155 to the tree 166. The mode selection input 164 allows the system to switch between MSAA mode and non-MSAA mode. The root unit 155 can also be modified to rearrange the way samples are directed to the tree 166 in response to the mode selection input 164. The tree 166, including stages 166A, 166B, and 166C, can also be modified to process additional nodes at each stage of the hierarchy. The number of nodes in each stage can be multiplied by, for example, the number of samples per pixel in MSAA mode. For example, stage 166A can process (9 × NUM_SAMPLES) nodes, which can be 36 nodes when NUM_SAMPLES = 4. Increasing the size of the stages by the same multiple as the number of samples per pixel in MSAA mode may facilitate switching the tree between MSAA mode and non-MSAA mode. Depending on the implementation details, this could provide substantial improvements in simplicity and performance, potentially outweighing any increase in hardware costs.

[0059] In some implementations, in MSAA mode (i.e., when mode selection input 164 is active), the modified root cell 155 can begin by finding / selecting one of multiple pixels in the center pixel of the grid as the root sample. (For example, a sample in the left corner of the center pixel could be selected as the root sample.) The root cell 155 can then expand from the root sample and interpolate the number of samples in the center pixel, assumed to be four in this example (NUM_SAMPLES = 4). The root cell 155 and redirection unit 162 can then orient the four samples from the center pixel to tree 166, and a diagonal hierarchical 3×3 topology can then be applied to compute the values ​​of other samples in other pixels adjacent to the center pixel, and so on. Thus, a hierarchical tree structure can be implemented independently for each of the multiple samples.

[0060] In MSAA mode, the layout of the sample output 160 may need to be rotated to suit the expectations of downstream processing units, for example, to compensate for the arrangement of samples in each pixel. The redirection unit 162 can redirect... Figure 8 Adding a logical level to the architecture is possible, but it may be relatively cost-effective.

[0061] In non-MSAA mode (i.e., when mode selection input 164 is active), the root unit 155 and the redirection unit 162 can reconfigure the input of tree 166 for reuse by adding a value corresponding to the original pixel grid divided by NUM_SAMPLES to the root and the nodes connected to it.

[0062] In some alternative embodiments, tree 166 can be configured to branch from the center samples of the 3×3 grid from previous stages to span samples within a pixel. In this embodiment, a hybrid tree can be used, where one or more stages can be implemented with a conventional configuration for design simplification.

[0063] although Figure 8 The embodiment is shown as having a 3×3 topology, but any topology can be used, including... Figure 14 The general form of the embodiment is as follows. Each node can branch to "I" nodes at the next level, where I = W * Z, and W and Z can represent the number of nodes in the x and y directions, respectively.

[0064] In some embodiments, an N×M grid can be subdivided into smaller subgrids, allowing different properties to be interpolated for each subgrid. This can be achieved, for example, by starting at the center of each subgrid and determining the root value of the property to be interpolated at that subgrid's center. After finding the root value for each subgrid, the property values ​​for each entire subgrid can be interpolated using a hierarchical tree topology.

[0065] In some embodiments, the system may be configured with multiple trees and / or root cells, each of which can be used to interpolate a value in one of the subgrids. For example, if the grid is subdivided into k subgrids, the system may include k hierarchical trees to interpolate the child nodes of each root node, and k root cells to determine the starting root value at the center of each subgrid.

[0066] Figures 9 to 11 An embodiment of a mesh that can be subdivided according to the principles of this disclosure is shown. Figure 9 In this model, grid 180 is not subdivided (k=1), and the entire grid can be interpolated by a single hierarchical tree that starts as the root node, marked as ROOT at the center of the entire grid, and expands outwards as indicated by the arrows. Figure 10 In this model, the grid is subdivided into two subgrids, 182 and 184 (k=2). Each subgrid can be interpolated using different properties from different hierarchical trees, starting from one of the root nodes ROOT1 and ROOT2 at the center of the two subgrids. Figure 11In this model, grid 180 is subdivided into four subgrids: 186, 188, 190, and 192 (k = 4). Each subgrid can be interpolated using different properties by different hierarchical trees, starting from one of the root nodes ROOT1, ROOT2, ROOT3, and ROOT4 at the center of the four subgrids. Regardless of the subdivision level, different subgrids can be used to interpolate the same or different primitive properties.

[0067] Figure 12 This is a block diagram illustrating the microarchitecture of the structure and data flow of an embodiment of a multi-attribute hierarchical interpolation system according to the principles of this disclosure. Figure 12 Example system 194 illustrates an embodiment with two trees (k=2), but the principle can be extended to embodiments with any number of trees for any number of subgrids. System 194 is shown with functionality for supporting MSAA, but functionality related to multi-attribute interpolation is independent of MSAA functionality and can be omitted.

[0068] Figure 12 System 194 includes a first hierarchical tree 166A, root unit 155A, and metadata unit 156A, which can operate substantially independently of a parallel second hierarchical tree 166B, root unit 155B, and metadata unit 156B. However, it may be advantageous to operate both halves according to the same clock and / or to make them work together in certain modes. Each half of the system can receive separate root location and plane equation inputs 152A and 152B. Scheduler 196 can be configured to provide different inputs 152A and 152B to the two halves of system 194. For example, scheduler 196 can provide different root locations and plane equations so that the system can perform... Figure 10 The parallel interpolation is shown.

[0069] Figure 12 The system can be used to independently interpolate two distinct properties of two different subgrids based on two different plane equations and two different root locations per clock cycle. Each half of the system can use its corresponding root location and plane equation to find the property value at the center of its respective grid, and then implement a hierarchical tree (such as tree 166A or 166B) to estimate the property value through the rest of its subgrids. For example, the first root cell 155A can be determined Figure 10 The value of ROOT1 in the code, and the root unit 155B can be determined. Figure 10 The value of ROOT2 in the example. In this example, the tree implements a diagonal 3x3 topology, but other topologies can be used. For example, any general topology could be used, such as... Figure 14As shown in the embodiment, each node can branch to "I" nodes at the next level, where I = W * Z, and W and Z can represent the number of nodes in the x and y directions, respectively.

[0070] As with the other embodiments described above, Figure 12 Implementations can be carried out in hardware, software, or any suitable combination thereof. If the combinational logic of Tree 166A and 166B is implemented in hardware, the system may be able to interpolate two subgrids in a single clock cycle, for example... Figure 10 Those shown. The system can also be scaled to include any number of trees for simultaneous interpolation of any number of subgrids. For example... Figures 9-11 As shown, subdividing the entire mesh into equal-sized subgrids can be beneficial because it can balance the tree and reduce its logical level. The system's hardware configuration can also be adapted to balance various factors such as cost, power and energy consumption, and performance. For example, Figure 12 Each tree in the multi-attribute embodiment can be implemented with half the amount of hardware, which, as in the single-attribute embodiment, might result in each half operating at approximately half the speed as a single-attribute version, but still maintaining the same N×M sample throughput per clock cycle in the combined output. Alternatively, each half can be implemented with the same amount of hardware as in the single-attribute embodiment. This effectively doubles the amount of hardware and doubles the sample throughput of the combined N×M sample output.

[0071] In some embodiments, such as when interpolation of fewer than k attributes per clock cycle is required, a multi-attribute hierarchical tree can be configured to share resources. This can be achieved, for example, by including multiplexers and / or adders near the head of the tree. In some embodiments, this allows the system to maintain the same N×M sample throughput per clock cycle even while sharing resources.

[0072] Figure 12The embodiments include functionality that allows it to be reconfigured to share resources. For example, if only one attribute needs to be interpolated for the entire mesh, the system can be reconfigured so that two trees can be configured to interpolate half of the mesh using the same root location and plane equation inputs. In this operating mode, the first tree 166A can operate normally using the first root cell 155A to determine the center sample at ROOT1 using the first root location and plane equation from input 152A. However, in this resource-sharing operating mode, multiplexer 202 can select the first root location and plane equation from input 152A as input to the second metadata cell 156B of the second tree. Additionally, in this resource-sharing operating mode, another multiplexer 200 can select the output of the first root cell 155A, but with an offset added by adder 198 to place the root location of the second tree at an offset from ROOT1. That is, adder 198 and multiplexer 200 can substantially replace ROOT2 with appropriate values ​​so that the second tree can interpolate its submesh using the first attribute. Therefore, the two halves of the system can operate in parallel to interpolate an attribute over the entire grid 180.

[0073] about Figure 12 The principles illustrated may help configure interpolation systems to suit various system requirements. For example, as the demand for system sample throughput increases, such as due to the increasing number of samples per grid, there may become a growing need for simultaneous interpolation of multiple attributes (from the same or different primitives) to ensure sufficient samples are interpolated. The ability to interpolate multiple attributes simultaneously can be useful when the primitive size is small and / or when interpolating at the corners of primitives with only partial sample coverage, thus potentially improving utilization. Regarding... Figure 12 The principles shown can be applied to any of these situations to help improve system performance, efficiency, etc.

[0074] Figure 13An embodiment of imaging device 204 is illustrated, and any methods or apparatus described in this disclosure can be integrated into imaging device 204. Imaging device 204 can be of any form, such as a panel display for PCs, laptops, mobile devices, etc., a projector, VR goggles, etc., and can be based on any imaging technology, such as cathode ray tube (CRT), digital light projector (DLP), light-emitting diode (LED), liquid crystal display (LCD), organic LED (OLED), quantum dot, etc., for displaying a rasterized image 206 with pixels. Image processor 210, such as a graphics processing unit (GPU) and / or driver circuitry 212, can process and / or convert the image into a form that can be displayed on or through imaging device 204. A portion of image 206 is magnified so that pixels 208 are visible. Any methods or apparatus described in this disclosure can be integrated into imaging device 204, processor 210, and / or driver circuitry 212 to... Figure 13 Interpolation is performed on any of the pixels 208 shown. In some embodiments, the image processor 210 may include any of the hierarchical tree topologies described above, for example, implemented on the integrated circuit 211. In some embodiments, the integrated circuit 211 may also include driver circuitry 212 and / or any other components that may implement any other function of the imaging device 204.

[0075] In addition to those mentioned above, and depending on the implementation details and circumstances, the principles of this disclosure may provide any or all of the following advantages and / or features: methods and / or apparatuses that can be scaled to various pixel grid dimensions; hierarchical topologies, including diagonal 3×3 topologies. It can reduce area, energy, and / or power consumption, and can be applied to any sample / pixel interpolation unit / module; hierarchical topology, including diagonal 3×3 topology, can be applied to boundary equation-based interpolation, which may be useful for efficient rasterization; hybrid tree topology, including diagonal 3×3 topology, can save costs and reduce complexity when combined with conventional designs; sample interpolation with hierarchical topology, including diagonal 3×3 topology, can be implemented in conjunction with MSAA mode operation; hierarchical topology, including diagonal 3×3 topology, can be applied to any interpolation throughput of adjacent sample integer arrays in the x and y directions; hierarchical topology, including diagonal 3×3 topology, can be scaled to any other sample / pixel set for use with tree interpolation; the methods and apparatus disclosed herein can be used with any attribute data format; to support interpolation of multiple attributes on multiple blocks (e.g., k blocks), an interpolation tree can be constructed using a branch point with k leaf nodes near the head of the tree.

[0076] In some embodiments, the number of nodes at each stage, i.e., at each level, can follow a geometric progression. Additionally, in the case of a 3×3 topology, the cost of each stage may be approximately nine times the cost of the previous stage. Therefore, if the area of ​​the final stage is A, the total area TA can be given by: TA = A + A / 9 + A / 81 + A / 729… = A×(9 / 8). Using this approximation, example cost summaries based on area are provided in Table 1 for rasterization implementations based on the following assumptions: (1) the approximation is based on an aliasing mode (i.e., not multi-sample anti-aliasing); (2) a fixed-point algorithm is used for area estimation based on the rasterizer dx, dy, and the starting point; and (3) a symmetric mesh with the same number of samples in the x and y directions is used. The values ​​shown in Table 1 are for illustrative purposes only and may not represent actual values ​​in physical or simulated implementations.

[0077] Table 1

[0078] Pixels Traditional technology Diagonal layered 3×3 topology % improvement rate 4×4 9 6 33 8×8 44 19 57 12×12 100 41 59 16×16 200 74 63 24×24 500 160 68 32×32 1000 260 74

[0079] Figure 15 An embodiment of a computing system according to this disclosure is shown. Figure 15 System 300 can be used to implement any or all of the methods and / or apparatuses described in this disclosure. System 300 may include a central processing unit (CPU) 302, memory 304, storage device 306, graphics processing unit (GPU) 307, user interface 308, network interface 310, and power supply 312. A complete hardware implementation of the hierarchical tree structure according to this disclosure can be implemented in GPU 307, while a complete software implementation can be implemented within CPU 302. In other embodiments, the complete hardware implementation of the hierarchical tree structure can be implemented as an integrated graphics processing unit (IGPU) in CPU 302. In other embodiments, GPU 307 can be used to implement a serial hybrid configuration, wherein higher levels of the hierarchical tree structure 307 can be implemented in the GPU using conventional hardware, while lower levels can be implemented in hardware and / or software using a hierarchical tree topology in GPU 307 and / or CPU 302. In other embodiments, the hierarchical tree structure according to this disclosure can be distributed among any suitable combination of hardware and / or software using any components of system 300. Furthermore, the principles of this disclosure are not limited to utilizing... Figure 15 It can be implemented using any of the components shown, but can be implemented using any suitable hardware, software or a combination thereof.

[0080] In different embodiments, the system may omit any of these components, or may include a repetition or any additional number of any of these components, as well as any other type of components that implement any of the methods and / or apparatuses described in this disclosure.

[0081] CPU 302 may include any number of cores, cache, buses and / or interconnect interfaces and / or controllers. Memory 304 may include any arrangement of dynamic and / or static RAM, non-volatile memory (e.g., flash memory), etc. Storage device 306 may include hard disk drives (HDDs), solid-state drives (SSDs), and / or any other type of data storage device or any combination thereof. User interface 308 may include any type of human-machine interface device, such as a keyboard, mouse, monitor, video capture or transmission device, microphone, speaker, touchscreen, etc., and any virtual or remote versions of these devices. Network interface 310 may include one or more adapters or other devices to communicate via Ethernet, Wi-Fi, Bluetooth, or any other computer network arrangement, enabling components to communicate over physical and / or logical networks (such as intranets, the Internet, local area networks, wide area networks, etc.). Power supply 312 may include a battery and / or power source capable of receiving power from AC or DC power and converting it into a form suitable for the components of system 300.

[0082] Any or all components of system 300 can be interconnected via system bus 301, which can be collectively referred to as various interfaces, including power buses, address and data buses, high-speed interconnects such as Serial AT Accessory (SATA), peripheral component interconnect (PCI), peripheral component interconnect Express (PCI-e), system management bus (SMB), and any other type of interface that enables these components to work together locally in one location and / or between different locations.

[0083] System 300 may also include various chipsets, interfaces, adapters, glue logic, embedded controllers such as programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), embedded computers, smart cards, etc., arranged to enable the various components of system 300 to work together to implement any of the methods and / or apparatuses described in this disclosure. Any component of system 300 may be implemented in hardware, software, firmware, or any combination thereof. In some embodiments, any or all components may be implemented in a virtualized form and / or in a cloud-based implementation with flexible resource configuration, such as within a data center or distributed across multiple data centers.

[0084] The blocks or steps of methods, algorithms, and functions described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in one or more software modules executed by a processor, or in a combination of both, including system 300. If implemented in software, the functions may be stored or transferred as one or more instructions or code on a tangible, non-transitory computer-readable medium. Software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium. Any system or component or portion thereof disclosed herein may be implemented as part of the software stack of a larger system (e.g., a graphics processing unit (GPU) or other larger system). Any system or component or portion thereof disclosed herein may be implemented as its own software stack.

[0085] The embodiments disclosed above have been described in the context of various implementation details, but the principles of this disclosure are not limited to these or any other specific details. For example, some functions have been described as being implemented by certain components, but in other embodiments, the functions may be distributed among different systems and components with various user interfaces in different locations. Some embodiments have been described as having specific processes, steps, etc., but these terms also cover embodiments in which specific processes, steps, etc. may be implemented by multiple processes, steps, etc., or embodiments in which multiple processes, steps, etc. may be integrated into a single process, step, etc. References to components or elements may refer only to a portion of that component or element. For example, a reference to an integrated circuit may refer to all or only a portion of the integrated circuit, and a reference to a block may refer to the entire block or one or more sub-blocks. Although the principles of this disclosure have been described in the context of certain applications, these principles can be applied to any attribute interpolation and / or rasterizer processing, and they can be useful in any mathematical calculation that interpolates or extrapolates one or more values ​​using boundary equations, plane equations, or any other equations. In some embodiments, calculations may be performed for locations in the lowest level of a hierarchical structure, and locations may correspond to various things such as pixels, samples, centroids, etc., depending on the resolution of the grid or other array. In some embodiments, interpolation can operate at any spatial sampling frequency of the planar primitives. In some embodiments, zero offset can refer to substantially zero offset, which makes it possible to ignore the value for computational purposes without significantly degrading the results.

[0086] The use of terms such as “first” and “second” in this disclosure and claims is merely to distinguish what they modify and may not indicate any spatial or temporal order unless it is obvious from the context. Referring to the first thing may not imply the existence of the second thing.

[0087] Based on the inventive principles disclosed in this patent, the various details and embodiments described above can be combined to produce other embodiments. Since the inventive principles disclosed in this patent can be modified in arrangement and detail without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A method of interpolating attribute values for a grid of images, the method comprising: determining a primary root value of an attribute at a primary root node located at a center of the grid of images; calculating primary metadata based on a first gradient of the attribute in a first direction and a second gradient of the attribute in a second direction; and deriving, based on the primary root value and the primary metadata, primary child values of the attribute for two or more primary child nodes arranged radially around the primary root node in the grid of images, wherein the primary root node is located at a center of a center cell and each primary child node is located at a center of one of outer cells, the method further comprising: using one of the primary child nodes and its corresponding primary child value as a secondary root node and a secondary root value for a cell of the grid of images, wherein the root node of the cell is located at a center of the cell; calculating secondary metadata based on the first gradient and the second gradient; and deriving, based on the secondary root value and the secondary metadata, secondary child values of the attribute for two or more secondary child nodes arranged radially around the secondary root node in the cell. Each primary child node is symmetrically offset from the primary root node in the first direction and the second direction.

2. The method of claim 1, wherein, Each primary child node is offset from the primary root node in the first direction and the second direction by substantially zero or substantially the same distance.

3. The method of claim 2, wherein, 4. The method of claim 1, wherein: the grid of images comprises a 3x3 array of cells having a center cell and eight outer cells; and the two or more primary child nodes comprise eight primary child nodes. The primary metadata comprises attribute delta values offset in the first direction and the second direction.

5. The method of claim 1, wherein, 6. The method of claim 1, wherein: a value of a first parameter A is based on the first gradient; and a value of a second parameter B is based on the second gradient. The primary metadata comprises values A, B, A+B, and A-B.

8. The method of claim 1, wherein:

7. The method of claim 6, wherein, a value of a first parameter A is based on the first gradient; a value of a second parameter B is based on the second gradient; the grid of images comprises a 3x3 array of cells; the primary metadata comprises values 3A, 3B, 3(A+B), and 3(A-B); and the secondary metadata comprises values A, B, A+B, and A-B. The primary metadata is calculated based on a plane equation.

10. The method of claim 9, wherein: the plane equation is of the form P(x,y) = A*(x-Seed_X) + B*(y-Seed_Y) + C; 9. The method of claim 1, wherein, P is a parameter of a two-dimensional surface interpolated at each location (x,y), where x is a distance in an x direction and y is a distance in a y direction; A is a gradient per pixel or other cell in the x direction; B is a gradient per pixel or other cell in the y direction; and C is a value of P at a location (Seed_X, Seed_Y). Deriving the primary child values comprises adding one or more of the primary metadata to the primary root value. The primary root node and each primary child node correspond to a pixel. The primary root node and each primary child node correspond to a sample.

11. The method of claim 1, wherein, The image is rasterized in response to the attribute values.

12. The method of claim 1, wherein, The attribute comprises a first value indicating that a node is inside a primitive and a second value indicating that the node is outside the primitive.

13. The method of claim 1, wherein, ​ 14. The method of claim 1, further comprising: ​ 15. The method of claim 14, wherein, ​ 16. A method for interpolating attribute values of an image grid, the method comprising: determining a root value of an attribute of a root node located at a center of the image grid; pre-computing metadata of a plurality of child nodes in one or more levels based on one or more gradients of the attribute; and deriving an attribute value of each child node of each level based on a corresponding root value and metadata of the level of each child node; wherein each child node serves as a root node in a next level, wherein the root node is located at a center of a center cell and each child node is located at a center of one of a plurality of outer cells, deriving an attribute value of each child node of each level comprises: using one of the primary child nodes and its corresponding primary child value as a secondary root node and a secondary root value of a cell of the image grid, wherein the root node of the cell is located at a center of the cell; computing secondary metadata based on the first gradient and the second gradient; and deriving secondary child values of the attribute of two or more secondary child nodes radially arranged around the secondary root node in the cell based on the secondary root value and the secondary metadata.

17. The method of claim 16, wherein: the image grid has a plurality of outer cells radially arranged around a center cell.

18. The method of claim 16, wherein, the root node is located in a first cell having one or more additional nodes, the method further comprising: determining attribute values of the one or more additional nodes in the first cell; and deriving attribute values of additional child nodes corresponding to each additional node in the first cell of each level, wherein the attribute value of each additional child node is derived based on the attribute value of the corresponding additional node in the first cell and the metadata of the corresponding level.

19. An apparatus for interpolating attribute values of an image grid, the apparatus comprising: a tree of one or more logical stages configured to derive attribute values of a plurality of child nodes located around a root node at a center location in each of one or more levels based on a corresponding attribute value at the root node and metadata of the level, wherein the root node is located at a center of a center cell and each child node is located at a center of one of a plurality of outer cells, wherein the tree of one or more logical stages is further configured to: use one of the primary child nodes and its corresponding primary child value as a secondary root node and a secondary root value of a cell of the image grid, wherein the root node of the cell is located at a center of the cell; compute secondary metadata based on the first gradient and the second gradient; and derive secondary child values of the attribute of two or more secondary child nodes radially arranged around the secondary root node in the cell based on the secondary root value and the secondary metadata.

Images