Memory device and operating method thereof, memory module and operating method thereof

Abstract

A method for operating a non-volatile dual in-line memory module (NVDIMM) is disclosed. The NVDIMM includes a dynamic random access memory (DRAM) and a non-volatile memory (NVM) device, the DRAM including a first input / output (I / O) port and a second I / O port, and the second I / O port connected to the NVM device. The method includes receiving an externally provided command signal representing a read / write command and a transfer mode, driving a multiplexer according to the transfer mode of the command signal to select at least one of the first I / O port and the second I / O port, and reading or writing data in at least one of the DRAM and the NVM device according to the read / write command of the command signal using the at least one of the first I / O port and the second I / O port selected by driving the multiplexer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 863,936, filed June 20, 2019 with the United States Patent and Trademark Office; U.S. Patent Application No. 16 / 821,615, filed March 17, 2020 with the United States Patent and Trademark Office; and Korean Patent Application No. 10-2020-0009397, filed January 23, 2020 with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a memory device, a method of operating the memory device, a memory module, and a method of operating the memory module, and more specifically, to a dual-port memory device, a method of operating the memory device, a memory module, and a method of operating the memory module. Background Technology

[0004] Mobile-oriented memory devices, such as low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM), are already widely used in mobile electronic devices such as smartphones, tablet PCs, and ultrabooks. As mobile operating systems (OS) become increasingly powerful to support multitasking in mobile electronic devices, there is a growing demand for mobile electronic devices that offer both low power consumption and high-speed operation.

[0005] Furthermore, due to the advantages of non-volatile memory such as flash memory, such as large capacity, low noise, and low power consumption, non-volatile memory has been widely used as storage devices in various fields. Specifically, flash-based solid-state drives (SSDs) are used as high-capacity storage devices in personal computers (PCs), laptops, workstations, server systems, and so on. Typical SSD devices connect to computer systems via either a Serial Advanced Technology Attachment (SATA) interface or a High-Speed ​​Peripheral Component Interconnect (PCI-E) interface. However, in recent years, with the increase in the amount of data processed in computing systems, data bottlenecks have emerged due to the increased data throughput relative to the data bandwidth or communication speed of the interface connected to the SSD device. These phenomena can degrade the performance of computing systems, and various techniques have been developed to improve performance and address these issues. Summary of the Invention

[0006] According to one aspect of the present invention, a method for operating a non-volatile dual in-line memory module (NVDIMM) is provided. The NVDIMM includes dynamic random access memory (DRAM) and a non-volatile memory (NVM) device. The DRAM includes a first input / output (I / O) port and a second I / O port, the second I / O port being connected to the NVM device. The method includes: receiving an externally provided command signal, the command signal representing a read / write command and a transfer mode; driving a multiplexer according to the transfer mode of the command signal to select at least one of the first I / O port and the second I / O port; and reading or writing data in at least one of the DRAM and the NVM device using at least one of the first I / O port and the second I / O port selected by driving the multiplexer, according to the read / write command of the command signal.

[0007] According to another aspect of the present invention, a method for operating a non-volatile dual in-line memory module (NVDIMM) is provided. The NVDIMM includes dynamic random access memory (DRAM) and a non-volatile memory (NVM) device. The DRAM includes a first input / output (I / O) port and a second I / O port, wherein the first I / O port is connected to an external device and the second I / O port is connected to the NVM device. The method includes: receiving an externally provided read / write command signal, the read / write command signal representing a read / write command and one of a plurality of transfer modes; and, according to the read / write command and in accordance with the indication of one of the plurality of transfer modes, using at least one of the first I / O port and the second I / O port of the DRAM to read data from or write data to at least one of the DRAM and the NVM device. The multiple transmission modes include: a first transmission mode in which data is exchanged between the DRAM and an external device using the DRAM's first I / O port when the DRAM's second I / O port is idle; a second transmission mode in which data is exchanged between the DRAM and an NVM device using the DRAM's second I / O port when the DRAM's first I / O port is idle; and a third transmission mode in which data is exchanged simultaneously between the DRAM and an external device using the DRAM's first I / O port and between the DRAM and an NVM device using the DRAM's second I / O port.

[0008] According to another aspect of the present invention, a method for operating a non-volatile dual in-line memory module (NVDIMM) is provided. The NVDIMM includes a multi-port dynamic random access memory (DRAM) and an NVM device including non-volatile memory (NVM) and an NVM controller. The method includes: receiving a first command provided externally; in response to the first command, reading data from the NVM and storing the data in the NVM controller; sending a ready signal to an external source of the NVDIMM; receiving a second command provided externally; in response to the second command, sending an internal read command to the NVM controller; after a period of time following the sending of the internal read command to the NVM controller, sending an internal write command to the DRAM; and in response to the internal read command and the internal write command, transferring data from the NVM controller to the DRAM.

[0009] According to another aspect of the present invention, a method for operating a memory system is provided. The memory system includes: a host device, and a first non-volatile dual in-line memory module (NVDIMM) and a second NVDIMM connected to the host device via the same channel. The method includes: sending a flush command from the host to the first NVDIMM via the channel; flushing first data from the DRAM of the first NVDIMM to the non-volatile memory (NVM) of the first NVDIMM in response to the flush command; and simultaneously transferring second data between the host and the second NVDIMM via the channel while flushing the first data from the DRAM of the first NVDIMM to the NVM of the first NVDIMM.

[0010] According to another aspect of the present invention, a non-volatile dual in-line memory module (NVDIMM) is provided, comprising: a multi-port dynamic random access memory (DRAM) including memory cells, a first input / output (I / O) port, and a second I / O port, and a non-volatile memory (NVM) connected to the second I / O port of the multi-port DRAM. The multi-port DRAM further includes: a data path generation circuit configured to selectively form: a first data path between the memory cells and the first I / O port, a second data path between the memory cells and the second I / O port, and a third data path bypassing the memory cells between the first I / O port and the second I / O port.

[0011] According to another aspect of the present invention, a multi-port dynamic random access memory (DRAM) is provided, comprising: a memory cell; control logic configured to control reading data from the memory cell and writing data to the memory cell; a first input / output (I / O) port; a second I / O port; and a data path generation circuit configured to selectively form a first data path between the memory cell and the first I / O port, a second data path between the memory cell and the second I / O port, and a third data path bypassing the memory cell between the first I / O port and the second I / O port. Attached Figure Description

[0012] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a diagram of a data processing system according to an example embodiment;

[0014] Figure 2 This is a diagram of the first command signal according to an example embodiment;

[0015] Figure 3 This is a reference flowchart describing a method of operating a sub-memory system according to an example embodiment;

[0016] Figure 4 This is a diagram of a memory device according to an example embodiment;

[0017] Figure 5A and Figure 5B This is a diagram illustrating a first command signal and a data communication method for a memory device according to an example embodiment;

[0018] Figure 6A and Figure 6B This is a diagram illustrating a first command signal and a data communication method for a memory device according to an example embodiment;

[0019] Figure 7A and Figure 7B This is a diagram illustrating a first command signal and a data communication method for a memory device according to an example embodiment;

[0020] Figure 8A and Figure 8B This is a diagram illustrating a first command signal and a data communication method for a memory device according to an example embodiment;

[0021] Figure 9 This is a diagram illustrating a first command signal and a data communication method for a memory device according to an example embodiment;

[0022] Figure 10A and Figure 10B This is a diagram illustrating a first command signal and a data communication method for a memory device according to an example embodiment;

[0023] Figure 11 It is a timing diagram used to describe the first command signal and the data signals of the first I / O port and the second I / O port according to the example embodiment;

[0024] Figure 12 This is a diagram of a data processing system according to an example embodiment;

[0025] Figure 13 This is a diagram of a register clock driver according to an example embodiment;

[0026] Figure 14 This is a diagram of a data processing system 1000 according to an example embodiment;

[0027] Figure 15A and Figure 15B These are a reference schematic diagram and a timing diagram illustrating a method for operating a data processing system according to an embodiment of the present invention;

[0028] Figure 16A and Figure 16B These are a reference timing diagram and a flowchart, respectively, describing a method for operating a data processing system according to an embodiment of the present invention.

[0029] Figure 17A , Figure 17B and Figure 17C This is a schematic diagram of a DRAM configuration according to an embodiment of the present invention;

[0030] Figure 18A and Figure 18B These are reference timing diagrams and flowcharts illustrating examples of multiple data transfers using a single activation command, according to embodiments of the present invention.

[0031] Figure 19A and Figure 19B These are reference timing diagrams and flowcharts illustrating examples of such cache operations in a DRAM device according to embodiments of the present invention; and

[0032] Figure 20A and Figure 20B These are reference timing diagrams and flowcharts illustrating examples of multiple data transfers using a single activation command, according to embodiments of the present invention. Detailed Implementation

[0033] Figure 1This is a schematic diagram of a data processing system 10 according to an example embodiment. The example data processing system 10 includes a host 100 and a sub-memory system 200. The data processing system 10 can be applied to or implemented in a variety of different electronic devices that require data storage capabilities. Non-limiting examples of such devices include servers, desktop computers, laptop computers, smartphones, tablet computers, printers, scanners, monitors, digital cameras, digital music players, digital media recorders, and portable game consoles.

[0034] The host 100 can process data and control the components included in the data processing system 10. For example, the host 100 can drive one or more operating systems (OS) and execute various applications on one or more OS. In these operations, the host 100 can write data to and / or read data from the sub-memory system 200. In some embodiments, the sub-memory system 200 is a non-volatile dual in-line memory module (NVDIMM).

[0035] The host 100 can provide a first command signal CMD1 to the sub-memory system 200 via the command / address line CMD1, and transmit data MDQ with the sub-memory system 200 via the data line MDQ. For ease of illustration, in this description, the signal and the line carrying the signal are assigned the same alphanumeric descriptor (e.g., CMD1, MDQ, etc.).

[0036] Refer to later Figure 2 The first command signal CMD1 is described in more detail. In some embodiments, the first command signal CMD1 includes a read command or a write command (collectively referred to as a read / write command) and a flag signal indicating the transfer mode (described later). The first command signal CMD1 may also include the memory address of the memory device 240 and / or the non-volatile memory system (NVM) 260 of the sub-memory system 200. Additionally, the first command signal CMD1 may also include other signals not described herein. Furthermore, the host 100 can provide data to or receive data from the sub-memory system 200 via the data line MDQ.

[0037] like Figure 1As shown, the sub-memory system 200 may include a register clock driver (RCD) 220, a memory device 240, and an NVM 260. The sub-memory system 200 may store data in the memory device 240 or provide data to the NVM 260 upon request from the host 100. In some embodiments, the memory device 240 is a dynamic random access memory (DRAM) used as a cache memory for the NVM 260. In a non-limiting example, the sub-memory system 200 may be implemented as a multi-chip module or a single chip. When the sub-memory system 200 is implemented as a multi-chip module, it may be referred to as a memory module. As described above, in some embodiments, the sub-memory system is a non-volatile dual in-line memory module (NVDIMM).

[0038] In operation, RCD 220 can receive a first command signal CMD1 provided by host 100. Additionally, RCD 220 can receive a second command signal CMD2 provided by NVM 260. Furthermore, in response to the first command signal CMD1 and / or the second command signal CMD2, RCD 220 can generate a memory command signal MCMD to be sent to memory device 240 and / or an NVM command signal ICMD to be sent to NVM 260. In an embodiment, the memory command signal MCMD includes an internal flag signal indicating the transmission mode represented by the flag signal of the first command signal CMD1. Alternatively, in an embodiment, the memory command signal MCMD may omit the flag signal and instead embed data indicating the transmission mode. Alternatively, a signal indicating the transmission mode may be sent separately. In an embodiment, RCD 220 may also perform at least some of the common functions of the memory controller and data buffer.

[0039] Memory device 240 may be a dual-port device. For example, memory device 240 may include a first I / O port 241 and a second I / O port 242. In some embodiments, memory device 240 is a dual-port DRAM. Memory device 240 can exchange data with host 100 via data lines MDQ of one or more data communication channels connected via the first I / O port 241. Additionally, memory device 240 can exchange data with NVM 260 via data lines LDQ connected via the second I / O port 242. In this document, the phrase "exchanging data" refers to the sending and receiving of data and may generally be referred to as data communication. In this document, as an example, communication channels may conform to standards such as Double Data Rate (DDR), DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (e-MMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), and High Speed ​​Non-Volatile Memory (NVMe). Regarding the first I / O port 241 and the second I / O port 242, the term "port" broadly refers to an electrical interconnect point used for an integrated circuit (IC). Examples of ports include contact pins, pads, and other interconnects.

[0040] Memory device 240 can be implemented as a volatile memory device. As described above, volatile memory device 240 can be DRAM. The volatile memory device can also be implemented as random access memory (RAM) or static RAM (SRAM), but the inventive concept is not limited thereto. As an example, memory device 240 can correspond to DDR synchronous dynamic RAM (DDRSDRAM), LPDDR SDRAM, graphics DDR (GDDR) SDRAM, or Rambus DRAM (RDRAM). Alternatively, memory device 260 can be implemented as high-bandwidth memory (HBM). Furthermore, memory device 260 can be implemented as a non-volatile memory device, such as resistive memory, phase-change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM), instead of a volatile memory device.

[0041] The NVM 260 may include various components, such as a processing unit, multiple cores included in the processing unit, a multi-format codec (MFC), a video module processor, a video processor, a three-dimensional (3D) graphics core, an audio system, drivers, display drivers, volatile memory, non-volatile memory, a memory controller, an input / output (I / O) interface block, and / or cache memory. In an embodiment, the NVM 260 may include a non-volatile memory system, which includes non-volatile memory devices and a non-volatile memory controller. In an embodiment, the NVM 260 may include a volatile memory.

[0042] NVM 260 can transmit data to memory device 240 based on the NVM command signal ICMD generated by RCD 220. For example, in response to the NVM command signal ICMD, NVM 260 can send data to or receive data from memory device 240 via data line LDQ. In one embodiment, NVM 260 can provide a second command signal CMD2 to RCD 220, but the inventive concept is not limited thereto. In another embodiment, NVM 260 may not provide commands to RCD 220.

[0043] According to an example embodiment, the memory device 240 can send or receive data through a first I / O port 241 and / or a second I / O port 242 based on a memory command signal MCMD. In the embodiment, each of the first I / O port 241 and the second I / O port 242 can be set to a data transmission state, a data reception state, or a floating state. Here, the data transmission state can indicate the state in which the memory device 240 sends data to an external device through the port, and the data reception state can indicate the state in which the memory device 240 receives data through the port. Here, the floating state can indicate a situation where the corresponding port is not used or the corresponding port is electrically open. In the example embodiment, the state of each of the first I / O port 241 and the second I / O port 242 can be determined based on the memory command signal MCMD. Reference will be made later in the context of the example embodiment. Figures 5A to 10B This describes the combination of the states of the first I / O port 241 and the second I / O port 242.

[0044] In an embodiment, the memory device 240 may further include control logic devices, which will be referred to later. Figure 4 Describe an example of its operation. The control logic device can be a circuit that controls the operation of the memory device 240 based on the memory command signal MCMD. Additionally, the control logic device can control the input and / or output of data via the first I / O port 241 and / or the second I / O port 242 based on the memory command signal MCMD.

[0045] Figure 2 This is a reference diagram used to illustrate the first command signal CMD1 according to an example embodiment. Reference will also be made to... Figure 1 To describe Figure 2 .

[0046] In an embodiment, the first command signal CMD1 may be a digital signal including a data operation command and a flag signal. For example, the data operation command may include a read command or a write command. The flag signal may indicate the transmission mode of the memory device 240 as one of a variety of transmission modes. The memory device 240 may perform data communication through the first I / O port 241 and / or the second I / O port 242 according to the transmission mode indicated by the flag signal. (Referring later...) Figures 5A to 10B Various embodiments of the memory device 240 that perform data operations based on data operation commands and flag signals are described.

[0047] In one embodiment, the host 100 can provide a first command signal CMD1 to the sub-memory system 200 via the command / address lines. In this case, in another embodiment, the host 100 can provide a flag signal via an unused pin in the address pins.

[0048] Figure 3 This is a reference flowchart describing a method of operating a sub-memory system 200 according to an example embodiment.

[0049] Let's refer to each other. Figure 1 and Figure 3 The sub-memory system 200 can receive an externally provided first command signal CMD1, which includes a command and a flag signal indicating a transfer mode (S120). Alternatively, for example, data indicating the transfer mode can be embedded in the command of the first command signal CMD1, or the signal indicating the transfer mode can be sent separately. This command can be a read / write command. An example of a read / write command is a command for flushing data from memory device 240 to NVM 260.

[0050] Next, the memory device 240 included in the sub-memory system 200 is operated according to the command and transmission mode, thereby performing data communication using at least one of the first I / O port 241 and the second I / O port 242 (S140). For example, the operation of the memory device 240 may be a response to an internal memory command signal MCMD generated by the RCD 220 based on the transmission mode of the first command signal CMD1.

[0051] Figure 4This is a schematic diagram of a multiplexer 243 and a control logic device 246 of a memory device 240 according to an example embodiment.

[0052] As in Figure 4 The multiplexer 243 configured in the diagram is a non-limiting example of a data path generation circuit configured to selectively form: a first data path between a memory cell of memory device 240 and a first I / O port 241, a second data path between a memory cell of memory device 240 and a second I / O port 242, and a third data path between the first I / O port 241 and the second I / O port 242 bypassing the memory cell of memory device 240.

[0053] Let's refer to each other. Figure 1 and Figure 4 The memory device 240 in this example includes a first I / O port 241, a second I / O port 242, a multiplexer 243, and a control logic device 246.

[0054] Control logic device 246 can control the overall operation of memory device 240, including operations not explicitly described herein. In conjunction with... Figure 4 In the context of the relevant operation, control logic device 246 controls multiplexer 243 by generating a first control signal CTRL_1 and a second control signal CTRL_2. As will be described later in the context of several examples of different transmission modes, the first control signal CTRL_1 and the second control signal CTRL_2 are generated by control logic device 246 in response to a read / write command based on the first command signal CMD1 and the internal memory command signal MCMD of the transmission mode.

[0055] Multiplexer 243 can selectively form a data transmission path between at least one of the following: internal data lines of the first I / O port 241, internal data lines of the second I / O port 242, and internal data lines connected to the internal memory component of the memory device 240. The internal data lines connected to the internal memory component may include: a first read data line RDQ1 for transmitting first read data RDQ1; a second read data line RDQ2 for transmitting second read data RDQ2; a first write data line WDQ1 for transmitting first write data WDQ1; and a second write data line WDQ2 for transmitting second write data WDQ2.

[0056] exist Figure 4In the example, multiplexer 243 includes: a first switching device 244 for selectively outputting one of two inputs in response to a first control signal CTRL_1; and a second switching device 245 for selectively outputting one of two inputs in response to a second control signal CTRL_2. However, the inventive concept is not limited to this. Figure 4 The specific configuration can be varied, and other circuits can be used to achieve the same overall function. The first switching device 244 and the second switching device 245 can also be referred to as multiplexer circuits.

[0057] One input terminal of the first switching device 244 is coupled to the internal data line RDQ1, and the other input terminal of the first switching device 244 is coupled to the internal data line of the second I / O port 242. The output terminal of the first switching device 244 is coupled to the internal data line of the first I / O port 241.

[0058] Similarly, one input of the second switching device 245 is coupled to the internal data line RDQ2, and the other input of the second switching device 245 is coupled to the internal data line of the first I / O port 241. The output of the second switching device 245 is coupled to the internal data line of the second I / O port 242. Thus, the first write data RDQ1 can be sent to the host 100 through the first switching device 244 and the first I / O port 241, and the second write data RDQ2 can be sent to the NVM 260 through the second switching device 245 and the second I / O port 242.

[0059] Additionally, the first write data line WDQ1 is coupled to the first I / O port 241, and the second write data line WDQ2 is coupled to the second I / O port 242. Thus, data received from the host 100 at the first I / O port 241 can be written to the memory cell of the memory device 240 via the first write data line WDQ1, or output to the NVM 260 via the second switching device 245 at the second I / O port 242. Similarly, data received from the NVM at the second I / O port 242 can be written to the memory cell of the memory device 240 via the second write data line WDQ2, or output to the host 100 via the first switching device 244 at the first I / O port 241.

[0060] Because the data is sent from the host 100 to the NVM 260 without being stored in the memory cells of the memory device 240, the operation of sending the data from the first I / O port 241 to the second I / O port 242 via the second switching device 245 can be referred to as a bypass operation. Furthermore, because the data is sent from the NVM 260 to the host 100 without being stored in the memory cells of the memory device 240, the operation of sending the data from the second I / O port 242 to the first I / O port 241 via the first switching element 244 can also be referred to as a bypass operation.

[0061] Now refer to Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9 , Figure 10A and Figure 10B This describes methods for performing data communication based on different transmission modes.

[0062] Figure 5A and Figure 5B This is a reference diagram describing data transmission when the flag signal of the first command signal CMD1 indicates the first transmission mode.

[0063] Let's refer to each other. Figure 1 , Figure 4 and Figure 5A The first command signal CMD1 received from the host 100 by the RCD 220 of the sub-memory system 200 includes a read command and a flag signal indicating a first transmission mode. Here, the flag signal indicating the first transmission mode can be "000", but the inventive concept is not limited to the details of the flag signal. Instead, the flag signal can be any arbitrary predefined signal, such as a predefined n-bit signal (n is a natural number). Alternatively, as described above, the transmission mode can be embedded in the command or sent separately from the command.

[0064] In response to the indication of the first transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to a data transmission state and the second I / O port 242 to a floating (or unused) state. Additionally, since this command is a read command, the control logic device 246 of memory device 240 generates a first control signal CTRL_1 in response to the internal memory command MCMD. This first control signal CTRL_1 causes the first switching device 244 to select the first read data line RDQ1. In this way, the first read data RDQ1 can be sent to host 100 through the first switching device 244 and the first I / O port 241. It should be understood that host 100 reads the first read data RDQ1 based on a memory address included with the first command signal CMD1 or a memory address sent separately from the first command signal CMD1.

[0065] Let's refer to each other. Figure 1 , Figure 4 and Figure 5B The first command signal CMD1 received from the host 100 by the RCD 220 of the sub-memory system 200 includes a write command and a flag signal indicating a first transmission mode.

[0066] If involved Figure 5A As in the previous example, in response to the indication of the first transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data receive state and the second I / O port 242 to floating (or unused) state. Furthermore, it is assumed here that the write command is a write to memory device 240. In this case, write data from host 100 is sent from the first I / O port 241 to the first write data line WDQ1, and is thus stored in the memory cell of memory device 240. In this example, the first switching device 244 and the second switching device 245 are not used. It should be understood that the write data is stored by host 100 at a memory address in memory device 240 that is included with the first command signal CMD1 or sent separately from the first command signal CMD1.

[0067] Figure 6A and Figure 6B This is a reference diagram illustrating data transmission when the flag signal of the first command signal CMD1 indicates the second transmission mode.

[0068] Let's refer to each other. Figure 1 , Figure 4 and Figure 6AIn this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a read command and a flag signal indicating a second transmission mode. Here, the flag signal indicating the second transmission mode can be "001", but the inventive concept is not limited to the details of the flag signal. Instead, the flag signal can be any arbitrary predefined signal, such as a predefined n-bit signal (n is a natural number). Alternatively, as described above, the transmission mode can be embedded in the command or sent separately from the command.

[0069] In response to the indication of the second transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the second I / O port 242 to a data transmission state and set the first I / O port 241 to a floating (or unused) state. Additionally, since this command is a read command, the control logic device 246 of memory device 240 generates a second control signal CTRL_2 in response to the internal memory command MCMD. This second control signal CTRL_2 causes the second switching device 245 to select the second read data line RDQ2. In this way, the second read data RDQ2 can be sent to NVM 260 through the second switching device 245 and the second I / O port 242. It should be understood that host 100 reads the second read data RDQ2 based on a memory address included with or sent separately from the first command signal CMD1.

[0070] Let's refer to each other. Figure 1 , Figure 4 and Figure 6B In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a write command and a flag signal indicating a second transmission mode.

[0071] If involved Figure 6AAs in the previous example, in response to the indication of the second transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the second I / O port 242 to data receive state and the first I / O port 241 to floating (or unused) state. Furthermore, it is assumed here that the write command is a write operation to memory device 240. In this case, write data from NVM 260 is sent from the second I / O port 242 to the second write data line WDQ2, and is thus stored in the memory cell of memory device 240. In this example, the first switching device 244 and the second switching device 245 are not used. It should be understood that the write data is stored by host 100 at a memory address in memory device 240 that is included with the first command signal CMD1 or sent separately from the first command signal CMD1.

[0072] Figure 7A and Figure 7B This is a reference diagram illustrating data transmission when the flag signal of the first command signal CMD1 indicates a third transmission mode. Since no data is read from or written to the memory cells of the memory device 240, this third transmission mode can be referred to as a bypass mode.

[0073] Let's refer to each other. Figure 1 , Figure 4 and Figure 7A In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a read command and a flag signal indicating a third transmission mode. Here, the flag signal indicating the third transmission mode can be "010", but the inventive concept is not limited to the details of the flag signal. Instead, the flag signal can be any arbitrary predefined signal, such as a predefined n-bit signal (n is a natural number). Alternatively, as described above, the transmission mode can be embedded in the command or sent separately from the command.

[0074] In response to the instruction for the third transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data transmission mode and the second I / O port 242 to data reception mode. Furthermore, since the command accompanying the third transmission mode is a read command, the control logic device 246 of memory device 240 generates a first control signal CTRL_1 in response to the internal memory command MCMD. This first control signal CTRL_1 causes the first switching device 244 to select the second I / O port 242. Additionally, control logic device 246 sends an NVM command signal ICMD to NVM 260, causing NVM 260 to transmit read data on the internal data line LDQ. In this way, read data on the internal data line LDQ of NVM 260 can be transmitted to host 100 via the second port I / O 242 of memory device 240, the first switching device 244, and the first I / O port 241. Data can be read from NVM 260 and sent to host 100 without storing the read data in the memory cells of memory device 240. That is, the memory cells of memory device 240 can be bypassed. It should be understood that host 100 reads the data based on a memory address included with or sent separately from the first command signal CMD1.

[0075] Let's refer to each other. Figure 1 , Figure 4 and Figure 7B In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a write command and a flag signal indicating a third transfer mode.

[0076] In response to the instruction for the third transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data receive mode and the second I / O port 242 to data transmit mode. Furthermore, since the command accompanying the third transmission mode is a write command, the control logic device 246 of memory device 240 generates a second control signal CTRL_2 in response to the internal memory command MCMD. This second control signal CTRL_2 causes the second switching device 245 to select the second I / O port 242. Additionally, control logic device 246 sends an NMV command signal ICMD to NVM 260, causing NVM 260 to write data transmitted on the internal data line LDQ. In this way, the write data on the external data line MDQ of host 100 can be sent to NVM 260 through the first port I / O 241 of memory device 240, the second switching device 245, and the second I / O port 242. Write data can be sent from host 100 to NVM 260 without storing the write data in the memory cells of memory device 240. That is, the memory cells of memory device 240 can be bypassed. It should be understood that host 100 writes the write data based on a memory address included with or sent separately from the first command signal CMD1.

[0077] Figure 8A and Figure 8B This is a reference diagram illustrating data transmission when the flag signal of the first command signal CMD1 indicates a fourth transmission mode. This fourth transmission mode can be considered a modification of the previously described third transmission mode. Specifically, data read from and written to the NVM 260 by the host 100 is not only bypassed at the memory device 240, but also written to the memory cells of the memory cell array (MCA) 247 of the memory device 240. The MCA 247 in the diagram represents one or more memory cell arrays of the memory device 240 and is operatively coupled to... Figure 4 The first read data line RDQ1 and the second read data line RDQ2, as well as the first write data line WDQ1 and the second write data line WDQ2, are shown.

[0078] Let's refer to each other. Figure 1 , Figure 4 and Figure 8AIn this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a read command and a flag signal indicating a fourth transmission mode. Here, the flag signal indicating the fourth transmission mode can be "011", but the inventive concept is not limited to the details of the flag signal. Instead, the flag signal can be any arbitrary predefined signal, such as a predefined n-bit signal (n is a natural number). Alternatively, as described above, the transmission mode can be embedded in the command or sent separately from the command.

[0079] In response to the instruction for the fourth transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data transmission mode and the second I / O port 242 to data reception mode. Furthermore, since the command accompanying the fourth transmission mode is a read command, the control logic device 246 of memory device 240 generates a first control signal CTRL_1 in response to the internal memory command MCMD. This first control signal CTRL_1 causes the first switching device 244 to select the second I / O port 242. Additionally, RCD 220 sends an NVM command signal ICMD to NVM 260, causing NVM 260 to transmit read data on the internal data line LDQ. In this way, the read data on the internal data line LDQ of NVM 260 can be transmitted to host 100 via the second port I / O 242 of memory device 240, the first switching device 244, and the first I / O port 241. Additionally, the same read data is simultaneously sent on the second write data line WDQ2 to write the read data to the MCA 247 of the memory device 240.

[0080] Let's refer to each other. Figure 1 , Figure 4 and Figure 8B In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a write command and a flag signal indicating a fourth transfer mode.

[0081] In response to the instruction for the fourth transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data receive mode and the second I / O port 242 to data transmit mode. Furthermore, since the command accompanying the fourth transmission mode is a write command, the control logic device 246 of memory device 240 generates a second control signal CTRL_2 in response to the internal memory command MCMD. This second control signal CTRL_2 causes the second switching device 245 to select the first I / O port 241. Additionally, RCD 220 sends an NVM command signal ICMD to NVM 260, causing NVM 260 to write data transmitted on the internal data line LDQ. In this way, the write data on the external data line MDQ of host 100 can be sent to NVM 260 through the first port I / O 241 of memory device 240, the second switching device 245, and the second I / O port 242. Write data can be sent from host 100 to NVM 260 without storing the write data in the memory cell of memory device 240. Additionally, the same read data is simultaneously sent on the first write data line WDQ1 to write the read data to MCA 247 of memory device 240.

[0082] Figure 9 This is a reference diagram illustrating data transmission when the flag signal of the first command signal CMD1 indicates the fifth transmission mode. In this example, read data from memory device 240 is simultaneously sent to host device 100 and NVM 260.

[0083] Let's refer to each other. Figure 1 , Figure 4 and Figure 9 In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a read command and a flag signal indicating a fifth transmission mode. Here, the flag signal indicating the fifth transmission mode can be "100", but the inventive concept is not limited to the details of the flag signal. Instead, the flag signal can be any arbitrary predefined signal, such as a predefined n-bit signal (n is a natural number). Alternatively, as described above, the transmission mode can be embedded in the command or sent separately from the command.

[0084] In response to the instruction of the fifth transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set both the first I / O port 241 and the second I / O port 242 to data transmission mode. Furthermore, since the command accompanying the fifth transmission mode is a read command, the control logic device 246 of memory device 240 generates a first control signal CTRL_1 in response to the internal memory command MCMD. This first control signal CTRL_1 causes the first switching device 244 to select the first read data line RDQ1 and the second switching device 245 to select the second read data line RDQ2. Additionally, RCD 220 sends an NVM command signal ICMD to NVM 260, causing NVM 260 to write data transmitted from memory device 240 on the internal data line LDQ. The first data stored in memory device 240 is read and sent to host 100 via the first read data line RDQ1, the first switching device 244, and the first I / O port 241. Similarly, the second data stored in the memory device 240 is read and sent to the NVM 260 via the second read data line RDQ2, the second switching device 245, and the second I / O port 242. The first data and the second data can be the same data or different data.

[0085] Figure 10A and Figure 10B This is a reference diagram describing data transmission when the flag signal of the first command signal CMD1 indicates the sixth transmission mode.

[0086] Let's refer to each other. Figure 1 , Figure 4 and Figure 10A In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a write command and a flag signal indicating a sixth transmission mode. Here, the flag signal indicating the sixth transmission mode can be "101", but the inventive concept is not limited to the details of the flag signal. Instead, the flag signal can be any arbitrary predefined signal, such as a predefined n-bit signal (n is a natural number). Alternatively, as described above, the transmission mode can be embedded in the command or sent separately from the command.

[0087] In response to the indication of the sixth transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data receive mode and the second I / O port 242 to data transmit mode. Furthermore, since the command accompanying the sixth transmission mode is a write command, the control logic device 246 of memory device 240 generates a second control signal CTRL_2 in response to the internal memory command MCMD. This second control signal CTRL_2 causes the second switching device 245 to select the second read data line RDQ2. Additionally, RCD 220 sends an NVM command signal ICMD to NVM 260, causing NVM 260 to write the data transmitted on the internal data line LDQ. In operation, the write data on the external data line MDQ of host 100 can be sent to and stored in the memory cells of memory device 240 via the first write data line WDQ1 coupled to the first I / O port 241. Simultaneously, stored data is read from the memory cell of memory device 240 and transmitted on the second read data line RDQ2. The read data is then transmitted to NVM 260 via the second switching device 245 and the second port I / O 242. Write data is then written to NVM 260 according to the NVM command signal ICMD received from RCD 220. These operations can overlap in time, allowing data to be transmitted simultaneously on the external data line MDQ and the internal data line LDQ.

[0088] Let's refer to each other. Figure 1 , Figure 4 and Figure 10B In this example, the first command signal CMD1 received by the RCD 220 of the sub-memory system 200 from the host 100 includes a read command and a flag signal indicating a sixth transmission mode.

[0089] In response to the indication of the sixth transmission mode, RCD 220 generates an internal memory command MCMD, which causes memory device 240 to set the first I / O port 241 to data transmission mode and the second I / O port 242 to data reception mode. Furthermore, since the command accompanying the sixth transmission mode is a read command, the control logic device 246 of memory device 240 generates a first control signal CTRL_1 in response to the internal memory command MCMD. This first control signal CTRL_1 causes the first switching device 244 to select the first read data line RDQ1. Additionally, RCD 220 sends an NVM command signal ICMD to NVM 260, causing NVM 260 to read data and transmit the read data on the internal data line LDQ. In operation, the read data on the internal data line LDQ can be transmitted to and stored in the memory cell of memory device 240 via the second write data line WDQ2 coupled to the second I / O port 242. Simultaneously, write data is read from the memory cell of memory device 240 and sent on the first read data line RDQ1. Then, the read data is sent to host 100 via the first switching device 244 and the first port I / O 241. These operations can overlap in time, allowing data to be sent simultaneously on the external data line MDQ and the internal data line LDQ.

[0090] Figure 11 This is a timing reference diagram describing the timing of the first command signal CMD1 and the data signal MDQ of the first I / O port 241 and the data signal LDQ of the second I / O port 242 in the example embodiment. In this embodiment, data is transmitted simultaneously, at least partially, on the data line MDQ and the data line LDQ. For example, this can be combined with the above. Figure 9 , Figure 10A and Figure 10B This occurs in the fifth and sixth transmission modes described.

[0091] Let's refer to each other. Figure 1 and Figure 11 The sub-memory system 200 can receive a flag signal and a data operation command (i.e., a read command or a write command) as a first command signal CMD1 during the interval between the first time point tp_1 and the second time point tp_2.

[0092] In response to the first command signal CMD1, the memory device 240 can send or receive the first data DQ1 via the data line MDQ during the time period between the second time point tp_2 and the third time point tp_3.

[0093] Furthermore, in response to the first command signal CMD1, the memory device 240 can transmit or receive the second data DQ2 via the data line LDQ during at least a portion of the time period for transmitting the first data DQ1. Although Figure 11 The illustration shows the transmission of second data DQ2 during a time period between a second time point tp_2 and a third time point tp_3, which coincides with the time period for transmitting the first data DQ1. However, the inventive concept is not limited to this. For example, the duration of transmitting the first data DQ1 may only partially overlap with the duration of transmitting the second data DQ2.

[0094] Figure 12 This is a schematic diagram of a data processing system 1000 according to an example embodiment. Except for examples showing additional details of the NVM 260 and illustrating the memory device 240 as a DRAM device, Figure 12 Implementation examples and Figure 1 The embodiments are the same. Therefore, in Figure 1 and Figure 12 Similar elements are depicted using similar reference numerals in the accompanying drawings, and repeated descriptions of these elements are omitted here to avoid redundancy.

[0095] Reference Figure 12 The NVM system 260 includes an NVM controller 1262 and an NVM device 1264 connected via an NVM channel NVM_CH.

[0096] NVM controller 1262 can control NVM device 1264. NVM controller 1262 can transmit data to DRAM device 240 based on the NVM command signal ICMD. For example, NVM controller 1262 can send data to or receive data from DRAM device 240 via data line LDQ. In one embodiment, NVM controller 1262 can provide a second command signal CMD2 to RCD 220, but the inventive concept is not limited thereto. In another embodiment, NVM controller 1262 may not provide commands to RCD 220.

[0097] NVM device 1264 can be connected to NVM controller 1262 via NVM channel NVM_CH. NVM device 1264 may include flash memory. NVM device 1264 can write or read data under the control of NVM controller 1262. As an example, NVM device 1264 may include at least one of various NVM devices, such as electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0098] Figure 13 According to the example embodiment Figure 1 and Figure 12 A schematic diagram of a register clock driver (RCD) 220. The RCD 220 may include a selector 1222, a memory command generator 1224, and an NVM command generator 1226. Further reference will be made to... Figure 1 and Figure 12 To describe Figure 13 The RCD 220.

[0099] Selector 1222 can select at least one of a first command signal CMD1 provided by host 100 and a second command signal CMD2 provided by NVM 260, and provides the selected at least one command to memory command generator 1224 and NVM command generator 1226.

[0100] The memory command generator 1224 can generate a memory command signal MCMD based on at least one selected command. The memory command generator 1224 can provide the memory command signal MCMD to the memory device 240.

[0101] NVM command generator 1226 can generate NVM command signal ICMD based on at least one selected command. NVM command generator 1226 can provide NVM command signal ICMD to NVM 260.

[0102] Figure 14 This is a diagram of a data processing system 1000 according to an example embodiment.

[0103] The data processing system 1000 may include a host 1100 and a sub-memory system 1200. The sub-memory system 1200 may include an RCD 1220, a DRAM device 1240, a selection circuit 1250, and an NVM system 1260. The RCD 1220, NVM 1260, and DRAM 1240 are the same as or similar to components with similar names in previous embodiments, and therefore detailed descriptions of these elements are omitted herein to avoid redundancy.

[0104] Figure 14The data processing system 1000 is characterized at least in part by a selection circuit 1250, which is used to simulate a communication mode with host 1100 with a bit width greater than the bit width between DRAM device 1240 and the host. For example, suppose DRAM device 1240 has eight (8x) data pins, four of which form a first I / O port 1241 and four of which form a second I / O port 1242. In this case, host 1100 performs data communication with DRAM 1240 in x4 mode. Selection circuit 1250 selectively connects NVM 1260 to the host's data line MDQ2 instead of the data line LDQ to DRAM device 1240. Assuming data line MDQ2 is four bits wide, this allows the host to selectively perform data communication in x4 mode via data line MDQ1 or in x8 mode via data lines MDQ1 and MDQ2. Note that the number of pins such as "4" and "8" are merely examples, and the inventive concept is not limited thereto.

[0105] Figure 15A and Figure 15B These are, respectively, a reference schematic diagram and a timing diagram illustrating a method for operating a data processing system according to an embodiment of the present invention. For convenience, Figure 15A The processing system 1000 is close to the timing Figure 15B As shown, and in accordance with the previously described Figure 12 The processing system shown is the same.

[0106] Figure 15B An exemplary timing diagram of data flushing from DRAM device 240 to NVM device 1264 is shown. It should be understood that this operation requires read operations on DRAM device 240 and write operations on NVM 1264. Figure 15B In this context, CK represents the clock signal, and T1 to T5 represent consecutive time periods.

[0107] First, at time T1, host 100 sends the activation command ACT as command signal CMD1 to sub-memory system 200, thus activating sub-memory system 200.

[0108] Next, at time T2, host 100 sends a read command RD as command signal CMD1 to sub-memory system 200. Additionally, although not shown, command signal CMD1 includes a flag signal indicating the transfer mode. For example, the transfer mode could be a second transfer mode, in which the second I / O port 242 is set as previously configured. Figure 6A The data transmission status is described above. In response, RCD 220 sends an internal read command (at MCMD) to DRAM device 1240.

[0109] Next, host 100 sends the write address XADR at time T3, followed by the write command XWR at time T4. As a result, RCD 220 sends the internal write command (at ICMD) to the NVM controller of NVM 260.

[0110] Next, at time T5, according to the internal read command and the internal write command, read data (RD_DATA) is sent from DRAM device 1240 through second I / O port 242 and data line LDQ as write data (XWR_DATA) stored in NVM controller 1262 of NVM 260.

[0111] As described above, an internal read command is sent to the DRAM device 240 a certain period of time before an internal write command is sent to the NVM controller 1262. According to an embodiment, this difference in time period corresponds to the difference between the read latency (RL) of the DRAM device 240 and the write latency (XWL) of the NVM 260. Figure 15B In the example, the read latency RL of DRAM device 240 is the period between time T2 and time T5 (e.g., 8 clock cycles), while the write latency XWL is the period between time T4 and time T5 (e.g., 3 clock cycles). The difference between the read latency RL and the write latency XWL is the period between T2 and T4 (e.g., 5 clock cycles). Thus, in the embodiment, an internal write command XWR is sent to NVM controller 1262 some time after an internal read command is sent to DRAM device 240, where this period corresponds to the difference between the latency RL and the latency XWL.

[0112] Note that writing data to the NVM 260 may require two write operations. The first write operation is from the DRAM device 240 to the buffer of the NVM controller 1252, and the second write operation is from the NVM controller 1252 to the NVM device 1264. (The above is a summary of the previous text.) Figure 15B The write wait time XWL mentioned refers to the write wait time for the first write operation on the NVM controller.

[0113] Advantageously, in conjunction with the above Figure 15A and Figure 15B During the described operation, the data bus of host 100 is not occupied. That is, data is transferred directly between DRAM device 240 and NVM 260.

[0114] In the case of transferring data from NVM 260 to DRAM 240, it may be desirable to have separate commands for transferring data from NVM device 1264 to NVM controller 1262 and subsequently for transferring data from NVM controller 1262 to DRAM 240. That is, in such an operation, in response to a first command from host 100, data can be read from the NVM and stored in the NVM controller, and a ready signal can then be sent externally to host 100. Then, in response to a second command from the host, an internal read command can be sent to the NVM controller, and an internal write command can be sent to the DRAM within a certain period after the internal read command is sent to the NVM controller. Then, in response to the internal read command and the internal write command, data can be transferred from the NVM controller to the DRAM. Here, this period can correspond to the difference between the read latency of the NVM controller and the write latency of the DRAM.

[0115] Figure 16A and Figure 16B These are a reference timing diagram and a flowchart, respectively, describing a method for operating a data processing system according to an embodiment of the present invention. It is assumed that the method is derived from the previously described... Figure 12 The processing system 1000 executes.

[0116] The operations shown from time T1 to time T5 are combined with the previous ones. Figure 15B The described operation is the same. That is, at S41 (T1), the host sends an ACT command via RCD 220, which activates the DRAM device 240. At S42 (T2), the host sends a read command to the DRAM device 240. At S43 (T3), the host sends the NVM write address XADR, and then at S44 (T4), it sends a write command XWR, which is applied to the NVM controller 1262 via RCD 220. As described above, the time difference between T2 and T4 corresponds to the difference between the read latency RL and the write latency XWL as described above. As a result, the data RD_DATA read from the DRAM device 240 is sent as write data XWR_DATA on the data line LDQ to the NVM controller 1262. Figure 16A As shown, these operations do not occupy the MDQ data line and therefore do not occupy the host's DQ bus.

[0117] Figure 16A and Figure 16BThe subsequent write operation from host 100 to DRAM device 240 is also illustrated. Specifically, at S46 (T6), a write command WR is sent from host 100 to DRAM device 240 via RCD 220. Although not shown, the write command WR may include the write address of DRAM device 240. Additionally, although not shown, the write command WR may be accompanied by an indication. Figure 5B The first transmission mode flag signal is used to set the first I / O port 241 to data receiving state.

[0118] After the write wait time WL of DRAM device 240, write data WR_DATA is sent on the data line MDQ to write to DRAM device 240.

[0119] Figure 17A , Figure 17B and Figure 17C This is a schematic diagram of a DRAM configuration according to an embodiment of the inventive concept.

[0120] When flushing data using the standard configuration, the host reads data from DRAM and then writes it to the NVM. This results in a relatively long DQ bus occupancy time for the host and utilizes host resources. Furthermore, in the standard configuration, only the x4 option of DRAM is used, while the remaining x4 DRAM slots remain idle. In the above embodiment, the remaining x4 DRAM slots can be used for communication with the NVM device. This... Figure 17A As shown, x4 of the DRAM is used for communication with the host, while the remaining x4 of the DRAM is used for communication with the NVM.

[0121] Furthermore, the first I / O port 241 and the second I / O port 242 in this embodiment may belong to the same DRAM chip or different DRAM chips. For example, the DRAM device 240 may be such as Figure 17B The diagram shows a stack of multi-port DRAM chips, such as multi-port DRAM chips. In this case, the multiplexer of the DRAM device 240 can be configured to be driven according to the transmission mode of the command signal, such as... Figure 17BThe first and second I / O ports of the multi-port DRAM chips can be selected as shown, or the first and second I / O ports of the same multi-port DRAM chip can be selected. Additionally, a multiplexer can be driven to simultaneously transmit first data from either the first or second I / O port of one multi-port DRAM chip in the stack to an NVM device, and second data from either the first or second I / O port of another multi-port DRAM chip in the stack to an external device. Furthermore, the multiplexer can be configured to simultaneously transmit data from the first I / O port of one multi-port DRAM chip in the stack to an NVM, and from the second I / O port of said one multi-port DRAM chip in the stack to an external device. Additionally, as... Figure 17C As shown, different DRAM chips can be used to receive data from the host, send data to the host, receive data from the NMV, and send data to the NMV.

[0122] Figure 18A and Figure 18B This is a reference timing diagram and flowchart describing an example of multiple data transfers from DRAM device 240 to NMV 260 using a single activation command ACT and address XADR.

[0123] Reference Figure 18A and Figure 18B At time T1, the activation command ACT is sent from host 100 to DRAM device 240 (S61), and at time T2a, the address XADR is sent from host 100 to NVM 260 (S62). Thereafter, continuous data transfer operations are performed from DRAM device 240 to NVM 260, each data transfer being similar to the above combined... Figure 15B The operation discussed is as follows: A first read command is sent to DRAM 240 at time T3_1, and a first write command is sent to NVM 260 at time T4_1, where the difference between time T3_1 and time T4_1 corresponds to the difference between the read latency of DRAM 240 and the write latency of NVM 260. As a result, the first read data RD1_DATA from DRAM 240 is sent to NVM 260 as the first write data XWR1_DATA on the data line LDQ. Figure 18A and Figure 18BAs shown, this process is repeated sequentially for each of the following commands: read command RD2_CMD and write command XWR2_CMD, read command RD3_CMD and write command XWR3_CMD, and read command RD4_CMD and write command XWR4_CMD. Throughout the process, the DQ bus of host 100 is not occupied.

[0124] As mentioned above, DRAM 240 can be used as a cache memory for NVM 260. Figure 19A and Figure 19B These are reference timing diagrams and flowcharts illustrating an example of such cache operation of DRAM device 240.

[0125] First, after sending the activation command ACT (Ta, S81) to the DRAM device 240, the host 100 sends a first read command RD1_CMD (Tb, S82) to the DRAM device 240. It should be understood that this command can be sent via RCD 220 along with a flag signal indicating the transmission mode as described above. Subsequently, first read data RD1_DATA is sent from the DRAM device 240 to the host 100 (Tc, S83). Figure 19B At S84, a cache hit check is assumed.

[0126] Next, the same data read process is performed for the second read command RD2_CMD (Td, S85) and the second read data RD2_DATA (Te, S86), and a cache miss is assumed at S87. In this case, the address XADR (Tf, S88) and the read command XRD_CMD (Tg, S89) are sent to the NMV 260. As described above, data can then be read from the NVM device 1264 and stored in the buffer of the NVM controller 1262. The duration for storing the read data in the NVM controller 1262 can vary considerably, so when the read data has been transferred to the buffer of the memory controller 1262, the NVM controller 1262 can send an external ready signal XR_RDY (Th, S90) to the host. In response to the ready signal XR_RDY, host 100 will send the send signal XR_SEND to controller 1262 (Ti, S91) and send the data XRD_DATA stored in the buffer of NVM controller 1262 to host 100 (Tj, S92).

[0127] Figure 20A and Figure 20B This is a reference timing diagram and flowchart describing an example of multiple data transfers from NVM 260 to DRAM 240 using a single activation ACT and address XADR.

[0128] Reference Figure 20A and Figure 20B At time Ta, address XADR is sent from host 100 to NVM 260 (S100), and at time Tb, activation command ACT is sent from host 100 to DRAM device 240 (S101). Thereafter, continuous data transfer operations are performed from NVM 260 to DRAM device 240. That is, at time Tc_1, a first read command XRD1_CMD is sent to NVM 260, and at time Td_1, a first write command is sent to DRAM 240, where the difference between time Tc_1 and time Td_1 corresponds to the difference between the read latency of NVM 260 and the write latency of DRAM 240. As a result, at time Te_1, the first read data XRD1_DATA from NVM 260 is sent as the first write data WR1_DATA on data line LDQ to DRAM 240. Figure 18A and Figure 18B As shown, this process is repeated sequentially for each of the following commands: read command XRD2_CMD and write command WR2_CMD, read command XRD3_CMD and write command WR3_CMD, and read command XRD4_CMD and write command WR4_CMD. Throughout the process, the DQ bus of host 100 is not occupied.

[0129] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a non-volatile dual in-line memory module (NVDIMM), the NVDIMM including dynamic random access memory (DRAM) and a non-volatile memory (NVM) device, the DRAM including a first input / output (I / O) port and a second I / O port, the second I / O port being connected to the NVM device, the method comprising: Receive command signals provided externally, the command signals representing read / write commands and transmission modes; The multiplexer is driven according to the transmission mode of the command signal to select at least one I / O port among the first I / O port and the second I / O port; as well as According to the read / write command of the command signal, data is read or written to at least one of the DRAM and the NVM device using at least one of the first I / O port and the second I / O port selected by driving the multiplexer. The driving of the multiplexer includes: driving the multiplexer according to the transmission mode of the command signal to select both the first I / O port and the second I / O port, and the reading or writing of data includes: using both the first I / O port and the second I / O port simultaneously, so as to exchange data simultaneously between the DRAM and the external device using the first I / O port and between the DRAM and the NVM device using the second I / O port.

2. The method according to claim 1, wherein, The multiplexer is located in the DRAM, and driving the multiplexer includes: The first switching device is driven according to the transmission mode to selectively apply data received on the second I / O port or data read from the DRAM to the first I / O port; and The second switching device is driven according to the transmission mode to selectively apply data received on the first I / O port or data received from the DRAM to the second I / O port.

3. The method according to claim 1, wherein, The command signal also includes the address of the NVM.

4. The method according to claim 1, wherein, The command signal includes one of a read command or a write command, and a flag signal indicating the transmission mode.

5. The method according to claim 1, wherein, The command signal is one of a read command or a write command that is embedded with an indication of the transmission mode.

6. The method according to claim 1, wherein, The externally provided command signal is used to flush data from the DRAM to the NVM device.

7. The method according to claim 6, further comprising: Send an internal read command to the DRAM; After a period of time following the sending of the internal read command to the DRAM, an internal write command is sent to the NVM device; as well as According to the internal read command and the internal write command, data is transferred from the DRAM to the NVM device through the second I / O port of the DRAM.

8. The method according to claim 7, wherein, The time period corresponds to the difference between the read latency of the DRAM and the write latency of the NVM device.

9. The method according to claim 8, wherein, Transferring data from the DRAM to the NVM device includes: A first write operation, in which data from the DRAM is written to the buffer of the controller of the NVM device; and A second write operation is performed in which data from the buffer is written to the non-volatile memory cell array of the NVM device. Wherein, the write wait time is the wait time for the first write operation.

10. The method according to claim 1, wherein, The DRAM is a cache memory used in the NVM device.

11. The method according to claim 1, wherein, The DRAM is a stack of multi-port DRAM chips, and the method further includes: The multiplexer is driven according to the transmission mode of the command signal to select the first I / O port and the second I / O port of each different multi-port DRAM chip, or to select the first I / O port and the second I / O port of the same multi-port DRAM chip.

12. The method according to claim 11, wherein, The multiplexer is driven to simultaneously transmit first data from a first I / O port or a second I / O port of one of the multi-port DRAM chips in the stack of multi-port DRAM chips to the NVM device, and transmit second data from a first I / O port or a second I / O port of another multi-port DRAM chip in the stack of multi-port DRAM chips to an external device.

13. The method according to claim 11, wherein, The multiplexer is driven to simultaneously transmit data from a first I / O port of one of the multiport DRAM chips in the stack of multiport DRAM chips to the NVM, and transmit the data from a second I / O port of the same multiport DRAM chip in the stack of multiport DRAM chips to an external device.

14. A method of operating a non-volatile dual in-line memory module (NVDIMM), the NVDIMM including dynamic random access memory (DRAM) and a non-volatile memory (NVM) device, the DRAM including a first input / output (I / O) port and a second I / O port, the first I / O port being connected to an external device and the second I / O port being connected to the NVM device, the method comprising: Receives externally provided read / write command signals, wherein the read / write command signals represent a read / write command and one of multiple transmission modes; as well as According to the read / write command, and in accordance with the indication of one of the multiple transfer modes, at least one of the first I / O ports and the second I / O port of the DRAM is used to read data from or write data to at least one of the DRAM and the NVM device. The various transmission modes include: In the first transmission mode, when the second I / O port of the DRAM is idle, data is exchanged between the DRAM and the external device using the first I / O port of the DRAM. In the second transmission mode, when the first I / O port of the DRAM is idle, data is exchanged between the DRAM and the NVM device using the second I / O port of the DRAM. In the third transmission mode, data is simultaneously exchanged between the DRAM and the external device using the first I / O port of the DRAM and between the DRAM and the NVM device using the second I / O port of the DRAM.

15. The method according to claim 14, wherein, The multiple transmission modes also include a fourth transmission mode, in which data is directly transmitted between the first I / O port and the second I / O port using the data path of the DRAM bypassing the memory cell of the DRAM.

16. The method according to claim 15, wherein, The multiple transmission modes further include a fifth transmission mode, in which a first data path of the DRAM bypassing the memory cell of the DRAM is used to directly transmit data between the first I / O port and the second I / O port, and a second data path of the DRAM is used to read the data from or write the data to the memory cell of the DRAM.

17. The method of claim 14, wherein, The DRAM is a cache memory used in the NVM device.

18. The method according to claim 14, wherein, The DRAM is a stack of multi-port DRAM chips.

19. The method of claim 18, further comprising: According to the transmission mode of the command signal, the first I / O port and the second I / O port of their respective multi-port DRAM chips are used.

20. A method of operating a non-volatile dual in-line memory module (NVDIMM), the NVDIMM including multi-port dynamic random access memory (DRAM) and an NVM device including a non-volatile memory (NVM) and an NVM controller, the method comprising: Receive the first command provided from outside; In response to the first command, data is read from the NVM and stored in the NVM controller; Send a ready signal to the outside of the NVDIMM; Receive a second command provided externally; In response to the second command, an internal read command is sent to the NVM controller; After a period of time following the sending of the internal read command to the NVM controller, an internal write command is sent to the DRAM; as well as In response to the internal read command and the internal write command, the data is transferred from the NVM controller to the DRAM. The DRAM includes: a first input / output I / O port connected to an external device and a second I / O port connected to the NVM. The method further includes: driving a multiplexer to select both a first I / O port and a second I / O port according to the transmission mode of an externally provided command signal; and using both the first I / O port and the second I / O port simultaneously to exchange data between the DRAM and the external device using the first I / O port and between the DRAM and the NVM device using the second I / O port.

21. The method according to claim 20, wherein, The time period corresponds to the difference between the read latency of the NVM controller and the write latency of the DRAM.

22. The method according to claim 20, wherein, The NVDIMM further includes a register clock driver, which receives a first command and a second command provided externally, and sends the internal read command and the internal write command to the NVM controller and the DRAM, respectively.

23. The method according to claim 20, wherein, The data is transferred from the NVM controller to the DRAM using the second I / O port.

24. The method of claim 23, further comprising: The data is directly transferred from the second I / O port to the first I / O port using the bypass data path of the DRAM's memory cell.

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