semiconductor packages

Abstract

A semiconductor package includes: a first substrate having a first surface and including a first electrode; a first bump pad located on the first surface of the first substrate and connected to the first electrode; a second substrate having a second surface facing the first surface of the first substrate and including a second electrode; a second bump pad located on the second surface of the second substrate and an adjacent second bump pad; and a bump structure. The second bump pad has a recessed structure recessed from a side surface of the second bump pad toward a center of the second bump pad. The second bump pad can be connected to the second electrode. The bump structure can contact the first bump pad and the second bump pad. The bump structure can have a portion protruding through the recessed structure. The adjacent second bump pad can be adjacent to the second bump pad and include a recessed structure oriented in a different direction from the recessed structure of the second bump pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0073752, filed on June 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a bump structure. Background Art

[0004] With the rapid development of the electronics industry and the growth of user needs, electronic devices are becoming more compact and multifunctional. Therefore, the necessity of miniaturization and multifunctionalization of semiconductor devices (e.g., semiconductor chips) used in electronic devices is also increasing. Semiconductor devices with fine-pitch connection terminals are necessary, and connection terminals with fine dimensions (e.g., bump structures) are required to mount high-capacity semiconductor devices in the limited structure of semiconductor packages. In addition, the distance between the bump structures included in the semiconductor packages is continuously decreasing. Summary of the Invention

[0005] Some inventive concepts provide examples of semiconductor packages in which a bump pad having a recessed structure is located under a bump structure to improve electrical characteristics and reliability.

[0006] Aspects of the inventive concept should not be limited to the above description, and other not-mentioned aspects will be clearly understood by those having ordinary skill in the art from the exemplary embodiments described herein.

[0007] According to one aspect of the inventive concept, a semiconductor package includes: a first substrate having a first surface and including a first electrode; a first bump pad located on the first surface of the first substrate; a second substrate having a second surface facing the first surface of the first substrate; a second bump pad and an adjacent second bump pad located on the second surface of the second substrate; and a bump structure. The first bump pad is connected to the first electrode. The second substrate includes a second electrode. The second bump pad has a recessed structure recessed from a side surface of the second bump pad toward a center of the second bump pad. The second bump pad is connected to the second electrode. The adjacent second bump pad is adjacent to the second bump pad and includes a recessed structure. The recessed structure of the adjacent second bump pad is oriented in a different direction than the recessed structure of the second bump pad. The bump structure contacts the first and second bump pads. The bump structure has a portion protruding through the recessed structure of the second bump pad.

[0008] According to another aspect of the present inventive concept, a semiconductor package includes: a first substrate having a first surface; a first bump pad located on the first surface of the first substrate; a second substrate having a second surface positioned opposite the first surface of the first substrate; a second bump pad and an adjacent second bump pad located on the second surface of the second substrate; and a bump structure. The second bump pad has two recessed structures, each recessed from a side surface of the second bump pad toward a center of the second bump pad. The adjacent second bump pad is adjacent to the second bump pad and includes two recessed structures. A first imaginary line extending along the two recessed structures of the second bump pad is perpendicular to a second imaginary line extending along the two recessed structures of the adjacent second bump pad. The bump structure contacts the first bump pad and the second bump pad.

[0009] According to another aspect of the present inventive concept, a semiconductor package includes: a first substrate having a first surface and including a first through-electrode; a first bump pad located on the first surface of the first substrate; a second substrate having a second surface positioned opposite the first surface of the first substrate; a second bump pad and an adjacent second bump pad located on the second surface of the second substrate; and a bump structure contacting the first bump pad and the second bump pad. The first bump pad is connected to the first through-electrode. The second substrate includes a second through-electrode and other second through-electrodes. The second bump pad has a recessed structure recessed from a side surface of the second bump pad toward a center of the second bump pad. The second bump pad is connected to the second through-electrode. The adjacent second bump pad is adjacent to the second bump pad and includes a recessed structure. The recessed structure of the adjacent second bump pad is oriented in a different direction than the recessed structure of the second bump pad. A corresponding one of the adjacent second bump pads is connected to at least two other second through-electrodes of the other second through-electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figures 1A to 1C is a diagram of a semiconductor package according to an embodiment;

[0012] Figures 2A to 2C is a diagram of a semiconductor package according to an embodiment;

[0013] Figure 3A and Figure 3B is a diagram of a semiconductor package according to an embodiment;

[0014] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment;

[0015] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment;

[0016] Figure 6 is a flowchart of a method for manufacturing a semiconductor package according to an embodiment;

[0017] 7A to 7F is a diagram showing a process sequence of a method for manufacturing a semiconductor package according to an embodiment;

[0018] Figure 8is a top view of a semiconductor module including a semiconductor package according to an embodiment; and

[0019] Figure 9 is a structural diagram of a system of a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0020] For ease of description, spatially relative terms such as "under," "beneath," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were flipped, an element described as "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "under" may encompass both the orientations of "above" and "under." The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0021] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0022] Figures 1A to 1C is a diagram of a semiconductor package 10 according to an embodiment.

[0023] Specifically, Figure 1A is a cross-sectional view of the semiconductor package 10, Figure 1B Shown Figure 1A An enlarged cross-sectional view (left) and an enlarged top view (right) of region B are shown. Figure 1C 1 is a perspective view showing the characteristics of the second bump pad 260 of the semiconductor package 10. The bump structure BS1 is Figure 1C is shown as transparent.

[0024] refer to Figures 1A to 1C , the semiconductor package 10 may include a first substrate 101 having first bump pads 130 , a second substrate 201 having second bump pads 260 , and bump structures BS1 contacting the first bump pads 130 and the second bump pads 260 , respectively.

[0025] Each of the first semiconductor device 100 and the second semiconductor device 200 included in the semiconductor package 10 may include a logic chip or a memory chip. For example, the first semiconductor device 100 and the second semiconductor device 200 may include the same type of memory chip. Alternatively, one of the first semiconductor device 100 and the second semiconductor device 200 may include a memory chip, while the other may include a logic chip.

[0026] The memory chip may include, for example, a volatile memory chip such as a dynamic random access memory (DRAM) chip or a static RAM (SRAM) chip, or a non-volatile memory chip such as a phase change RAM (PRAM) chip, a magnetoresistive RAM (MRAM) chip, a ferroelectric RAM (FeRAM) chip, or a resistive RAM (RRAM) chip. In addition, the logic chip may include, for example, a microprocessor (MP), an analog device, or a digital signal processor (DSP).

[0027] The first semiconductor device 100 may include a first substrate 101 , a first semiconductor device layer 110 , a first interconnection layer 120 , a first bump pad 130 , and a first through electrode 150 .

[0028] The first substrate 101, which may be a semiconductor substrate, may include a top surface 101T and a bottom surface 101B opposite to each other. The bottom surface 101B may be referred to as a first surface. The first substrate 101 may include a first semiconductor device layer 110 formed on the first surface 101B and a first through electrode 150 formed through the first substrate 101.

[0029] The first substrate 101 may include a silicon wafer including silicon (Si), such as crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first substrate 101 may include a semiconductor element (e.g., germanium (Ge)) or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). In addition, the first substrate 101 may have a silicon-on-insulator (SOI) structure. For example, the first substrate 101 may include a buried oxide (BOX) layer. The first substrate 101 may include a conductive region, such as a doped well or a doped structure. In addition, the first substrate 101 may have various device isolation structures, such as a shallow trench isolation (STI) structure.

[0030] The first semiconductor device layer 110 may include a first interconnect layer 120 configured to connect the plurality of semiconductor devices to other interconnects formed on the first substrate 101. The first interconnect layers 120 may each include a metal interconnect layer and a via plug. For example, the first interconnect layers 120 may each have a multi-layer structure in which at least two metal interconnect layers and at least two via plugs are alternately stacked.

[0031] The first bump pad 130 may be located on the first semiconductor device layer 110 and electrically connected to the first interconnect layer 120 in the first semiconductor device layer 110. The first bump pad 130 may be electrically connected to the first through electrode 150 through the first interconnect layer 120. The first bump pad 130 may also be considered to be on the first semiconductor device layer 110 regardless of the presence of an intermediate structure such as the first interconnect layer 120. The first bump pad 130 may include a conductive metal, such as at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), but is not limited thereto.

[0032] Although not shown, a lower passivation layer may be formed on first semiconductor device layer 110 to protect first interconnection layer 120 and other structures thereunder from external impact or moisture. The lower passivation layer may expose top surfaces of first bump pads 130.

[0033] The first through-electrodes 150 may pass through the first substrate 101 and extend from the top surface 101T of the first substrate 101 to the first surface 101B of the first substrate 101. The first through-electrodes 150 may be connected to the first interconnect layer 120 in the first semiconductor device layer 110. The first bump pads 130 may be formed on the first semiconductor device layer 110 and electrically connected to the first through-electrodes 150 through the first interconnect layer 120. At least a portion of each of the first through-electrodes 150 may have a columnar shape. The first through-electrodes 150 may each include a through-silicon via (TSV).

[0034] Although not shown, the first upper pad may be formed on the top surface 101T of the first substrate 101 and electrically connected to the first through electrode 150. The first upper pad may include substantially the same material as the first bump pad 130. In some embodiments, the first upper pad of the first substrate 101 may be substantially the same as the second bump pad 260 of the second substrate 201, which will be described below.

[0035] Although not shown, an upper passivation layer may be formed on the top surface 101T of the first substrate 101 and surround a portion of the side surface of each first through electrode 150. In some embodiments, the upper passivation layer of the first substrate 101 may be substantially the same as the upper passivation layer 240 of the second substrate 201, which will be described below.

[0036] The bump structures BS1 may contact the first bump pads 130. Through the bump structures BS1, the first semiconductor device 100 may receive at least one of a control signal, a power signal, and a ground signal for operation of the first semiconductor device 100 from the outside, receive a data signal to be stored in the first semiconductor device 100, or provide data stored in the first semiconductor device 100 to the outside. For example, each bump structure BS1 may have a columnar structure, a ball structure, or a solder layer. For example, each bump structure BS1 may have a columnar structure, a ball structure, or a solder layer.

[0037] The second semiconductor device 200 may be positioned such that a top surface 201T of the second semiconductor device 200 faces the first surface 101B of the first semiconductor device 100. The top surface 201T may be referred to as a second surface. The second semiconductor device 200 may be electrically connected to the first semiconductor device 100 via a bump structure BS1 between the first and second semiconductor devices 100 and 200.

[0038] In addition, the adhesive film F1 may be located between the first surface 101B of the first semiconductor device 100 and the second surface 201T of the second semiconductor device 200 and adhere the second semiconductor device 200 to the first semiconductor device 100. Figure 1A As shown in FIG, the adhesive film F1 may be in direct contact with the first semiconductor device 100 and the second semiconductor device 200 and surround the bump structure BS1. The adhesive film F1 may include a die-attach film (DAF). The DAF may be an inorganic adhesive or a polymer adhesive. The polymer adhesive may include one or more thermosetting resins and / or thermoplastic resins or may be a hybrid adhesive obtained by mixing a thermosetting resin with a thermoplastic resin.

[0039] The second semiconductor device 200 may include a second substrate 201, a second semiconductor device layer 210, a second interconnection layer 220, a second lower pad 230, a second through electrode 250, and a second bump pad 260. Because the second semiconductor device 200 has substantially the same characteristics as those of the first semiconductor device 100, the differences between the first semiconductor device 100 and the second semiconductor device 200 will be mainly described.

[0040] The second semiconductor device layer 210 may be a bottom surface 201B of the second semiconductor device 200. The second lower pad 230 may be located on the second semiconductor device layer 210 and electrically connected to the second interconnect layer 220 in the second semiconductor device layer 210. The second lower pad 230 may be electrically connected to the second through electrode 250 through the second interconnect layer 220. The second lower pad 230 may include substantially the same material as the first bump pad 130.

[0041] The second bump structures BS2 may contact the second lower pads 230. The second bump structures BS2 may electrically connect the semiconductor package 10 to an external base substrate (not shown). Through the second bump structures BS2, the second semiconductor device 200 may receive at least one of a control signal, a power signal, and a ground signal for operation of the second semiconductor device 200 from outside the semiconductor device 200, receive a data signal to be stored in the second semiconductor device 200, or provide data stored in the second semiconductor device 200 to the outside of the second semiconductor device 200. For example, each second bump structure BS2 may have a columnar structure, a ball structure, or a solder layer.

[0042] The second bump pad 260 may be located on the second surface 201T of the second substrate 201 and electrically connected to the second through electrode 250. The second bump pad 260 may include substantially the same material as the first bump pad 130.

[0043] Each second bump pad 260 may include a first conductive layer 261, a second conductive layer 263, and a third conductive layer 265. One of the first conductive layer 261, the second conductive layer 263, and the third conductive layer 265 may have a different thickness than the remaining layers. In addition, the first conductive layer 261, the second conductive layer 263, and the third conductive layer 265 may include different materials, or only the second conductive layer 263 may include a different material from the first conductive layer 261 and the third conductive layer 265.

[0044] In addition, each second bump pad 260 may have a recessed structure 260R that is recessed from the side surface of the second bump pad 260 toward the center thereof. In some embodiments, the recessed structures 260R of adjacent second bump pads 260 may be positioned and / or oriented in different directions. In addition, due to the recessed structure 260R, a portion of the top surface of the second through electrode 250 may be exposed by the second bump pad 260.

[0045] For example, the recessed structures 260R of adjacent second bump pads 260 may be positioned and / or oriented at a rotation angle of 90°, 180°, or 270° relative to each other. In some embodiments, each recessed structure 260R may include three sidewalls 260S adjacent to each other at right angles. When viewed from above, the first bump pad 130 may have a circular shape, while the second bump pad 260 may have a polygonal shape.

[0046] As described above, the bump structure BS1 may be in contact with the first bump pad 130 and the second bump pad 260, and each has a portion protruding through the recess structure 260R. The bump structure BS1 may respectively fill the recess structure 260R of the second bump pad 260. Therefore, the portion of the top surface of the second through electrode 250 exposed by the second bump pad 260 may be in direct contact with the bump structure BS1 and electrically connected to the bump structure BS1.

[0047] The upper passivation layer 240 may be formed on the second surface 201T of the second substrate 201 and surround a portion of the side surface of the second through electrode 250. The upper passivation layer 240 may include a first insulating layer 241, a second insulating layer 243, and a third insulating layer 245. At least one of the first insulating layer 241, the second insulating layer 243, and the third insulating layer 245 may include an etch stop film. One of the first insulating layer 241, the second insulating layer 243, and the third insulating layer 245 may have a different thickness than the remaining insulating layers. In addition, the first insulating layer 241, the second insulating layer 243, and the third insulating layer 245 may each include different materials, or only the second insulating layer 243 may include a different material from the first insulating layer 241 and the third insulating layer 245.

[0048] Here, by using the upper passivation layer 240 as an etch stop layer, a top surface of the upper passivation layer 240 may be at substantially the same level as a top surface of the second through electrode 250 .

[0049] In recent years, semiconductor packages used in electronic devices have been required to have high performance and large capacity along with miniaturization and lightweighting. To achieve high performance and large capacity along with miniaturization and lightweighting, research and development of semiconductor chips including through-electrodes and semiconductor packages stacked with semiconductor chips have been continuously conducted.

[0050] Since the thickness of the semiconductor chip is structurally reduced to achieve miniaturization and lightweight of the semiconductor package stacked with semiconductor chips, the distance between the bump structures included in the semiconductor package is also continuously reduced to enable uniform bonding of the semiconductor chips and combining of bump structures with fine sizes, and to obtain solder wettability, electrical reliability and structural reliability in the process of stacking semiconductor chips.

[0051] In a typical semiconductor package manufacturing process, during the process of bonding the upper and lower semiconductor chips facing each other under pressure using bump structures between them, if the number of bump structures protruding toward the periphery of the bump pads is excessive, the protruding portions of adjacent bump structures may bond to each other, causing a short circuit. As a result, the quality of the semiconductor package may be degraded.

[0052] In order to minimize or prevent the quality degradation of the semiconductor package 10, the second bump pad 260 having the recessed structure 260R may be below the bump structure BS1. Therefore, even under compression conditions (such as excessive pressure and / or misalignment between the first substrate 101 and the second substrate 201), the direction in which the bump structure BS1 protrudes can be guided in a desired (and / or alternatively predetermined) direction by the recessed structure 260R. In this way, the phenomenon of the protrusions of adjacent bump structures BS1 bonding to each other can be limited and / or prevented in advance, and therefore, failures such as short circuits can be limited and / or prevented. As a result, the electrical characteristics and reliability of the semiconductor package 10 can be improved.

[0053] Figures 2A to 2C is a diagram of a semiconductor package 20 according to an embodiment.

[0054] Most of the components of the semiconductor package 20 described below and the materials of these components can be the same as those in the above referenced Figures 1A to 1C Therefore, for the sake of brevity, the semiconductor package 20 will be mainly described in conjunction with the above-mentioned semiconductor package (refer to Figure 1A The difference between 10).

[0055] Specifically, Figure 2A is a cross-sectional view of the semiconductor package 20, Figure 2B Shown Figure 2A The enlarged cross-sectional view (left) and the enlarged top view (right) of region BB are shown. Figure 2C 2 is a perspective view showing the characteristics of the second bump pad 270 of the semiconductor package 20. For clarity, Figure 2C The bump structure BS1 is transparently shown in FIG.

[0056] refer to Figures 2A to 2C , the semiconductor package 20 may include a first substrate 101 having first bump pads 130 , a second substrate 201 having second bump pads 270 , and a bump structure BS1 contacting the first bump pads 130 and the second bump pads 270 .

[0057] Each second bump pad 270 may include a first conductive layer 271, a second conductive layer 273, and a third conductive layer 275. One of the first conductive layer 271, the second conductive layer 273, and the third conductive layer 275 may have a different thickness than the remaining conductive layers. In addition, the first conductive layer 271, the second conductive layer 273, and the third conductive layer 275 may include different materials, or only the second conductive layer 273 may include a different material from the first conductive layer 271 and the third conductive layer 275.

[0058] In addition, each second bump pad 270 may have two recessed structures 270R that are recessed from the side surfaces of the second bump pad 270 toward the center thereof. In some embodiments, the two recessed structures 270R of one of the adjacent second bump pads 270 may be positioned and / or oriented in different directions than the two recessed structures 270R of another second bump pad 270. In addition, due to the two recessed structures 270R, a portion of the top surface of each second through electrode 250 may be exposed by the second bump pad 270.

[0059] Specifically, the two recessed structures 270R of each second bump pad 270 may face each other toward the center of the second bump pad 270. Thus, a first virtual line 270L1 extending along the two recessed structures 270R of one second bump pad 270 may be perpendicular to a second virtual line 270L2 extending along the two recessed structures 270R of another second bump pad 270 positioned adjacent thereto. In some embodiments, both recessed structures 270R may include three sidewalls 270S adjacent to each other at right angles. Viewed from above, the first bump pad 130 may have a circular shape, while the second bump pad 270 may have an H-shape.

[0060] The number of the recessed structures of the second bump pad 270 is not limited thereto. For example, each second bump pad 270 may have at least three recessed structures, and thus the shape of the second bump pad 270 may be changed.

[0061] As described above, the bump structures BS1 may be in contact with the first bump pad 130 and the second bump pad 270, respectively, and each may have two portions protruding through the two recessed structures 270R. Each bump structure BS1 may fill the two recessed structures 270R of the second bump pad 270. Therefore, the portion of the top surface of each second through electrode 250 exposed by the second bump pad 270 may be in direct contact with the bump structure BS1 and electrically connected to the bump structure BS1.

[0062] Figure 3A and Figure 3B is a diagram of a semiconductor package 30 according to an embodiment.

[0063] Most of the components of the semiconductor package 30 described below and the materials of these components can be the same as those in the above referenced Figures 1A to 1C Therefore, for the sake of brevity, the semiconductor package 30 will be mainly described in conjunction with the above-mentioned semiconductor packages (see Figure 1A The difference between 10).

[0064] Specifically, Figure 3A is a cross-sectional view of the semiconductor package 30, Figure 3BShown Figure 3A Magnified cross-sectional view (left) and magnified top view (right) of a portion of the BBB.

[0065] refer to Figure 3A and Figure 3B , the semiconductor package 30 may include a first substrate 101 having first bump pads 130 , a second substrate 201 having second bump pads 270 , and a bump structure BS1 contacting the first bump pads 130 and the second bump pads 270 .

[0066] Each second bump pad 270 may have at least one recess structure 270R recessed from a side surface toward a center thereof. In some embodiments, recess structures 270R of adjacent second bump pads 270 may be positioned and / or oriented in different directions.

[0067] One second bump pad 270 may be connected to two second through-electrodes 252 and 254. The two second through-electrodes 252 and 254 may pass through the second substrate 201 and extend from the second surface 201T of the second substrate 201 toward its bottom surface 201B. Both second through-electrodes 252 and 254 may be connected to the second interconnect layer 220 included in the second semiconductor device layer 210. The second lower pad 230 may be formed on the second semiconductor device layer 210 and electrically connected to the two second through-electrodes 252 and 254 via the second interconnect layer 220. Although two second through-electrodes 252 and 254 are shown as examples, the number of second through-electrodes is not limited thereto. For example, at least three second through-electrodes may be stacked.

[0068] In addition, due to the orientation of the recess structure 270R, a portion of the top surfaces of the two second through electrodes 252 and 254 may not be exposed by the second bump pad 270. In other words, all of the top surfaces of the two second through electrodes 252 and 254 may be covered by the second bump pad 270, and the bump structure BS1 may not be in direct contact with the two second through electrodes 252 and 254.

[0069] The semiconductor package 30 may be a high bandwidth memory (HBM). The HBM may include multiple channels with interfaces, the multiple channels being independent of each other and having increased bandwidth. Therefore, the HBM may include relatively increased through-electrodes. For example, each core die included in the HBM may include two channels, the two channels corresponding to the two second through-electrodes 252 and 254, respectively. However, the inventive concept is not limited thereto.

[0070] Figure 4 is a cross-sectional view of a semiconductor package 40 according to an embodiment.

[0071] Most of the components of the semiconductor package 40 described below and the materials of these components can be the same as those in the above referenced Figures 1A to 1C Therefore, for the sake of brevity, the semiconductor package 40 and the semiconductor package described above (see Figure 1A The difference between 10).

[0072] refer to Figure 4 , the semiconductor package 40 may include a first substrate 101 having first bump pads 130 , a second substrate 201 having second bump pads 260 , and a third substrate 301 having third bump pads 360 .

[0073] The first semiconductor device 100, the second semiconductor device 200, and the third semiconductor device 300 included in the semiconductor package 40 may each include a logic chip or a memory chip. For example, the first semiconductor device 100, the second semiconductor device 200, and the third semiconductor device 300 may include the same type of memory chip. Alternatively, some of the first semiconductor device 100, the second semiconductor device 200, and the third semiconductor device 300 may include a memory chip, and the others may include a logic chip.

[0074] although Figure 4 Only the first semiconductor device 100 , the second semiconductor device 200 , and the third semiconductor device 300 are shown stacked in the semiconductor package 40 , but the number of semiconductor devices stacked in the semiconductor package 40 is not limited thereto. For example, at least four semiconductor devices may be stacked in the semiconductor package 40 .

[0075] The first semiconductor device 100 may include a first substrate 101, a first semiconductor device layer 110, a first interconnect layer 120, and a first bump pad 130. Unlike the second semiconductor device 200 and the third semiconductor device 300, the first semiconductor device 100 may not include a through-electrode. Unlike the second semiconductor device 200 and the third semiconductor device 300, the first semiconductor device 100 may not include a through-electrode.

[0076] The third semiconductor device 300 may include a third substrate 301, a third semiconductor device layer 310, a third interconnection layer 320, a third lower pad 330, a third through electrode 350, and a third bump pad 360. The third semiconductor device 300 may have substantially the same characteristics as those of the second semiconductor device 200.

[0077] The third semiconductor device 300 may be positioned such that a top surface 301T of the third semiconductor device 300 faces a bottom surface 201B of the second semiconductor device 200 . The third semiconductor device 300 may be electrically connected to the second semiconductor device 200 through a second bump structure BS2 therebetween.

[0078] In addition, the second adhesive film F2 may be located between the bottom surface 201B of the second semiconductor device 200 and the top surface 301T of the third semiconductor device 300 and adhere the third semiconductor device 300 to the second semiconductor device 200. Figure 4 As shown in FIG, the second adhesive film F2 may be in direct contact with the second and third semiconductor devices 200 and 300 and surround the second bump structure BS2. The second adhesive film F2 may be substantially the same as the adhesive film F1.

[0079] The third bump structures BS3 may respectively contact the third lower pads 330. The third bump structures BS3 may electrically connect the semiconductor package 40 to an external base substrate (not shown). Via the third bump structures BS3, the third semiconductor device 300 may receive at least one of a control signal, a power signal, and a ground signal for operation of the third semiconductor device 300 from outside the semiconductor package, receive a data signal to be stored in the third semiconductor device 300, or provide data stored in the third semiconductor device 300 to the outside of the semiconductor package. Each of the third bump structures BS3 may have a columnar structure, a ball structure, or a solder layer.

[0080] Each third bump pad 360 may have a recessed structure 360R that is recessed from the side surface of the third bump pad 360 toward the center thereof. In some embodiments, the recessed structures 360R of adjacent third bump pads 360 may be positioned and / or oriented in different directions. In addition, due to the recessed structure 360R, a portion of the top surface of the third through electrode 350 may be exposed by the third bump pad 360.

[0081] As described above, the second bump structure BS2 may be in contact with the second lower pad 230 and the third bump pad 360, respectively, and each may have a portion protruding through the recessed structure 360R. The second bump structure BS2 may fill the recessed structure 360R of the third bump pad 360, respectively. Therefore, the portion of the top surface of the third through electrode 350 exposed by the third bump pad 360 may be in direct contact with the second bump structure BS2 and electrically connected to the second bump structure BS2. In addition, the second bump structure BS2 may be connected to the two second through electrodes ( Figure 3A and Figure 3B 252 and 254).

[0082] Figure 5 is a cross-sectional view of a semiconductor package 50 according to an embodiment.

[0083] Most of the components of the semiconductor package 50 described below and the materials of these components can be the same as those in the above referenced Figures 1A to 1C Therefore, for the sake of brevity, the semiconductor package 50 will be mainly described in conjunction with the semiconductor package described above (see Figure 1A The difference between 10).

[0084] refer to Figure 5 , the semiconductor package 50 may include a first substrate 101 having first bump pads 130 , a package substrate 400 having second bump pads 460 , and bump structures BS1 contacting the first bump pads 130 and the second bump pads 460 , respectively.

[0085] The package substrate 400 as a supporting substrate may include a main body unit 401, an upper protective layer, and a lower protective layer. The package substrate 400 may be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, or a glass substrate. In the semiconductor package 50 according to this embodiment, the package substrate 400 may include a PCB.

[0086] In addition, an interconnection 420 may be formed on the package substrate 400. The interconnection 420 may be electrically connected to the first semiconductor device 100 through a bump structure BS1 connected to a second bump pad 460 formed on the top surface 401T of the package substrate 400.

[0087] Each second bump pad 460 may have a recessed structure 460R that is recessed from a side surface toward a center of the second bump pad 460. In some embodiments, the recessed structures 460R of adjacent second bump pads 460 may be positioned and / or oriented in different directions.

[0088] External connection terminals BS4 may be located on lower electrode pads 430 positioned on bottom surface 401B of package substrate 400. Semiconductor package 50 may be electrically connected to and mounted on a module substrate or system board of an electronic product through external connection terminals BS4.

[0089] Specifically, an interconnection 420 having a single or multi-layer structure may be formed in the body unit 401, and the external connection terminal BS4 may be electrically connected to the first semiconductor device 100 through the interconnection 420. The upper and lower protective layers may protect the body unit 401 and include, for example, solder resist.

[0090] When the package substrate 400 includes a PCB, the formation of the main body unit 401 may generally include forming a thin film by the following steps: forming a polymer material (e.g., thermosetting resin), an epoxy resin (e.g., flame retardant 4 (FR-4), bismaleimide triazine (BT), and ajinomoto The film is compressed to a uniform thickness using an ABF (Aluminum Alloy Fiber) or phenolic resin; both sides of the film are coated with copper foil; and patterning is performed to form interconnects 420. Interconnects 420 can be a transmission path for electrical signals. In addition to the lower electrode pads 430 and the second bump pads 460, the entire top and bottom surfaces of the main body unit 401 may also be coated with solder resist to form upper and lower protective layers.

[0091] The PCB can be a single-sided PCB with interconnects 420 formed on only one surface, or a double-sided PCB with interconnects 420 formed on both surfaces. Furthermore, an insulator such as prepreg can be used to form at least three copper foil layers, and at least three interconnects 420 can be formed depending on the number of copper foil layers formed. Thus, a PCB having a multilayer structure can be realized. However, package substrate 400 is not limited to the above-described structure or material of the PCB.

[0092] The molding member MB can protect the first semiconductor device 100 from external influences such as contamination and impact. To perform the above functions, the molding member MB can be formed to a thickness that completely covers at least the first semiconductor device 100. Because the molding member MB completely covers the package substrate 400, the width of the molding member MB can be substantially equal to the width of the semiconductor package 50.

[0093] In addition, the molding member MB may include, for example, epoxy molding compound (EMC). However, the molding member MB is not limited to EMC and may include various materials, for example, epoxy-based materials, thermosetting materials, thermoplastic materials, or ultraviolet (UV) curing materials.

[0094] An underfill (UF) may be formed between the first semiconductor device 100 and the package substrate 400. A gap may be formed between the first semiconductor device 100 and the package substrate 400. Because this gap may cause reliability issues in the connection between the first semiconductor device 100 and the package substrate 400, the underfill (UF) may be injected to strengthen the connection between the first semiconductor device 100 and the package substrate 400. In some cases, the underfill (UF) may be omitted, and a molded underfill (MUF) process may be used instead of the underfill (UF).

[0095] Figure 6 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment.

[0096] refer to Figure 6 , the method S10 of manufacturing a semiconductor package may include a first operation (S110) of positioning a second substrate synonymous with a lower substrate, a second operation (S120) of forming a mask pattern on the second substrate, a third operation (S130) of forming a second bump pad on the second substrate, a fourth operation (S140) of removing the mask pattern from the second substrate, a fifth operation (S150) of adhering an adhesive film to the second substrate, and a sixth operation (S160) of connecting the first substrate (e.g., upper substrate) to the second substrate using a bump structure.

[0097] The method S10 for manufacturing a semiconductor package may include the above-described operations S110 to S160. When some embodiments can be implemented in other ways, the corresponding process operations described herein may be performed in other ways. For example, two process operations described in a sequential order may be performed substantially simultaneously or in reverse order.

[0098] Will be referenced below 7A to 7F Technical characteristics of each of the first to sixth operations S110 to S160 are described in detail.

[0099] 7A to 7F 1 is a diagram illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention in order of processes.

[0100] refer to Figure 7A , a second semiconductor device 200 may be prepared. The semiconductor device 200 may include a second through-electrode 250 capable of extending an integrated circuit (IC) function of the second semiconductor device layer 210 formed on the second substrate 201 to the outside.

[0101] The second semiconductor device 200 may include a plurality of second through-electrodes 250. Generally, the methods for forming the second through-electrodes 250 may include a via-first method, a via-middle method, and a via-last method. The via-first method may refer to a method in which the second through-electrodes 250 are formed before forming an IC of the semiconductor device. The via-middle method may refer to a method in which the second through-electrodes 250 are formed after forming the IC of the semiconductor device and before forming an interconnect layer. The via-last method may refer to a method in which the second through-electrodes 250 are formed after forming an interconnect layer.

[0102] For example, in the via-last method, a second semiconductor device layer 210 and a second interconnect layer 220 may be formed on the bottom surface 201B of the second substrate 201, and a second through-electrode 250 may be formed to pass through the second substrate 201 from the top surface 201T of the second substrate 201 to the bottom surface 201B of the second substrate 201.

[0103] refer to Figure 7B, a mask pattern M1 may be formed on the second surface 201T of the second substrate 201 .

[0104] A mask pattern M1 may be formed on the second surface 201T of the second substrate 201 using a photolithography process and a development process. The mask pattern M1 may be formed in a pattern exposing a portion of the second through electrode 250 and a portion of the upper passivation layer 240.

[0105] The area of ​​the second surface 201T exposed by the mask pattern M1 may correspond to the second bump pad ( Figure 7C 260) in direct contact area.

[0106] refer to Figure 7C , second bump pads 260 may be formed on the top surface of the second substrate 201 to fill the holes M1H of the mask pattern M1.

[0107] The second bump pad 260 may include a first conductive layer 261, a second conductive layer 263, and a third conductive layer 265. The second bump pad 260 may be formed using a deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), but the inventive concept is not limited thereto.

[0108] The second bump pad 260 may include, but is not limited to, at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0109] The second bump pad 260 may be in direct contact with the second through electrode 250 and electrically connected to the second through electrode 250 .

[0110] refer to Figure 7D , the mask pattern can be removed (refer to Figure 7C M1 in the embodiment of the present invention) to form a second bump pad 260 having a recessed structure 260R.

[0111] A stripping process and / or an ashing process may be performed to remove the mask pattern (refer to Figure 7C M1 in ).

[0112] Each second bump pad 260 may have a recessed structure 260R that is recessed from the side surface of the second bump pad 260 toward the center thereof. In some embodiments, the recessed structures 260R of adjacent second bump pads 260 may be positioned and / or oriented in different directions. In addition, due to the recessed structure 260R, a portion of the top surface of the second through electrode 250 may be exposed by the second bump pad 260.

[0113] refer to Figure 7E, the adhesive film F1 may be formed to completely cover the top surface 201T of the second substrate 201 and the second bump pads 260 .

[0114] like Figure 7E As shown in FIG, the adhesive film F1 may be in direct contact with the second semiconductor device 200 and surround the second bump pad 260. The adhesive film F1 may include DAF.

[0115] refer to Figure 7F , the first surface 101B of the first semiconductor device 100 may be disposed opposite to the top surface 201T of the second semiconductor device 200 between the upper pressing plate 500T and the lower supporting plate 500B.

[0116] Due to the pressure CP applied to the upper pressing plate 500T, the second semiconductor device 200 may displace the adhesive film F1 and may be electrically connected to the first semiconductor device 100 through the bump structure BS1 disposed between the first and second semiconductor devices 100 and 200 .

[0117] The upper pressing plate 500T may be connected to a robot arm (not shown), and the lower supporting plate 500B may be a table-type. Therefore, the pressure applied to the first semiconductor device 100 and the second semiconductor device 200 may vary according to the arrangement and shape of the upper pressing plate 500T and the lower supporting plate 500B.

[0118] Return Reference Figure 1A In the semiconductor package 10 according to this embodiment, the second bump pad 260 having the recessed structure 260R can be disposed below the bump structure BS1. Therefore, even under compressive conditions (such as excessive pressure and / or misalignment between the first substrate 101 and the second substrate 201), the recessed structure 260R can guide the protrusion of the bump structure BS1 in a desired (and / or alternatively predetermined) direction. Consequently, the electrical characteristics and reliability of the semiconductor package 10 can be improved.

[0119] Figure 8 is a top view of a semiconductor module 1000 including a semiconductor package 1020 according to an embodiment.

[0120] refer to Figure 8 The semiconductor module 1000 may include a module substrate 1010 , a plurality of semiconductor packages 1020 and a controller chip 1030 mounted on the module substrate 1010 , and a notch structure 1040 and a port 1050 located on an edge of the module substrate 1010 .

[0121] The module substrate 1010 may be a support substrate on which a plurality of semiconductor packages 1020 and a controller chip 1030 are mounted. The module substrate 1010 may be a printed circuit board (PCB) having a desired (and / or alternatively predetermined) form factor. The form factor may define the thickness and top, bottom, left, and right widths of the module substrate 1010.

[0122] The plurality of semiconductor packages 1020 may include a semiconductor package according to a reference Figures 1A to 5 Any of the semiconductor packages 10 to 50 of the described embodiments. A plurality of semiconductor packages 1020 may be electrically connected to the port 1050 through interconnects (not shown) included in the module substrate 1010 .

[0123] The controller chip 1030 may control the plurality of semiconductor packages 1020. For example, the controller chip 1030 may read data stored in the plurality of semiconductor packages 1020 or program new data to the plurality of semiconductor packages 1020 in response to a command from an external host.

[0124] At least one notch structure 1040 may be included in the semiconductor module 1000 so that the module substrate 1010 may be mounted on and fixed to a main board or a system board.

[0125] The port 1050 may include a plurality of pins, and the number, size, and arrangement of the pins may be determined based on an interface protocol configured to communicate with an external host. The plurality of pins may be connected to a socket included in a main board or a system board.

[0126] Figure 9 is a configuration diagram of a system 1100 of a semiconductor package according to an embodiment.

[0127] refer to Figure 9 , the system 1100 may include a controller 1110 , an input / output (I / O) device 1120 , a memory 1130 , an interface 1140 , and a bus 1150 .

[0128] System 1100 may include a mobile system or a system configured to send or receive information. In some embodiments, the mobile system may be a portable computer, a netbook, a mobile phone, a digital music player, or a memory card.

[0129] The controller 1110 may be configured to control an execution program in the system 1100 and include an MP, a DSP, a microcontroller (MC), or a device similar thereto.

[0130] The I / O device 1120 may be used to input data to or output data from the system 1100. The system 1100 may be connected to an external device (e.g., a personal computer (PC) or a network) and exchange data with the external device using the I / O device 1120. The I / O device 1120 may include, for example, a touch panel, a keyboard, or a display device.

[0131] The memory 1130 may store data used for the operation of the controller 1110 or store data processed by the controller 1110. The memory 1130 may include a memory according to a reference Figures 1A to 5 Any of the semiconductor packages 10 to 50 of the described embodiments.

[0132] The interface 1140 may be a data transmission path between the system 1100 and external devices. The controller 1110 , the I / O device 1120 , the memory 1130 , and the interface 1140 may communicate with each other through a bus 1150 .

[0133] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first substrate having a first surface and comprising a first electrode; a first bump pad, the first bump pad being located on the first surface of the first substrate and connected to the first electrode; a second substrate having a second surface facing the first surface of the first substrate, the second substrate including a second electrode; a second bump pad and adjacent second bump pads located at the left and right sides of the second bump pad, the second bump pad and the adjacent second bump pads being located on the second surface of the second substrate, the second bump pad having a recessed structure recessed from a side surface of the second bump pad toward a center of the second bump pad, the second bump pad being connected to the second electrode, each of the adjacent second bump pads being adjacent to the second bump pad and including a recessed structure, the recessed structure of each of the adjacent second bump pads being oriented in a different direction from the recessed structure of the second bump pad; as well as A bump structure contacts the first bump pad and the second bump pad, the bump structure having a portion protruding through the recess structure of the second bump pad.

2. The semiconductor package according to claim 1, wherein The bump structure fills the recessed structure of the second bump pad.

3. The semiconductor package according to claim 2, wherein a portion of the second electrode is exposed by the recessed structure of the second bump pad to provide an exposed portion of the second electrode, Wherein, the exposed portion of the second electrode contacts the bump structure.

4. The semiconductor package according to claim 1, wherein The recessed structure of each of the adjacent second bump pads is oriented at a rotation angle of 90°, 180°, or 270° relative to the recessed structure of the second bump pad.

5. The semiconductor package according to claim 1, wherein The recessed structure of the second bump pad includes three sidewalls adjacent to each other at right angles.

6. The semiconductor package according to claim 1, wherein The first bump pad has a circular shape in a top view; and The second bump pad has a polygonal shape in a top view.

7. The semiconductor package according to claim 1, further comprising: An adhesive film surrounds the first bump pad, the second bump pad, and the bump structure.

8. The semiconductor package according to claim 1, wherein The first electrode and the second electrode each include a through-silicon via.

9. The semiconductor package according to claim 1, wherein The first substrate comprises a semiconductor substrate; and The second substrate includes a printed circuit board.

10. The semiconductor package according to claim 1, further comprising: a third substrate having a third surface facing a surface opposite to the second surface of the second substrate, the third substrate including a third electrode; a third bump pad and an adjacent third bump pad, the third bump pad and the adjacent third bump pad being located on the third surface of the third substrate, the third bump pad having a recessed structure oriented in one direction, the third bump pad being connected to the third electrode, the adjacent third bump pad being adjacent to the third bump pad and including a recessed structure, the recessed structure of the adjacent third bump pad being oriented in a different direction than the recessed structure of the third bump pad; as well as Another bump structure contacts the third bump pad, the another bump structure having a portion protruding through the recessed structure of the third bump pad.

11. A semiconductor package, comprising: a first substrate having a first surface; a first bump pad, the first bump pad being located on the first surface of the first substrate; a second substrate having a second surface positioned opposite the first surface of the first substrate; a second bump pad and an adjacent second bump pad, the second bump pad and the adjacent second bump pad being located on the second surface of the second substrate, the second bump pad having two recessed structures, the two recessed structures each being recessed from a side surface of the second bump pad toward a center of the second bump pad, the adjacent second bump pad being adjacent to the second bump pad and including two recessed structures, and a first imaginary line extending along the two recessed structures of the second bump pad being perpendicular to a second imaginary line extending along the two recessed structures of the adjacent second bump pad; and A bump structure contacts the first bump pad and the second bump pad.

12. The semiconductor package according to claim 11, wherein A portion of the second surface of the second substrate is exposed by the two recessed structures of the second bump pad to provide an exposed portion of the second surface of the second substrate, The bump structure fills the two recessed structures of the second bump pad, and The exposed portion of the second surface contacts the bump structure.

13. The semiconductor package according to claim 12, wherein The bump structure protrudes through the two recessed structures of the second bump pad.

14. The semiconductor package according to claim 11, wherein The two recessed structures of the second bump pad face each other toward the center of the second bump pad.

15. The semiconductor package according to claim 14, wherein The first bump pad has a circular shape in a top view, and The second bump pad has an H shape in a top view.

16. A semiconductor package, comprising: a first substrate having a first surface and comprising a first through electrode; a first bump pad, the first bump pad being located on the first surface of the first substrate and connected to the first through-electrode; a second substrate having a second surface positioned opposite to the first surface of the first substrate, the second substrate including a second through-electrode and other second through-electrodes; a second bump pad and an adjacent second bump pad, the second bump pad and the adjacent second bump pad being located on the second surface of the second substrate, the second bump pad having a recessed structure recessed from a side surface of the second bump pad toward a center of the second bump pad, the second bump pad being connected to the second through-electrode, the adjacent second bump pad being adjacent to the second bump pad and including a recessed structure, the recessed structure of the adjacent second bump pad being oriented in a different direction from the recessed structure of the second bump pad, a corresponding one of the adjacent second bump pads being connected to at least two other second through-electrodes among the other second through-electrodes; and A bump structure contacts the first bump pad and the second bump pad.

17. The semiconductor package according to claim 16, wherein The second bump pad has at least one recessed structure.

18. The semiconductor package according to claim 17, wherein The at least one recessed structure of the second bump pad includes two recessed structures; and A first imaginary line extending along the two recess structures of the second bump pad is perpendicular to a second imaginary line extending along the two recess structures of the corresponding one of the adjacent second bump pads.

19. The semiconductor package according to claim 16, wherein The second through electrode is not exposed by the recessed structure of the second bump pad, and The bump structure does not directly contact the second through-electrode.

20. The semiconductor package according to claim 16, wherein The first substrate and the second substrate include semiconductor devices; and The semiconductor device includes a high bandwidth memory.

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