Integrated circuit device and method for forming the same

Abstract

An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes a first active area and a first gate in the gate. The first transistor has a first threshold voltage (VT). A second transistor includes a first active area and a second gate in the gate. The second transistor has a second VT different from the first VT. A knotted transistor is located between the first transistor and the second transistor and includes a first active area and a third gate in the gate, wherein the third gate is connected to the first power rail. Embodiments of the present invention also relate to methods of forming an integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit devices and methods of forming the same. Background Art

[0002] A vertical semiconductor device such as a fin-based metal oxide semiconductor field effect transistor (FinFET) is a three-dimensional structure on the surface of a semiconductor substrate. The fin extends upward from the body of the substrate and may be formed by depositing fin material on the substrate, etching non-fin regions of the substrate, or a combination thereof. The channel of the FET is formed in this vertical fin, and a gate is provided above (e.g., wrapped around) the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate, and allows the gate to control the channel from both sides. As integrated circuit devices become smaller, the spacing or "pitch" between devices may cause electromagnetic interference between adjacent devices.

[0003] Adjacent devices such as FinFETs can be electrically isolated, where adjacent transistors can be used as isolation devices. Such isolation devices can be referred to as "tied" devices, where the active region of the knotted device is set to an off state. The gate of the isolation device ("tied gate") can be biased to place the isolation device in an off state and provide isolation for adjacent active devices. Summary of the invention

[0004] An embodiment of the present invention provides an integrated circuit device, comprising: a first power rail; a first active area extending in a first direction; a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction; a first transistor comprising the first active area and a first gate in the gates, the first transistor having a first threshold voltage (VT); a second transistor comprising the first active area and a second gate in the gates, the second transistor having a second threshold voltage different from the first threshold voltage; and a knotted transistor located between the first transistor and the second transistor, the knotted transistor comprising the first active area and a third gate in the gates, wherein the third gate is connected to the first power rail.

[0005] Another embodiment of the present invention provides an integrated circuit device, comprising: a first power rail; a second power rail; a first fin extending in a first direction; a first P-type metal oxide semiconductor transistor, comprising the first fin and a first gate, the first P-type metal oxide semiconductor transistor having a first threshold voltage (VT), the first gate extending in a second direction perpendicular to the first direction; a second P-type metal oxide semiconductor transistor, comprising the first fin and a second gate extending in the second direction, the second P-type metal oxide semiconductor transistor having a second threshold voltage different from the first threshold voltage, and wherein the second gate is connected to the first power rail; a second fin extending in the first direction; a first N-type metal oxide semiconductor transistor, comprising the second fin and the first gate, the first N-type metal oxide semiconductor transistor having the first threshold voltage; a second N-type metal oxide semiconductor transistor, comprising the second fin and the second gate, the second N-type metal oxide semiconductor transistor having the second threshold voltage, and wherein the second gate is connected to the second power rail.

[0006] Another embodiment of the present invention provides a method for forming an integrated circuit device, comprising: forming a first active region on a substrate, wherein the first active region includes a first threshold voltage (VT) region and a second threshold voltage region; forming a first gate, the first gate contacts the first threshold voltage region of the first active region to form a first transistor having a first threshold voltage; forming a second gate, the second gate contacts the second threshold voltage region of the first active region to form a second transistor having a second threshold voltage different from the first threshold voltage; forming a third gate, the third gate contacts the first active region between the first gate and the second gate to form a knotted transistor between the first transistor and the second transistor; and connecting the third gate to a power rail to keep the knotted transistor in a disconnected state. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a block diagram illustrating an example of a semiconductor device according to some embodiments.

[0009] Figure 2 is a diagram showing a method according to some embodiments Figure 1 A block diagram of example metal layers of a semiconductor device is shown.

[0010] Figure 3 is a block diagram illustrating an example FinFET device according to some embodiments.

[0011] Figure 4 is a block diagram illustrating an example semiconductor device according to some embodiments.

[0012] Figure 5 is a block diagram illustrating another example semiconductor device according to some embodiments.

[0013] Figure 6 is a block diagram illustrating another example semiconductor device according to some embodiments.

[0014] Figure 7 is a block diagram illustrating yet another example semiconductor device according to some embodiments.

[0015] Figure 8 is a block diagram illustrating another example semiconductor device according to some embodiments.

[0016] Fig. 9 is a block diagram illustrating another example semiconductor device according to some embodiments.

[0017] Fig.10 is a block diagram illustrating another example semiconductor device according to some embodiments.

[0018] Fig.11 is a flow chart illustrating an example of a method according to some embodiments.

[0019] Fig.12 is a block diagram illustrating aspects of an example of an electronic design automation (EDA) system in accordance with some embodiments.

[0020] Fig.13 is a block diagram illustrating aspects of an example of an IC manufacturing system and manufacturing flow in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relationship terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relationship descriptors used herein should be interpreted accordingly.

[0023] Multi-threshold voltage IC devices are sometimes used to optimize delay or power in various circuits and devices. A multi-threshold voltage IC device may include several different devices, each device having a different threshold voltage (i.e., operating voltage). For example, a multi-threshold voltage IC device may include two or more of a low threshold voltage (LVT) device, a standard threshold voltage (SVT) device, and a high threshold voltage (HVT) device.

[0024] Adjacent devices including adjacent multi-threshold IC devices (such as multi-threshold FinFETs) can be electrically isolated using one or more isolation devices. Such isolation devices can be referred to as "knotted" devices. In some examples, the transistor is configured as an isolation device, wherein the active region of the knotted device is set to an off state. The gate of the isolation device ("knotted gate") can be biased to place the isolation device in an off state and provide isolation for adjacent active devices. For example, the knotted device can be located at the threshold voltage (VT) boundary between the devices.

[0025] According to some disclosed embodiments, a polysilicon gate for a knotted transistor is located at a VT boundary of a hybrid VT structure. The transistor can be tied by a conductive via connecting the polysilicon gate to a power rail, thereby keeping the device in an off state. Positioning the polysilicon gate at the VT boundary and connecting the polysilicon gate directly to the power rail through a via can save device area.

[0026] Figure 1 is a block diagram illustrating a cross-section of an example semiconductor structure 10 according to some embodiments. Figure 1 The structure 10 is shown in the X-axis and Z-axis directions, while the Y-axis direction is Figure 1 The planes of the cross-sections shown are orthogonal. The structure 10 includes a base layer 12 and an interconnect layer 14.

[0027] Typically, the base layer 12 includes a semiconductor substrate, which in turn includes a polysilicon region (also referred to as "polysilicon" throughout the present invention), a diffusion region, a semiconductor well (e.g., an N-well, a P-well, a deep N-well, a deep P-well), etc., in which semiconductor devices (e.g., transistors, diodes, etc.) are formed. The interconnect layer 14 includes N (e.g., an integer number) of conductive layers (e.g., metal layers M1 to MN), which are used to interconnect devices within the layers in the interconnect layer 120 and to form electrical connections with external devices, etc. The interconnect layer 14 typically includes vias, interlayer dielectric materials, passivation layers, bonding pads, packaging resources, etc. Each metal (e.g., conductive) layer M in the interconnect layer 14 is typically referred to as a metal one, metal two, metal three (M1, M2, M3, etc.) layer, etc. Between each metal layer M is a dielectric material (e.g., high-K, low-K material, etc.) 16 for insulating the metal layer M. The substrate layer 12 and the interconnect layer 14 are often referred to as front-end structures and back-end structures, respectively, because they are the “front end of the line” (FEOL) and “back end of the line” (BEOL), respectively, in the semiconductor manufacturing process.

[0028] Figure 2 is a block diagram illustrating an example interconnect metal layer structure 20 according to some embodiments. The metal layer structure 20 includes a plurality of conductive layers M (e.g., M1, M2, M3, etc.). In the illustrated embodiment, the metal layer structure 20 only shows two layers (e.g., M2 and M3). Metal layer structures with different numbers of layers (e.g., from 1 to N layers) are within the scope of the disclosed embodiments.

[0029] exist Figure 2 In the illustrated embodiment, each metal layer M includes a plurality of metal strips MB, for example, metal strips MB21, MB22, and MB23 in layer M2 and metal strips MB31, MB32, and MB33 in layer M3. In some embodiments, the shape of the metal strips is cylindrical or some other shape, and can be any cross-sectional shape. In the illustrated embodiment, each metal strip MB in layer M is substantially parallel to each other. In the illustrated embodiment, each metal layer M2 and M3 includes three metal strips MB, however, configurations in which each metal layer M has a different number of metal strips MB are within the scope of the disclosed embodiments. In some embodiments, a first group of metal strips MB (e.g., metal strips MB in metal layers M1, M3, M5, etc.) extend in a first direction (e.g., an X-axis direction), while a second group of metal strips MB (e.g., in metal layers M2, M4, M6, etc.) extend in a second direction (e.g., a Y-axis direction), wherein the X-axis direction is perpendicular to the Y-axis direction. Different configurations in which all bars MB extend in one direction (e.g., the X-axis direction, the Y-axis direction, or any other convenient direction or combination of directions (including non-vertical directions)) are within the scope of the disclosed embodiments. Figure 2In the illustrated embodiment, each metal strip MB has a width Wbar. In some embodiments, all widths Wbar have the same size, but the disclosed embodiments are not limited to this configuration. Depending on design choices, the widths Wbar may have different sizes (e.g., one width Wbar may be shorter / larger than another). Two adjacent metal strips MB are spaced or separated by a distance, such as a distance D. In some embodiments, the distance D is selected to meet the minimum spacing requirement between two metal strips MB to form a capacitor between the two strips. In some embodiments, all distances D in the metal layer structure 20 have the same size, but the disclosed embodiments are not limited to this configuration. That is, the distances D may have different sizes (e.g., one distance D may be shorter / longer than another distance). The thickness of the metal strips MB in the layer M is proportional to the thickness of the layer M, which may depend on the process technology, and different groups of layers M may have different thicknesses. For example, a first group of metal layers M (e.g., Mx) may have a first thickness, a second group of metal layers M (e.g., My) may have a second thickness, and a third group of metal layers (e.g., Mz) may have a third thickness, etc., where the first, second, and third thicknesses are different. In the illustrated embodiment, the metal layer structure 20 has a width W and a length L.

[0030] Figure 3 is a block diagram illustrating a cross-section of an example semiconductor structure 30 according to some embodiments. The illustrated embodiment includes a FEOL layer having a semiconductor structure and a BEOL layer having an interconnect metal layer structure.

[0031] In the illustrated embodiment, the FEOL layer includes a FinFET transistor 32. The FinFET transistor 32 includes a semiconductor substrate 34, a fin 36, an isolation region 38, a polysilicon structure (e.g., polysilicon 40), conductive contacts S and D connected to the fin, and a conductive contact G connected to the polysilicon 40. In the illustrated embodiment, the conduction path for the current is the fin 36 (the fin may also be referred to as an active region or area). The polysilicon 40 serves as a gate, allowing current to flow from the S (e.g., source) contact to the D (e.g., drain) contact in the fin. Typically, such a gate structure includes one or more conductive segments, which include one or more conductive materials, such as the polysilicon described above. Other gate materials may include one or more metals, doped polysilicon, and / or other conductive materials. Thus, the conductive segments are configured to control the voltage provided to the underlying dielectric layer. In various embodiments, the gate dielectric layer includes, for example, one or more of silicon dioxide and / or a high-k dielectric material (e.g., a dielectric material having a k value greater than 3.8 or 7.0). In some embodiments, the high-k dielectric material includes aluminum oxide, hafnium oxide, lanthanum oxide, or another suitable material. For example, for a voltage potential between the S and D contacts, current can flow from S to D in the fin depending on the voltage applied to the polysilicon 40. If the voltage applied to the polysilicon 40 is less than the threshold voltage (VT), then an assessable current cannot flow from the S contact to the D contact in the fin, and the transistor 32 is "off." If a voltage greater than or equal to VT is applied to the polysilicon 40, an assessable current flows from S to D through the fin, and the transistor 32 is turned on. In some embodiments, the S, D, and G contacts form connections between multiple fins and polysilicon in the FEOL layer, thereby connecting the source, drain, and gate of one or more transistors. In some embodiments, the source, drain, and gate of the transistor 32 are connected to the interconnect metal layer structure in the BEOL layer. For example, the gate of transistor 32 can be connected to other structures through one or more metal strips in one layer of the interconnect metal structure in the BEOL layer, and the S / D contacts of transistor 32 can similarly be connected to other structures using other metal strips in one or more metal layers in the BEOL layer. In some embodiments, the BEOL layer is used to connect transistor 32 to peripheral circuits. In the embodiment shown, the D and G contacts are connected to the metal strips in the BEOL layer using vias. For example, via 1 forms a connection between the D contact and the metal strip in the first metal layer M1 above the FEOL layer. In the embodiment shown, a separate via 1 connects the G contact to a conductive bonding pad in the M1 layer, while via 2 connects the conductive bonding pad to a metal strip in the M2 layer.

[0032] Figure 4 An example of an integrated circuit device 100 according to the disclosed aspects is shown. Generally, the device 100 may include a Figures 1 to 3The FinFET structure shown. Figure 4 The device 100 shown includes a first power rail 112, such as a VDD or VSS power rail. Figure 4 In some examples, the power rail 112 is a VDD rail. The first active region 110 extends in the X-axis direction. In some examples, the active region 110 includes a fin, such as Figure 3 The fin 36 shown in FIG. A plurality of polysilicon gates 120 contact the active region 110 and extend in the Y-axis direction. In other words, the polysilicon gates 120 extend substantially perpendicular to the active region 110. Figure 4 In the example shown, the plurality of polysilicon gates 120 includes five polysilicon gates labeled 120a - 120e .

[0033] The first transistor 130 is formed by the first active area 110 and the first polysilicon gate 120a, and the second transistor 132 is formed by the first active area 110 and the second polysilicon gate 120b. In the example shown, the first transistor 130 has a first VT, and the second transistor 132 has a second VT different from the first VT. The device 100 thus includes a continuous active area 110 defining two different VT levels. In the embodiment shown, the active area 110 includes a first VT region 140 and a second VT region 142. For example, the first and second VTs may be any one of a standard VT (SVT), a low VT (LVT), an ultra-low VT (uLVT), a high VT (HVT), etc. Therefore, for example, the first transistor 130 may have a standard VT (SVT), and the second transistor 132 may have a low VT (LVT).

[0034] Multiple VT devices can achieve better power efficiency in some IC devices. In some examples, the active region 110 is fabricated to have different VT characteristics by using channel and / or halo implant optimization. For example, HVT devices can be implemented by heavily implanting device channel / halo pockets including ion implantation and thermal annealing.

[0035] The tie transistor 134 is located between the first transistor 130 and the second transistor 134. The tie transistor 134 is formed by the first active region 110 and the third polysilicon gate 120c. The third polysilicon gate 120c of the tie transistor 134 is connected to the power rail 112 to keep the tie transistor in an off state. The tie transistor 134 is configured to electrically isolate the first transistor 130 having a first VT from the second transistor 132 having a second TV. Figure 1In the example shown, first and second transistors 130, 132 and tie transistor 134 are PMOS transistors. PMOS tie transistor 134 has a polysilicon gate 120c connected to VDD power rail 112 through conductive via 122 to keep tie transistor 134 off to electrically isolate first transistor 130 from second transistor 132.

[0036] In some examples, the knotted transistor 134 can be located at the boundary of the first VT region 140 and the second VT region 142. In this way, the polysilicon gate 120c connecting the knotted transistor 134 to the VDD rail 112 extends just above the VT boundary along the Y-axis direction. Using the polysilicon gate 120c to connect the knotted transistor to the power rail 112 saves area compared to using a metal line for the knotted device.

[0037] exist Figure 4 In the example of , the polysilicon gates 120d and 120e can be continuous polysilicon on an oxide defined edge (CPODE) pattern. In some embodiments, as IC devices such as metal oxide semiconductor field effect transistors (MOSFETs) are scaled down at various technology nodes, device layout and isolation challenge device packaging density and device performance. To avoid leakage between adjacent devices, polysilicon segments can be formed on the edges of active areas such as fins 110 in FinFETs. Such polysilicon segments are sometimes also referred to as polysilicon on OD edge (PODE). PODE helps achieve better device performance and better polysilicon profile control.

[0038] In some embodiments, a PODE structure is formed on the edge of the device 100 and is used to protect the ends of the fin 110 during processing. That is, the PODE polysilicon structure is not electrically connected as the gate of the transistor, but is a "dummy" structure that has no function in the circuit. The PODE structure covers and protects the ends of the fin 110, providing additional reliability during processing.

[0039] In general, the number of polysilicon gates 120 in contact with the fins 110 can be considered the "pitch" of the IC device along one dimension, often referred to as the "contacted poly pitch" or CPP. The CPP can determine, at least in part, the density of the IC device. By positioning the polysilicon gate 120c of the knotted transistor 134 just above the VT region boundary, the polysilicon gate 120c is "shared" by the first and second VT regions 140, 142, without the need for separate polysilicon lines to separate the knotted devices in each of the first and second VT regions 140, 142. In this way, one polysilicon pitch can be eliminated in the disclosed example, resulting in a 5CPP device.

[0040] Figure 5Another example integrated circuit device 101 according to disclosed aspects is shown. Figure 5 The device 101 shown is similar to Figure 4 1 , although device 101 includes a second power rail 114, which in the example shown is the VSS power rail and is not as Figure 4 The device 100 includes a PMOS transistor. Figure 5 An NMOS transistor is disclosed. Like the device 100 disclosed above, the device 101 includes an active region or fin 111 extending in the X-axis direction. A plurality of polysilicon gates 120 contact the active region 111 and extend in the Y-axis direction such that the polysilicon gates 120 extend substantially perpendicular to the active region 111 . Figure 5 The multiple polysilicon gates 120 shown are again labeled 120a-120e. In other words, the device 101 is also a five-CPP structure.

[0041] The first NMOS transistor 131 having a first VT is formed by the active region 111 and the first polysilicon gate 120a, and the second NMOS transistor 133 having a second VT is formed by the active region 111 and the second polysilicon gate 120b. The device 101 thus includes a continuous active region 111 having a first VT region 140 and a second VT region 142. As described above, the first VT and the second VT may be any one of a standard VT (SVT), a low VT (LVT), an ultra-low VT (uLVT), a high VT (HVT), etc.

[0042] The junction transistor 135 is located between the first NMOS transistor 131 and the second NMOS transistor 133. The junction transistor 135 is formed by the active region 111 and the third polysilicon gate 120c. Figure 5 In the example shown, the tie transistor 135 is an NMOS transistor with the polysilicon gate 120c connected to the VSS power rail 114 through the conductive via 125 to keep the tie transistor 135 open to electrically isolate the first NMOS transistor 131 and the second NMOS transistor 133. The tie transistor 135 is located at the boundary of the first and second VT regions 140, 142.

[0043] Figure 6An embodiment of an integrated circuit device 102 is shown, which includes PMOS and NMOS transistors, and a knotted transistor with a polysilicon gate that is coupled to the VDD and VSS power rails. As such, the device 102 includes a first fin 110 and a second fin 111 that define a PMOS region 150 and an NMOS region 152. In the example shown, the device 102 includes first and second power rails 112, 114, which are the VDD and VSS power rails, respectively. The active regions or fins 110 and 111 extend in the X-axis direction. A plurality of polysilicon gates 120 contact the active region 111 and extend in the Y-axis direction such that the polysilicon gates 120 extend generally perpendicular to the active regions 110, 111. The device 102 has five polysilicon gates 120a-120e, and thus also five CPP structures.

[0044] The PMOS region 150 includes a first PMOS transistor 130 formed by a first active region 110 and a first polysilicon gate 120a, and a second PMOS transistor 132 formed by the first active region 110 and the polysilicon gate 120b. The first NMOS transistor 131 is formed by the active region 111 and the first polysilicon gate 120a, and the second NMOS transistor 133 is formed by the active region 111 and the second polysilicon gate 120b. The device 102 includes continuous active regions 110, 111 having a first VT region 140 and a second VT region 142. Therefore, the first PMOS transistor 130 and the first NMOS transistor 131 have a first VT, and the second PMOS transistor 134 and the second NMOS transistor 135 have a second VT. As described above, the first VT and the second VT may be any one of a standard VT (SVT), a low VT (LVT), an ultra-low VT (uLVT), a high VT (HVT), etc.

[0045] The junction transistors 134 and 135 are formed by the active regions 110, 111 and the third polysilicon gate 120c and are located at the boundary of the first VT region 140 and the second VT region 142. Thus, the PMOS junction transistor 134 is located between the first and second PMOS transistors 130, 132, and the NMOS junction transistor 135 is located between the first and second NMOS transistors 131, 133.

[0046] exist Figure 6In the example shown, the knot transistor 134 is a PMOS transistor and the knot transistor 135 is an NMOS transistor. The polysilicon gate 120c is connected to the VDD power rail through the conductive via 122 and to the VSS power rail 114 through the conductive via 125. The polysilicon gate 120 is patterned or cut at the space 154 so that the upper portion of the polysilicon gate 120c connects the PMOS knot transistor 134 to the VDD rail 112, but does not connect the gate of the PMOS knot transistor 134 to the VSS terminal. The lower portion of the polysilicon gate 120c connects the NMOS knot transistor 135 to the VSS rail 114, but does not connect the gate of the NMOS knot transistor 135 to the VDD terminal. In other words, the polysilicon gate 120c does not directly connect or short the VDD rail to the VSS rail. In this manner, both the tie transistors 134 and 135 are maintained in an off state so that the first PMOS transistor 130 and the second PMOS transistor 132 are electrically isolated from each other, and the first NMOS transistor 131 and the second NMOS transistor 133 are electrically isolated from each other.

[0047] exist Figures 4 to 6 In the devices 100-102 shown in FIG. 1 , the polysilicon gate 120c for each of the tie transistors 134, 135 is connected to the power rail 112 or 114 through a conductive via 122 or 123. More specifically, the conductive vias 122 and 123 extend directly from the polysilicon gate 120c to the respective power rails. Figure 7 An exemplary integrated circuit device 103 is shown according to a further embodiment, wherein the polysilicon gate of the knotted transistor is connected to a power rail through one or more metal connections. Figure 7 The device 103 shown includes a first (VDD) power rail 112 and has a PMOS transistor. A first active region or fin 110 extends in the X-axis direction, and a polysilicon gate 120 contacts the active region 110 and extends in the Y-axis direction. Figure 7 In the example shown, the plurality of polysilicon gates 120 again includes five polysilicon gates labeled 120a-120e.

[0048] The first PMOS transistor 130 in the first VT region 140 is formed by the first active region 110 and the first polysilicon gate 120a, and the second PMOS transistor 132 in the second VT region 142 is formed by the first active region 110 and the second polysilicon gate 120b. Therefore, as described above, the first transistor 130 has a first VT, and the second transistor 132 has a second VT different from the first VT.

[0049] The PMOS junction transistor 134 is located between the first PMOS transistor 130 and the second PMOS transistor 132. The junction transistor 134 is formed by the first active region 110 and the polysilicon gate 120c. The polysilicon gate 120c of the junction transistor 134 is connected to the power rail 112 to keep the junction transistor in the off state. More specifically, in Figure 7 In the example shown, the conductive via 124 connects the polysilicon gate 120c to a metal conductor or metal strip in one of the metal layers 160 (such as the M0 metal layer). In the example shown, the M0 metal layer 160 extends in the X-axis direction. The metal layer 160 is connected to a metal strip 162 (such as a metal deposit above the active area 110) through a conductive via 125, and the metal strip 162 is connected to the VDD rail 112 through another conductive via 126. In the example shown, the metal strip 162 extends in the Y-axis direction. Therefore, the polysilicon gate 120c is connected to the VDD rail 112 through the M0 metal layer 160 and the metal strip 162 to keep the knot transistor 134 in the off state to isolate the PMOS transistors 130, 132 from each other.

[0050] Figure 8 Another example is shown in which the polysilicon gate of the knotted transistor is connected to a power rail through one or more metal connections. Figure 8 The device 104 shown includes a second (VSS) power rail 114 and has an NMOS transistor. An active region or fin 111 extends in the X-axis direction, and a polysilicon gate 120 contacts the active region 111 and extends in the Y-axis direction. Figure 8 In the example shown, the plurality of polysilicon gates 120 again includes five polysilicon gates labeled 120a-120e.

[0051] The first NMOS transistor 131 in the first VT region 140 is formed by the first active region 111 and the first polysilicon gate 120a, and the second NMOS transistor 133 in the second VT region 142 is formed by the active region 111 and the second polysilicon gate 120b. Therefore, as described above, the first NMOS transistor 131 has a first VT, and the second NMOS transistor 133 has a second VT different from the first VT.

[0052] The NMOS junction transistor 135 is located between the first NMOS transistor 131 and the second NMOS transistor 133. The junction transistor 135 is formed by the active region 111 and the polysilicon gate 120c connected to the VSS power rail 114 to keep the NMOS junction transistor 135 in the off state. More specifically, in Figure 8In the example shown, conductive via 124 connects polysilicon gate 120c to M0 metal layer 160. Metal layer 160 is connected to metal strip 162 (such as metal deposition above active area 110) through conductive via 125, and metal strip 162 is connected to VSS rail 114 through conductive via 127. Therefore, polysilicon gate 120c is connected to VSS rail 114 through M0 metal layer 160 and metal strip 162 to keep NMOS junction transistor 135 in an off state to isolate NMOS transistors 131, 133 from each other.

[0053] Fig. 9 and Fig.10 An example device is shown that uses a "soft" connection of a knotted transistor to the appropriate power rail. Fig. 9 A device 105 is shown that includes a first fin 110 and a second fin 111 that define a PMOS region 150 and an NMOS region 152. In the example shown, the device 105 includes first and second power rails 112, 114, which are VDD and VSS power rails, respectively. The active regions or fins 110 and 111 extend in the X-axis direction. A plurality of polysilicon gates 120 contact the active regions 111 and extend in the Y-axis direction such that the polysilicon gates 120 extend generally perpendicular to the active regions 110, 111. The device 105 has five polysilicon gates 120a-120e, and thus five CPP structures.

[0054] The PMOS region 150 includes a first PMOS transistor 130 formed by a first active region 110 and a first polysilicon gate 120a, and a second PMOS transistor 132 formed by the first active region 110 and the polysilicon gate 120b. The first NMOS transistor 131 is formed by the active region 111 and the first polysilicon gate 120a, and the second NMOS transistor 133 is formed by the active region 111 and the second polysilicon gate 120b. The device 105 includes continuous active regions 110, 111 having a first VT region 140 and a second VT region 142. Therefore, the first PMOS transistor 130 and the first NMOS transistor 131 have a first VT, and the second PMOS transistor 134 and the second NMOS transistor 135 have a second VT. As described above, the first VT and the second VT may be any one of a standard VT (SVT), a low VT (LVT), an ultra-low VT (uLVT), a high VT (HVT), etc.

[0055] exist Fig. 9In the embodiment of FIG. 1 , the conductive via 127 connects the VSS rail 114 to the polysilicon gate 120a of the first PMOS transistor 130. Therefore, the first PMOS transistor 130 is always on. However, the metal line 162MD is connected to VDD through the conductive via 128, and the polysilicon gate 120b of the second PMOS transistor 132 is connected to the metal line 164 through the M0 metal layer 160. The second polysilicon gate 132 includes cut polysilicon 154. In this way, the VDD voltage leaks from its source to the drain side of the PMOS transistor 130. The "leaked" VDD voltage is referred to as a "soft" VDD connection, which ties up the PMOS transistor 132.

[0056] Similarly, Fig.10 A device 106 is shown including a first fin 110 and a second fin 111 that define a PMOS region 150 and an NMOS region 152. In the example shown, the device 106 includes first and second power rails 112, 114, which are VDD and VSS power rails, respectively. The active regions or fins 110 and 111 extend in the X-axis direction. A plurality of polysilicon gates 120 contact the active regions 111 and extend in the Y-axis direction such that the polysilicon gates 120 extend generally perpendicular to the active regions 110, 111. The device 106 has five polysilicon gates 120a-120e, and therefore five CPP structures.

[0057] The PMOS region 150 includes a first PMOS transistor 130 formed by a first active region 110 and a first polysilicon gate 120a, and a second PMOS transistor 132 formed by the first active region 110 and the polysilicon gate 120b. The first NMOS transistor 131 is formed by the active region 111 and the first polysilicon gate 120a, and the second NMOS transistor 133 is formed by the active region 111 and the second polysilicon gate 120b. The device 106 includes continuous active regions 110, 111 having a first VT region 140 and a second VT region 142. Therefore, the first PMOS transistor 130 and the first NMOS transistor 131 have a first VT, and the second PMOS transistor 134 and the second NMOS transistor 135 have a second VT. As described above, the first VT and the second VT may be any one of a standard VT (SVT), a low VT (LVT), an ultra-low VT (uLVT), a high VT (HVT), etc.

[0058] exist Fig.10In the embodiment of FIG. 1 , conductive via 126 connects the VDD rail 112 to the polysilicon gate 120a of the first NMOS transistor 131. Therefore, the first NMOS transistor 131 is always on. Metal line 162 is connected to the VSS rail 114 through conductive via 129, and the polysilicon gate 120b of the second NMOS transistor 133 is connected to the metal line 164 through the M0 metal layer 160. The second polysilicon gate 120b includes cut polysilicon 154. Therefore, the VSS voltage leaks from its source to the drain side of the NMOS transistor 131. The "leaked" VSS voltage is referred to as a "soft VSS" connection, which ties up the NMOS transistor 133.

[0059] Fig.11 A method according to a disclosed embodiment is shown. The method 200 shown provides a knotted device. More specifically, the method includes forming a first active region on a substrate in step 210. The first active region (such as fin 110) has a first VT region 140 and a second VT region 142. In step 212, a first gate 120a is formed to contact the first VT region 140 of the first active region to form a first transistor having a first VT. In some examples, the first transistor can be, for example, Figures 4 to 10 In step 214, a second gate 120b is formed, which contacts the second VT region 142 of the first active region 110 to form a second transistor having a second VT different from the first VT. In some examples, the second transistor can be a PMOS transistor such as the PMOS transistor 130 shown, or an NMOS transistor such as the NMOS transistor 131. In step 214, a second gate 120b is formed, which contacts the second VT region 142 of the first active region 110 to form a second transistor having a second VT different from the first VT. Figures 4 to 10 In step 216, a third gate 120c is formed to contact the first active region 110 between the first gate 120a and the second gate 120b to form a knotted transistor located between the first transistor and the second transistor. In some examples, the knotted transistor may be Figures 4 to 10 The third gate 120c is connected to a power rail, such as a VDD or VSS power rail, to keep the knotted transistor 134 in an off state, thereby electrically isolating the first transistor from the second transistor.

[0060] In some embodiments, some or all of method 200 is performed by a processor of a computer. In some embodiments, some or all of method 200 is performed by a processor 302 of an EDA system 300, as described below. Fig.12 discuss.

[0061] Some or all of the operations of method 200 can be performed as described in a design studio (such as the following reference Fig.13 It is performed as part of the design process performed in the design studio 320 discussed.

[0062] Fig.12 300 is a block diagram of an electronic design automation (EDA) system 700 according to some embodiments. In some embodiments, the EDA system 300 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 300 is a general purpose computing device that includes a processor 302 and a non-transitory computer readable storage medium 304. The computer readable storage medium 304 may be encoded with (e.g., store) computer program code 306, i.e., a set of executable instructions. The processor 302 executes the instructions 306 to represent (at least in part) an EDA tool that implements, for example, the above description of Fig.11 Part or all of the method 200 described herein (hereinafter, the process and / or method described). In addition, the method disclosed herein (such as Fig.11 The method 200) includes a manufacturing tool 303 for layout and physical implementation of an IC device.

[0063] The processor 302 is electrically coupled to the computer readable storage medium 304 via a bus 308. The processor 302 is also electrically coupled to an I / O interface 310 via the bus 308. A network interface 312 is also electrically connected to the processor 302 via the bus 308. The network interface 312 is connected to a network 314 so that the processor 302 and the computer readable storage medium 304 can be connected to external elements via the network 314. The processor 302 is configured to execute a computer program code 306 encoded in the computer readable storage medium 304 so that the system 300 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0064] In one or more embodiments, the computer-readable storage medium 304 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 304 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0065] In one or more embodiments, the computer readable storage medium 304 stores computer program code 306 configured to enable the system 300 to be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the computer readable storage medium 304 also stores information that facilitates the performance of part or all of the processes and / or methods mentioned. In one or more embodiments, the computer readable storage medium 304 stores a library 307 of standard cells including various IC devices disclosed herein.

[0066] The EDA system 300 includes an I / O interface 310. The I / O interface 310 is coupled to external circuits. In one or more embodiments, the I / O interface 310 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor direction keys for transmitting information and commands to the processor 302.

[0067] The EDA system 300 also includes a network interface 312 coupled to the processor 302. The network interface 312 allows the system 300 to communicate with a network 314 connecting one or more other computer systems. The network interface 312 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1394. In one or more embodiments, a portion or all of the process and / or method is implemented in two or more systems 300.

[0068] The system 300 is configured to receive information through the I / O interface 310. The information received through the I / O interface 310 includes one or more of instructions, data, design rules, libraries of standard cells, and / or other parameters processed by the processor 302. The information is transmitted to the processor 302 via the bus 308. The EDA system 300 is configured to receive information related to the UI through the I / O interface 310. The information is stored in the computer readable medium 304 as a user interface (UI) 342.

[0069] In some embodiments, part or all of the processes and / or methods mentioned are implemented as independent software applications for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as software applications that are part of additional software applications. In some embodiments, part or all of the processes and / or methods are implemented as plug-ins for software applications. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as software applications used by an EDA system 300. In some embodiments, a layout diagram including standard cells is generated using tools such as VIRTUOSO or other suitable layout generation tools available from CADENCEDESIGN SYSTEMS.

[0070] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, for example, optical disks such as DVDs, magnetic disks such as hard disks, semiconductor memories such as ROM, RAM, memory cards, etc.

[0071] As described above, embodiments of the EDA system 300 may include fabrication tools 303 for implementing processes and / or methods stored in the storage medium 304. For example, a design may be synthesized, wherein the behavior and / or functionality required by the design may be converted into a functionally equivalent logic gate level circuit description by matching the design with standard cells selected from the standard cell library 307. The synthesis produces a functionally equivalent logic gate level circuit description, such as a gate level netlist. Based on the gate level netlist, a lithography mask may be generated, which is used by the fabrication tool 303 to fabricate the integrated circuit. In combination Fig.13 Other aspects of device fabrication are disclosed. Fig.13 is a block diagram of an IC manufacturing system 301 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 301 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0072] exist Fig.13, IC manufacturing system 301 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 360 (such as devices 100-106 disclosed herein), such as design room 320, mask room 330, and IC vendor / manufacturer ("fab") 350. The entities in system 301 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 320, mask room 330, and IC manufacturer 350 are owned by a single larger company. In some embodiments, two or more of design room 320, mask room 330, and IC manufacturer 350 coexist in a common facility and use common resources.

[0073] The design office (or design team) 320 generates an IC design layout 322. The IC design layout 322 includes various geometric patterns or IC layouts designed for an IC device 360 ​​(e.g., including one or more of the disclosed IC structures 100-106 discussed above). The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 360 ​​to be manufactured. The various layers are combined to form various IC components. For example, a portion of the IC design layout 322 includes various IC components, such as active regions, gate electrodes, source electrodes, and drain electrodes formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate, metal lines or vias of interlayer interconnects, and openings for forming bonding pads. The design office 320 implements a design process to form the IC design layout 322. The design process includes one or more of a logical design, a physical design, or a layout and routing. The IC design layout 322 is presented in one or more data files with geometric pattern information. For example, the IC design layout 322 can be represented in a GDSII file format or a DFII file format.

[0074] The mask chamber 330 includes data preparation 332 and mask manufacturing 334. The mask chamber 330 uses the IC design layout 322 to manufacture one or more masks 345 for manufacturing various layers of the IC device 360 ​​according to the IC design layout 322. The mask chamber 330 implements mask data preparation 332, wherein the IC design layout 322 is converted into a representative data file ("RDF"). The mask data preparation 332 provides the RDF to the mask manufacturing 344. The mask manufacturing 344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 345 or a semiconductor wafer 353. The IC design layout 322 is manipulated by the mask data preparation 332 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 350. In Fig.13 , mask data preparation 332 and mask manufacturing 344 are shown as separate elements. In some embodiments, mask data preparation 332 and mask manufacturing 344 may be collectively referred to as mask data preparation.

[0075] In some embodiments, mask data preparation 332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 322. In some embodiments, mask data preparation 332 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary components, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0076] In some embodiments, mask data preparation 332 includes a mask rule checker (MRC) that checks an IC design layout 322 that has been subjected to a process in OPC using a set of mask creation rules that contain certain geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 322 to compensate for the constraints during mask fabrication 344, which may undo some of the modifications implemented by the OPC to satisfy the mask creation rules.

[0077] In some embodiments, mask data preparation 332 includes a lithography process check (LPC), which simulates a process to be performed by IC manufacturer 350 to manufacture IC device 360. LPC simulates the process based on IC design layout diagram 322 to create a simulated manufactured device, such as IC device 360. Process parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after creating a simulated manufactured device through LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 322.

[0078] It should be understood that the above description of mask data preparation 332 has been simplified for the sake of clarity. In some embodiments, data preparation 332 includes additional features such as logic operations (LOPs) to modify IC design layout 322 according to manufacturing rules. In addition, the processes applied to IC design layout 322 during data preparation 332 can be implemented in a variety of different orders.

[0079] After mask data preparation 332 and during mask manufacturing 344, a mask 345 or a set of masks 345 is manufactured based on the modified IC design layout 322. In some embodiments, mask manufacturing 344 includes performing one or more photolithography exposures based on the modified IC design layout 322. In some embodiments, based on the modified IC design layout 322, a pattern is formed on a mask (photomask or intermediate mask) 345 using an electron beam (e-beam) or a plurality of electron beams. Mask 345 can be formed using various techniques. In some embodiments, mask 345 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque region and a transparent region. A radiation beam (such as an ultraviolet (UV) beam) for exposing an image sensitive material layer (e.g., photoresist) already coated on a wafer is blocked by an opaque region and transmitted through the transparent region. In one example, a binary mask version of mask 345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque region of the mask. In another example, the mask 345 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 345, various components in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 344 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 353, in an etching process to form various etched regions in the semiconductor wafer 353, and / or in other suitable processes.

[0080] IC manufacturer 350 includes wafer fabrication 352. IC manufacturer 350 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer 350 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry business.

[0081] IC manufacturer 350 uses mask (or multiple masks) 345 manufactured by mask chamber 330 to manufacture IC device 360. Therefore, IC manufacturer 350 at least indirectly uses IC design layout 322 to manufacture IC device 360. In some embodiments, semiconductor wafer 353 is manufactured by IC manufacturer 350 using mask (or multiple masks) 345 to form IC device 360. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 322 at least indirectly. Semiconductor wafer 353 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 353 also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0082] Thus, disclosed embodiments include an integrated circuit device including a first power rail and a first active area extending in a first direction. A plurality of gates contact the first active area and extend in a second direction perpendicular to the first direction. A first transistor includes a first active area and a first gate in the gate. The first transistor has a first VT. A second transistor includes a first active area and a second gate in the gate, and the second transistor has a second VT different from the first VT. A knotted transistor is located between the first transistor and the second transistor. The knotted transistor includes a first active area and a third gate in the gate, wherein the third gate is connected to the first power rail.

[0083] In the above integrated circuit device, the third gate is connected to the first power rail through a first conductive via.

[0084] In the above integrated circuit device, wherein the first active region includes a fin.

[0085] In the above integrated circuit device, wherein the knotted transistor is a P-type metal oxide semiconductor (PMOS) transistor, and wherein the first power rail is a VDD power rail.

[0086] In the above integrated circuit device, wherein the knotted transistor is an N-type metal oxide semiconductor (NMOS) transistor, and wherein the first power rail is a VSS power rail.

[0087] In the above integrated circuit device, wherein the knotted transistor is a P-type metal oxide semiconductor (PMOS) transistor, and wherein the first power rail is a VDD power rail, wherein the first transistor and the second transistor are P-type metal oxide semiconductor transistors.

[0088] In the above integrated circuit device, wherein the knotted transistor is an N-type metal oxide semiconductor (NMOS) transistor, and wherein the first power rail is a VSS power rail, the first transistor and the second transistor are N-type metal oxide semiconductor transistors.

[0089] In the above integrated circuit device, wherein the knotted transistor is a P-type metal oxide semiconductor (PMOS) transistor, and wherein the first power rail is a VDD power rail, wherein the first transistor and the second transistor are P-type metal oxide semiconductor transistors, wherein the plurality of gates are polysilicon gates, and the integrated circuit device further includes: a VSS power rail; a second active region extending in the first direction, wherein a plurality of polysilicon gates contact the second active region; a first N-type metal oxide semiconductor transistor including the second active region and the first polysilicon gate, the first N-type metal oxide semiconductor transistor having the first threshold a second N-type metal oxide semiconductor transistor including the second active area and a second polysilicon gate, the second N-type metal oxide semiconductor transistor having the second threshold voltage; and an N-type metal oxide semiconductor junction transistor located between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor, the N-type metal oxide semiconductor junction transistor including the first active area and a third polysilicon gate, wherein the third polysilicon gate is connected to the VSS power rail, and wherein the third polysilicon gate includes cut polysilicon located between the first active area and the second active area.

[0090] In the above integrated circuit device, wherein the knotted transistor is a P-type metal oxide semiconductor (PMOS) transistor, and wherein the first power rail is a VDD power rail, wherein the first transistor and the second transistor are P-type metal oxide semiconductor transistors, wherein the plurality of gates are polysilicon gates, and the integrated circuit device further includes: a VSS power rail; a second active region extending in the first direction, wherein a plurality of polysilicon gates contact the second active region; a first N-type metal oxide semiconductor transistor including the second active region and the first polysilicon gate, the first N-type metal oxide semiconductor transistor having the first threshold voltage; a second N-type metal oxide semiconductor a transistor including the second active area and a second polysilicon gate, the second N-type metal oxide semiconductor transistor having the second threshold voltage; and an N-type metal oxide semiconductor junction transistor located between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor, the N-type metal oxide semiconductor junction transistor including the first active area and a third polysilicon gate, wherein the third polysilicon gate is connected to the VSS power rail, and wherein the third polysilicon gate includes cut polysilicon located between the first active area and the second active area, wherein the third polysilicon gate is connected to the VSS power rail through a second conductive via.

[0091] In the above integrated circuit device, wherein the knotted transistor is a P-type metal oxide semiconductor (PMOS) transistor, and wherein the first power rail is a VDD power rail, wherein the first transistor and the second transistor are P-type metal oxide semiconductor transistors, wherein the plurality of gates are polysilicon gates, and the integrated circuit device further comprises: a VSS power rail; a second active region extending in the first direction, wherein a plurality of polysilicon gates contact the second active region; a first N-type metal oxide semiconductor transistor including the second active region and the first polysilicon gate, the first N-type metal oxide semiconductor transistor having the first threshold voltage; a second N-type metal oxide semiconductor transistor including the second active region and the second polysilicon gate a silicon gate, the second N-type metal oxide semiconductor transistor having the second threshold voltage; and an N-type metal oxide semiconductor junction transistor located between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor, the N-type metal oxide semiconductor junction transistor including the first active area and a third polysilicon gate, wherein the third polysilicon gate is connected to the VSS power rail, and wherein the third polysilicon gate includes cut polysilicon located between the first active area and the second active area, wherein the third polysilicon gate is connected to the VSS power rail through a second conductive via, and wherein the third polysilicon gate is connected to the VSS power rail through a metal layer and a third conductive via.

[0092] According to other disclosed embodiments, a semiconductor device includes a first power rail and a second power rail. A first PMOS transistor includes a first fin and a first gate extending in a first direction. The first PMOS transistor has a first VT, and the first gate extends in a second direction perpendicular to the first direction. A second PMOS transistor includes a first fin and a second gate extending in a second direction. The second PMOS transistor has a second VT different from the first VT. The second gate is connected to the first power rail. The second fin extends in the first direction. A first NMOS transistor includes a second fin and a first gate. The first NMOS transistor has a first VT. A second NMOS transistor includes a second fin and a second gate. The second NMOS transistor has a second VT. The second gate is connected to the second power rail.

[0093] In the above device, wherein the first gate is connected to the second power rail, and wherein the second gate is connected to the first power rail through the first P-type metal oxide semiconductor transistor.

[0094] In the above device, wherein the first gate is connected to the first power rail, and wherein the second gate is connected to the second power rail through the first N-type metal oxide semiconductor transistor.

[0095] In the above device, the first gate is connected to the second power rail, and the second gate is connected to the first power rail through the first P-type metal oxide semiconductor transistor, and the second gate is connected to the first P-type metal oxide semiconductor transistor through a metal layer extending in the first direction and a metal strip extending in the second direction.

[0096] The above device also includes: a third P-type metal oxide semiconductor transistor, including the first fin and the third gate, the third P-type metal oxide semiconductor transistor having the second threshold voltage, wherein the second P-type metal oxide semiconductor transistor is located between the first P-type metal oxide semiconductor transistor and the third P-type metal oxide semiconductor transistor; a third N-type metal oxide semiconductor transistor, including the first fin and the third gate, the third N-type metal oxide semiconductor transistor having the second threshold voltage, wherein the second N-type metal oxide semiconductor transistor is located between the first N-type metal oxide semiconductor transistor and the third N-type metal oxide semiconductor transistor.

[0097] In the above device, wherein the first gate, the second gate and the third gate include corresponding first polysilicon gates, second polysilicon gates and third polysilicon gates, and wherein the second polysilicon gate includes cut polysilicon located between the first fin and the second fin, and wherein the second polysilicon gate is directly connected to the first power rail.

[0098] According to another embodiment, a method includes forming a first active region on a substrate, wherein the first active region has a first VT region and a second VT region. Forming a first gate, the first gate contacts the first VT region of the first active region to form a first transistor having a first VT. Forming a second gate, the second gate contacts the second VT region of the first active region to form a second transistor having a second VT different from the first VT. Forming a third gate, the third gate contacts the first active region between the first gate and the second gate to form a knotted transistor between the first transistor and the second transistor. The third gate is connected to a power rail to keep the knotted transistor in an off state.

[0099] In the above method, wherein the knotted transistor is a P-type metal oxide semiconductor transistor, and wherein connecting the third gate to the power rail to keep the knotted transistor in an off state includes: connecting the third gate to a VDD power rail.

[0100] In the above method, wherein the knotted transistor is a P-type metal oxide semiconductor transistor, and wherein connecting the third gate to the power rail to keep the knotted transistor in an off state includes: connecting the third gate to a VDD power rail, wherein connecting the third gate to the VDD power rail includes providing a conductive via extending between the third gate and the VDD power rail.

[0101] In the above method, wherein the knotted transistor is a P-type metal oxide semiconductor transistor, and wherein connecting the third gate to the power rail to keep the knotted transistor in an off state includes: connecting the third gate to a VDD power rail, wherein the first transistor and the second transistor and the knotted transistor are P-type metal oxide semiconductor transistors, and the method further includes: forming a second active area on the substrate, the second active area including the first threshold voltage region and the second threshold voltage region; forming the first gate to also contact the second active area to form a first N-type metal oxide semiconductor transistor having the first threshold voltage; forming the second gate to also contact the second active area to form a second N-type metal oxide semiconductor transistor having the second threshold voltage; forming the third gate to also contact the second active area to form an N-type metal oxide semiconductor knotted transistor located between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor; and connecting the third gate to a second power rail to keep the N-type metal oxide semiconductor knotted transistor in an off state.

[0102] The present invention summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that this equivalent configuration is not directed away from the spirit and scope of the present invention, and in the case of not directed away from the spirit and scope of the present invention, they can make multiple changes, replacements and changes herein.

Claims

1. An integrated circuit device comprising: First power rail; a first active region extending in a first direction, the first active region including a first area defining a first threshold voltage and a second area defining a second threshold voltage different from the first threshold voltage, the first area and the second area being adjacent to each other to define a boundary between the first area and the second area; a plurality of gates contacting the first active region and extending in a second direction perpendicular to the first direction; a first transistor including the first region of the first active region and a first gate of the gates, the first transistor having the first threshold voltage; a second transistor including the second region of the first active region and a second gate of the gates, the second transistor having the second threshold voltage; as well as A knotted transistor is located between the first transistor and the second transistor, the knotted transistor includes the first active region and a third gate among the gates, wherein the third gate is located just above the boundary and connected to the first power rail.

2. The integrated circuit device according to claim 1, wherein: The third gate is connected to the first power rail through a first conductive via.

3. The integrated circuit device according to claim 1, wherein: The first active region includes a fin.

4. The integrated circuit device according to claim 1, wherein: The junction transistor is a P-type metal oxide semiconductor transistor, and wherein the first power rail is a VDD power rail.

5. The integrated circuit device according to claim 1, wherein: The junction transistor is an N-type metal oxide semiconductor transistor, and wherein the first power rail is a VSS power rail.

6. The integrated circuit device according to claim 4, wherein: The first transistor and the second transistor are P-type metal oxide semiconductor transistors.

7. The integrated circuit device according to claim 5, wherein: The first transistor and the second transistor are N-type metal oxide semiconductor transistors.

8. The integrated circuit device according to claim 6, wherein: The plurality of gates are polysilicon gates, and the integrated circuit device further comprises: VSS power rail; a second active region extending in the first direction, wherein a plurality of polysilicon gates contact the second active region; a first N-type metal oxide semiconductor transistor, comprising the second active region and a first polysilicon gate, the first N-type metal oxide semiconductor transistor having the first threshold voltage; A second N-type metal oxide semiconductor transistor, comprising the second active region and a second polysilicon gate, the second N-type metal oxide semiconductor transistor having the second threshold voltage; and An N-type metal oxide semiconductor junction transistor is located between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor, the N-type metal oxide semiconductor junction transistor includes the first active area and a third polysilicon gate, wherein the third polysilicon gate is connected to the VSS power rail, and wherein the third polysilicon gate includes cut polysilicon located between the first active area and the second active area.

9. The integrated circuit device according to claim 8, wherein: The third polysilicon gate is connected to the VSS power rail through a second conductive via.

10. The integrated circuit device according to claim 9, wherein: The third polysilicon gate is connected to the VSS power rail through a metal layer and a third conductive via.

11. An integrated circuit device comprising: First power rail; Second power rail; a first fin extending in a first direction, the first fin having a first active region defining a first threshold voltage and a second active region defining a second threshold voltage different from the first threshold voltage, the first active region and the second active region of the first fin being adjacent to each other and sharing a boundary therebetween; a first P-type metal oxide semiconductor transistor, comprising the first active region of the first fin and a first gate, the first P-type metal oxide semiconductor transistor having a first threshold voltage, and the first gate extending in a second direction perpendicular to the first direction; a second P-type metal oxide semiconductor transistor including the first fin and a first portion of a second gate extending in the second direction, the second P-type metal oxide semiconductor transistor having a second threshold voltage different from the first threshold voltage, and wherein the first portion of the second gate is located directly above the boundary and connected to the first power rail; a second fin extending in the first direction, the second fin having a first active region defining the first threshold voltage and a second active region defining the second threshold voltage, the first active region and the second active region of the second fin being adjacent to each other and sharing the boundary therebetween; A first N-type metal oxide semiconductor transistor, comprising the second fin and the first gate, the first N-type metal oxide semiconductor transistor having the first threshold voltage; A second N-type metal oxide semiconductor transistor includes the second fin and a second portion of the second gate, the first portion and the second portion of the second gate are cut and separated by a gap, the second N-type metal oxide semiconductor transistor has the second threshold voltage, and wherein the second portion of the second gate is located directly above the boundary and connected to the second power rail.

12. The integrated circuit device according to claim 11, wherein: The first gate is connected to the second power rail, and wherein the first portion of the second gate is connected to the first power rail through the first P-type metal oxide semiconductor transistor.

13. The integrated circuit device according to claim 11, wherein: The first gate is connected to the first power rail, and wherein the second portion of the second gate is connected to the second power rail through the first N-type metal oxide semiconductor transistor.

14. The integrated circuit device according to claim 12, wherein: The first portion of the second gate is connected to the first P-type metal oxide semiconductor transistor through a metal layer extending in the first direction and a metal strip extending in the second direction.

15. The integrated circuit device according to claim 11, further comprising: a third P-type metal oxide semiconductor transistor, comprising the first fin and a third gate, the third P-type metal oxide semiconductor transistor having the second threshold voltage, wherein the second P-type metal oxide semiconductor transistor is located between the first P-type metal oxide semiconductor transistor and the third P-type metal oxide semiconductor transistor; A third N-type metal oxide semiconductor transistor includes the first fin and the third gate, the third N-type metal oxide semiconductor transistor has the second threshold voltage, wherein the second N-type metal oxide semiconductor transistor is located between the first N-type metal oxide semiconductor transistor and the third N-type metal oxide semiconductor transistor.

16. The integrated circuit device according to claim 15, wherein: The first gate, the second gate and the third gate include respective first polysilicon gates, second polysilicon gates and third polysilicon gates, and wherein the second polysilicon gate includes cut polysilicon located between the first fin and the second fin, and wherein the second polysilicon gate is directly connected to the first power rail.

17. A method of forming an integrated circuit device, comprising: forming a first active region on a substrate, wherein the first active region includes a first threshold voltage region and a second threshold voltage region, the first threshold voltage region and the second threshold voltage region being adjacent to each other to define a boundary between the first threshold voltage region and the second threshold voltage region; forming a first gate, the first gate contacting the first threshold voltage region of the first active region to form a first transistor having a first threshold voltage; forming a second gate, the second gate contacting the second threshold voltage region of the first active region to form a second transistor having a second threshold voltage different from the first threshold voltage; forming a third gate, the third gate contacting the first active region between the first gate and the second gate to form a junction transistor between the first transistor and the second transistor; and The third gate is placed just above the boundary and connected to a power rail to keep the knotted transistor in an off state.

18. The method according to claim 17, wherein: The junction transistor is a P-type metal oxide semiconductor transistor, and wherein connecting the third gate to the power rail to maintain the junction transistor in an off state includes connecting the third gate to a VDD power rail.

19. The method according to claim 18, wherein: Connecting the third gate to the VDD power rail includes providing a conductive via extending between the third gate and the VDD power rail.

20. The method according to claim 18, wherein: The first transistor, the second transistor and the junction transistor are P-type metal oxide semiconductor transistors, and the method further includes: forming a second active region on the substrate, wherein the second active region includes the first threshold voltage region and the second threshold voltage region; forming the first gate to also contact the second active region to form a first N-type metal oxide semiconductor transistor having the first threshold voltage; forming the second gate to also contact the second active region to form a second N-type metal oxide semiconductor transistor having the second threshold voltage; forming the third gate to also contact the second active region to form an N-type metal oxide semiconductor junction transistor located between the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor; and The third gate is connected to a second power rail to keep the NMOS junction transistor in an off state.

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