Vertical memory device

Abstract

A vertical memory device is provided that includes a first structure on a substrate. The first structure includes gate patterns spaced apart from one another in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of tiers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of respective tiers of the plurality of tiers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and is electrically connected with a pad pattern of one tier of the plurality of tiers. The first contact plug is electrically insulated from gate patterns of other tiers. At least one bend is included in each of a sidewall of the channel structure and a sidewall of the first contact plug.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0073611, filed on June 20, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0002] The present inventive concepts relate to a vertical memory device. BACKGROUND

[0003] Recently, a vertical memory device including a plurality of memory cells vertically stacked on a base has been developed. One example of the vertical memory device includes a NAND-type flash memory. Although the vertical memory device has increased integration, as the number of stacked memory cells increases, a wiring structure for connecting the memory cells can become complex. SUMMARY

[0004] According to an example embodiment of the present inventive concepts, a vertical memory device includes a first structure on a base. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the base to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of respective layers of the plurality of layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and is electrically connected to the pad pattern of one layer of the plurality of layers. The first contact plug is electrically insulated from the gate patterns of other layers. At least one curved portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.

[0005] According to an example embodiment of the present inventive concepts, a vertical memory device includes a circuit pattern on a base. A base pattern and a base insulating layer are disposed on the circuit pattern. A first structure is disposed on the base pattern. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the base. The gate patterns extend in a first direction parallel to the upper surface of the base. A second structure is connected to the first structure, and the second structure includes pad patterns in a separate plurality of layers. The pad patterns are electrically connected to the gate patterns of the same layer. A channel structure passes through the gate patterns, and the channel structure extends in the vertical direction. A first contact plug passing through the second structure is electrically connected to the pad pattern of one layer of the plurality of layers, and the first contact plug extends in the vertical direction.

[0006] According to an exemplary embodiment of the inventive concept, there is provided a vertical memory device including a first structure disposed on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. The gate patterns extend in a first direction parallel to the upper surface of the substrate. A second structure is connected to the first structure, the second structure including pad patterns spaced apart among a plurality of layers and electrically connected to gate patterns of the same layer. A channel structure passes through the gate patterns. The channel structure extends in the vertical direction. A first contact plug passes through the second structure and is electrically connected to a pad pattern of one of the plurality of layers, and the first contact plug extends in the vertical direction. The first contact plug is electrically insulated from gate patterns of other layers. A third structure is spaced apart from the second structure, and a second contact plug passes through the third structure, and the second contact plug extends in the vertical direction. An upper surface of the channel structure is coplanar with an upper surface of the first contact plug and an upper surface of the second contact plug. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other features of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0008] FIG. 1 is a plan view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept;

[0009] FIG. 2 is a cross-sectional view illustrating a cross-section of the vertical memory device of FIG. 1 along lines I-I' and II-II' of

[0010] FIG. 3A is a cross-sectional view illustrating a cross-section of the vertical memory device of FIG. 1 along line III-III' of

[0011] FIG. 3B is a plan view illustrating gate patterns, conductive patterns, and pad patterns (or called "land patterns") at one level in the vertical memory device of FIG. 1 according to an exemplary embodiment of the inventive concept;

[0012] FIG. 4A , FIG. 4B and FIG. 4C are cross-sectional views illustrating lower portions of the vertical memory device according to an exemplary embodiment of the inventive concept;

[0013] FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 ,FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 , FIG. 16 , FIG. 17 , FIG. 18 , FIG. 19 , FIG. 20 , FIG. 21 , FIG. 22 , FIG. 23 and FIG. 24 are plan and sectional views showing stages of a method of manufacturing a vertical memory device according to exemplary embodiments of the inventive concept;

[0014] FIG. 25 , FIG. 26 , FIG. 27 , FIG. 28 , FIG. 29 and FIG. 30 are sectional views showing stages of a method of manufacturing a vertical memory device according to exemplary embodiments of the inventive concept;

[0015] FIG. 31 is a sectional view showing a vertical memory device according to exemplary embodiments of the inventive concept;

[0016] FIG. 32 and FIG. 33 are sectional views showing stages of a method of manufacturing a vertical memory device according to exemplary embodiments of the inventive concept;

[0017] FIG. 34 is a sectional view showing a vertical memory device according to exemplary embodiments of the inventive concept;

[0018] FIG. 35 , FIG. 36 , FIG. 37 , FIG. 38 and FIG. 39 are sectional views showing stages of a method of manufacturing a vertical memory device according to exemplary embodiments of the inventive concept;

[0019] FIG. 40 is a sectional view showing a vertical memory device according to exemplary embodiments of the inventive concept;

[0020] FIG. 41 is a plan view showing a vertical memory device according to exemplary embodiments of the inventive concept; and

[0021] FIG. 42 is a plan view showing a vertical memory device according to exemplary embodiments of the inventive concept; FIG. 41FIG. 3 is a cross-sectional view of a cross section taken along line III-III' of the vertical memory device of FIG. 1. DETAILED DESCRIPTION

[0022] FIG. 1 FIG. 1 is a plan view of a vertical memory device according to an exemplary embodiment of the present inventive concept. FIG. 2 FIG. 2 is a cross-sectional view of a cross section taken along line I-I' and line II-II' of the vertical memory device of FIG. 1. FIG. 1 FIG. 3 is a cross-sectional view of a cross section taken along line III-III' of the vertical memory device of FIG. 1. FIG. 3A FIG. 4 is a cross-sectional view of a cross section taken along line IV-IV' of the vertical memory device of FIG. 1. FIG. 1 FIG. 5 is a cross-sectional view of a cross section taken along line V-V' of the vertical memory device of FIG. 1. FIG. 3B FIG. 6 is a plan view of a gate pattern, a conductive pattern, and a pad pattern located at one level in the vertical memory device of FIG. 1. FIG. 1 FIG. 7 is a plan view of a gate pattern, a conductive pattern, and a pad pattern located at one level in the vertical memory device of FIG. 1. FIG. 4A FIG. 8 is a cross-sectional view of a lower portion of the vertical memory device according to an exemplary embodiment of the present inventive concept. FIG. 4B FIG. 9 is a cross-sectional view of a lower portion of the vertical memory device according to an exemplary embodiment of the present inventive concept. FIG. 4C FIG. 10 is a cross-sectional view of a lower portion of the vertical memory device according to an exemplary embodiment of the present inventive concept.

[0023] Hereinafter, a direction substantially perpendicular to an upper surface of a substrate can be a vertical direction, and two directions crossing each other in a horizontal direction substantially parallel to the upper surface of the substrate can be a first direction and a second direction, respectively. In an exemplary embodiment of the present inventive concept, the first direction and the second direction can be perpendicular to each other.

[0024] Referring to FIG. 1 , FIG. 2 , FIG. 3A and FIG. 3BThe vertical memory device can include a circuit pattern formed on the substrate 100. The substrate 100 can include a cell region A, a through-cell wiring region B, and a through-wiring region C. The channel structure 190 can be formed in the cell region A, the first contact plug 202a can be formed in the through-cell wiring region B, and the second contact plug 202b can be formed in the through-wiring region C. The channel structure 190, the first contact plug 202a, and the second contact plug 202b can each have a tapered shape that narrows in a vertical direction perpendicular to an upper surface of the substrate 100. The channel structure 190, the first contact plug 202a, and the second contact plug 202b can be formed above the circuit pattern. For example, the channel structure 190 can be formed above the circuit pattern in the cell region A, and the first contact plug 202a and the second contact plug 202b can be formed above the circuit pattern in the through-cell wiring region B and the through-wiring region C, respectively. Each of the first contact plug 202a and the second contact plug 202b can be electrically connected to the circuit pattern. The vertical memory device can have a cell-on-periphery (COP) structure. In other words, a peripheral circuit for driving a memory cell can be formed on the substrate 100 below the memory cell.

[0025] The substrate 100 can include a semiconductor material, for example, silicon, germanium, silicon-germanium, and / or a III-V semiconductor compound (e.g., GaP, GaAs, GaSb, etc.). In example embodiments of the present inventive concept, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0026] The circuit pattern can include a lower transistor 104, a lower contact plug 106, a lower wiring 108, etc. In example embodiments of the present inventive concept, the lower contact plug 106 and the lower wiring 108 can be formed to have multiple layers.

[0027] A lower insulating intermediate layer 110 covering the circuit pattern can be formed on the substrate 100. The lower contact plug 106 can contact an impurity region 104a and / or a gate structure 104b of the lower transistor 104.

[0028] The lower wiring 108 can include a lower pad 108a. In example embodiments of the present inventive concept, the lower pad 108a can be a pattern disposed at an uppermost portion in the lower wiring 108. The lower pad 108a can directly contact bottom surfaces of the first contact plug 202a and the second contact plug 202b.

[0029] A bulk pattern 112 can be formed on (e.g., an upper surface of) the lower insulating intermediate layer 110. In example embodiments of the present inventive concept, the bulk pattern 112 can be formed below the cell region A. The bulk pattern 112 can include, for example, a polysilicon layer and / or a single-crystal silicon layer.

[0030] The base insulating layer 114 can be formed on the lower insulating interlayer 110 between the base patterns 112. The base insulating layer 114 can be disposed at the penetrating portions of the first and second contact plugs 202a and 202b. In other words, the sidewalls of the first and second contact plugs 202a and 202b can contact the base insulating layer 114. The base insulating layer 114 can include, for example, silicon oxide. The base patterns 112 can be disposed between the penetrating portions of the first and second contact plugs 202a and 202b.

[0031] The first structure can be formed on the base patterns 112 in the cell region A. The first structure can include a structure in which the first insulating layers 120 and the conductive patterns are alternately and repeatedly stacked, and a structure in which the second insulating layers 150 and the conductive patterns are alternately and repeatedly stacked on the aforementioned structure. The third insulating interlayer 172 can be formed on the first structure. Each of the conductive patterns can function as a gate pattern 230.

[0032] The gate pattern 230 can include a metallic material. For example, the gate pattern 230 can include tungsten (W).

[0033] The third insulating interlayer 172 can include silicon oxide. In an exemplary embodiment of the inventive concept, the third insulating interlayer 172 can include a tetraethyl orthosilicate (TEOS) material.

[0034] The second trench 210b can be formed to pass through the first structure and the third insulating interlayer 172, and can extend in the first direction. Accordingly, a plurality of first structures can be divided by the second trench 210b. For example, the plurality of first structures can be arranged in the second direction. The base patterns 112 or the base insulating layer 114 can be exposed by a bottom surface of the second trench 210b.

[0035] At least one of the gate patterns 230 can function as one of a ground select line (GSL), a word line, and a string select line (SSL).

[0036] A channel hole can be formed to pass through the third insulating interlayer 172 and the first structure, and the channel hole can extend to an upper surface of the base pattern 112. A channel structure 190 can be formed on the channel hole. Accordingly, the channel structure 190 can contact the upper surface of the base pattern 112.

[0037] The memory cell can include the channel structure 190 and the gate pattern 230.

[0038] In an exemplary embodiment of the inventive concept, as shown in FIG. 1B, the channel structure 190 can include a charge storage structure 180, a channel 182, and an upper conductive pattern 186. The charge storage structure 180 can include a stack of a charge trapping layer 184 and a blocking layer 185. The channel 182 can include a semiconductor material. The upper conductive pattern 186 can include a metallic material. FIG. 2 In an exemplary embodiment of the inventive concept, as shown in FIG. 1B, the channel structure 190 can include a charge storage structure 180, a channel 182, and an upper conductive pattern 186. The charge storage structure 180 can include a stack of a charge trapping layer 184 and a blocking layer 185. The channel 182 can include a semiconductor material. The upper conductive pattern 186 can include a metallic material.FIG. 14 The barrier pattern 180c, the charge storage pattern 180b, and the tunnel insulation pattern 180a can be formed on the sidewall of the channel structure 190 (as shown in FIG. 1B). The upper conductive pattern 186 can be formed on the channel 182 and can fill an upper portion of the channel hole 176a. The channel 182 and the upper conductive pattern 186 can include polysilicon.

[0039] In an exemplary embodiment of the inventive concept, as shown in FIG. 1B, the channel structure 190 can include the charge storage structure 180, the channel 182, the fill insulation pattern 184, and the upper conductive pattern 186. The channel 182 can have a cylindrical shape. In addition, the fill insulation pattern 184 can be formed on the channel 182 to fill the channel hole 176a. FIG. 4B

[0040] In an exemplary embodiment of the inventive concept, as shown in FIG. 1B, the channel structure 190 can include the charge storage structure 180, the channel 182, the fill insulation pattern 184, and the upper conductive pattern 186. The channel 182 can have a cylindrical shape. In addition, the fill insulation pattern 184 can be formed on the channel 182 to fill the channel hole 176a. FIG. 4C

[0041] The channel hole 176a can include two curved portions. Accordingly, the sidewall of the channel structure 190 formed in the channel hole 176a can include two curved portions b1 and b2.

[0042] An upper surface of the channel structure 190 can be coplanar with an upper surface of the third insulating intermediate layer 172.

[0043] In addition, the first trench 210a can be formed through the third insulating intermediate layer 172 and the first structure, and can extend in the first direction. The first trench 210a can be formed in the first structure such that the first trench 210a can serve as a cut region of a word line. The base pattern 112 can be exposed by a bottom surface of the first trench 210a.

[0044] In an exemplary embodiment of the inventive concept, the third trench 210c serves as a cut region of a string selection line SSL. The third trench 210c can be formed by etching at least one of an uppermost gate pattern and a gate pattern below the uppermost gate pattern.

[0045] The second structure can be formed on the base insulating layer 114 in the through-cell wiring region B, and the second structure can have a stepped shape at an edge portion in the first direction. Accordingly, the edge portion of the second structure in the first direction can have different levels (heights) for each layer. For example, the second structure can have a stepped shape in which a length of each step extends in the first direction, and the steps have a decreasing length as the steps are spaced further apart in the vertical direction from the upper surface of the base 100. ​​

[0046] The second structure can include a structure in which the first insulating layer 120, the second insulating layer 150, the conductive pattern 230b, and the pad pattern 230a are stacked, and a structure in which the first insulating layer 120, the second insulating layer 150, the first sacrificial layer 122, and the fourth sacrificial layer 152 are stacked. In other words, a portion of the second structure can have the conductive pattern 230b disposed between the insulating layers, and the remaining portion of the second structure can include only the stacked insulating material layers.

[0047] The first insulating intermediate layer 134 and the second insulating intermediate layer 164 can be formed to cover the second structure. The first insulating intermediate layer 134 can cover a lower stepped portion of the second structure, and the second insulating intermediate layer 164 can cover an upper stepped portion of the second structure. The third insulating intermediate layer 172 can be formed on the second structure.

[0048] The first structure and the second structure can be connected to each other such that the first structure and the second structure can be merged into an integrated structure (e.g., integrally formed).

[0049] The second structure can be divided by the second trench 210b to form a plurality of second structures. In other words, the second trench 210b can extend from the cell region A to the through-cell wiring region B in the first direction, and the second structure can be spaced apart in a second direction orthogonal to the first direction in a plan view. A trench or an opening can not be included in each of the second structures. In other words, each cell block can form one second structure.

[0050] The conductive pattern (i.e., the gate pattern 230) of the first structure can extend to the second structure in the first direction. In other words, the gate pattern 230 can be connected to the conductive pattern 230b included in the second structure. The conductive pattern 230b can extend to an edge of the second structure adjacent to the second trench 210b in the second direction.

[0051] According to an example embodiment of the inventive concept, in a plan view, the set of pad patterns 230a can have a straight line shape in the through-cell wiring region B, the straight line shape including two first sides extending in the first direction and two second sides extending in the second direction. The conductive pattern 230b can contact one of the second sides of the pad pattern 230a. Further, the conductive pattern 230b can contact one of the first sides of the pad pattern 230a. An inner surface of the first side of the pad pattern 230a can surround the first sacrificial pattern 122 and the first insulating layer 120 alternately disposed.

[0052] Further, a pad pattern 230a can be formed at a stepped portion of the second structure, and a sidewall of the pad pattern 230a can be connected to a conductive pattern 230b. The gate pattern 230 can be electrically connected to the pad pattern 230a via the conductive pattern 230b. Thus, the same level of the gate pattern 230 can be electrically connected with the same level of the conductive pattern 230b and the pad pattern 230a.

[0053] The gate pattern 230, the conductive pattern 230b, and the pad pattern 230a can include substantially the same conductive material.

[0054] The pad pattern 230a can further protrude from the conductive pattern in the second direction toward a central portion of the second structure. The pad pattern 230a can serve as a pad for contacting the first contact plug 202a electrically connected with the gate pattern 230 and the circuit pattern.

[0055] In an exemplary embodiment of the inventive concept, a structure including the stacked first insulating layer 120, the second insulating layer 150, and the first and fourth sacrificial layers 122 and 152 can be located below the pad pattern 230a in the vertical direction. Thus, no conductive material can be disposed below the pad pattern 230a in the vertical direction.

[0056] In an exemplary embodiment of the inventive concept, an upper surface of the pad pattern 230a can be higher than an upper surface of a gate pattern disposed in the same layer as the pad pattern 230a in the vertical direction, and a thickness of the pad pattern 230a can be greater than a thickness of the gate pattern disposed in the same layer as the pad pattern 230a.

[0057] The first contact hole 200a can pass through the third insulating intermediate layer 172, the second insulating intermediate layer 164, the first insulating intermediate layer 134, the second structure, and the base insulating layer 114, and the first contact hole 200a can extend to an upper portion of the lower insulating intermediate layer 110 (e.g., partially penetrate the upper portion of the lower insulating intermediate layer 110). An upper surface of the lower pad 108a can be exposed by a bottom surface of the first contact hole 200a. The first contact plug 202a can be formed in the first contact hole 200a.

[0058] A sidewall of the first contact plug 202a can contact the pad pattern 230a (e.g., penetrate an end portion of a stepped portion of the second structure on which the pad pattern 230a is disposed), and a bottom surface of the first contact plug 202a can contact an upper surface of the lower pad 108a. Thus, at least one of the gate pattern 230 and the peripheral circuit can be electrically connected by the first contact plug 202a.

[0059] In an exemplary embodiment of the inventive concept, the first contact plug 202a can include a metal. The first contact plug 202a can include a metal such as W, copper (Cu), aluminum (Al), etc. For example, the first contact plug 202a can include a barrier metal pattern and / or a metal pattern.

[0060] The first contact hole 200a can include two curved portions. Accordingly, a sidewall of the first contact plug 202a formed in the first contact hole 200a can include two curved portions b1 and b2. For example, the two curved portions b1 and b2 can each have a tapered shape that narrows toward the upper surface of the substrate 100 in a vertical direction. A narrow end of the curved portion b2 can be disposed on a widest portion of the curved portion b1.

[0061] An upper surface of the first contact plug 202a can be coplanar with an upper surface of the third insulating intermediate layer 172.

[0062] A third structure including the stacked first insulating layer 120, the first sacrificial layer 122, the second insulating layer 150, and the fourth sacrificial layer 152 can be formed on the base insulating layer 114 in the through-wiring area C. The third structure can include the second lower molding structure 132 and the second upper molding structure 162. In an exemplary embodiment of the inventive concept, the third structure can not have a conductive material.

[0063] The third insulating intermediate layer 172 can be formed to cover the third structure.

[0064] In other words, the third insulating intermediate layer 172 can be formed on the first structure to the third structure.

[0065] The second contact hole 200b can be formed to pass through the third insulating intermediate layer 172, the third structure, and the base insulating layer 114, and the second contact hole 200b can extend to an upper portion of the lower insulating intermediate layer 110. An upper surface of the lower pad 108a can be exposed by a bottom surface of the second contact hole 200b. The second contact plug 202b can be formed in the second contact hole 200b.

[0066] A sidewall of the second contact plug 202b can not contact a conductive material, and a bottom surface of the second contact plug 202b can contact the upper surface of the lower pad 108a. Accordingly, the second contact plug 202b can be electrically connected to the peripheral circuit.

[0067] In an exemplary embodiment of the inventive concept, the second contact plug 202b can include substantially the same metal as the metal of the first contact plug 202a.

[0068] The second contact hole 200b can include two curved portions. Accordingly, a sidewall of the second contact plug 202b formed in the second contact hole 200b can include two curved portions b1 and b2. According to an exemplary embodiment of the inventive concept, the curved portions b1 and b2 can have substantially the same shape as the curved portions b1 and b2 described with reference to the second structure.

[0069] An upper surface of the second contact plug 202b can be coplanar with an upper surface of the third insulating intermediate layer 172.

[0070] In an exemplary embodiment of the inventive concept, an upper surface of the channel structure 190, an upper surface of the first contact plug 202a, and an upper surface of the second contact plug 202b can be coplanar with each other.

[0071] The first curved portions b1 of the first contact plug 202a and the second contact plug 202b disposed at a lower portion of the channel structure 190 can be coplanar with each other. In addition, the second curved portions b2 of the first contact plug 202a and the second contact plug 202b disposed at an upper portion of the channel structure 190 can be coplanar with each other.

[0072] In an exemplary embodiment of the inventive concept, an insulating pattern 232 can be formed in the first trench 210a and the second trench 210b.

[0073] A fourth insulating intermediate layer 240 can be formed on the channel structure 190, the first contact plug 202a, the second contact plug 202b, the insulating pattern 232, and the third insulating intermediate layer 172.

[0074] A first upper contact 242 can be formed through the fourth insulating intermediate layer 240 to contact the upper conductive pattern 186 of the channel structure 190. A second upper contact 254 can be formed through the fourth insulating intermediate layer 240 to contact the second contact plug 202b.

[0075] In addition, a first upper wiring 244 can be electrically connected to the first upper contact 242, and a second upper wiring 256 can be electrically connected to the second upper contact 254, and can be formed on the fourth insulating intermediate layer 240. The first upper wiring 244 can function as a bit line.

[0076] In an exemplary embodiment of the inventive concept, an additional upper wiring can not be formed on the first contact plug 202a.

[0077] In an exemplary embodiment of the inventive concept, an SSL contact 250 can also be formed through the fourth insulating intermediate layer 240, the third insulating intermediate layer 172, and the second insulating intermediate layer 164 to contact the gate pattern 230. In addition, a third upper wiring 252 can also be formed to contact the SSL contact 250.

[0078] In the exemplary embodiment of the present inventive concept, a fifth insulating intermediate layer can also be formed to cover the first upper wiring 244, the second upper wiring 256, and the third upper wiring 252.

[0079] FIG. 5 、 FIG. 6 、 FIG. 7 、 FIG. 8 、 FIG. 9 、 FIG. 10 、 FIG. 11 、 FIG. 12 、 FIG. 13 、 FIG. 14 、 FIG. 15 、 FIG. 16 、 FIG. 17 、 FIG. 18 、 FIG. 19 、 FIG. 20 、 FIG. 21 、 FIG. 22 、 FIG. 23 and FIG. 24 are plan views and sectional views showing stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the present inventive concept.

[0080] FIG. 18 、 FIG. 20 and FIG. 22 are plan views. FIG. 5 、 FIG. 6 、 FIG. 7 、 FIG. 8 、 FIG. 9 、 FIG. 10 、 FIG. 11 、 FIG. 12 、 FIG. 13 、 FIG. 14 、 FIG. 15 、 FIG. 16 、 FIG. 17 、 FIG. 19 、 FIG. 21 、 FIG. 23 and FIG. 24 are sectional views taken along lines I-I' and lines II-II' of FIG. 1 .

[0081] Referring to FIG. 5 , a circuit pattern constituting a peripheral circuit can be formed on the base 100, and a lower insulating intermediate layer 110 can be formed to cover the circuit pattern. The base 100 can include a cell region A, a through-cell wiring region B, and a through-wiring region C.

[0082] A trench isolation process can be performed on the base 100 to form a field region having an isolation pattern 102 and an active region not having the isolation pattern.

[0083] The circuit pattern can include lower transistors 104, lower contact plugs 106, lower wiring lines 108, etc. Each lower transistor 104 can include a gate structure 104b and an impurity region 104a. The lower contact plugs 106 can be formed to contact the gate structure 104b and / or the impurity region 104a. For example, a first lower contact plug 106 can have a lower surface in contact with the gate structure 104b or the impurity region 104a and an upper surface in contact with a lower wiring line 108 or a lower pad 108a. The lower wiring line 108 can be electrically connected to the lower contact plug 106.

[0084] Some of the lower wiring lines 108 can be used as lower pads 108a for contacting first and second contact plugs to be described later. In an exemplary embodiment of the inventive concept, the lower contact plugs 106 and the lower wiring lines 108 can be formed to have multiple layers.

[0085] A base pattern 112 can be formed on the lower insulating interlayer 110. The base pattern 112 can include, for example, polysilicon and / or silicon. The base pattern 112 can be etched or otherwise processed to create gaps between remaining portions. Further, a base insulating layer 114 can be formed on the lower insulating interlayer 110 to fill spaces between the base patterns 112. In an exemplary embodiment of the inventive concept, an upper surface of the base pattern 112 and an upper surface of the base insulating layer 114 can be coplanar with each other. According to an exemplary embodiment of the inventive concept, the base insulating layer 114 can be disposed on the lower insulating interlayer 110 before the base pattern 112 is formed, and the base pattern 112 can be disposed in etched spaces between remaining portions of the base insulating layer 114. A first base pattern 112 can be disposed under a final first structure in the cell region A, and a second base pattern 112 can be disposed at an edge portion of the through wiring region C.

[0086] A plurality of base insulating layers 114 can be formed at portions for forming first and second contact plugs, respectively.

[0087] Referring to FIG. 6 A first insulating layer 120 and a first sacrificial layer 122 can be alternately and repeatedly stacked on the base pattern 112 and the base insulating layer 114. The first insulating layer 120 can include, for example, silicon oxide. The first sacrificial layer 122 can include a material having etching selectivity with respect to the first insulating layer 120. The first sacrificial layer 122 can include a nitride such as silicon nitride.

[0088] The structure including the first insulating layer 120 and the first sacrificial layer 122 stacked repeatedly can be patterned to form the first lower molding structure 130 having a stair shape (e.g., a step shape) at an edge portion of the structure. The lowermost step of the stair shape can be aligned with an outer surface of the rest of the base pattern 112 in a vertical direction. In addition, the second lower molding structure 132 can be formed adjacent to the first lower molding structure 130. The second lower molding structure 132 can not have a stair shape at an edge portion thereof. For example, a sidewall of the second lower molding structure 132 can have a vertical slope.

[0089] The first lower molding structure 130 can be formed on the cell region A and the through-cell wiring region B of the substrate 100. The stepped portion of the first lower molding structure 130 can be formed on the through-cell wiring region B. The second lower molding structure can be formed on the through-wiring region C.

[0090] In the example embodiment of the inventive concept, the first sacrificial layer 122 can be exposed by an upper surface of each stepped portion of the first lower molding structure 130. For example, the upper surface of each stepped portion can be an end portion of the corresponding first sacrificial layer 122.

[0091] Referring to FIG. 7 The second sacrificial layer 128a can be conformally formed on a surface of the first lower molding structure 130. The second sacrificial layer 128a can include a silicon nitride-based material similar to that of the first sacrificial layer 122, but the second sacrificial layer 128a can have an etching rate higher than that of the first sacrificial layer 122.

[0092] A plasma surface treatment process can be performed on a surface of the second sacrificial layer 128a. When plasma is injected onto the surface of the second sacrificial layer 128a, plasma damage can occur on a flat upper surface portion of the second sacrificial layer 128a. In this case, plasma damage can hardly occur on the second sacrificial layer formed on the sidewall of the stepped portion. Hereinafter, the plasma-treated portion of the second sacrificial layer 128a can also be referred to as a third sacrificial pattern 128b.

[0093] The third sacrificial pattern 128b can have a density higher than that of the second sacrificial layer 128a, and the third sacrificial pattern 128b can have an impurity concentration higher than that of the second sacrificial layer 128a. Accordingly, the third sacrificial pattern 128b can have an etching rate lower than that of the second sacrificial layer 128a.

[0094] Then, the second sacrificial layer 128a formed on the sidewall of the stepped portion of the first lower molding structure 130 can be selectively etched to form a second sacrificial pattern 128a. The etching process can include a wet etching process. In this case, the third sacrificial pattern 128b can serve as an etching mask in the wet etching process. Accordingly, a structure including the stacked second sacrificial pattern 128a and the third sacrificial pattern 128b can be formed on the first sacrificial layer 122 formed on the stepped portion (i.e., the exposed edge portion) of the first lower molding structure 130.

[0095] In an exemplary embodiment of the inventive concept, the first sacrificial layer 122 can have a first etching rate, the second sacrificial pattern 128a can have a second etching rate higher than the first etching rate, and the third sacrificial pattern 128b can have a third etching rate lower than the second etching rate. Further, the third etching rate can be lower than the first etching rate.

[0096] An insulating layer can be formed to cover the edge portion of the first lower molding structure 130, and an upper surface of the insulating layer can be planarized to form a first insulating intermediate layer 134. In an exemplary embodiment of the inventive concept, an upper surface of the first lower molding structure 130, an upper surface of the first insulating intermediate layer 134, and an upper surface of the second lower molding structure 132 can be coplanar with each other. In addition, the first insulating intermediate layer 134 can form a shape complementary to the stepped structure of the first lower molding structure 130.

[0097] Referring to FIG. 8 The first insulating intermediate layer 134, the first lower molding structure 130, the second sacrificial pattern 128a and the third sacrificial pattern 128b, the second lower molding structure 132, the base insulating layer 114, and the lower insulating intermediate layer 110 can be partially etched to form a first trench hole 140a, a first via hole 140b, and a second via hole 140c.

[0098] The first trench hole 140a can be formed through the first lower molding structure 130 on the cell region A. An upper surface of the base pattern 112 can be exposed by a bottom surface of the first trench hole 140a.

[0099] The first via holes 140b can pass through the first insulating intermediate layer 134, the first lower molding structure 130, the second sacrificial pattern 128a and the third sacrificial pattern 128b, and the base insulating layer 114 on the through-cell wiring area B. In addition, the upper portion of the lower insulating intermediate layer 110 can be partially etched so that the upper surface of the lower pad 108a is exposed by the first via holes 140b. Some of the first via holes 140b can pass through a portion of the second sacrificial pattern 128a and a portion of the third sacrificial pattern 128b in the through-cell wiring area B. Accordingly, the side surface of the second sacrificial pattern 128a and the side surface of the third sacrificial pattern 128b can be exposed by the sidewall of the first via holes 140b. In addition, some of the first via holes 140b can pass through only the first lower molding structure 130.

[0100] The second via holes 140c can pass through the second lower molding structure 132 and the base insulating layer 114 on the through-wiring area C. In addition, the upper portion of the lower insulating intermediate layer 110 can be partially etched so that the upper surface of the lower pad 108a is exposed by the second via holes 140c.

[0101] The first trench holes 140a, the first via holes 140b, and the second via holes 140c can be formed together by one etching process. The etching process can include an anisotropic etching process.

[0102] Referring to FIG. 9 A fill layer can be formed to fill the first trench holes 140a, the first via holes 140b, and the second via holes 140c, and the fill layer can be planarized until the upper surface of the first insulating intermediate layer, the upper surface of the first lower molding structure 130, and the upper surface of the second lower molding structure 132 can be exposed. Accordingly, a first fill pattern 142a can be formed in each of the first trench holes 140a, a second fill pattern 142b can be formed in each of the first via holes 140b, and a third fill pattern 142c can be formed in each of the second via holes 140c.

[0103] The first fill pattern 142a, the second fill pattern 142b, and the third fill pattern 142c can include a material having a high etching selectivity with respect to each of the first sacrificial layer 122 and the first insulating layer 120. In some exemplary embodiments of the inventive concept, the first fill pattern 142a, the second fill pattern 142b, and the third fill pattern 142c can include polysilicon.

[0104] Referring to FIG. 10 A first upper molding structure 160 and a second upper molding structure 162 can be formed on the first insulating intermediate layer 134, the first lower molding structure 130, the second lower molding structure 132, and the first fill pattern 142a, the second fill pattern 142b, and the third fill pattern 142c.

[0105] Specifically, the second insulating layers and the fourth sacrificial layers can be alternately and repeatedly stacked on the first insulating intermediate layer 134, the first lower molding structure 130, the second lower molding structure 132, and the first, second, and third filling patterns 142a, 142b, and 142c. The second insulating layers 150 and the fourth sacrificial layers 152 can be patterned to form the first upper molding structure 160 and the second upper molding structure 162.

[0106] The first upper molding structure 160 can be formed on the first lower molding structure 130. The edge of the first upper molding structure 160 can have a stair shape (e.g., a stepped shape) connected to the stepped portion of the edge of the first lower molding structure 130. For example, the edge of the first upper molding structure 160 can be aligned with the edge of the first lower molding structure 130.

[0107] Then, the fifth and sixth sacrificial patterns 158a and 158b are stacked on the fourth sacrificial layers 152 at the edge of the first upper molding structure 160. The process for forming the fifth and sixth sacrificial patterns 158a and 158b can be substantially the same as the process for forming the second and third sacrificial patterns 128a and 128b with reference to FIGS. 12A and 12B. FIG. 7

[0108] With reference to FIG. 11 An insulating layer can be formed to cover the edge portion of the first upper molding structure 160, and the insulating layer can be planarized to form a second insulating intermediate layer 164. In an exemplary embodiment of the inventive concept, the upper surface of the first upper molding structure 160, the upper surface of the second insulating intermediate layer 164, and the upper surface of the second upper molding structure 162 can be coplanar with each other.

[0109] The second insulating intermediate layer 164, the first upper molding structure 160, the fifth and sixth sacrificial patterns 158a and 158b, and the second upper molding structure 162 can be partially etched to form the second trench hole 170a, the third and fourth via holes 170b and 170c.

[0110] The second trench hole 170a can be formed through the first upper molding structure 160 on the cell region A. The upper surface of the first filling pattern 142a can be exposed by the bottom surface of the second trench hole 170a.

[0111] The third via holes 170b can be formed through the second insulating intermediate layer 164, the first upper molding structure 160, and the fifth and sixth sacrificial patterns 158a and 158b on the through-cell wiring region B. Some of the third via holes 170b can pass through only the second insulating intermediate layer 164. The upper surface of the second filling pattern 142b can be exposed by the bottom surface of the third via holes 170b. ​

[0112] A fourth via hole 170c can be formed through the second upper molding structure 162 on the through-wiring region C. An upper surface of the third fill pattern 142c can be exposed by a bottom surface of the fourth via hole 170c.

[0113] The second trench hole 170a, the third via hole 170b, and the fourth via hole 170c can be formed together by one etching process. The etching process can include, for example, an anisotropic etching process.

[0114] Referring to FIG. 12 A third insulating intermediate layer 172 can be formed to cover the first upper molding structure 160, the second upper molding structure 162, and the second insulating intermediate layer 164. The third insulating intermediate layer 172 can be formed not to fill the second trench hole 170a, the third via hole 170b, and the fourth via hole 170c. Accordingly, an inner space of the second trench hole 170a, an inner space of the third via hole 170b, and an inner space of the fourth via hole 170c can be maintained under the third insulating intermediate layer 172.

[0115] The third insulating intermediate layer 172 can include silicon oxide. The third insulating intermediate layer 172 can be formed by a deposition process having poor step coverage properties. For example, the third insulating intermediate layer 172 can be formed by a chemical vapor deposition process. In an exemplary embodiment of the inventive concept, the third insulating intermediate layer 172 can include a TEOS material.

[0116] Referring to FIG. 13 The third insulating intermediate layer 172 on the cell region A can be etched to form a first upper hole 174a connected to the second trench hole 170a. Accordingly, an upper surface of the first fill pattern 142a can be exposed by the first upper hole 174a and the second trench hole 170a. In an exemplary embodiment of the inventive concept, a sidewall of a portion between the first upper hole 174a and the second trench hole 170a can have a curved shape.

[0117] In this case, an upper portion of the third via hole 170b and an upper portion of the fourth via hole 170c can be covered by the third insulating intermediate layer 172.

[0118] Referring to FIG. 14 The first fill pattern 142a exposed by the first upper hole 174a and the second trench hole 170a can be removed. The removing process can include, for example, an isotropic etching process.

[0119] Accordingly, the first upper hole 174a, the second trench hole 170a, and the first trench hole 140a can be connected to each other in a vertical direction to form one trench hole 176a. In the trench hole 176a, a side wall of a portion between the first upper hole 174a and the second trench hole 170a and a side wall of a portion between the second trench hole 170a and the first trench hole 140a can have a curved portion, respectively. In other words, the trench hole 176a can include two curved portions b1 and b2.

[0120] Referring to FIG. 15 A trench structure 190 can be formed in the trench hole 176a.

[0121] In exemplary embodiments of the inventive concept, the trench structure 190 can include the charge storage structure 180, a channel 182, and an upper conductive pattern 186. The channel 182 can be electrically connected to the base pattern 112.

[0122] Specifically, the charge storage structure 180 including a blocking pattern 180c, a charge storage pattern 180b, and a tunnel insulating pattern 180a can be formed on a side wall of each trench hole 176a. Thereafter, a channel layer can be formed on the charge storage structure 180 to fill the trench hole 176a, and an upper surface of the channel layer can be planarized. Accordingly, the channel 182 can be formed to fill the first trench hole 140a and the second trench hole 170a, and the upper conductive pattern 186 can be formed in the first upper hole 174a. The channel 182 and the upper conductive pattern 186 can include, for example, polysilicon.

[0123] In some exemplary embodiments of the inventive concept, as shown in FIG. 4B The trench structure 190 can include the charge storage structure 180, the channel 182, a fill insulating pattern 184, and the upper conductive pattern 186. In other words, the channel 182 can be formed to have a cylindrical shape. Further, the fill insulating pattern 184 can be formed on the channel to fill the first trench hole 140a and the second trench hole 170a.

[0124] In some exemplary embodiments of the inventive concept, as shown in FIG. 4C A channel connection pattern 188 can also be formed on the base pattern 112 to surround an outer wall of a lower portion of the channel 182. Accordingly, the channel connection pattern 188 can be electrically connected with the adjacent channel 182 and the base pattern 112.

[0125] Referring to FIG. 16A third insulating intermediate layer 172 can be formed on the through-cell wiring region B, and the third insulating intermediate layer 172 can be etched to form a second upper hole 194a connected with the third via hole 170b. In addition, the third insulating intermediate layer 172 on the through-wiring region C can be etched to form a third upper hole 194b in communication with the fourth via hole 170c. The second upper hole 194a and the third upper hole 194b can be formed together through the same etching process.

[0126] Accordingly, an upper surface of the second fill pattern 142b can be exposed by the second upper hole 194a and the third via hole 170b. In addition, an upper surface of the third fill pattern 142c can be exposed by the third upper hole 194b and the fourth via hole 170c.

[0127] Referring to FIG. 17 and FIG. 18 The second fill pattern 142b exposed by the second upper hole 194a and the third via hole 170b can be removed, and the third fill pattern 142c exposed by the third upper hole 194b and the fourth via hole 170c can be removed to form a first contact hole 200a and a second contact hole 200b.

[0128] Accordingly, the second upper hole 194a, the third via hole 170b, and the first via hole 140b can be connected to each other in a vertical direction to form the first contact hole 200a. The second sacrificial pattern 128a and the third sacrificial pattern 128b or the fifth sacrificial pattern 158a and the sixth sacrificial pattern 158b can be exposed by a sidewall of the first contact hole 200a. In addition, an upper surface of the lower pad 108a can be exposed by a bottom of the first contact hole 200a. The first contact hole 200a can include two curved portions b1 and b2.

[0129] In addition, the third upper hole 194b, the fourth via hole 170c, and the second via hole 140c can be connected to each other in a vertical direction to form the second contact hole 200b. An upper surface of the lower pad 108a can be exposed by a bottom of the second contact hole 200b. The second contact hole 200b can include two curved portions b1 and b2.

[0130] Referring to FIG. 19 and FIG. 20 A conductive layer can be formed to fill the first contact hole 200a and the second contact hole 200b, and the conductive layer can be planarized until an upper surface of the third insulating intermediate layer 172 can be exposed to form a first contact plug 202a and a second contact plug 202b. The first contact plug 202a can be formed in the first contact hole 200a, and the second contact plug 202b can be formed in the second contact hole 200b. The first contact plug 202a and the second contact plug 202b can include a metal.

[0131] In exemplary embodiments of the inventive concept, an upper surface of the channel structure 190 can be coplanar with an upper surface of the first contact plug 202a and an upper surface of the second contact plug 202b.

[0132] Subsequently, portions of the stack structure including the first upper molding structure 160 and the first lower molding structure 130 can be etched to form first and second trenches 210a and 210b extending in the first direction and spaced apart in the second direction. An upper surface of the base pattern 112 or an upper surface of the base insulating layer 114 can be exposed by bottoms of the first and second trenches 210a and 210b.

[0133] The first trench 210a can serve as a word line cut portion. Accordingly, the first trench 210a can be disposed on the cell region A. The second trench 210b can serve as a block cut portion. Accordingly, the second trench 210b can be disposed on the cell region A and the through-cell wiring region B.

[0134] Sides of the first and second insulating layers 120 and 150 and sides of the first and fourth sacrificial layers 122 and 152 can be exposed by sides of the first and second trenches 210a and 210b.

[0135] Adjacent stack structures including the first upper molding structure 160 and the first lower molding structure 130 can be separated by the second trench 210b. In some exemplary embodiments of the inventive concept, the second trench 210b can extend through the through-wiring region C such that stack structures including the second upper molding structure 162 and the second lower molding structure 132 can be separated by the second trench 210b.

[0136] In exemplary embodiments of the inventive concept, a third trench 210c serving as a string selection line SSL cut region can also be formed. In the first upper molding structure 160, an uppermost fourth sacrificial layer 152 and at least one fourth sacrificial layer 152 thereunder can be partially etched to form the third trench 210c.

[0137] Referring to FIG. 21 and FIG. 22 Portions of the first and fourth sacrificial layers 122 and 152 exposed by the first and second trenches 210a and 210b can be removed to form gaps between the first and second insulating layers 120 and 150, respectively. The removing process can include, for example, an isotropic etching process.

[0138] For example, all of the first and fourth sacrificial layers 122 and 152 disposed on the cell region A can be removed. Accordingly, a first gap 212 can be formed in the cell region A.

[0139] The first and fourth sacrificial layers 122 and 152, the second and third sacrificial patterns 128a and 128b, and the fifth and sixth sacrificial patterns 158a and 158b disposed on the through-cell wiring region B can be partially removed.

[0140] In this case, the first and fourth sacrificial layers 122 and 152 adjacent to the second trenches 210b can be etched to form second gaps 214. Also, portions in which the first sacrificial layer 122 is stacked with the second and third sacrificial patterns 128a and 128b and the fourth sacrificial layer 152 is stacked with the fifth and sixth sacrificial patterns 158a and 158b can be etched to form third gaps 216.

[0141] Since the interval between the second trenches 210b is greater than the interval between the first trenches 210a, the first and fourth sacrificial layers 122 and 152, the second and third sacrificial patterns 128a and 128b, and the fifth and sixth sacrificial patterns 158a and 158b can be partially removed by the etching process. In other words, portions of the first lower molding structure 130 and the first upper molding structure 160 between the second trenches 210b can remain without being removed.

[0142] The second gaps 214 can have a first length from the second trenches 210b in a second direction perpendicular to the first direction.

[0143] The second and fifth sacrificial patterns 128a and 158a can be etched faster than the first and fourth sacrificial layers 122 and 152 and the third and sixth sacrificial patterns 128b and 158b. Also, the etchant can further penetrate in the first direction from the gaps formed by removing the second and fifth sacrificial patterns 128a and 158a. Accordingly, the sacrificial layer and sacrificial pattern portions formed above and below the second and fifth sacrificial patterns 128a and 158a can be further etched. Thus, the portions including the second and fifth sacrificial patterns 128a and 158a can be etched to form the third gaps 216 having a second length greater than the first length in the second direction. In other words, the third gaps 216 can protrude from the second gaps 214 in the second direction.

[0144] The etchant can flow out from portions adjacent to the ends of the first trenches 210a to form fourth gaps in the through-cell wiring region B adjacent to the cell region A. In the same level in the vertical direction, the first, second, third, and fourth gaps 212, 214, 216, and 218 can be connected to each other.

[0145] Referring to FIG. 23The first conductive layer can be formed to fill the first gap 212, the second gap 214, the third gap 216, and the fourth gap 218, and can be formed in the first trench 210a and the second trench 210b. The first conductive layer can include a metal such as W, Cu, Al, or the like. Before the first conductive layer is formed, a barrier metal layer can also be formed on the surfaces of the first trench 210a and the second trench 210b, and the surfaces of the first gap 212, the second gap 214, the third gap 216, and the fourth gap 218.

[0146] Thereafter, the first conductive layer formed in the first trench 210a and the second trench 210b can be removed to form a conductive pattern in the first gap 212, the second gap 214, the third gap 216, and the fourth gap 218.

[0147] In the exemplary embodiment of the inventive concept, the conductive pattern formed in the first gap 212 can be used as a gate pattern 230. The conductive pattern formed in the third gap 216 can be used as a pad pattern 230a. In addition, the conductive patterns formed in the second gap 214 and the fourth gap 218 can be used as connection lines for connecting the gate pattern 230 and the pad pattern 230a.

[0148] In other words, the same level of conductive patterns can be electrically connected to each other. The pad pattern 230a can be used as an actual pad for contacting the first contact plug 202a.

[0149] The portion of the through-unit wiring area B in which the second gap 214, the third gap 216, and the fourth gap 218 are not formed can not be replaced with a conductive material, so that an insulating structure including the first insulating layer 120, the first sacrificial layer 122, the second and third sacrificial patterns 128a and 128b, the second insulating layer 150, the fourth sacrificial layer 152, and the fifth and sixth sacrificial patterns 158a and 158b can be preserved.

[0150] Referring to FIG. 24 The insulating pattern 232 can be formed to fill each of the first trench 210a and the second trench 210b.

[0151] By performing the above-described process, the sidewall of the first contact plug 202a can contact the pad pattern 230a. In addition, the bottom of the first contact plug 202a can contact the lower pad 108a. Thus, the pad pattern 230a connected to the gate pattern of one layer and the lower pad 108a connected to the peripheral circuit can be electrically connected through the first contact plug 202a.

[0152] In addition, the bottom of the second contact plug 202b can contact the lower pad 108a. Thus, the second contact plug 202b can be electrically connected to the peripheral circuit.

[0153] As described above, the via for forming the channel structure 190 as well as the first and second contact plugs 202a and 202b can not be formed through a separate etching process, but can be formed together through the same etching process. Thus, the process for forming the channel structure 190 as well as the first and second contact plugs 202a and 202b can be simplified.

[0154] Referring again to FIG. 5 A fourth insulating interlayer 240 can be formed on the third insulating interlayer 172, the channel structure 190, the first and second contact plugs 202a and 202b, and the insulating pattern 232.

[0155] A first upper contact 242 in contact with the upper conductive pattern 186 of the channel structure 190 and a second upper contact 254 in contact with the second contact plug 202b can be formed through the fourth insulating interlayer 240. Further, a first upper wiring 244 electrically connected to the first upper contact 242 can be formed on the first upper contact 242, a second upper wiring 256 can be electrically connected to the second upper contact 254, and can be formed on the second upper contact 254.

[0156] In exemplary embodiments of the inventive concept, an upper contact and an upper wiring can not be formed on the first contact plug 202a.

[0157] In some exemplary embodiments of the inventive concept, an SSL contact 250 can be formed through the second, third, and fourth insulating interlayers 164, 172, and 240 to contact the upper surface of each gate pattern corresponding to a string select line SSL. In addition, a third upper wiring 252 can be formed to connect the SSL contact 250.

[0158] According to exemplary embodiments of the inventive concept, a fifth insulating interlayer covering the first, second, and third upper wirings 244, 256, and 252 can be formed on the fourth insulating interlayer 240.

[0159] Thereafter, additional upper wirings can be formed so that a vertical memory device can be manufactured.

[0160] Hereinafter, a method of manufacturing a vertical memory device according to some exemplary embodiments of the inventive concept will be described.

[0161] FIG. 32 、 FIG. 6 、 FIG. 7 、 FIG. 33 、 FIG. 8 and FIG. 9is a cross-sectional view showing stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the present inventive concept.

[0162] Referring to FIG. 10 , the process shown in FIG. 11 , FIG. 12 , FIG. 13 , and FIG. 14 may be performed to form the first channel hole 140a, the first via hole 140b, and the second via hole 140c.

[0163] A fill layer can be formed to fill the first channel hole 140a, the first via hole 140b, and the second via hole 140c. The fill layer can include a material having a high etch selectivity with respect to each of the first sacrificial layer 122 and the first insulating layer 120.

[0164] The fill layer can include a conductive material. In an exemplary embodiment of the present inventive concept, the fill layer can include a metal such as W, Cu, Al, or the like. For example, the fill layer can include a barrier metal layer and / or a metal layer.

[0165] The fill layer can be planarized until an upper surface of the first insulating intermediate layer 134, an upper surface of the first lower molding structure 130, and an upper surface of the second lower molding structure 132 can be exposed to form a first fill pattern 272a, a first lower contact plug 272b, and a second lower contact plug 272c. The first fill pattern 272a can be formed in each of the first channel holes 140a, the first lower contact plug 272b can be formed in each of the first via holes 140b, and the second lower contact plug 272c can be formed in each of the second via holes 140c.

[0166] Referring to FIG. 31 , the process shown in FIG. 34 , FIG. 1 , FIG. 2 , FIG. 3A , and FIG. 3B may be performed to form a channel hole 176a including the first upper hole 174a, the second channel hole 170a, and the first channel hole 140a connected to each other in a vertical direction. In the channel hole 176a, the curved portions b1 and b2 can be located at sidewalls of portions between the first upper hole 174a and the second channel hole 170a and between the second channel hole 170a and the first channel hole 140a, respectively. In other words, the channel hole 176a can include two curved portions b1 and b2.

[0167] Referring to FIG. 4A , a channel structure 190 can be formed in the channel hole 176a. The process for forming the channel structure 190 can be substantially the same as the process shown in FIG. 4B .

[0168] Referring to FIG. 4C A portion of the third insulating intermediate layer 172 formed on the through-cell wiring region B can be etched to form a second upper hole 194a connected with the third via hole 170b. Also, a portion of the third insulating intermediate layer 172 formed on the through-wiring region C can be etched to form a third upper hole 194b connected with the fourth via hole 170c. The second upper hole 194a and the third upper hole 194b can be formed together by the same etching process.

[0169] An upper surface of the first lower contact plug 272b can be exposed by the second upper hole 194a and the third via hole 170b. Also, an upper surface of the second lower contact plug 272c can be exposed by the third upper hole 194b and the fourth via hole 170c.

[0170] Referring to FIG. 34 A conductive layer can be formed on the third insulating intermediate layer 172 to fill the second upper hole 194a, the third via hole 170b, and the third upper hole 194b, the fourth via hole 170c. The conductive layer can be planarized until an upper surface of the third insulating intermediate layer 172 can be exposed. Thus, a first upper contact plug 274a can be formed in the second upper hole 194a and the third via hole 170b, and a second upper contact plug 274b can be formed in the third upper hole 194b and the fourth via hole 170c. The first upper contact plug 274a and the second upper contact plug 274b can include a metallic material. For example, the first upper contact plug 274a and the second upper contact plug 274b can include a barrier metal pattern and / or a metal pattern.

[0171] Thus, a stack including the first lower contact plug 272b and the first upper contact plug 274a can function as a first contact plug. A stack including the second lower contact plug 272c and the second upper contact plug 274b can function as a second contact plug. Thereafter, as shown in FIG. 2 a first trench 210a and a second trench 210b are formed.

[0172] Also, substantially the same or similar processes as shown in FIG. 35 , FIG. 36 , FIG. 37 and FIG. 38 may be performed, so that a vertical memory device as shown in FIG. 39 may be manufactured.

[0173] FIG. 5 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept.

[0174] The vertical memory device can be substantially the same as the vertical memory device shown in FIGS. 1A to 1C except that the second lower molding structure 132 and the second upper molding structure 162 can not be formed on the through-wiring region C. FIG. 35 、 FIG. 6 、 FIG. 7 、 FIG. 36 、 FIG. 37 、 FIG. 38 and FIG. 15 .

[0175] Referring to FIG. 39 , the first insulating intermediate layer 134a and the second insulating intermediate layer 164a can be formed on the base insulating layer 114 of the through-wiring region C.

[0176] Accordingly, the second contact plug 202b can pass through the third insulating intermediate layer 172, the second insulating intermediate layer 164a, the first insulating intermediate layer 134a, and the base insulating layer 114, and the second contact plug 202b can extend to the upper portion of the lower insulating intermediate layer 110. The bottom surface of the second contact plug 202b can contact the upper surface of the lower pad 108a.

[0177] FIG. 19 and FIG. 19 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment of the present inventive concept.

[0178] The vertical memory device can be manufactured by the same or similar processes as those illustrated with reference to FIG. 20 、 FIG. 21 、 FIG. 22 、 FIG. 23 、 FIG. 24 、 FIG. 34 、 FIG. 40 、 FIG. 34 、 FIG. 40 、 FIG. 41 、 FIG. 42 、 FIG. 42 、 FIG. 41 、 FIG. 1 、 FIG. 2 、 FIG. 3A 、 FIG. 3B 、 FIG. 4A 、 FIG. 4B and FIG. 4C . However, the second lower molding structure 132 and the second upper molding structure 162 can not be formed.

[0179] First, the same processes as those illustrated with reference to FIG. 41 may be performed.

[0180] Referring to FIG. 42The first insulating layer 120 and the first sacrificial layer 122 can be alternately and repeatedly stacked on the substrate pattern 112 and the substrate insulating layer 114. The structure including the repeatedly stacked first insulating layer 120 and the first sacrificial layer 122 can be patterned to form a first undermolded structure 130. The first undermolded structure can be formed on the cell region A and the through-cell wiring region B of the substrate 100, and the edge portions of the first undermolded structure 130 can have a stepped shape (e.g., a step shape). In this case, a second undermolded structure may not be formed on the through-wire region C.

[0181] After that, it can be executed and referenced. ​ and ​ The process shown is substantially the same as that used to form a structure including a second sacrificial pattern 128a and a third sacrificial pattern 128b stacked on a first sacrificial layer 122 of a stepped portion of a first lower molded structure 130.

[0182] Reference ​ It can be executed and referenced. ​ and ​ The process shown is the same. In this case, the first insulating intermediate layer 134a may cover the substrate insulating layer 114 that runs through the wiring region C.

[0183] In addition, it can be executed and referenced. ​ The same process described is used to form the first upper molding structure 160, the fifth sacrificial pattern 158a, and the sixth sacrificial pattern 158b. However, in the process used to form the first upper molding structure 160, the second upper molding structure 162 may not be formed on the through wiring region C.

[0184] A second insulating intermediate layer 164a may be formed to cover the edge portion of the first upper molded structure 160 and the first insulating intermediate layer 134a. In an exemplary embodiment of the inventive concept, the upper surface of the first upper molded structure 160 and the upper surface of the second insulating intermediate layer 164a may be substantially coplanar with each other.

[0185] Then, it can be executed and referenced. ​ , ​ , ​ and ​ The process described is the same as the process used to manufacture... ​ The vertical memory device shown in the figure.

[0186] ​ This is a cross-sectional view illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0187] In addition to the channel structure and the shapes of the first and second contact plugs, the vertical memory device can be compared with a reference.​ 、 ​ 、 ​ 、 ​ 、 ​ 、 ​ and ​ The vertical memory device shown in FIG. 17 is substantially the same as the vertical memory device shown in FIG. 16. In other words, the channel structure, and each of the first and second contact plugs can include only one curved portion of the upper portion thereof.

[0188] Referring to ​ , the first insulating intermediate layer 136 can be formed to cover the second structure. In other words, the second insulating intermediate layer as shown in ​ may not be formed.

[0189] The channel structure 190 can include a curved portion b between the third insulating intermediate layer 172 and the first structure therebelow. The first contact plug 300a can include a curved portion b between the third insulating intermediate layer 172 and the first insulating intermediate layer 136 therebelow. The second contact plug 300b can include a curved portion b between the third insulating intermediate layer 172 and the third structure therebelow.

[0190] In exemplary embodiments of the inventive concept, the curved portion b of the channel structure 190, the curved portion b of the first contact plug 300a, and the curved portion b of the second contact plug 300b can be substantially coplanar with each other.

[0191] In exemplary embodiments of the inventive concept, the upper surface of the channel structure 190, the upper surface of the first contact plug 300a, and the upper surface of the second contact plug 300b can be substantially coplanar with each other.

[0192] ​ 、 ​ 、 ​ 、 ​ and ​ are cross-sectional views showing a method of manufacturing a vertical memory device according to exemplary embodiments of the inventive concept.

[0193] First, the same processes as those shown with reference to ​ may be performed.

[0194] Referring to ​The first insulating layer 120 and the first sacrificial layer 122 can be alternately and repeatedly formed on the base pattern 112 and the base insulating layer 114, and a stack including the first insulating layer 120 and the first sacrificial layer 122 can be patterned to form a first mold structure 130a. The first mold structure 130a can be formed on the cell region A and the through-cell wiring region B of the substrate, and the first mold structure can have a stepped shape (e.g., a stair shape) at the edge portion. In addition, a second mold structure 132a can be formed on the through-wiring region C.

[0195] Subsequently, a process substantially the same as the process described with reference to ​ and ​ may be performed to form a stack structure including a second sacrificial pattern 128a and a third sacrificial pattern 128b on the first sacrificial layer 122 at the stepped portion of the first mold structure 130a. In addition, an insulating layer can be formed to cover the edge portion of the first mold structure 130a, and an upper surface of the insulating layer can be planarized to form a first insulating intermediate layer 136.

[0196] With reference to ​ , the first insulating intermediate layer 136, the first mold structure 130a, the second sacrificial pattern 128a and the third sacrificial pattern 128b, the second mold structure 132a, and the base insulating layer 114 and the lower insulating intermediate layer can be partially etched to form a first trench hole 302a, a first via hole 302b, and a second via hole 302c, respectively. The etching process can include, for example, an anisotropic etching process.

[0197] The first trench hole 302a can be formed through the first mold structure 130a on the cell region A. An upper surface of the base pattern 112 can be exposed by a lower surface of the first trench hole 302a.

[0198] The first via hole 302b can pass through the first insulating intermediate layer 136, the first mold structure 130a, the second sacrificial pattern 128a and the third sacrificial pattern 128b, and the base insulating layer on the through-cell wiring region B. The second sacrificial pattern 128a and the third sacrificial pattern 128b can be exposed by side walls of the first via hole 302b, and an upper surface of the lower pad 108a can be exposed by a lower surface of the first via hole 302b.

[0199] The second via hole 302c can pass through the second mold structure 132a and the base insulating layer 114 on the through-wiring region C. An upper surface of the lower pad 108a can be exposed by a lower surface of the second via hole 302c.

[0200] With reference to ​A third insulating intermediate layer 172 can be formed to cover the first molding structure 130a, the second molding structure 132a, and the first insulating intermediate layer 136. The third insulating intermediate layer 172 can be formed not to fill the first trench hole 302a, the first via hole 302b, and the second via hole 302c.

[0201] Referring to ​ A portion of the third insulating intermediate layer 172 formed on the cell region A can be etched to form a first upper hole connected with the first trench hole 302a. Accordingly, the first upper hole and the first trench hole 302a can be connected with each other so that the first upper hole and the first trench hole 302a can function as a trench hole. In an exemplary embodiment of the inventive concept, a side wall between the first upper hole and the first trench hole 302a can have a curved shape in the trench hole. For example, the curved shape of the trench hole and the corresponding trench structure 190a can have a continuous curved shape characterized by a uniform slope.

[0202] A trench structure 190a can be formed in the trench hole. The trench structure 190a can be formed by the same process as the process shown in FIG. 6. ​ The trench structure 190a can have one curved portion b extending in a vertical direction at an upper portion thereof.

[0203] Referring to ​ A portion of the third insulating intermediate layer 172 formed on the through-cell wiring region B can be etched to form a second upper hole 194a connected with the first via hole 302b. In addition, a portion of the third insulating intermediate layer 172 formed on the through-wiring region C can be etched to form a third upper hole 194b connected with the second via hole 302c. The second upper hole 194a and the third upper hole 194b can be formed together by the same etching process.

[0204] The second upper hole 194a and the first via hole 302b can be connected with each other in a vertical direction to form a first contact hole 304a.

[0205] In addition, the third upper hole 194b and the second via hole 140c can be connected with each other in a vertical direction to form a second contact hole 304b. An upper surface of the lower pad 108a can be exposed by a lower surface of the second contact hole 304b. Each of the first contact hole 304a and the second contact hole 304b can include one curved portion b.

[0206] Thereafter, a conductive layer can be formed to fill in the first contact hole 304a and the second contact hole 304b, and the conductive layer can be planarized until an upper surface of the third insulating intermediate layer 172 can be exposed, to form the first contact plug 300a and the second contact plug 300b. Thus, the first contact plug 300a can be formed in the first contact hole 304a, and the second contact plug 300b can be formed in the second contact hole 304b. Thereafter, as shown with reference to ​ the first trench 210a and the second trench 210b can be formed.

[0207] Subsequently, the same processes as shown with reference to ​ , ​ , ​ , ​ , ​ and ​ may be performed, to thereby fabricate the vertical memory device shown in ​ .

[0208] ​ is a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the inventive concept.

[0209] The vertical memory device can be the same as the vertical memory device described with reference to ​ , except that the second molded structure 132a can not be formed on the through-wiring region C.

[0210] With reference to ​ , the first insulating intermediate layer 136a can be formed on the base insulating layer 114 of the through-wiring region C.

[0211] Thus, the second contact plug 300b can pass through the third insulating intermediate layer 172, the first insulating intermediate layer 136a, and the base insulating layer 114. An lower surface of the second contact plug 300b can contact an upper surface of the lower pad 108a.

[0212] ​ and ​ are a plan view and a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the inventive concept.

[0213] ​ is a cross-sectional view taken along line III-III' of ​ . The vertical memory device can be the same as the vertical memory device described with reference to ​ , ​ , ​ , ​ , ​ , ​ and ​The illustrated vertical memory devices are the same.

[0214] With regard to ​ and ​ The third contact plugs 202c can be further formed at only a portion of the insulating material in the second structure of the through-cell wiring region B. In other words, the plurality of third contact plugs 202c can extend from the third insulating intermediate layer 172 to the lower pad 108a in the vertical direction. Some of the third contact plugs 202c can pass through the first insulating layer 120, the second insulating layer 150, the first sacrificial layer 122, and the fourth sacrificial layer 152 in the second structure. Some of the third contact plugs 202c can pass through the second sacrificial pattern 128a and the third sacrificial pattern 128b in the second structure.

[0215] The upper surfaces of the third contact plugs 202c and the first contact plugs 202a and the upper surface of the second contact plugs 202b can be coplanar with each other. The lower surfaces of the third contact plugs 202c can contact the upper surface of the lower pad 108a.

[0216] The upper wiring 350 can be further formed on the third contact plugs 202c.

[0217] While exemplary embodiments have been described with reference to the figures, it will be understood by those having ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the application as defined by the following claims.

Claims

1. A vertical memory device, the vertical memory device comprising: a first structure on a substrate, the first structure including gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers; a second structure connected to the first structure, the second structure including pad patterns electrically connected to the gate patterns of respective layers of the plurality of layers; a channel structure passing through the gate patterns; and a first contact plug passing through the second structure and electrically connected to the pad pattern electrically connected to the gate pattern of one of the plurality of layers, wherein the first contact plug is electrically insulated from the gate patterns of other layers, wherein each of a sidewall of the channel structure and a sidewall of the first contact plug includes at least one curved portion. The curved portion of the channel structure and the curved portion of the first contact plug are coplanar with each other.

2. The vertical memory device of claim 1, wherein, An upper surface of the channel structure and an upper surface of the first contact plug are coplanar with each other.

3. The vertical memory device of claim 1, wherein, A lower surface of the channel structure is higher than a lower surface of the first contact plug.

4. The vertical memory device of claim 1, wherein, 5. The vertical memory device of claim 1, further comprising: a circuit pattern formed on the substrate; a lower pad electrically connected to the circuit pattern; and a base pattern and a base insulating layer on the lower pad, wherein the first structure and the second structure are formed on the base pattern or the base insulating layer. The lower surface of the channel structure contacts the base pattern, and the lower surface of the first contact plug contacts the lower pad.

7. The vertical memory device of claim 1, further comprising:

6. The vertical memory device of claim 5, wherein, a third structure spaced apart from the second structure, and the third structure including an insulating material; and a second contact plug passing through the third structure, and the second contact plug including a curved portion at a sidewall thereof.

8. The vertical memory device of claim 7, further comprising: a first upper wiring on the channel structure, the first upper wiring electrically connected to the channel structure; and a second upper wiring on the second contact plug, the second upper wiring electrically connected to the second contact plug.

9. The vertical memory device of claim 1, further comprising an insulating interlayer covering the first structure and the second structure, and an upper surface of the insulating interlayer is coplanar with an upper surface of each of the channel structure and the first contact plug. The curved portion of the channel structure is positioned between the first structure and the insulating interlayer, and the curved portion of the first contact plug is positioned between the second structure and the insulating interlayer.

11. A vertical memory device, the vertical memory device comprising: a circuit pattern on a substrate; wherein a base pattern and a base insulating layer on the circuit pattern; 10. The vertical memory device of claim 9, wherein, a first structure on the base pattern, the first structure including gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and the gate patterns extending in a first direction parallel to the upper surface of the substrate; a second structure connected to the first structure, the second structure including pad patterns in separate plurality of layers, wherein the pad patterns are electrically connected to the gate patterns of the same layer; a channel structure passing through the gate patterns, and the channel structure extending in the vertical direction; and a first contact plug passing through the second structure and electrically connected to the pad pattern electrically connected to the gate pattern of one of the plurality of layers, wherein the first contact plug is electrically insulated from the gate patterns of other layers, wherein each of a sidewall of the channel structure and a sidewall of the first contact plug includes at least one curved portion. ​ ​ a first contact plug passing through the second structure and electrically connected to the pad pattern electrically connected to the gate pattern of one of the plurality of layers, and the first contact plug extending in the vertical direction, wherein the first contact plug is electrically insulated from the gate patterns of the other layers, wherein the upper surface of the channel structure and the upper surface of the first contact plug are coplanar with each other.

12. The vertical memory device of claim 11, further comprising at least one curved portion at at least one of a sidewall of the channel structure and a sidewall of the first contact plug.

13. The vertical memory device of claim 12, wherein, the curved portion of the channel structure and the curved portion of the first contact plug are coplanar with each other.

14. The vertical memory device of claim 11, further comprising an insulating intermediate layer covering the first structure and the second structure, and wherein an upper surface of the insulating intermediate layer is coplanar with an upper surface of at least one of the channel structure and the first contact plug.

15. The vertical memory device of claim 11, wherein, a lower surface of the channel structure contacts an upper surface of the base pattern, and the first contact plug passes through the base insulating layer, wherein a lower surface of the first contact plug is disposed lower than the lower surface of the channel structure.

16. The vertical memory device of claim 11, further comprising a lower pad electrically connected to the circuit pattern, and wherein a sidewall of the first contact plug contacts a portion of the pad pattern, and a lower surface of the first contact plug contacts the lower pad.

17. A vertical memory device, comprising: a first structure on a base, the first structure including gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the base, and the gate patterns extending in a first direction parallel to the upper surface of the base; a second structure connected to the first structure, the second structure including pad patterns spaced apart among a plurality of layers individually and electrically connected to the gate patterns of the same layer; a channel structure passing through the gate patterns, and the channel structure extending in the vertical direction; a first contact plug passing through the second structure and electrically connected to the pad pattern electrically connected to the gate pattern of one of the plurality of layers, and the first contact plug extending in the vertical direction, wherein the first contact plug is electrically insulated from the gate patterns of the other layers; a third structure spaced apart from the second structure; and a second contact plug passing through the third structure, and the second contact plug extending in the vertical direction, wherein an upper surface of the channel structure is coplanar with an upper surface of the first contact plug and an upper surface of the second contact plug with each other.

18. The vertical memory device of claim 17, wherein, at least one of a sidewall of the channel structure, a sidewall of the first contact plug, and a sidewall of the second contact plug includes at least one curved portion.

19. The vertical memory device of claim 18, wherein, the curved portion of the channel structure is coplanar with the curved portion of the first contact plug and the curved portion of the second contact plug with each other.

20. The vertical memory device of claim 17, further comprising a circuit pattern formed on the base, the circuit pattern disposed below the first structure and the second structure; wherein, each of the first contact plug and the second contact plug is electrically connected to the circuit pattern.

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