Electronic panel and electronic device having an electronic panel

Abstract

An electronic panel and an electronic device having the same are provided. The electronic panel includes a base substrate, a display unit, a sensing unit, a planarization portion, and a crack sensing portion, wherein the display unit includes a pixel and an encapsulation layer; the sensing unit includes first and second conductive patterns disposed on different layers and senses that an insulating layer is interposed between the first and second conductive patterns; the planarization portion is disposed between the display unit and the sensing unit and includes a flat surface, an inclined surface, and a recessed portion; the crack sensing portion is spaced apart from the first and second conductive patterns and includes a crack sensing pattern, a first connection line, and a second connection line, the crack sensing pattern overlaps the planarization portion, the first connection line is connected to one end of the crack sensing pattern and extends in a first direction, the second connection line is connected to the other end of the crack sensing pattern, is spaced apart from the first connection line, and extends in the first direction, wherein at least one of the first connection line and the second connection line overlaps the recessed portion.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0074367, filed on June 21, 2019, which is incorporated by reference herein for all purposes as if fully set forth herein. TECHNICAL FIELD

[0003] Exemplary embodiments of the present application relate generally to an electronic panel and an electronic device having the same, and more particularly, to an electronic panel having a planarization portion including a recessed portion and sensing an external input, and an electronic device having the same. BACKGROUND

[0004] An electronic device is activated in response to an electrical signal applied thereto. The electronic device includes a device formed of various electronic components such as an electronic panel and an electronic module. The electronic panel includes a display unit displaying an image or a sensing unit sensing an external input. The electronic components are electrically connected to each other through signal lines arranged in various ways.

[0005] The display unit includes a light emitting device generating an image. The sensing unit includes a sensing electrode to sense an external input. The sensing electrode is arranged within an active area. The sensing unit is generally designed to have a uniform sensitivity across the active area.

[0006] The above information disclosed in this Background section is only for the understanding of the background of the present application, and therefore it can contain information that does not constitute prior art. SUMMARY

[0007] An electronic device constructed according to exemplary embodiments of the present application has improved reliability.

[0008] Additional features of the inventive concept will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the inventive concept.

[0009] An electronic panel according to an exemplary embodiment includes a base substrate, a display unit, a sensing unit, a planarization portion, and a crack sensing portion, wherein the display unit is disposed on the base substrate and includes a plurality of pixels and an encapsulation layer covering the pixels; the sensing unit is disposed on the display unit and includes a sensing insulating layer, a first conductive pattern, and a second conductive pattern, the first conductive pattern and the second conductive pattern are disposed on different layers from each other and the sensing insulating layer is interposed between the first conductive pattern and the second conductive pattern; the planarization portion is disposed between the display unit and the sensing unit and includes a flat surface, an inclined surface inclined from the flat surface at a predetermined inclination angle, and a recessed portion recessed from the flat surface and the inclined surface; and the crack sensing portion is disposed on the sensing insulating layer, spaced apart from the first conductive pattern and the second conductive pattern, and includes a crack sensing pattern, a first connection line, and a second connection line, wherein the crack sensing pattern overlaps the planarization portion, the first connection line is connected to one end of the crack sensing pattern and extends in a first direction, and the second connection line is connected to the other end of the crack sensing pattern, spaced apart from the first connection line and extending in the first direction, wherein at least one of the first connection line and the second connection line overlaps the recessed portion.

[0010] A thickness of the recessed portion measured from an imaginary plane extending from the flat surface can increase in the first direction.

[0011] A width of the recessed portion in a direction perpendicular to the first direction can increase in a direction toward an upper end of the planarization portion at which the flat surface contacts the inclined surface.

[0012] The recessed portion can have a polygonal shape when viewed in a plan view.

[0013] The recessed portion can have a semicircular shape in an area overlapping the inclined surface when viewed in a plan view.

[0014] The inclination angle can be equal to or less than about 90 degrees.

[0015] At least a portion of the planarization portion can contact the encapsulation layer.

[0016] The electronic panel can further include a module hole defined through the display unit, the sensing unit, and the planarization portion, wherein the planarization portion can surround an edge of the module hole.

[0017] The crack sensing pattern can have an open curve shape surrounding at least a portion of the module hole.

[0018] The base substrate can further include a groove recessed from a portion of an upper surface of the base substrate and having a closed line shape.

[0019] At least one of the first connection line and the second connection line can be covered by the sensing insulating layer.

[0020] The at least one of the first connection line and the second connection line covered by the sensing insulating layer can be connected to the crack sensing pattern via a contact hole defined through the sensing insulating layer.

[0021] The sensing unit can include a first sensing electrode, a second sensing electrode, and a dummy pattern portion, wherein the first sensing electrode includes a first sensing pattern and a first connection pattern disposed on a different layer from the first sensing pattern and connected to the first sensing pattern after penetrating the sensing insulating layer, the second sensing electrode includes a second sensing pattern disposed on the same layer as the first sensing pattern while being spaced apart therefrom and a second connection pattern connected to the second sensing pattern, and the dummy pattern portion includes a floating pattern disposed on the same layer as the first sensing pattern, spaced apart from the first sensing pattern and the second sensing pattern, and connected to each of the first connection line and the second connection line, wherein the second conductive pattern can include the first connection pattern, and the first conductive pattern can include the first sensing pattern, the second sensing pattern, the second connection pattern, and the dummy pattern portion.

[0022] The crack sensing portion can include crack sensing lines disposed on the sensing insulating layer and spaced apart from the first sensing electrode and the second sensing electrode, and each of the floating patterns can be connected to a corresponding one of the crack sensing lines.

[0023] An electronic device according to another exemplary embodiment includes an electronic panel and an electronic module, wherein the electronic panel has a front surface and a rear surface opposite the front surface and includes a module hole defined through the front surface and the rear surface, the electronic module overlaps the module hole, the electronic panel includes a base substrate, a display unit, a sensing unit, a planarization portion, a crack sensing portion, wherein the base substrate has an active area and a peripheral area adjacent to the active area, the active area includes a hole area overlapping the module hole; the display unit is disposed on the base substrate and includes a plurality of pixels arranged in the active area and an encapsulation layer covering the pixels; the sensing unit is disposed on the display unit and includes a sensing insulating layer, a first conductive pattern, and a second conductive pattern, the first conductive pattern and the second conductive pattern are disposed on different layers from each other and the sensing insulating layer is interposed between the first conductive pattern and the second conductive pattern; the planarization portion is disposed in the hole area between the display unit and the sensing unit and includes a planar surface, an inclined surface inclined from the planar surface at a predetermined inclined angle, and a recessed portion recessed from the planar surface and the inclined surface; the crack sensing portion includes a crack sensing pattern, a first connection line, and a second connection line, the crack sensing pattern is disposed in the hole area to surround at least a portion of the module hole and overlaps the planarization portion, the first connection line is connected to one end of the crack sensing pattern and overlaps a portion of the active area and the hole area, the second connection line is connected to the other end of the crack sensing pattern, is spaced apart from the first connection line, and overlaps a portion of the active area and the hole area, wherein at least one of the first connection line and the second connection line overlaps the recessed portion.

[0024] A thickness of the recessed portion measured from an imaginary plane extending from the planar surface can increase along a first direction in which the first connection line extends.

[0025] A width of the recessed portion in a second direction perpendicular to the first direction can increase along the first direction.

[0026] The recessed portion can have a polygonal shape when viewed in a plan view.

[0027] A portion of the recessed portion overlapping the inclined surface can have a V-shape or a U-shape when viewed in a plan view.

[0028] The crack sensing pattern can have an open curve shape, and the module hole can be defined inside the open curve shape of the crack sensing pattern to penetrate each of the display unit, the sensing unit, and the planarization portion.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the inventive concepts.

[0031] Figure 1A is a perspective view of an electronic device according to an exemplary embodiment.

[0032] Figure 1B is Figure 1A an exploded perspective view of the electronic device of

[0033] Figure 2 is Figure 1A a block diagram of the electronic device of

[0034] Figure 3A is a plan view of a display unit according to an exemplary embodiment.

[0035] Figure 3B is Figure 3A an enlarged view of a portion of the display unit of

[0036] Figure 4A is a plan view of a sensing unit according to an exemplary embodiment.

[0037] Figure 4B is a plan view of a portion of an electronic panel according to an exemplary embodiment.

[0038] Figure 4C is a cross-sectional view taken along line I-I' of Figure 4B

[0039] is a cross-sectional view taken along line II-II' of Figure 5A

[0040] is a cross-sectional view taken along line III-III' of Figure 5B

[0041] is a cross-sectional view taken along line IV-IV' of Figure 6A Figure 5B is a cross-sectional view taken along line V-V' of

[0042] Figure 6B Figure 5B is a cross-sectional view taken along line VI-VI' of

[0043] Figure 6C is a cross-sectional view taken along line VII-VII' of Figure 5B

[0044] is a cross-sectional view taken along line VIII-VIII' of Figure 6D Figure 5B is a cross-sectional view taken along line IX-IX' of​​​

[0045] Figure 7A is a cross-sectional view of a portion of an electronic panel according to an exemplary embodiment.

[0046] Figure 7B is a plan view of a portion of an electronic panel according to an exemplary embodiment.

[0047] Figure 8A is a cross-sectional view of a portion of an electronic panel according to an exemplary embodiment.

[0048] Figure 8B and Figure 8C is a plan view of a portion of an electronic panel according to an exemplary embodiment.

[0049] Figure 9A is an enlarged plan view of a portion of an electronic panel according to an exemplary embodiment.

[0050] Figure 9B is an enlarged perspective view of a portion of an electronic panel according to an exemplary embodiment.

[0051] Figure 10A and Figure 10B is a plan view showing a portion of an electronic device according to an exemplary embodiment.

[0052] Figure 11A is Figure 10A an enlarged plan view of the portion shown in

[0053] Figure 11B is Figure 4A an enlarged plan view of the portion shown in

[0054] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 12H and Figure 12I are views showing a method of manufacturing an electronic panel according to an exemplary embodiment. DETAILED DESCRIPTION

[0055] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more exemplary embodiments or examples of the present application. As used herein, "exemplary embodiment" and "embodiment" are used non-limitingly to mean an example of a device or method applying one or more of the inventive concepts disclosed herein. As will be obvious, however, the exemplary embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the exemplary embodiments. In addition, each of the exemplary embodiments can be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of a particular exemplary embodiment can be used in another exemplary embodiment without departing from the inventive concepts.

[0056] Unless otherwise indicated, the exemplary embodiments shown are understood to provide exemplary features of different details of some ways in which the inventive concepts can be practiced. Thus, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and / or aspects of each embodiment (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged, and / or rearranged without departing from the inventive concepts.

[0057] The use of cross-hatching and / or shading in the drawings is generally used to illustrate the boundaries, or edges, of adjacent structures. As such, unless otherwise indicated, the presence or absence of cross-hatching and / or shading is not intended to convey or imply any preference or requirement for particular materials, material properties, dimensions, proportions, commonality of elements between illustrations, and / or any other characteristic, attribute, property, or the like of the elements being illustrated. In addition, in the drawings, the size and relative sizes of elements and regions can be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be carried out in different ways, the particular sequence of processes described can be varied without departing from the essence of the exemplary embodiments. For example, two or more processes described sequentially can be performed at the same time or in an order opposite to that described. Additionally, identical reference numerals can denote identical elements.

[0058] When an element or layer is referred to as being on another element or layer, being connected to or being coupled to another element or layer, it may be directly on the another element or layer, being connected to or being coupled to the another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being directly on another element or layer, being directly connected to or being directly coupled to another element or layer, there may not be an intervening element or layer. For this reason, the term "connection" may represent a physical connection, electrical connection and / or fluid connection with or without an intermediate element. In addition, the D1 axis, D2 axis and D3 axis are not limited to the three axes of a rectangular coordinate system, such as an x-axis, a y-axis and a z-axis, but can be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0060] Spatially relative terms, such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes and, thus, may be used to describe the relationship of one element to another element as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms "comprises", "comprising", "includes", "including" and the like are specifically intended to be open-ended. Such terms are, therefore, permitted to mean "including but not limited to" throughout the specification. Additionally, it is to be understood that the description of the example embodiments is intended to be illustrative, and not restrictive, of the present teachings. Many embodiments of the present teachings are specifically made to the skilled artisan in this art which, given the benefit of this disclosure, can then modify the generic principles described herein to specific situations.

[0062] The various example embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of idealized embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the example embodiments disclosed herein are not to be construed as being limited to the particular shapes of regions as illustrated and described herein but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures can not have a shape that is completely consistent with that of the illustrations, but are rather schematic representations reflecting the functions of the regions. As used herein, such terms are intended to be approximating terms and are not intended to be degree terms, and as such, inherent deviations in measurements and / or provided values by those of ordinary skill in the art are to be expected.

[0063] As is customary in the art, some of the example embodiments are described and illustrated in the attached drawings in terms of functional blocks, units and / or modules. It is understood by those skilled in the art that these blocks, units and / or modules are implemented in physical form by electronic (or optical) circuitry, e.g., logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, etc., which are formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In cases where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions, and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Furthermore, each block, unit and / or module of some of the example embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the inventive concept. Moreover, blocks, units and / or modules of some of the example embodiments can be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0065] Figure 1A is an assembled perspective view of an electronic device EA according to an example embodiment. Figure 1B is Figure 1A is an exploded perspective view of the electronic device EA shown. Figure 2 is Figure 1A is a block diagram of the electronic device EA shown.

[0066] The electronic device EA can be a device that is enabled in response to an electrical signal applied thereto. The electronic device EA can be used in various technical fields. For example, the electronic device EA can be a tablet computer, a notebook computer, a desktop computer, or a smart television. In the example embodiments shown, the electronic device EA will be described with reference to a smart phone.

[0067] Referring to Figure 1A and Figure 1BThe electronic device EA can display an image IM on a front surface FS thereof. The front surface FS can be substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. The front surface FS includes a transmissive area TA and a bezel area BZA adjacent to the transmissive area TA.

[0068] The electronic device EA displays an image IM through the transmissive area TA. The image IM includes at least one of a still image and a moving image. Figure 1A A clock widget and an application icon are exemplarily illustrated as the image IM.

[0069] The transmissive area TA can have a quadrangular shape substantially parallel to each of the first direction DR1 and the second direction DR2. However, the inventive concept is not limited thereto, and in other exemplary embodiments, the transmissive area TA can have various shapes.

[0070] The bezel area BZA is formed adjacent to the transmissive area TA. The bezel area BZA can surround the transmissive area TA. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the bezel area BZA can be formed adjacent to only one side of the transmissive area TA, or can be omitted.

[0071] A normal direction of the front surface FS can correspond to a thickness direction DR3 (hereinafter, referred to as a "third direction") of the electronic device EA. As used herein, a front (or upper) surface and a rear (or lower) surface of each member are defined with respect to a direction in which the image IM is displayed. The front surface and the rear surface are opposite in the third direction DR3.

[0072] The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are defined with respect to each other, and the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be changed to other directions. Hereinafter, a first direction axis, a second direction axis, and a third direction axis are indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and are assigned with the same reference numerals.

[0073] The electronic device EA can sense a user input TC applied thereto. The user input TC can include various types of external inputs (thus, the user input TC can also be referred to as an external input TC), such as a part of a user's body, light, heat, or pressure. In addition, the electronic device EA can sense a proximity input as well as a touch input with respect to the electronic device EA.

[0074] In Figure 1AIn the present embodiment, the user input TC is exemplarily shown as a user's hand applied to the front surface FS. However, as described above, the user input TC can be provided in various forms, and thus, in some exemplary embodiments, the electronic device EA can sense the user input TC applied to a side surface or a rear surface of the electronic device EA according to the structure of the electronic device EA.

[0075] The electronic device EA includes a window 100, an electronic panel 200, a circuit board 300, an electronic module 400, and a housing 500. The window 100 and the housing 500 are coupled to each other to define the appearance of the electronic device EA.

[0076] The window 100 is disposed on the electronic panel 200 to cover the front surface FS of the electronic panel 200. The window 100 includes an optically transparent insulating material. For example, the window 100 includes glass or plastic. The window 100 has a single layer structure or a multi-layer structure. For example, the window 100 has a stacked structure of a plurality of plastic films attached to each other by an adhesive, or a stacked structure of a glass substrate and a plastic film attached to each other by an adhesive.

[0077] The window 100 includes the front surface FS exposed to the outside. The front surface FS of the electronic device EA can be defined by the front surface FS of the window 100.

[0078] In detail, the transmission area TA can be an optically transparent area. The transmission area TA can have a shape corresponding to the active area AA. For example, the transmission area TA can overlap at least a portion or an entire surface of the active area AA. An image IM displayed through the active area AA of the electronic panel 200 can be viewed from the outside through the transmission area TA.

[0079] The bezel area BZA can be an area having a transmittance relatively lower than that of the transmission area TA. The bezel area BZA can define the shape of the transmission area TA. The bezel area BZA can be disposed adjacent to the transmission area TA and can surround the transmission area TA.

[0080] The bezel area BZA can have a predetermined color. When the window 100 includes a glass or plastic substrate, the bezel area BZA can be a colored layer printed or deposited on one surface of the glass or plastic substrate. As another example, the bezel area BZA can be formed by coloring a corresponding area of the glass or plastic substrate.

[0081] The bezel area BZA can cover the peripheral area NAA of the electronic panel 200 to prevent the peripheral area NAA from being perceived from the outside. However, the present inventive concept is not limited thereto, and in some exemplary embodiments, the bezel area BZA can be omitted from the window 100.

[0082] The electronic panel 200 can display the image IM and can sense the external input TC. The electronic panel 200 can include a front surface IS defining an active area AA and a non-active area NAA. The active area AA can be an area enabled in response to an electrical signal.

[0083] In the illustrated exemplary embodiment, the active area AA can be an area in which the image IM is displayed and the external input TC is sensed. The transmissive area TA can overlap the active area AA of the window 100. For example, the transmissive area TA can overlap at least a portion of or an entire surface of the active area AA. Accordingly, a user can perceive the image IM through the transmissive area TA, or can apply the external input TC through the transmissive area TA. However, the inventive concept is not limited thereto. In some exemplary embodiments, an area in which the image IM is displayed in the active area AA can be separated from an area in which the external input TC is sensed in the active area AA.

[0084] The bezel area BZA of the window 100 can cover the non-active area NAA. The non-active area NAA can be disposed adjacent to the active area AA. The non-active area NAA can surround the active area AA. A driving circuit or a driving line can be disposed in the non-active area NAA to drive the active area AA.

[0085] Various signal lines, pads PD, or electronic devices can be arranged in the non-active area NAA to apply an electrical signal to the active area AA. The non-active area NAA can be covered by the bezel area BZA, and thus, the non-active area NAA can not be visible from the outside.

[0086] In the illustrated exemplary embodiment, the electronic panel 200 is assembled in a flat state such that the active area AA and the non-active area NAA face the window 100. However, the inventive concept is not limited thereto, and in some exemplary embodiments, a portion of the non-active area NAA of the electronic panel 200 can be bent. In this case, the portion of the non-active area NAA can be bent toward the rear surface of the electronic device EA, and the bezel area BZA in the front surface FS of the electronic device EA can be reduced. As another example, the electronic panel 200 can be assembled in a state in which a portion of the active area AA is bent. As another example, the non-active area NAA can be omitted from the electronic panel 200.

[0087] Reference Figure 2 The electronic panel 200 can include a display unit 210 and a sensing unit 220. The display unit 210 can have a configuration to substantially generate the image IM. The image IM generated by the display unit 210 can be viewed by a user from the outside through the transmissive area TA.

[0088] The sensing unit 220 can sense an external input TC applied thereto from the outside. As described above, the sensing unit 220 can sense an external input TC applied thereto through the window 100.

[0089] A predetermined hole region HA can be defined in the electronic panel 200. In the illustrated exemplary embodiment, the hole region HA can be included in the active region AA. Accordingly, the hole region HA can be disposed in the active region AA and can be surrounded by the active region AA. When viewed in a plan view, the hole region HA can overlap the electronic module 400 which will be described later. In the illustrated exemplary embodiment, the hole region HA is spaced apart from the peripheral region NAA.

[0090] The electronic panel 200 can include a module hole MH defined in the hole region HA and penetrating the electronic panel 200. The module hole MH can penetrate at least one of the display unit 210 and the sensing unit 220. An edge of the hole region HA can be spaced apart from an edge of the module hole MH and can surround the edge of the module hole MH. The edge of the hole region HA can have a shape corresponding to the module hole MH.

[0091] The circuit board 300 can be connected to the electronic panel 200. The circuit board 300 can include a flexible board CF and a main board MB. The flexible board CF can include an insulating film and a conductive wire mounted on the insulating film. The conductive wire can be connected to the pad PD to electrically connect the circuit board 300 to the electronic panel 200.

[0092] In the illustrated exemplary embodiment, the flexible board CF can be assembled in a bent state. Accordingly, the main board MB can be disposed on the rear surface of the electronic panel 200 and can be stably accommodated in a space defined by the housing 500. In some exemplary embodiments, the flexible board CF can be omitted, and in this case, the main board MB can be directly connected to the electronic panel 200.

[0093] The main board MB can include a signal line and an electronic device connected to the signal line to be electrically connected to the electronic panel 200. The electronic device can generate various electrical signals such as a signal for generating the image IM or a signal for sensing the external input TC, or can process the sensed signal. In some exemplary embodiments, a plurality of main boards MB can be provided to respectively correspond to electrical signals to be generated or processed, but are not limited thereto.

[0094] According to an exemplary embodiment, a driving circuit to which an electrical signal is applied to the active region AA can be directly mounted on the electronic panel 200. In this case, the driving circuit can be mounted in the form of a chip or can be formed together with the pixel PX (see Figure 3A ). In this way, the circuit board 300 can be omitted, or the area of the circuit board 300 can be reduced.

[0095] The electronic module 400 is disposed below the window 100. When viewed in a plan view, the electronic module 400 can overlap the module hole MH, and can overlap the hole area HA. The electronic module 400 can receive an external input TC transmitted thereto via the hole area HA, or can provide an output via the hole area HA.

[0096] When viewed in a plan view, in the electronic module 400, a receiving portion that receives the external input TC or an output portion that provides an output can overlap the hole area HA. A portion or the entire electronic module 400 can be accommodated in the hole area HA or the module hole MH. According to an exemplary embodiment, the electronic module 400 is disposed to overlap the active area AA, and thus, an increase in the size of the bezel area BZA can not be required.

[0097] Referring to Figure 2 , the electronic device EA can include the electronic panel 200, the power module PM, the first electronic module EM1, and the second electronic module EM2. The electronic panel 200, the power module PM, the first electronic module EM1, and the second electronic module EM2 are electrically connected to each other. Figure 2 The display unit 210 and the sensing unit 220 among the components of the electronic panel 200 are exemplarily illustrated.

[0098] The first electronic module EM1 and the second electronic module EM2 can include various functional modules to operate the electronic device EA. The first electronic module EM1 can be directly mounted on a mother board electrically connected to the electronic panel 200, or can be electrically connected to the mother board through a connector after being mounted on a separate board.

[0099] The first electronic module EM1 can include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some modules can be electrically connected to the mother board through a flexible printed circuit board, instead of being mounted on the mother board.

[0100] The control module CM can control the overall operation of the electronic device EA. According to an exemplary embodiment, the control module CM can be a microprocessor, without being limited thereto. For example, the control module CM can enable or disable the electronic panel 200. The control module CM can control other modules, such as the image input module IIM or the audio input module AIM, based on a touch signal provided from the electronic panel 200.

[0101] The wireless communication module TM can transmit / receive a wireless signal to / from another terminal by using a Bluetooth or Wi-Fi line. The wireless communication module TM can transmit / receive a voice signal by using a conventional communication line. The wireless communication module TM can include a transmitter TM1 that modulates a signal to be transmitted and transmits the modulated signal, and a receiver TM2 that demodulates a signal applied thereto.

[0102] The image input module IIM can process an image signal and convert the image signal into image data that can be displayed through the electronic panel 200. The audio input module AIM can receive an external audio signal through a microphone in a recording mode and a voice recognition mode, and convert the audio signal into electronic voice data.

[0103] The external interface IF can serve as an interface between the control module CM and external devices, such as an external charger, a wired / wireless data port, and a card socket (e.g., a memory card and a SIM / UIM card).

[0104] The second electronic module EM2 can include an audio output module AOM, a light emitting module LM, a light receiving module LRM, and a camera module CMM. The components of the second electronic module EM2 can be directly mounted on the mother board, or electrically connected to the electronic panel 200 through a connector after being mounted on a separate board, or electrically connected to the first electronic module EM1.

[0105] The audio output module AOM can convert and output audio data provided from the wireless communication module TM or audio data stored in the memory MM to the outside.

[0106] The light emitting module LM can generate and emit light. For example, the light emitting module LM can emit infrared light. The light emitting module LM can include a light emitting diode (LED) device. The light receiving module LRM can sense infrared light. The light receiving module LRM can be enabled when infrared light equal to or greater than a predetermined level is sensed. The light receiving module LRM can include a complementary metal-oxide-semiconductor (CMOS) sensor. Infrared light generated by the light emitting module LM, after being output from the light emitting module LM and reflected by an external object such as a user's finger or face, can be incident into the light receiving module LRM. The camera module CMM can take an external image.

[0107] The electronic module 400 according to the exemplary embodiments can include at least one of the components of the first electronic module EM1 and the second electronic module EM2. For example, the electronic module 400 can include at least one of a camera, a speaker, a light sensing sensor, and a heat sensing sensor. The electronic module 400 can sense an external object through the hole area HA, or can provide a sound signal such as a voice to the outside through the hole area HA. In addition, the electronic module 400 can include a plurality of components, without being limited to the illustrated exemplary embodiments.

[0108] The electronic module 400 disposed to overlap the hole area HA can easily recognize an external object via the hole area HA, or an output signal generated by the electronic module 400 can be easily transmitted to the outside. In some exemplary embodiments, the electronic device EA can further include a transparent member disposed between the electronic module 400 and the electronic panel 200. The transparent member can be an optically transparent film so that an external input TC transmitted through the module hole MH is transmitted to the electronic module 400 after passing through the transparent member. The transparent member can be attached to the rear surface of the electronic panel 200, or can be disposed between the electronic panel 200 and the electronic module 400 without a separate adhesive.

[0109] According to the exemplary embodiments, the electronic module 400 can be assembled to overlap the transmission area TA when viewed in a plan view. Accordingly, it can not be necessary to increase the size of the bezel area BZA to accommodate the electronic module 400, and thus, the aesthetic design of the electronic device EA can be improved.

[0110] Figure 3A is a plan view of the display unit 210 according to exemplary embodiments. Figure 3B is Figure 3A is an enlarged view of a portion of the display unit 210 illustrated.

[0111] Referring to Figure 3A , the display unit 210 can include a base substrate BS, a plurality of pixels PX, a plurality of signal lines GL, DL, and PL, and a plurality of display pads DPD. An active area AA and a non-active area NAA can be defined by an area in which light emitted from the pixels PX is provided or not provided.

[0112] The base substrate BS can include an insulating substrate. For example, the base substrate BS can include a glass substrate, a plastic substrate, or a combination thereof.

[0113] The signal lines GL, DL, and PL can be connected to the pixels PX and can transmit an electrical signal to the pixels PX. In Figure 3AThe scan line GL, the data line DL, and the power line PL among the signal lines included in the display unit 210 are exemplarily illustrated. However, the inventive concept is not limited thereto. In some exemplary embodiments, the signal lines included in the display unit 210 can further include at least one of a power line, an initialization voltage line, and a light emission control line.

[0114] The pixel PX can be arranged in the active area AA. In Figure 3A In the signal circuit diagram of one of the plurality of pixels PX, the first thin film transistor TR1, the capacitor CP, the second thin film transistor TR2, and the light emitting element EE are exemplarily illustrated. The pixel PX can include the first thin film transistor TR1, the capacitor CP, the second thin film transistor TR2, and the light emitting element EE. The first thin film transistor TR1 can be a switching device that controls the turn-on and turn-off of the pixel PX. The first thin film transistor TR1 can transmit or block a data signal applied thereto through the data line DL in response to a scan signal applied thereto through the scan line GL.

[0115] The capacitor CP can be connected to the first thin film transistor TR1 and the power line PL. The capacitor CP is charged with an amount of charge corresponding to a difference between the data signal supplied from the first thin film transistor TR1 and a first power signal applied to the power line PL.

[0116] The second thin film transistor TR2 is connected to the first thin film transistor TR1, the capacitor CP, and the light emitting element EE. The second thin film transistor TR2 controls a driving current flowing through the light emitting element EE in response to the amount of charge charged in the capacitor CP. The turn-on time of the second thin film transistor TR2 is determined according to the amount of charge charged in the capacitor CP. During the turn-on time, the second thin film transistor TR2 applies the first power signal applied thereto via the power line PL to the light emitting element EE.

[0117] The light emitting element EE can emit light or can control the amount of light in response to an electrical signal. For example, the light emitting element EE can include an organic light emitting element, a quantum dot light emitting element, an electrophoretic element, or an electrowetting element.

[0118] The light emitting element EE can be connected to a power terminal VSS to receive a power signal (hereinafter referred to as a "second power signal") different from the first power signal supplied through the power line PL. In the light emitting element EE, a driving current corresponding to a difference between an electrical signal supplied from the second thin film transistor TR2 and the second power signal can be applied, and the light emitting element EE can generate light corresponding to the driving current. However, the inventive concept is not limited thereto, and in some exemplary embodiments, each pixel PX can include electronic devices having various configurations and arrangements.

[0119] The pixel PX can be arranged around the module hole MH and can surround the module hole MH. In Figure 3BIn the middle, the hole region HA is shown by a dotted line. The region XX' includes a region in which the module hole MH is defined. Hereinafter, the portion of the display unit 210 in which the module hole MH is defined will be described with reference to Figure 3B The portion of the display unit 210 in which the module hole MH is defined will be described in more detail.

[0120] As described above, the module hole MH can be defined in the active area AA. In this way, at least a portion of the plurality of pixels PX can be disposed adjacent to the module hole MH. Some of the pixels PX can surround the module hole MH.

[0121] A predetermined groove GV can be defined in the hole region HA. When viewed in a plan view, the groove GV is disposed along an edge of the module hole MH. The groove GV according to the illustrated exemplary embodiment has a closed linear shape to surround the module hole MH. However, the inventive concept is not limited thereto. In some exemplary embodiments, the groove GV can have a shape different from the module hole MH, and can have a closed linear shape including a polygon, an ellipse, or at least a portion of a curve, or can have a plurality of patterns partially broken.

[0122] The groove GV can be formed by recessing from the upper surface of the base substrate BS. The groove GV blocks a path for moisture or oxygen introduced from the outside through the module hole MH to permeate into the display unit 210 (to be described in greater detail later).

[0123] A plurality of signal lines SL1 and SL2 connected to the pixels PX can be disposed in the hole region HA. The signal lines SL1 and SL2 are connected to the pixels PX via the hole region HA. Figure 3B A first signal line SL1 and a second signal line SL2 among the signal lines connected to the pixels PX are exemplarily shown.

[0124] The first signal line SL1 extends along a first direction DR1. The first signal line SL1 is connected to pixels among the pixels PX that are arranged in the same row along the first direction DR1. The first signal line SL1 will be described as corresponding to a scan line GL.

[0125] Some of the pixels connected to the first signal line SL1 are disposed at a left side with respect to the module hole MH, and other pixels connected to the first signal line SL1 are disposed at a right side with respect to the module hole MH. Accordingly, even if some of the pixels are omitted around the module hole MH, the pixels connected to the first signal line SL1 and arranged in the same row can be turned on / off in response to substantially the same gate signal.

[0126] The second signal line SL2 extends along a second direction DR2. The second signal line SL2 is connected to pixels among the pixels PX that are arranged in the same column along the second direction DR2. The second signal line SL2 will be described as corresponding to a data line DL.

[0127] Some of the pixels connected to the second signal line SL2 are disposed at the upper side with respect to the module hole MH, and the other of the pixels connected to the second signal line SL2 are disposed at the lower side with respect to the module hole MH. Thus, even if some of the pixels are omitted around the module hole MH, the pixels connected to the second signal line SL2 and arranged in the same column can receive the data signal through substantially the same line.

[0128] The electronic panel 200 according to the illustrated exemplary embodiment can further include a connection pattern disposed in the hole area HA. In this case, the first signal line SL1 can be disconnected in an area overlapping the hole area HA. The disconnected portions of the first signal line SL1 are connected to each other by the connection pattern. In addition, the second signal line SL2 can be disconnected in an area overlapping the hole area HA, and a connection pattern connecting the disconnected portions of the second signal line SL2 can be further provided.

[0129] Referring again to Figure 3A A power pattern VDD can be disposed in the non-active area NAA. In the illustrated exemplary embodiment, the power pattern VDD is connected to a plurality of power lines PL. Thus, since the display unit 210 includes the power pattern VDD, the same first power signal can be provided to each of the pixels PX.

[0130] The display pad DPD can include a first pad P1 and a second pad P2. A plurality of first pads P1 can be provided, and the plurality of first pads P1 can be connected to the data lines DL, respectively. The second pad P2 can be connected to the power pattern VDD and can be electrically connected to the power line PL. The display unit 210 can apply an electrical signal applied thereto from the outside to the pixels PX via the display pad DPD. The display pad DPD can include pads to receive other electrical signals in addition to the first pad P1 and the second pad P2.

[0131] Figure 4A is a plan view of a sensing unit 220 according to an exemplary embodiment. Figure 4B is a plan view of a portion of an electronic panel 200 according to an exemplary embodiment. Figure 4C is a cross-sectional view taken along line I-I' of Figure 4B .

[0132] Referring to Figure 4A and Figure 4B , the sensing unit 220 can be disposed on the display unit 210 (refer to Figure 3A ). The sensing unit 220 can sense an external input TC (refer to Figure 1A), to obtain information about a position and / or intensity of an external input TC. The sensing unit 220 can include a plurality of first sensing electrodes TE1, a plurality of second sensing electrodes TE2, a plurality of sensing lines TL1, TL2, and TL3, and a plurality of sensing pads T1, T2, and T3.

[0133] The first sensing electrodes TE1 and the second sensing electrodes TE2 are arranged in the active area AA. The sensing unit 220 can obtain information about an external input TC based on a change in capacitance between the first sensing electrodes TE1 and the second sensing electrodes TE2.

[0134] The first sensing electrodes TE1 can be arranged in the first direction DR1 and can extend in the second direction DR2. Each of the first sensing electrodes TE1 can include a first main pattern SP1, a first adjacent pattern SP1H, and a first connection pattern BP1. As used herein, the first main pattern SP1 and the first adjacent pattern SP1H can be collectively referred to as a "first sensing pattern."

[0135] The first main pattern SP1 of the first sensing pattern is spaced apart from the module hole MH. The first main pattern SP1 can have a predetermined shape and can have a first area. In the illustrated exemplary embodiment, the first main pattern SP1 can have a rhombus shape, but the inventive concept is not limited thereto. For example, in some exemplary embodiments, the first main pattern SP1 can have various other shapes.

[0136] The first adjacent pattern SP1H of the first sensing pattern is disposed adjacent to the hole area HA. The first adjacent pattern SP1H can have a second area that is smaller than the first area of the first main pattern SP1. The first adjacent pattern SP1H can have a shape obtained by removing an area overlapping the hole area HA from the rhombus shape of the first main pattern SP1.

[0137] The first connection pattern BP1 can extend along the second direction DR2. The first connection pattern BP1 can be connected to the first main pattern SP1. The first connection pattern BP1 can be disposed between two first main patterns SP1 to connect the two first main patterns SP1 to each other. As another example, the first connection pattern BP1 can be disposed between the first main pattern SP1 and the first adjacent pattern SP1H to connect the first main pattern SP1 and the first adjacent pattern SP1H spaced apart from each other.

[0138] The second sensing electrodes TE2 can be arranged in the second direction DR2 and can extend in the first direction DR1. Each of the second sensing electrodes TE2 can include a second main pattern SP2, a second adjacent pattern SP2H, and a second connection pattern BP2. As used herein, the second main pattern SP2 and the second adjacent pattern SP2H can be collectively referred to as a "second sensing pattern."

[0139] The second main pattern SP2 of the second sensing pattern can be disposed to be spaced apart from the module hole MH. The second main pattern SP2 can be spaced apart from the first main pattern SP1. In the illustrated exemplary embodiment, the spacing between the first main pattern SP1 and the second main pattern SP2 can be a spacing in a cross-sectional view. For example, the first main pattern SP1 and the second main pattern SP2 can be disposed on the same layer and can be spaced apart from each other. The first main pattern SP1 and the second main pattern SP2 can not be in contact with each other and can transmit and receive independent electrical signals.

[0140] In the illustrated exemplary embodiment, the second main pattern SP2 can have substantially the same shape as the first main pattern SP1. For example, the second main pattern SP2 can have a rhombus shape. However, in other exemplary embodiments, the second main pattern SP2 can have various other shapes, and the inventive concept is not limited to a particular shape of the second main pattern SP2.

[0141] The second adjacent pattern SP2H of the second sensing pattern is disposed adjacent to the module hole MH. The second adjacent pattern SP2H can have an area smaller than that of the second main pattern SP2. The second adjacent pattern SP2H can have a shape obtained by removing an area overlapping the hole area HA from the rhombus shape of the second main pattern SP2.

[0142] The second connection pattern BP2 can extend along the first direction DR1. The second connection pattern BP2 can be connected to the second main pattern SP2. The second connection pattern BP2 can be disposed between two second main patterns SP2 to connect the two second main patterns SP2 to each other. As another example, the second connection pattern BP2 can be disposed between the second main pattern SP2 and the second adjacent pattern SP2H to connect the second main pattern SP2 and the second adjacent pattern SP2H.

[0143] The sensing lines TL1, TL2, and TL3 can be disposed in the non-active area NAA. The sensing lines TL1, TL2, and TL3 can include a first sensing line TL1, a second sensing line TL2, and a third sensing line TL3.

[0144] The first sensing lines TL1 can be connected to the first sensing electrodes TE1, respectively. In the illustrated exemplary embodiment, the first sensing lines TL1 can be connected to one of two ends of the first sensing electrodes TE1 spaced apart from each other in the second direction DR2, respectively.

[0145] The second sensing lines TL2 can be connected to one end of the second sensing electrodes TE2, respectively. In the illustrated exemplary embodiment, the second sensing lines TL2 can be connected to the left end of two ends of the second sensing electrodes TE2 spaced apart from each other in the first direction DR1, respectively.

[0146] The third sensing line TL3 can be connected to the other of the two ends of the first sensing electrode TE1 that are spaced apart from each other in the second direction DR2, respectively. In the illustrated exemplary embodiment, the first sensing electrode TE1 can be connected to the first sensing line TL1 and the third sensing line TL3, respectively. In this way, the sensitivity of the region of the first sensing electrode TE1 having a length longer than that of the second sensing electrode TE2 can be uniformly maintained. However, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the third sensing line TL3 can be omitted in the sensing unit 220.

[0147] The sensing pads T1, T2, and T3 are disposed in the peripheral region NAA. The sensing pads T1, T2, and T3 can include a first sensing pad T1, a second sensing pad T2, and a third sensing pad T3. The first sensing pad T1 can be connected to the first sensing line TL1, respectively, to apply an external signal to the first sensing electrode TE1. The second sensing pad T2 can be connected to the second sensing line TL2, respectively, and can be electrically connected to the second sensing electrode TE2, and the third sensing pad T3 can be connected to the third sensing line TL3, respectively, and can be electrically connected to the first sensing electrode TE1.

[0148] The sensing unit 220 can include a crack sensing portion HCC. The crack sensing portion HCC receives independent electrical signals from the first sensing electrode TE1 and the second sensing electrode TE2. The crack sensing portion HCC can include a crack sensing pattern HCP, a crack sensing line HCL, and a connection line BRH.

[0149] The crack sensing pattern HCP can be disposed in the hole region HA. The crack sensing pattern HCP extends along an edge of the hole region HA in the hole region HA. In the illustrated exemplary embodiment, the crack sensing pattern HCP can have an open curve shape that surrounds a portion of the edge of the module hole MH.

[0150] The crack sensing pattern HCP includes an electrically conductive material. The crack sensing pattern HCP can have electrical conductivity. In the illustrated exemplary embodiment, the crack sensing pattern HCP can have a one-piece shape.

[0151] The crack sensing line HCL is disposed in the peripheral region NAA. In the illustrated exemplary embodiment, the crack sensing line HCL is disposed farther from the active region AA than the first sensing line TL1, the second sensing line TL2, and the third sensing line TL3.

[0152] The crack sensing line HCL is electrically connected to the crack sensing pattern HCP. The crack sensing line HCL can include a first line HCL1 and a second line HCL2 that are spaced apart from each other.

[0153] One end of the first line HCL1 is connected to a first pad H11, and one end of the second line HCL2 is connected to a second pad H12. The first pad H11 and the second pad H12 can be disposed to be spaced apart from the area in which the display pad DPD is disposed. For example, the first pad H11 and the second pad H12 can be disposed at the left side with respect to the area in which the display pad DPD is disposed.

[0154] The other end of the first line HCL1 is connected to a third pad H21, and the other end of the second line HCL2 is connected to a fourth pad H22. The third pad H21 and the fourth pad H22 can be disposed to be spaced apart from the area in which the display pad DPD is disposed. For example, the third pad H21 and the fourth pad H22 can be disposed at the right side with respect to the area in which the display pad DPD is disposed. The first pad H11 and the second pad H12 are disposed to be spaced apart from the third pad H21 and the fourth pad H22, and the display pad DPD is interposed between the first pad H11 and the second pad H12 and the third pad H21 and the fourth pad H22.

[0155] The connection line BRH includes a first connection line BRH1 and a second connection line BRH2. The first connection line BRH1 connects the first line HCL1 with one end of the crack sensing pattern HCP. The second connection line BRH2 connects the second line HCL2 with the other end of the crack sensing pattern HCP.

[0156] In the illustrated exemplary embodiment, the first connection line BRH1 and the second connection line BRH2 can be spaced apart from each other in the cross-section or plane. The first connection line BRH1 extends in the second direction DR2 to connect the one end of the crack sensing pattern HCP and the first line HCL1. The second connection line BRH2 extends in the second direction DR2 to connect the other end of the crack sensing pattern HCP and the second line HCL2.

[0157] Accordingly, the first connection line BRH1 and the second connection line BRH2 can extend from the hole area HA to the non-hole area NAA in the second direction DR2 via the active area AA.

[0158] In the illustrated exemplary embodiment, the connection line BRH can be spaced apart from the patterns of the first sensing electrode TE1 and the second sensing electrode TE2 that overlap the connection line BRH in the cross-section or plane. Accordingly, the connection line BRH can be electrically insulated from the first sensing electrode TE1 and the second sensing electrode TE2, which will be described in greater detail later.

[0159] According to the exemplary embodiment, the crack sensing portion HCC can be used to determine whether a defect such as a crack is generated in the hole area HA of the electronic panel 200 or in the non-hole area NAA in the physical sense.

[0160] In the crack sensing portion HCC, the first pad H11 and the third pad H21 can be used as input terminals, and the second pad H12 and the fourth pad H22 can be used as output terminals.

[0161] An electrical signal received through the first pad H11 can pass through the crack sensing pattern HCP via the first line HCL1. Then, the electrical signal output from the crack sensing pattern HCP is output to the second pad H12 through the second line HCL2.

[0162] Similarly, an electrical signal received through the third pad H21 can pass through the crack sensing pattern HCP via the first line HCL1. Then, the electrical signal output from the crack sensing pattern HCP is output to the fourth pad H22 through the second line HCL2.

[0163] For example, when the signals sensed from the second pad H12 and the fourth pad H22, respectively, are detected as defective, for example, when the sensed signals have a low level value or a zero (0) level value with respect to a reference signal, there is a high probability that the first line HCL1 and the second line HCL2 can have been damaged or that the crack sensing pattern HCP can have been damaged. In this way, it can be determined whether a crack has occurred in the hole region HA.

[0164] As another example, when the signal sensed from only one of the second pad H12 and the fourth pad H22 is not detected as defective, there is a high probability that the crack sensing line HCL can have been damaged. In this way, it can be determined whether a crack has occurred in the peripheral region NAA.

[0165] However, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the first pad H11 and the third pad H21 can be used as output terminals, and the second pad H12 and the fourth pad H22 can be used as input terminals.

[0166] Reference Figure 4C The display unit 210 and the sensing unit 220 of the electronic panel 200 can be stacked with each other in the third direction DR3. The display unit 210 includes a base substrate BS, pixels PX, a plurality of insulating layers 10, 20, 30, 40, and 50, and an encapsulation layer 60.

[0167] Figure 4C The pixel PX shown in FIG. 1A illustrates Figure 3AThe light emitting element EE and the thin film transistor TR corresponding to the second thin film transistor TR2 among the components of the equivalent circuit diagram of the pixel PX shown in FIG. 1A. The insulating layers 10, 20, 30, 40, and 50 can include the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50, which are sequentially stacked. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 can include an organic material and / or an inorganic material, and can have a single layer structure or a multi-layer structure.

[0168] The first insulating layer 10 is disposed on the base substrate BS to cover the front surface of the base substrate BS. The first insulating layer 10 can include a barrier layer 11 and / or a buffer layer 12. As such, the first insulating layer 10 can prevent oxygen or moisture flowing through the base substrate BS from entering the pixel PX, or can reduce the surface energy of the base substrate BS so that the pixel PX is stably formed on the base substrate BS.

[0169] However, the inventive concept is not limited thereto. For example, in some exemplary embodiments, at least one of the barrier layer 11 and the buffer layer 12 can be omitted from the first insulating layer 10, and the first insulating layer 10 can have a structure in which a plurality of layers are stacked on each other.

[0170] The thin film transistor TR is disposed on the first insulating layer 10. The thin film transistor TR includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10.

[0171] The semiconductor pattern SP can include a semiconductor material. The control electrode CE can be spaced apart from the semiconductor pattern SP, and the second insulating layer 20 is interposed between the control electrode CE and the semiconductor pattern SP. The control electrode CE can be connected to the first thin film transistor TR1 (refer to FIG. 1A) and one electrode (refer to FIG. 1A) of the capacitor CP. Figure 3A ) and the other electrode (refer to FIG. 1A) of the capacitor CP. Figure 3A ) and the other electrode (refer to FIG. 1A) of the capacitor CP.

[0172] The input electrode IE and the output electrode OE are disposed on the third insulating layer 30 and are spaced apart from each other when viewed in a plan view. The input electrode IE and the output electrode OE are connected to one side and the other side of the semiconductor pattern SP, respectively, after passing through the second insulating layer 20 and the third insulating layer 30.

[0173] The display unit 210 according to the exemplary embodiment shown can further include an upper electrode UE. Accordingly, the third insulating layer 30 can include a lower layer 31 and an upper layer 32. The upper electrode UE is disposed between the lower layer 31 and the upper layer 32. The upper electrode UE can overlap the control electrode CE when viewed in a plan view.

[0174] In the illustrated example embodiment, the upper electrode UE can receive substantially the same electrical signal as the electrical signal applied to the control electrode CE, or can receive a different electrical signal from the electrical signal applied to the control electrode CE to serve as one electrode of the capacitor. However, the present inventive concept is not limited thereto. For example, in some example embodiments, the upper electrode UE can be omitted from the electronic panel 200.

[0175] The fourth insulating layer 40 is provided over the third insulating layer 30 to cover the input electrode IE and the output electrode OE. In the thin film transistor TR, the control electrode CE can be provided over the semiconductor pattern SP.

[0176] As another example, the semiconductor pattern SP can be provided over the input electrode IE and the output electrode OE. Alternatively, the input electrode IE and the output electrode OE can be provided on the same layer as the semiconductor pattern SP, and can be directly connected to the semiconductor pattern SP. As described above, the present inventive concept is not limited to the specific structure of the thin film transistor TR, and the thin film transistor TR can have various structures known in the art.

[0177] The light emitting element EE is provided over the fourth insulating layer 40. The light emitting element EE includes the first electrode E1, the organic layer EL, and the second electrode E2.

[0178] The first electrode E1 can be connected to the thin film transistor TR after passing through the fourth insulating layer 40. In some example embodiments, the electronic panel 200 can further include a separate connection electrode provided between the first electrode E1 and the thin film transistor TR, and in this case, the first electrode E1 can be electrically connected to the thin film transistor TR via the connection electrode.

[0179] The fifth insulating layer 50 is provided over the fourth insulating layer 40. The fifth insulating layer 50 can include an organic material and / or an inorganic material, and can have a single layer structure or a multi-layer structure. The fifth insulating layer 50 can provide an opening defined therethrough. At least a portion of the first electrode E1 can be exposed through the opening. The fifth insulating layer 50 can be a pixel defining layer, but is not limited thereto.

[0180] The organic layer EL is provided between the first electrode E1 and the second electrode E2. The organic layer EL can include at least one light emitting layer. For example, the organic layer EL can include a material that emits at least one of red light, green light, and blue light, and can include a fluorescent material or a phosphorescent material. The organic layer EL can include an organic light emitting material or an inorganic light emitting material. The organic layer EL can emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0181] The organic layer EL is shown as having a single unitary form overlapping with the plurality of openings, however, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the organic layer EL can be provided as a plurality of patterns corresponding to the openings, respectively.

[0182] The organic layer EL can further include a charge control layer in addition to the light emitting layer. The charge control layer can control movement of charges to improve light emitting efficiency and lifespan of the light emitting element EE. In this case, the organic layer EL can include at least one of a hole transport material, a hole injection material, an electron transport material, and an electron injection material.

[0183] The second electrode E2 is disposed on the organic layer EL. The second electrode E2 can face the first electrode E1. The second electrode E2 can extend from the active area AA to the non-active area NAA, and can have a single unitary form. The second electrode E2 can be generally disposed in the pixel. The light emitting element EE disposed in each of the pixels can receive a common power voltage (hereinafter referred to as a "second power voltage") via the second electrode E2.

[0184] The second electrode E2 can include a transmissive or semi-transmissive conductive material. Accordingly, light generated by the light emitting element EE can easily propagate in the third direction DR3 via the second electrode E2. However, the inventive concept is not limited thereto. For example, the light emitting element EE in some exemplary embodiments can operate in a rear surface light emitting manner in which the first electrode E1 includes a transmissive or semi-transmissive material according to its design, or can operate in a dual surface light emitting manner in which light is emitted to both front and rear surfaces.

[0185] An encapsulation layer 60 is disposed on the light emitting element EE to encapsulate the light emitting element EE. In some exemplary embodiments, a capping layer can also be disposed between the second electrode E2 and the encapsulation layer 60 to cover the second electrode E2.

[0186] The encapsulation layer 60 can include a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63 sequentially stacked in the third direction DR3. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the encapsulation layer 60 can further include a plurality of inorganic layers and organic layers.

[0187] The first inorganic layer 61 can cover the second electrode E2. The first inorganic layer 61 can prevent external moisture or oxygen from entering the light emitting element EE. For example, the first inorganic layer 61 can include silicon nitride, silicon oxide, or a compound thereof. The first inorganic layer 61 can be formed by a chemical vapor deposition process.

[0188] The organic layer 62 is disposed on the first inorganic layer 61 to be in contact with the first inorganic layer 61. The organic layer 62 can provide a flat surface on the first inorganic layer 61. An uneven shape formed on the upper surface of the first inorganic layer 61 or a particle present on the first inorganic layer 61 can be covered by the organic layer 62, and thus, a surface state of the upper surface of the first inorganic layer 61 can be prevented from affecting a component formed on the organic layer 62. In addition, the organic layer 62 can alleviate stress between layers in contact with each other. The organic layer 62 can include an organic material, and can be formed by a solution process such as spin coating, slot coating, or an inkjet process.

[0189] The second inorganic layer 63 is disposed on the organic layer 62 to cover the organic layer 62. The second inorganic layer 63 can be stably formed on a relatively flat surface, rather than being disposed on the first inorganic layer 61. The second inorganic layer 63 can include silicon nitride, silicon oxide, or a compound thereof. The second inorganic layer 63 can be formed by a chemical vapor deposition process.

[0190] The electronic panel 200 includes a planarization portion YOC. The planarization portion YOC is disposed between the display unit 210 and the sensing unit 220. The planarization portion YOC is disposed in the hole area HA between the display unit 210 and the sensing unit 220. The planarization portion YOC is covered by the first sensing insulating layer 71. The planarization portion YOC can include an organic material, and can be formed by a solution process such as spin coating, slot coating, or an inkjet process.

[0191] The planarization portion YOC can provide a flat surface that compensates for a step difference formed by components of the display unit 210 in an area adjacent to the hole area HA. Accordingly, a flat surface can be provided in an area in the hole area HA in which the organic layer 62 is not disposed.

[0192] The grooves GV1, GV2, and GV3 can be defined in the display unit 210. In the grooves GV1, GV2, and GV3, the first groove GV1 can be adjacent to the active area AA, and the second groove GV2 and the third groove GV3 can overlap the hole area HA. Figure 3B The groove GV shown in the middle corresponds to one of the first groove GV1, the second groove GV2, and the third groove GV3.

[0193] Each of the first groove GV1, the second groove GV2, and the third groove GV3 can have a closed line shape around the module hole MH, or can have a broken line shape around at least a portion of the edge of the module hole MH, without being limited thereto. Figure 4C The first groove GV1, the second groove GV2, and the third groove GV3, which are sequentially formed in a direction close to the module hole MH, are exemplarily shown.

[0194] Each of the first groove GV1, the second groove GV2, and the third groove GV3 can be defined by being recessed from the upper surface of the base substrate BS. Each of the first groove GV1, the second groove GV2, and the third groove GV3 can be formed by removing at least a portion of the base substrate BS. The deposition pattern ELP can be disposed in each of the first groove GV1, the second groove GV2, and the third groove GV3, and can be covered by at least one of the first inorganic layer 61 and the second inorganic layer 63. In addition, the first groove GV1 adjacent to the active area AA can be filled with the organic layer 62.

[0195] Since the electronic panel 200 according to the illustrated exemplary embodiment includes the first groove GV1, the second groove GV2, and the third groove GV3, continuity between the deposition pattern ELP and the light emitting element EE can be blocked. Accordingly, a penetration path of external moisture or oxygen can be blocked, and thus it is possible to prevent elements disposed in the active area AA from being damaged.

[0196] In addition, since the deposition pattern ELP disposed in each of the first groove GV1, the second groove GV2, and the third groove GV3 is covered by the first inorganic layer 61 or the second inorganic layer 63, it is possible to prevent the deposition pattern ELP from moving to and affecting other elements when the electronic panel 200 is manufactured. Accordingly, it is possible to improve process reliability of the electronic panel 200.

[0197] However, the inventive concept is not limited thereto, and in some exemplary embodiments, at least one of the first groove GV1, the second groove GV2, and the third groove GV3 can be provided in a single integrated form, or can be omitted from the electronic panel 200.

[0198] The dam portion DMP is disposed in the hole area HA. The dam portion DMP limits an area in which the organic layer 62 is formed, and prevents expansion of the area formed by the organic layer 62. The dam portion DMP can be provided in a plurality, and the dam portion DMP can be disposed between the first groove GV1, the second groove GV2, and the third groove GV3.

[0199] The dam portion DMP can have a stacked structure of a first layer P11, a second layer P12, and a third layer P13. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the dam portion DMP can have a single layer structure.

[0200] The sensing unit 220 can include a plurality of conductive patterns and a plurality of sensing insulating layers 71, 72, and 73. The sensing insulating layers 71, 72, and 73 include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73, which are sequentially stacked in the third direction DR3.

[0201] The first sensing insulating layer 71 can cover the planarization portion YOC. In the illustrated exemplary embodiment, the first sensing insulating layer 71 can cover the upper surface of the planarization portion YOC in the hole region HA, and can cover the upper surface of the second inorganic layer 63 in the active region AA.

[0202] The second sensing insulating layer 72 and the third sensing insulating layer 73 can have a single integrated form overlapping the hole region HA and the active region AA. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 can include an inorganic layer and / or an organic layer. In the illustrated exemplary embodiment, each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 has a single layer structure. However, in some exemplary embodiments, each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 can have a stacked structure of multiple layers in contact with each other.

[0203] Hereinafter, the conductive pattern of the conductive pattern disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72 can be referred to as a "first conductive pattern". In addition, the conductive pattern of the conductive pattern disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73 can be referred to as a "second conductive pattern".

[0204] Figure 4C An exemplary structure is illustrated in which the first conductive pattern includes the second sensing electrode TE2 and components of the first sensing electrode TE1 excluding the first connection pattern BP1, and the second conductive pattern includes the first connection pattern BP1.

[0205] The crack sensing pattern HCP is disposed in the hole region HA. The crack sensing pattern HCP is disposed to be spaced apart from the first conductive pattern and the second conductive pattern. Accordingly, the crack sensing pattern HCP can receive an electrical signal independently of the first conductive pattern and the second conductive pattern, and can operate independently of the first conductive pattern and the second conductive pattern.

[0206] In the illustrated exemplary embodiment, the crack sensing pattern HCP can be disposed on the planarization portion YOC. The crack sensing pattern HCP is disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. The crack sensing pattern HCP is disposed on the same layer as the second conductive pattern.

[0207] The crack sensing pattern HCP and the second conductive pattern can be formed substantially simultaneously using one mask. Accordingly, the manufacturing process thereof can be simplified, and the process cost can be reduced. However, the inventive concept is not limited thereto. In some exemplary embodiments, the crack sensing pattern HCP can be disposed on the same layer as the first conductive pattern.

[0208] The connection line BRH can be provided on the same layer as the crack sensing pattern HCP. Figure 4C An example of a structure in which the first connection line BRH1 is provided on the same layer as the crack sensing pattern HCP is illustrated. The first connection line BRH1 is provided between the second sensing insulating layer 72 and the third sensing insulating layer 73.

[0209] The connection line BRH can extend from the hole region HA to the active region AA in one direction. Accordingly, a portion of the connection line BRH can cross a step region formed by a height difference between the planarization portion YOC and the encapsulation layer 60.

[0210] A height from a lower surface of the base substrate BS to an upper surface of the planarization portion YOC in contact with the first sensing insulating layer 71 can be higher than a height from the lower surface of the base substrate BS to an upper surface of the encapsulation layer 60 in contact with the first sensing insulating layer 71. Accordingly, the planarization portion YOC can form a step difference with the encapsulation layer 60.

[0211] Figure 5A is an enlarged plan view of a portion of the electronic panel 200 according to an example embodiment. Figure 5B is an enlarged perspective view of a portion of the electronic panel 200 according to an example embodiment. Figure 6A is a cross-sectional view taken along Figure 5B line II-II’ of Figure 6B is a cross-sectional view taken along Figure 5B line III-III’ of Figure 6C is a cross-sectional view taken along Figure 5B line IV-IV’ of Figure 6D is a cross-sectional view taken along Figure 5B line V-V’ of Figure 6C is a cross-sectional view of a region of the planarization portion YOC overlapping the first recessed portion RC1, and Figure 6D is a cross-sectional view of a region of the planarization portion YOC not overlapping the first recessed portion RC1.

[0212] Figure 5B An enlarged plan view of the first sensing insulating layer 71 and the second sensing insulating layer 72 covering the front surface of the planarization portion YOC and the second inorganic layer 63 is illustratively shown.

[0213] Referring to Figure 5A , the planarization portion YOC can include recessed portions RC1 and RC2. The recessed portions RC1 and RC2 can overlap the connection line BRH. For example, the first recessed portion RC1 can overlap the first connection line BRH1, and the second recessed portion RC2 can overlap the second connection line BRH2.

[0214] Figure 5B is Figure 5A An enlarged view of the first recessed portion RC1 of the recessed portions RC1 and RC2 shown in FIG. 1A, which overlaps the first connection line BRH1. In Figure 5B In FIG. 1B, some components are not shown, and the first recessed portion RC1 is shown by hatching. The second recessed portion RC2 has substantially the same structure as the first recessed portion RC1, and thus a detailed description thereof will be omitted.

[0215] The planarization portion YOC includes a flat surface YF and an inclined surface YI. The inclined surface YI can be inclined at a predetermined angle with respect to the flat surface YF. Hereinafter, a portion of the flat surface YF at which the flat surface YF contacts the inclined surface YI is referred to as an "upper end" YU, an edge of the inclined surface YI which contacts the encapsulation layer 60 is referred to as a "lower end" YB, and an edge of the hole region HA can be substantially the same as the lower end YB of the planarization portion YOC.

[0216] The first recessed portion RC1 can be a region recessed from the flat surface YF and the inclined surface YI. The first recessed portion RC1 can be recessed from the flat surface YF in a thickness direction of the planarization portion YOC, and can be recessed from the inclined surface YI in a thickness direction of the inclined surface YI.

[0217] According to an exemplary embodiment, the first recessed portion RC1 has a shape in which a width and a thickness thereof increase in a direction from the flat surface YF to the inclined surface YI.

[0218] The first recessed portion RC1 overlaps the first connection line BRH1. Accordingly, a portion of the first connection line BRH1 which overlaps the first recessed portion RC1 can have a shape corresponding to a shape of the first recessed portion RC1. The first connection line BRH1 extends in one direction, and crosses the upper end YU and the lower end YB of the planarization portion YOC.

[0219] Figure 6A and Figure 6B are cross-sectional views taken along lines II-II' and III-III', respectively, to show widths between two portions spaced apart from each other in an extension direction of the first connection line BRH1.

[0220] Referring to 6A to 6D , the first recessed portion RC1 has a shape in which a width and a thickness thereof increase in a direction from the flat surface YF to the inclined surface YI. For example, a portion of the first recessed portion RC1 which overlaps the line II-II' can have a first width W1 and a first thickness T1. A portion of the first recessed portion RC1 which overlaps the line III-III' can have a second width W2 and a second thickness T2. The thicknesses T1 and T2 can be thicknesses defined by an imaginary plane extending from the flat surface YF.

[0221] The first width W1 is smaller than the second width W2, and the first thickness T1 is smaller than the second thickness T2. The width and the thickness of the first recessed portion RC1 can gradually increase in a direction from the flat surface YF to the inclined surface YI.

[0222] According to an exemplary embodiment, since the planarization portion YOC includes the first recessed portion RC1 having a gentle inclination compared to the inclined surface YI, the first connection line BRH1 can be prevented from being disconnected. Accordingly, the reliability of the electronic panel 200 can be improved, which will be described in greater detail later.

[0223] Figure 7A is a cross-sectional view of a portion of the electronic panel 200 according to an exemplary embodiment. Figure 7B is a plan view of a portion of the electronic panel 200 according to an exemplary embodiment. Figure 8A is a cross-sectional view of a portion of the electronic panel 200 according to an exemplary embodiment. Figure 8B and Figure 8C is a plan view of a portion of the electronic panel 200 according to an exemplary embodiment. In 7A to 8C , the same reference numerals are used to refer to the same elements as those shown in 5A to 6D , and thus a repeated description thereof will be omitted.

[0224] Referring to Figure 7A and Figure 7B , the planarization portion YOC-A includes the flat surface YF-A and the inclined surface YI-A. The inclined surface YI-A can be inclined at a first inclination angle θ1 with respect to the flat surface YF-A. The first inclination angle θ1 according to an exemplary embodiment can be a right angle. Accordingly, the upper end YU and the lower end YB can overlap each other when viewed in a plan view.

[0225] When the first inclination angle θ1 is a right angle, the recessed portion RC-A can have a triangular shape when viewed in a plan view.

[0226] Referring to Figure 8A and Figure 8B , the planarization portion YOC-B includes the flat surface YF-B and the inclined surface YI-B. The inclined surface YI-B can be inclined at a second inclination angle θ2 with respect to the flat surface YF-B. The second inclination angle θ2 according to an exemplary embodiment can be an acute angle. Accordingly, the upper end YU and the lower end YB can be spaced apart from each other when viewed in a plan view.

[0227] When the second inclination angle θ2 is an acute angle, the recessed portion RC-B1 can have a polygonal shape when viewed in a plan view. For example, a recessed portion RB-1 of the recessed portion RC-B1 that overlaps the flat surface YF-B can have a triangular shape, and a recessed portion RU-1 of the recessed portion RC-B1 that overlaps the inclined surface YI-B can have a triangular shape (i.e., a V-shape). In this way, the shape of the recessed portion RC-B1 can be a quadrangular shape.

[0228] Reference Figure 8C , the recessed portion RC-B2 can have a different shape from the recessed portion RC-B1. For example, a recessed portion RB-2 of the recessed portion RC-B2 that overlaps the flat surface YF-B can have a triangular shape, and a recessed portion RU-2 of the recessed portion RC-B1 that overlaps the inclined surface YI-B can have a semicircular or semi-elliptical shape (i.e., a U-shape).

[0229] Figure 9A is an enlarged plan view of a portion of the electronic panel 200 according to an exemplary embodiment. Figure 9B is an enlarged perspective view of a portion of the electronic panel 200 according to an exemplary embodiment. In Figure 9A and Figure 9B , the same / similar reference numerals denote the same / similar elements as those shown in 5A to 6D , and thus, a repeated description thereof will be omitted. Figure 9A and Figure 9B exemplarily show the first and second sensing insulating layers 71 and 72 that cover the planarization portion YOC-1 and the front surface of the second inorganic layer 63.

[0230] Reference Figure 9A and Figure 9B , the planarization portion YOC-1 according to the exemplary embodiment shown includes recessed portions RC1 and RC2 and additional recessed portions SC1 and SC2. The recessed portions RC1 and RC2 can correspond to the recessed portions RC1 and RC2 described with reference to 5A to 6D . In this way, the additional recessed portions SC1 and SC2 will be described in more detail hereinafter.

[0231] The additional recessed portions SC1 and SC2 can be regions recessed from the flat surface YF of the planarization portion YOC-1. The additional recessed portions SC1 and SC2 can be recessed from the flat surface YF along the thickness direction of the planarization portion YOC-1.

[0232] The additional recessed portions SC1 and SC2 have shapes in which their width and thickness vary in a direction from the flat surface YF to the inclined surface YI. In the illustrated exemplary embodiment, the recessed portions RC1 and RC2 and the additional recessed portions SC1 and SC2 can have a triangular pyramid shape in cross section.

[0233] The additional recessed portions SC1 and SC2 can overlap the corresponding connection lines BRH1 and BRH2. In addition, the additional recessed portions SC1 and SC2 can be disposed to overlap components included in the electronic panel 200 that have a step difference among the components. For example, the additional recessed portions SC1 and SC2 can be disposed in the planarization portion YOC-1 in regions overlapping the dam portions DMP illustrated in Figure 4C .

[0234] In this way, since the additional recessed portions SC1 and SC2 are formed between the connection lines BRH of the electronic panel 200 and components that form a step difference with their adjacent components, the connection lines BRH can be more easily formed.

[0235] Figure 10A and Figure 10B is a plan view showing a portion of the electronic device EA according to an exemplary embodiment. In Figure 10A and Figure 10B , the same / similar reference numerals denote the same / similar elements as those illustrated in Figures 1A to 6D , and thus, a repeated description thereof will be omitted. Figure 10A The hole region HA and the active region AA adjacent to the hole region HA are schematically illustrated. Figure 10B Patterns disposed on the same layer are merely exemplarily illustrated, and some components are omitted.

[0236] Referring to Figure 10A , the first and second sensing patterns SP1C and SP2C can include dummy pattern portions FP1C and FP2C, respectively. Specifically, each of the first sensing patterns SP1C can include a main portion MP1C and a first dummy pattern portion FP1C spaced apart from the main portion MP1C. Each of the second sensing patterns SP2C can include a main portion MP2C and a plurality of second dummy pattern portions FP2C spaced apart from the main portion MP2C.

[0237] Portions of the connection lines BRH1 and BRH2 connected to the dummy pattern portions FP1C and FP2C connected to the crack sensing pattern HCP can be defined as “floating patterns,” and the floating patterns can function as a portion of the connection lines BRH1 and BRH2.

[0238] In the illustrated exemplary embodiment, portions of the first dummy pattern portions FP1C among the plurality of first sensing patterns SP1C disposed on the crack sensing pattern HCP may be connected to each other to form a first floating pattern FL_C1 connected to the first connection line BRH1, and other portions may be connected to each other to form a second floating pattern FL_C2. Among the dummy pattern portions FP1C and FP2C, the remaining patterns not used as the first floating pattern FL_C1 and the second floating pattern FL_C2 may be electrically isolated from each other.

[0239] In the exemplary embodiment shown, the bridge pattern BL may connect a plurality of first sensing patterns SP1C that are spaced apart from each other and between which the module hole MH is inserted. The bridge pattern BL may surround a portion of the module hole MH. The bridge pattern BL may connect the first sensing patterns SP1C that have been deformed or partially removed by the module hole MH. Figure 10A Only the bridge pattern BL is shown, connecting the plurality of first sensing patterns SP1C spaced apart from each other and with the module hole MH interposed therebetween. However, the present invention is not limited thereto. In some exemplary embodiments, a bridge pattern may be additionally formed, connecting the plurality of second sensing patterns SP2C spaced apart from each other and with the module hole MH interposed therebetween.

[0240] Figure 10B The first sensing patterns SP1M and the second sensing patterns SP2M shown may have Figure 10A The first and second sensing patterns SP1C and SP2C shown in FIG. 8 have shapes corresponding to those of the first and second sensing patterns SP1C and SP2C, and may include grid lines. Figure 10B One first sensing pattern SP1M, one second sensing pattern SP2M, and one second connecting pattern BP2M disposed on the same layer among the components of the electronic panel 200 are exemplarily shown.

[0241] The first sensing pattern SP1M and the second sensing pattern SP2M may include a plurality of grid lines MSP. The grid lines MSP include a first grid line MSP1 and a second grid line MSP2. The grid lines MSP define a plurality of openings. The openings may overlap with the light emitting regions defined by the light emitting elements EE.

[0242] The boundary between the first sensing pattern SP1M and the second sensing pattern SP2M can be defined by disconnecting a portion of the mesh line MSP. In the exemplary embodiment shown, the disconnected portion of the mesh line MSP is shown as a thick line. Figure 10B The boundary between the first sensing pattern SP1M and the second sensing pattern SP2M according to the illustrated exemplary embodiment has a zigzag shape defined by a plurality of curved lines.

[0243] The first sensing pattern SP1M includes a first main portion MP1M and a first dummy pattern portion FP1M. The first dummy pattern portion FP1M can be spaced apart from the first main portion MP1M when viewed in a plan view. The thick line surrounding the first dummy pattern portion FP1M can be a space for defining the boundary between the first dummy pattern portion FP1M and the first main portion MP1M.

[0244] Each of the first dummy pattern portions FP1M can include a mesh line MSP, and can be electrically insulated from the mesh line MSP forming an adjacent first main portion MP1M. The first sensing pattern SP1M can be provided in a plurality of numbers, and the first sensing patterns SP1M can be spaced apart from each other.

[0245] In the illustrated exemplary embodiment, a first connection pattern can connect the first sensing patterns SP1M to each other. The first connection pattern can be provided on a different layer from the first sensing patterns SP1M. Accordingly, the first connection pattern can be connected to the first sensing patterns SP1M through predetermined contact holes.

[0246] The second sensing pattern SP2M includes a second main portion MP2M and a second dummy pattern portion FP2M. The second dummy pattern portion FP2M can be spaced apart from the second main portion MP2M when viewed in a plan view. The second sensing pattern SP2M can be provided in a plurality of numbers, and the second sensing patterns SP2M can be spaced apart from each other.

[0247] The second dummy pattern portion FP2M according to the illustrated exemplary embodiment is illustrated as having a different shape from the first dummy pattern portion FP1M, but the inventive concept is not limited thereto. For example, in some exemplary embodiments, the second dummy pattern portion FP2M can have substantially the same shape as the first dummy pattern portion FP1M.

[0248] The second connection pattern BP2M can connect the second sensing patterns SP2M. The second connection pattern BP2M can be provided on the same layer as the second sensing patterns SP2M. The second connection pattern BP2M includes a plurality of mesh lines MSP. In the illustrated exemplary embodiment, the second connection pattern BP2M can be provided integrally with the second sensing patterns SP2M, more particularly, with the second main portions MP2M.

[0249] The first dummy pattern portion FP1M and the second dummy pattern portion FP2M are disposed adjacent to each other while being spaced apart from each other. The disconnected mesh lines MSP can be formed between the first dummy pattern portion FP1M and the second dummy pattern portion FP2M.

[0250] According to an exemplary embodiment, the floating patterns FL1_M and FL2_M can be disposed on the same layer as the first sensing pattern SP1M. The floating patterns FL1_M and FL2_M include a first floating pattern FL1_M and a second floating pattern FL2_M spaced apart from each other. Figure 10B The floating patterns FL1_M and FL2_M shown in FIG. 1A can perform the same functions as the reference Figure 10A The floating patterns FL_C1 and FL_C2 described above perform the same functions. Accordingly, the floating patterns FL1_M and FL2_M can be used as a part of the connection lines BRH1 and BRH2.

[0251] The first floating pattern FL1_M and the second floating pattern FL2_M are spaced apart from the first main portion MP1M when viewed in a plan view. Also, the first floating pattern FL1_M and the second floating pattern FL2_M can be spaced apart from the first dummy pattern portion FP1M when viewed in a plan view.

[0252] In the exemplary embodiment shown, the first floating pattern FL1_M and the second floating pattern FL2_M can be defined by connecting a plurality of portions of the first dummy pattern portion FP1M. Accordingly, the first floating pattern FL1_M and the second floating pattern FL2_M can be surrounded by the first main portion MP1M and can be disposed in the first sensing pattern SP1M.

[0253] According to the exemplary embodiment shown, the first conductive pattern and the second conductive pattern can be defined by Figure 4C the first sensing insulating layer 71 and the second sensing insulating layer 72 shown in FIG. 1A. For example, the first sensing pattern SP1M, the second sensing pattern SP2M, the second connection pattern BP2M, and the floating patterns FL1_M and FL2_M can be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72 and can be defined as the first conductive pattern.

[0254] Also, the first connection pattern can be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73 and can be defined as the second conductive pattern.

[0255] Figure 11A is Figure 10A is an enlarged plan view of the portion shown in FIG. 1A. Figure 11B is Figure 4A is an enlarged plan view of the portion shown in FIG. 1A. Figure 11AA hole region HA and an active region AA adjacent to the hole region HA are shown, and Figure 11B A peripheral region NAA and an active region AA adjacent to the peripheral region NAA are shown.

[0256] Referring to Figure 11A The connection lines BRH1 and BRH2 extending from the hole region HA to the active region AA can be connected to the floating patterns FL1_M and FL2_M. For example, the first connection line BRH1 can be connected to the first floating pattern FL1_M, and the second connection line BRH2 can be connected to the second floating pattern FL2_M. Accordingly, the floating patterns FL1_M and FL2_M can serve as a part of the connection lines BRH1 and BRH2.

[0257] The bridge pattern BL can correspond to the bridge pattern BL described with reference to Figure 10A The bridge pattern BL can connect the first sensing patterns SP1C spaced apart from each other to each other.

[0258] Figure 11B A connection relationship between the first floating pattern FL1_M of the floating patterns FL1_M and FL2_M and the crack sensing line HCL is schematically shown. The floating patterns FL1_M and FL2_M can be connected to each other and can extend from the active region AA to the peripheral region NAA. The first floating pattern FL1_M and the first line HCL1 can be connected to each other via the line connection portion BLL.

[0259] The second floating pattern FL2_M can extend from the active region AA to the peripheral region NAA and can be connected to the second line HCL2 via the line connection portion connecting the second floating pattern FL2_M and the second line HCL2.

[0260] According to the exemplary embodiment shown, since the crack sensing pattern HCP and the crack sensing line HCL are connected to each other by using the floating patterns FL1_M and FL2_M, which are parts of the dummy patterns FP1M and FP2M including the mesh line MSP of the sensing patterns SP1M and SP2M, the process cost and time required to form separate connection lines can be reduced. In addition, since the floating patterns FL1_M and FL2_M include the mesh line MSP, the connection lines can be prevented from being recognized from the outside. Accordingly, the visibility of the electronic panel can be improved.

[0261] The electronic panel according to the presently illustrated embodiment can further include a dummy pattern DM. The dummy pattern DM is disposed between the sensing line TL3 and the crack sensing line HCL. The dummy pattern DM transmits an electrical signal different from the sensing line TL3 and the crack sensing line HCL. Since the dummy pattern DM is disposed between the sensing line TL3 and the crack sensing line HCL which transmit electrical signals different from the electrical signal from the dummy pattern DM, it is possible to prevent a parasitic capacitance from being generated between the sensing line TL3 and the crack sensing line HCL. Accordingly, it is possible to improve the electrical characteristics of the electronic panel. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the dummy pattern DM can be omitted from the electronic panel.

[0262] 12A to 12I is a view illustrating a method of manufacturing an electronic panel according to an exemplary embodiment. In 12A to 12I , the same / similar reference numerals denote the same / similar elements as those illustrated in FIGS. 1A to Figure 6D , and thus, a repeated description thereof will be omitted. Hereinafter, a method of manufacturing an electronic panel according to an exemplary embodiment will be described with reference to 12A to 12I .

[0263] Referring to Figure 12A , the method of manufacturing an electronic panel includes providing a preliminary electronic panel.

[0264] The preliminary electronic panel can be provided in a state in which a preliminary planarization portion YOC-A is formed in a hole area HA of the display unit 210 in the assembly described with reference to Figure 4C . The preliminary planarization portion YOC-A can be in contact with a portion of the second inorganic layer 63 of the encapsulation layer 60 formed on the organic layer 62 (refer to Figure 4C ).

[0265] A portion in which the flat surface YF and the inclined surface YI of the preliminary planarization portion YOC-A are in contact with each other can be referred to as an "upper end YU", and an edge of the inclined surface YI in contact with the second inorganic layer 63 can be referred to as a "lower end YB". An edge of the hole area HA can correspond to a boundary in which the lower end YB of the planarization portion YOC-A is in contact with the encapsulation layer 60 (refer to Figure 4C ).

[0266] Referring to Figure 12B and Figure 12C , the method of manufacturing an electronic panel includes forming a recessed portion RC.

[0267] The recessed portion RC can be formed by removing a portion of the preliminary planarization portion YOC-A using a mask MSK in which an opening OPM is defined therethrough. The preliminary planarization portion YOC-A in which the recessed portion RC is formed is referred to as a "planarization portion" YOC.

[0268] The recessed portion RC can be formed to be recessed from the flat surface YF and the inclined surface YI in the thickness direction and the width direction. In the currently illustrated embodiment, the recessed portion RC can have a substantially triangular pyramid shape, but is not limited thereto.

[0269] The recessed portion RC can have a shape in which the width and the thickness thereof increase from the hole area HA to the active area AA. In addition, when observed in a cross-section, the inclination of the lower end of the recessed portion RC can be gentle compared to the inclination of the inclined surface YI.

[0270] Referring to Figure 12D and Figure 12E , the method of manufacturing an electronic panel includes forming an inorganic layer.

[0271] The sensing insulating layer 71 and the sensing insulating layer 72 can be deposited on the entire surfaces of the hole area HA and the active area AA. Portions of the sensing insulating layer 71 and the sensing insulating layer 72 that overlap the recessed portion RC can be formed on the recessed portion RC to correspond to the shape of the recessed portion RC. The sensing insulating layer 71 and the sensing insulating layer 72 can be formed by a chemical vapor deposition process.

[0272] Referring to Figure 12F , the method of manufacturing an electronic panel includes forming a preliminary conductive layer BRH-A. The preliminary conductive layer BRH-A can be formed to cover the entire surface of the second sensing insulating layer 72. The preliminary conductive layer BRH-A can include a conductive material. By taking into account the thicknesses of the sensing insulating layer 71 and the sensing insulating layer 72 that overlap the recessed portion RC, portions of the preliminary conductive layer BRH-A that overlap the recessed portion RC can be formed to correspond to the shape of the recessed portion RC.

[0273] Then, referring to Figure 12G , the method of manufacturing an electronic panel includes forming a photoresist layer PR.

[0274] The photoresist layer PR can be formed to cover the entire surface of the preliminary conductive layer BRH-A. During a photolithography process, the photoresist layer PR can serve as a mask layer of a material to be patterned.

[0275] Compared to the inclined surface YI on the preliminary conductive layer BRH-A, portions of the photoresist layer PR that overlap the recessed portion RC can be formed with a gentle inclination. In Figure 12G , when observed in a cross-section, the planarized portion YOC adjacent to the recessed portion RC is represented by a dotted line.

[0276] Due to the predetermined inclination angle of the flat surface YF and the inclined surface YI, the photoresist layer PR can be coated with a relatively small thickness in a region adjacent to the upper end YU. Accordingly, the preliminary conductive layer BRH-A having a relatively small thickness formed under the photoresist layer PR can be removed using the photoresist layer PR after the exposure and development processes, and thus, can be disconnected from the adjacent preliminary conductive layer BRH-A.

[0277] According to an exemplary embodiment, the photoresist layer PR disposed on the recessed portion RC can have a gentle inclination compared to the photoresist layer PR disposed on the inclined surface YI, and can be coated with a uniform thickness TH without being disconnected in a region adjacent to the upper end YU. In addition, in a region in which the width of the recessed portion RC on the plane is small, the thickness of the photoresist layer PR can be maximized.

[0278] Then, referring to Figure 12H and Figure 12I The manufacturing method of the electronic panel includes forming a connection line BRH.

[0279] The connection line BRH can be formed by patterning the preliminary conductive layer BRH-A using the photoresist layer PR as a mask. The connection line BRH can extend in a direction from the hole region HA toward the active region AA. Accordingly, the connection line BRH can pass over the flat surface YF and the inclined surface YI.

[0280] According to an exemplary embodiment, the connection line BRH is formed to overlap the recessed portion RC. Since the photoresist layer PR is coated with a uniform thickness TH in a region overlapping the recessed portion RC, the connection line BRH can extend to the active region AA on the planarized portion YOC without being disconnected. Accordingly, the electrical characteristics of the electronic panel can be improved.

[0281] According to an exemplary embodiment, since the crack sensing portion is formed in the electronic panel, it can be easily determined whether a crack has occurred in the electronic panel. In addition, since the recessed portion is defined in the organic layer disposed under the crack sensing portion, the disconnection of the crack sensing portion caused by a step difference on the organic layer can be prevented.

[0282] While certain exemplary embodiments and examples have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather the scope of the inventive concept is to be accorded the broadest interpretation of the appended claims to encompass all equivalent things and modifications as will be obvious to one of ordinary skill in the art, in light of the foregoing description.

Claims

1. Electronic panel, including: base substrate; a display unit, provided on the base substrate and comprising a plurality of pixels and an encapsulation layer covering the pixels; a sensing unit disposed on the display unit and including a sensing insulating layer, a first conductive pattern, and a second conductive pattern, the first conductive pattern and the second conductive pattern being disposed on different layers from each other and the sensing insulating layer being interposed between the first conductive pattern and the second conductive pattern; a flattening portion provided between the display unit and the sensing unit and including a flat surface, an inclined surface inclined at a predetermined inclination angle from the flat surface, and a recessed portion recessed from the flat surface and the inclined surface; as well as a crack sensing portion, disposed on the sensing insulating layer, spaced apart from the first conductive pattern and the second conductive pattern, and comprising: a crack sensing pattern overlapping the planarized portion; a first connection line connected to one end of the crack sensing pattern and extending in a first direction; and a second connecting line connected to the other end of the crack sensing pattern, spaced apart from the first connecting line, and extending in the first direction; Wherein, at least one of the first connecting line and the second connecting line overlaps with the recessed portion.

2. The electronic panel according to claim 1, wherein: A thickness of the recessed portion measured from an imaginary plane extending from the flat surface increases along the first direction.

3. The electronic panel according to claim 1, wherein: The width of the recessed portion in a direction perpendicular to the first direction increases in a direction toward an upper end of the flattened portion where the flat surface contacts the inclined surface.

4. The electronic panel according to claim 3, wherein: The recessed portion has a polygonal shape when viewed in a plan view.

5. The electronic panel according to claim 3, wherein: The recessed portion has a semicircular shape in a region overlapping with the inclined surface when viewed in a plan view. The electronic panel according to claim 1 , wherein: The inclination angle is equal to or less than 90 degrees.

7. The electronic panel according to claim 1, wherein: At least a portion of the planarized portion contacts the encapsulation layer.

8. The electronic panel according to claim 7, further comprising: a module hole defined to penetrate the display unit, the sensing unit, and the planarization portion, The planarized portion surrounds an edge of the module hole.

9. The electronic panel according to claim 8, wherein: The crack sensing pattern has an open curved shape surrounding at least a portion of the module hole.

10. The electronic panel according to claim 8, wherein: The base substrate further includes a groove recessed from a portion of an upper surface of the base substrate and having a closed line shape.

11. The electronic panel according to claim 1, wherein: At least one of the first connection line and the second connection line is covered by the sensing insulation layer.

12. The electronic panel according to claim 11, wherein: The at least one of the first and second connection lines covered by the sensing insulation layer is connected to the crack sensing pattern via a contact hole defined through the sensing insulation layer.

13. The electronic panel according to claim 1, wherein: The sensing unit includes: a first sensing electrode including a first sensing pattern and a first connecting pattern, the first connecting pattern being disposed on a different layer from the first sensing pattern and connected to the first sensing pattern after penetrating the sensing insulating layer; a second sensing electrode including a second sensing pattern and a second connection pattern connected to the second sensing pattern, the second sensing pattern being disposed on the same layer as the first sensing pattern while being spaced apart from the first sensing pattern; and a dummy pattern portion including a floating pattern disposed on the same layer as the first sensing pattern, spaced apart from the first sensing pattern and the second sensing pattern, and connected to each of the first connection line and the second connection line, The second conductive pattern includes the first connecting pattern, and the first conductive pattern includes the first sensing pattern, the second sensing pattern, the second connecting pattern, and the dummy pattern portion.

14. The electronic panel according to claim 13, wherein: The crack sensing portion includes a crack sensing line disposed on the sensing insulating layer and spaced apart from the first sensing electrode and the second sensing electrode; as well as Each of the floating patterns is connected to a corresponding crack sensing line among the crack sensing lines.

15. Electronic devices, including: an electronic panel having a front surface and a rear surface opposite the front surface and including a module hole defined through the front surface and the rear surface; as well as an electronic module, overlapping with the module hole, The electronic panel comprises: a base substrate having an active area and a peripheral area adjacent to the active area, the active area including an aperture area overlapping the module aperture; a display unit provided on the base substrate and comprising a plurality of pixels arranged in the active area and an encapsulation layer covering the pixels; a sensing unit disposed on the display unit and including a sensing insulating layer, a first conductive pattern, and a second conductive pattern, the first conductive pattern and the second conductive pattern being disposed on different layers from each other and the sensing insulating layer being interposed between the first conductive pattern and the second conductive pattern; a flattening portion provided in the hole region between the display unit and the sensing unit and including a flat surface, an inclined surface inclined at a predetermined inclination angle from the flat surface, and a recessed portion recessed from the flat surface and the inclined surface; and Crack sensing part, including: a crack sensing pattern disposed in the hole region to surround at least a portion of the module hole and overlap with the planarization portion; a first connection line connected to one end of the crack sensing pattern and overlapping a portion of the active area and the hole area; and a second connection line connected to the other end of the crack sensing pattern, spaced apart from the first connection line, and overlapping a portion of the active area and the hole area, Wherein, at least one of the first connecting line and the second connecting line overlaps with the recessed portion.

16. The electronic device according to claim 15, wherein: A thickness of the recessed portion measured from an imaginary plane extending from the flat surface increases along a first direction, and the first connection line extends in the first direction.

17. The electronic device according to claim 16, wherein: The width of the recessed portion in a second direction perpendicular to the first direction increases along the first direction.

18. The electronic device according to claim 15, wherein: The recessed portion has a polygonal shape when viewed in a plan view.

19. The electronic device according to claim 18, wherein: A portion of the recessed portion overlapping the inclined surface has a V-shape or a U-shape when viewed in a plan view.

20. The electronic device according to claim 15, wherein The crack sensing pattern has an open curve shape; and The module hole is defined inside the open curved shape of the crack sensing pattern to penetrate each of the display unit, the sensing unit, and the planarization portion.

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