Semiconductor device

Abstract

A semiconductor device includes: a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. A first gate electrode among the plurality of first gate electrodes and a second gate electrode among the plurality of second gate electrodes are arranged between adjacent insulating layers among the plurality of insulating layers, the first gate electrode and the second gate electrode being spaced apart from each other in the first direction.

Description

TECHNICAL FIELD

[0001] The inventive concept herein relates to a semiconductor device and a method of fabricating a semiconductor device, and more particularly, to a semiconductor device including a channel structure extending in a vertical direction and a method of fabricating such a semiconductor device. BACKGROUND

[0002] As the demand for high integration of memory devices increases, memory devices having a vertical transistor structure in contrast to a general planar transistor structure have been developed. The memory devices having the vertical transistor structure include a channel structure extending in a vertical direction on a substrate. However, as the integration of the memory device increases, the number of gate electrode layers stacked in the vertical direction increases, and thus the difficulty of the fabrication process can increase. SUMMARY

[0003] The inventive concept provides a semiconductor device including a plurality of pairs of gate electrodes having a reduced height in a vertical direction.

[0004] The inventive concept provides a method of fabricating a semiconductor device that prevents collapse or falling of a mold stack during a process of forming a plurality of pairs of gate electrodes having a reduced height in a vertical direction.

[0005] An embodiment of the inventive concept provides a semiconductor device including: a channel structure disposed on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers disposed on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. A first gate electrode among the plurality of first gate electrodes and a second gate electrode among the plurality of second gate electrodes are disposed between adjacent insulating layers among the plurality of insulating layers, the first gate electrode and the second gate electrode being spaced apart from each other in the first direction.

[0006] An embodiment of the inventive concept further provides a semiconductor device including: a channel structure disposed on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers disposed on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of pairs of gate electrodes respectively disposed between adjacent insulating layers among the plurality of insulating layers, each of the plurality of pairs of gate electrodes including a first gate electrode and a second gate electrode spaced apart from each other; and a cap insulating layer structure surrounding the channel structure between the first gate electrode and the second gate electrode of each of the plurality of pairs of gate electrodes, the cap insulating layer structure covering edge portions of the plurality of pairs of gate electrodes.

[0007] Embodiments of the present inventive concept additionally provide a semiconductor device including: a channel structure disposed on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers disposed on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. A first gate electrode among the plurality of first gate electrodes and a second gate electrode among the plurality of second gate electrodes, and an air space between the first gate electrode and the second gate electrode are disposed between adjacent insulating layers among the plurality of insulating layers, the first gate electrode and the second gate electrode being spaced apart from each other in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 An equivalent circuit diagram of a memory cell array of a semiconductor device according to an example embodiment of the present inventive concept is shown;

[0010] Figure 2 A top view of a representative configuration of a semiconductor device according to an example embodiment of the present inventive concept is shown;

[0011] Figure 3 A cross-sectional view taken along line A1-A1' in Figure 2 is shown;

[0012] Figure 4 An enlarged view of a region CX1 in Figure 3 is shown;

[0013] Figure 5 A cross-sectional view of a semiconductor device according to an example embodiment of the present inventive concept is shown;

[0014] Figure 6 An enlarged cross-sectional view of a region CX1 in Figure 5 is shown;

[0015] Figure 7 A cross-sectional view of a semiconductor device according to an example embodiment of the present inventive concept is shown;

[0016] Figure 8 A cross-sectional view of a semiconductor device according to an example embodiment of the present inventive concept is shown;

[0017] Figure 9 A cross-sectional view of a semiconductor device according to an example embodiment of the present inventive concept is shown;

[0018] Figure 10A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention is shown;

[0019] Figure 11 A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention is shown;

[0020] Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 A schematic diagram illustrating a method for manufacturing a semiconductor device in process sequence according to an exemplary embodiment of the present invention is shown; and

[0021] Figure 27 and Figure 28 A schematic diagram of a method for manufacturing a semiconductor device in process sequence according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0022] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 An equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device according to an exemplary embodiment of the present invention is shown. More specifically, Figure 1 An equivalent circuit diagram of a vertical NAND (VNAND) flash memory device with a vertical channel structure is shown.

[0024] Reference Figure 1 The memory cell array (MCA) can be included on a substrate (not shown) along the vertical direction. Figure 1 Multiple memory cell strings MS are arranged in the Z direction. Each of the multiple memory cell strings MS may include multiple memory cells MC1, MC2, ..., MCn-1 and MCn connected in series with each other, at least one string select transistor SST, and a ground select transistor GST. The multiple memory cells MC1, MC2, ..., MCn-1 and MCn can store data, and multiple word lines WL1, WL2, ..., WLn-1 and WLn can be connected to memory cells MC1, MC2, ..., MCn-1 and MCn respectively to control the corresponding memory cells MC1, MC2, ..., MCn-1 and MCn.

[0025] A gate terminal of the ground selection transistor GST of the memory cell string MS can be connected to a ground selection line GSL, and a source terminal of the ground selection transistor GST can be connected to a common source line CSL. A gate terminal of the string selection transistor SST can be connected to a string selection line SSL, and a source terminal of the lowermost string selection transistor SST can be connected to a drain terminal of the memory cell MCn, and a drain terminal of the uppermost string selection transistor SST can be connected to a corresponding bit line among a plurality of bit lines BL (BL1, BL2, …, BLm). Although Figure 1 Although it is exemplarily shown that each memory cell string MS includes one ground selection transistor GST and two string selection transistors SST, unlike this case, a plurality (for example, two or more) of ground selection transistors GST and one or more than three string selection transistors SST can be formed in each memory cell string MS. That is, each memory cell string MS can include one or more ground selection transistors GST and one or more string selection transistors SST.

[0026] When a signal is applied to the gate terminal of the string selection transistor SST via the string selection line SSL, a signal applied via the plurality of bit lines BL can be applied to the plurality of memory cells MC1, MC2, …, MCn-1, and MCn to perform a data write operation. When a signal is applied to the gate terminal of the ground selection transistor GST via the ground selection line GSL, an erase operation of the plurality of memory cells MC1, MC2, …, MCn-1, and MCn can be performed.

[0027] Figure 2 A plan view showing a representative configuration of the semiconductor device 100 according to the example embodiment of the present inventive concept is shown. Figure 3 A cross-sectional view taken along line A1-A1' in Figure 2 A plan view showing a representative configuration of the semiconductor device 100 according to the example embodiment of the present inventive concept is shown. Figure 4 An enlarged view of the region CX1 in Figure 3 An enlarged view of the region CX1 in Figure 2 In the semiconductor device 100, only some components of the semiconductor device 100 are schematically shown for convenience of illustration and understanding.

[0028] Referring to Figures 2 to 4 The substrate 110 can include a memory cell region MCR, a connection region CON, and a peripheral circuit region PERI. The memory cell array MCA can be on the memory cell region MCR, and the memory cell array MCA can be included in a memory cell array having a vertical channel structure as described above with reference to Figure 1The peripheral circuit transistor 190T can be on the peripheral circuit region PERI, and the peripheral circuit transistor 190T can include a peripheral circuit active region 192, a peripheral circuit gate electrode 194 on the peripheral circuit active region 192, and a peripheral circuit contact 196 connected to the peripheral circuit active region 192 and the peripheral circuit gate electrode 194. The connection region CON can be a region in which a pad portion PAD for connecting the memory cell array MCA in the memory cell region MCR to the peripheral circuit transistor 190T is formed.

[0029] The substrate 110 can have a main surface 110M extending in a first direction (X direction) and a second direction (Y direction). The substrate 110 can include a semiconductor material such as, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor can include silicon (Si), germanium (Ge), or silicon germanium. The substrate 110 can be provided as a bulk wafer or an epitaxial layer. In further embodiments, the substrate 110 can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0030] On the memory cell region MCR of the substrate 110, a plurality of insulating layers 120 can extend in the first direction (X direction) and the second direction (Y direction) parallel to the main surface 110M of the substrate 110, and can be separated from each other in a third direction (Z direction) perpendicular to the main surface 110M of the substrate 110.

[0031] Each of the pairs of gate electrodes 130 can be between two adjacent insulating layers 120 among the plurality of insulating layers 120. Each pair of gate electrodes 130 can include a first gate electrode 130X and a second gate electrode 130Y separated from each other in the third direction (Z direction). For example, an insulating layer 120 can be on the main surface 110M of the substrate 110, the first gate electrode 130X and the second gate electrode 130Y (i.e., a pair of gate electrodes 130) can be on the insulating layer 120, and another insulating layer 120 can be on the second gate electrode 130Y. A first top insulating layer 122 can be on the uppermost pair of gate electrodes 130.

[0032] The first gate electrode 130X can include a first conductive barrier layer 132X and a first metal layer 134X, which are sequentially disposed on a top surface of the insulating layer 120 disposed therebelow. The second gate electrode 130Y can include a second conductive barrier layer 132Y and a second metal layer 134Y, which are sequentially disposed on a bottom surface of the insulating layer 120 disposed thereabove. For example, the first conductive barrier layer 132X and the first metal layer 134X can be on a top surface of a lower insulating layer 120 among two adjacent insulating layers 120, and the second conductive barrier layer 132Y and the second metal layer 134Y can be on a bottom surface of an upper insulating layer 120 among the two adjacent insulating layers 120. For example, the first metal layer 134X can face the second metal layer 134Y between the two adjacent insulating layers 120, the first conductive barrier layer 132X can be between the lower insulating layer 120 among the two adjacent insulating layers 120 and the first metal layer 134X, and the second conductive barrier layer 132Y can be between the upper insulating layer 120 among the two adjacent insulating layers 120 and the second metal layer 134Y.

[0033] In an example embodiment, the first conductive barrier layer 132X and the second conductive barrier layer 132Y can include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), or a combination thereof. The first metal layer 134X and the second metal layer 134Y can include, for example, at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), silicides thereof, and alloys thereof.

[0034] In an example embodiment, the first gate electrode 130X can have a first thickness t11 of about 1 nm to about 30 nm in a third direction (Z direction), and the second gate electrode 130Y can have a second thickness t12 of about 1 nm to about 30 nm in the third direction (Z direction). However, the first thickness t11 of the first gate electrode 130X and the second thickness t12 of the second gate electrode 130Y are not limited thereto, respectively.

[0035] In example embodiments, multiple pairs of gate electrodes 130 may correspond to ground select line GSL, word lines WL1, WL2, ..., WLn-1 and WLn, and serial select line SSL. For example, the bottommost first gate electrode 130X may be used as ground select line GSL, the topmost second gate electrode 130Y may be used as serial select line SSL, and the remaining first gate electrodes 130X and the remaining second gate electrodes 130Y may be used as word lines WL1, WL2, ..., WLn-1 and WLn. In some embodiments, the topmost first gate electrode 130X, which is directly disposed below the topmost second gate electrode 130Y, may be used as a dummy word line. In another embodiment, the bottom pair of gate electrodes 130 (e.g., the bottom first gate electrode 130X and the bottom second gate electrode 130Y) can be used as the ground select line GSL, the top pair of gate electrodes 130 (e.g., the top first gate electrode 130X and the top second gate electrode 130Y) can be used as the string select line SSL, and the remaining pairs of gate electrodes 130 can be used as word lines WL1, WL2, ..., WLn-1 and WLn. Therefore, a memory cell string MS can be provided in which the ground select transistor GST, the string select transistor SST, and the memory cells MC1, MC2, ..., MCn-1 and MCn are connected in series.

[0036] like Figure 2 As shown, multiple word line cut regions (WLCs) can extend parallel to the main surface 110M of the substrate 110 in a first direction (X direction). Multiple pairs of gate electrodes 130 between a pair of word line cut regions (WLCs) can form a block, and the pair of word line cut regions (WLCs) can define the width of the multiple pairs of gate electrodes 130 in a second direction (Y direction).

[0037] Multiple channel structures 150 can extend from the main surface 110M of the substrate 110 through multiple pairs of gate electrodes 130 in a vertical direction (Z direction) within the memory cell region MCR. The multiple channel structures 150 can be spaced apart from each other in a first direction (X direction), a second direction (Y direction), and a fourth direction (e.g., a diagonal direction). The multiple channel structures 150 can be in a Z-shaped or staggered shape.

[0038] Each of the plurality of channel structures 150 can be inside a channel hole 150H passing through the plurality of pairs of gate electrodes 130, the insulating layer 120, and the first top insulating layer 122. A gate insulating layer 152 and a channel layer 154 can be sequentially arranged on an inner wall of the channel hole 150H, and a filling insulating layer 156 filling a remaining space of the channel hole 150H can be arranged on the channel layer 154. A conductive plug 158 contacting the channel layer 154 and blocking an entrance of the channel hole 150H can be arranged on a top side of the channel hole 150H. In another embodiment, the filling insulating layer 156 can be omitted, and the channel layer 154 can be formed in a column shape to fill a remaining portion of the channel hole 150H.

[0039] The gate insulating layer 152 can have a structure including a tunneling dielectric layer 152X, a charge storage layer 152Y, and a blocking dielectric layer 152Z sequentially formed on a sidewall of the channel layer 154. In other words, the blocking dielectric layer 152Z, the charge storage layer 152Y, and the tunneling dielectric layer 152X can be sequentially arranged on an inner wall of the channel hole 150H. The relative thicknesses of the tunneling dielectric layer 152X, the charge storage layer 152Y, and the blocking dielectric layer 152Z constituting the gate insulating layer 152 are not limited to the relative thicknesses illustrated, and can be variously modified. Figure 4

[0040] The tunneling dielectric layer 152X can include, for example, silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. The charge storage layer 152Y can be a region in which electrons that have passed through the tunneling dielectric layer 152X from the channel layer 154 are stored, and can include, for example, silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer 152Z can include, for example, silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide can include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0041] The first gate electrode 130X and the second gate electrode 130Y of each pair of gate electrodes 130 can be separated from each other in a third direction (Z direction) by a cap insulating layer structure 140. The cap insulating layer structure 140 can include a first cap insulating layer 142, an air space 144, and a second cap insulating layer 146. The first cap insulating layer 142 can surround a sidewall of the channel structure 150, the second cap insulating layer 146 can cover an edge portion 130XE of the first gate electrode 130X adjacent to the word line cut region WLC and an edge portion 130YE of the second gate electrode 130Y adjacent to the word line cut region WLC. The air space 144 can denote a space limited between the first gate electrode 130X and the second gate electrode 130Y by the first cap insulating layer 142 and the second cap insulating layer 146.

[0042] ​For example, when the first cap insulating layer 142 is formed by using an insulating material having poor step coverage, and then the second cap insulating layer 146 is formed by using an insulating material having poor step coverage, a portion of the space between the first gate electrode 130X and the second gate electrode 130Y can remain unfilled by the first cap insulating layer 142 or the second cap insulating layer 146, and the remaining unfilled space can be referred to as an air space 144.

[0043] The first cap insulating layer 142 can surround the sidewall of the channel structure 150, and the first cap insulating layer 142 can contact the sidewall of the gate insulating layer 152. As Figure 4 illustrated, the first cap insulating layer 142 can include a recess 142R, and a first protrusion 152ZP can be formed in a portion of the sidewall of the gate insulating layer 152 facing the recess 142R (e.g., on a portion of the sidewall of the blocking dielectric layer 152Z). However, the shape and size of the recess 142R or the shape and size of the first protrusion 152ZP are not limited to Figure 4 the shapes and sizes illustrated.

[0044] In some embodiments, at least one of the plurality of first cap insulating layers 142 at different vertical levels can not include a recess 142R, in which case a portion of the gate insulating layer 152 contacting the at least one first cap insulating layer 142 can have a sidewall that extends substantially vertically. In some embodiments, at least one recess 142R of the plurality of first cap insulating layers 142 at different vertical levels can have a greater depth than the remaining recesses 142R of the plurality of first cap insulating layers 142. A first protrusion 152ZP contacting the at least one recess 142R can protrude further outward relative to the first protrusions 152ZP contacting the remaining recesses 142R.

[0045] As Figure 4 illustrated exemplarily, the second cap insulating layer 146 can cover the edge portion 130XE of the first gate electrode 130X and the edge portion 130YE of the second gate electrode 130Y, and in addition, can cover the sidewall 120S of the insulating layer 120 adjacent to the word line cut region WLC. The second cap insulating layer 146 can cover the edge portion of the insulating layer 120 adjacent to the word line cut region WLC. The edge portion 130XE of the first gate electrode 130X can be recessed inward (e.g., toward the channel structure 150) relative to the sidewall 120S of the insulating layer 120 adjacent to the word line cut region WLC. For example, the sidewall of the first conductive barrier layer 132X can be recessed inward relative to the sidewall 120S of the insulating layer 120, and the sidewall of the first metal layer 134X can be recessed inward relative to the sidewall 120S of the insulating layer 120 or the sidewall of the first conductive barrier layer 132X. As Figure 4Exemplarily shown, the second cap insulating layer 146 can include a curved sidewall profile that conforms to sidewalls 120S of the conformal insulating layer 120, sidewalls of the first gate electrode 130X, and sidewalls of the second gate electrode 130Y. In further embodiments, unlike shown in Figure 4

[0046] A separation distance d11 between the first gate electrode 130X and the second gate electrode 130Y can be about 1 nm to about 30 nm, but is not limited thereto. Since the first gate electrode 130X and the second gate electrode 130Y are arranged apart from each other in a space between two adjacent insulating layers 120, the first gate electrode 130X can have a relatively smaller first thickness t11 in the third direction (Z direction), the second gate electrode 130Y can have a relatively smaller second thickness t12 in the third direction (Z direction), and the separation distance d11 between the first gate electrode 130X and the second gate electrode 130Y can also be relatively smaller.

[0047] On the substrate 110, a plurality of common source lines 180 can be arranged in the second direction (Y direction) vertically overlapping the plurality of word line cut regions WLC. Insulating spacers 182 can be on two sidewalls of each of the plurality of common source lines 180. For example, the second cap insulating layer 146 and the insulating spacers 182 can be between pairs of gate electrodes 130 and common source lines 180. The plurality of common source lines 180 are shown in Figure 3

[0048] The plurality of common source regions 112 can be under the common source lines 180 in the substrate 110 and can extend in the first direction (X direction). The plurality of common source regions 112 can be impurity regions including n-type impurities heavily doped thereon. The plurality of common source regions 112 can serve as source regions for supplying current to the plurality of memory cells MC1, MC2, …, MCn-1, and MCn. The plurality of common source regions 112 can vertically overlap the plurality of word line cut regions WLC.

[0049] The second top insulating layer 124 can be on the first top insulating layer 122, and a bit line BL can extend in the second direction (Y direction) on the second top insulating layer 124. A bit line contact BLC can be between the bit line BL and the conductive plug 158, and the second top insulating layer 124 can surround the bit line contact BLC.

[0050] As Figure 2 ​​As shown in the top view, within a block, the uppermost pair of gate electrodes 130 can be divided into two parts by a string separator insulating layer 174. Although not shown, the string separator insulating layer 174 can extend from the same level as the top surface of the first top insulating layer 122 to a level lower than the bottom surface of the uppermost pair of gate electrodes 130.

[0051] In the connection region CON, multiple pairs of gate electrodes 130 may extend to form pad portions PADs. As the vertical distance of the multiple pairs of gate electrodes 130 from the main surface 110M of the substrate 110 increases, the multiple pairs of gate electrodes 130 may extend in the first direction (X direction) to have a shorter length. The pad portion PAD may refer to the stepped portion of the multiple pairs of gate electrodes 130. A second top insulating layer 124 may be disposed above the multiple pairs of gate electrodes 130 including the pad portion PADs, and pad contacts 172 passing through the second top insulating layer 124 and connected to the multiple pairs of gate electrodes 130 may be arranged in the connection region CON.

[0052] like Figure 2 As shown, multiple dummy channel structures D150 can extend from the main surface 110M of the substrate 110 through multiple pairs of gate electrodes 130 and extend along a third direction (Z direction) in the connection region CON. The dummy channel structures D150 can be formed to ensure the structural stability of the semiconductor device 100 during the manufacturing process of the semiconductor device 100. Each of the multiple dummy channel structures D150 can have the same structure as the channel structure 150. When viewed in top view, the multiple dummy channel structures D150 can have a larger dimension (e.g., diameter) than the channel structure 150, but are not limited thereto.

[0053] Generally speaking, as the integration density of semiconductor devices increases, the vertical height of semiconductor devices can increase, and due to the relatively large vertical height of the molded stack of semiconductor devices, defects such as collapse or fall of the molded stack may occur during the process of removing the sacrificial layer used to form the gate electrode.

[0054] However, according to an embodiment of the semiconductor device 100 conceived in accordance with the present invention, as an example, a sacrificial layer 310 has been removed therefrom (see reference). Figure 14 The gate space GS (reference) Figure 15In the space between two adjacent insulating layers 120, a pair of gate electrodes 130, including a first gate electrode 130X and a second gate electrode 130Y separated from each other, can be formed. Therefore, the first gate electrode 130X and the second gate electrode 130Y can each have relatively small thicknesses t11 and t12, respectively, and the separation distance d11 between the first gate electrode 130X and the second gate electrode 130Y can be relatively small. Therefore, the vertical height of the semiconductor device 100 can be relatively reduced, and the occurrence of defects attributable to collapse or falling of the molding stack during the manufacturing process of the semiconductor device 100 can be reduced or prevented.

[0055] Figure 5 A cross-sectional view of a semiconductor device 100A according to an exemplary embodiment of the present invention is shown. Figure 6 It shows Figure 5 An enlarged sectional view of region CX1 in the image. Figure 5 and Figure 6 In, with Figures 1 to 4 Similar reference numerals in the accompanying drawings can represent similar parts, and for the sake of brevity, [the following is a simplified explanation of the reference numerals]. Figure 5 and Figure 6 In and Figures 1 to 4 The description of features similar to those in the data can be omitted from the following content.

[0056] Reference Figure 5 and Figure 6 The semiconductor device 100A may include multiple pairs of gate electrodes 130A, each pair of gate electrodes 130A including recessed regions 130R formed on the sidewalls facing the channel structure 150. Each pair of gate electrodes 130A may include a first gate electrode 130XA and a second gate electrode 130YA separated from each other in the third direction (Z direction). The first gate electrode 130XA may include a first conductive barrier layer 132XA and a first metal layer 134XA, and the second gate electrode 130YA may include a second conductive barrier layer 132YA and a second metal layer 134YA. Furthermore, the first cap insulating layer 142 may include a recess 142R, and the gate insulating layer 152A may include a first protrusion 152ZP and a second protrusion 152YP, the first protrusion 152ZP being on the sidewall portion of the recess 142R contacting the first cap insulating layer 142, and the second protrusion 152YP being on the sidewall portion of the recessed regions 130R contacting the multiple pairs of gate electrodes 130A. The second protrusion 152YP may protrude further outward than the first protrusion 152ZP (e.g., in the direction toward the word line cutting area WLC).

[0057] In the example embodiment, since the gate electrode 130A includes a recessed region 130R, the distance between the gate electrode 130A and the channel layer 154 can be greater than that of the reference layer. Figures 2 to 4The distance between the gate electrode 130 and the channel layer 154 of the semiconductor device 100 described.

[0058] The gate insulating layer 152A may include a tunneling dielectric layer 152XA, a charge storage layer 152YA, and a barrier dielectric layer 152ZA, and portions of the recessed regions 130R of the charge storage layer 152YA and the barrier dielectric layer 152ZA facing the gate electrode 130A may be disposed in the second protrusion 152YP. Since the portion of the recessed region 130R of the charge storage layer 152YA facing the gate electrode 130A is disposed in the second protrusion 152YP, the separation distance from the channel layer 154 to this portion of the charge storage layer 152YA can be relatively large, and therefore, the charge transfer path from the channel layer 154 to this portion of the charge storage layer 152YA can be relatively long. Therefore, data loss caused by the diffusion of charge stored in the charge storage layer 152YA of one memory cell to a portion of the charge storage layer 152YA of an adjacent memory cell (i.e., diffusion in the same direction as the extension direction of the channel layer 154) can be prevented.

[0059] In the manufacturing process according to the example embodiment, the recessed region 130R can be achieved by removing the initial conductive layer 132L (see reference). Figure 27 The portion of the lateral (horizontal) exposed on the inner wall of the channel hole 150HA and the initial metal layer 134L (refer to) Figure 27 The portion of the gate insulating layer 152A exposed in the lateral direction (horizontal direction) at the inner wall of the channel hole 150HA is formed. Next, the gate insulating layer 152A can be formed on the inner wall of the channel hole 150HA, and then the second protrusion 152YP of the gate insulating layer 152A can be formed in the recessed region 130R.

[0060] According to an embodiment of the semiconductor device 100A conceived in accordance with the present invention, as an example, a sacrificial layer 310 has been removed therefrom (see reference). Figure 14 The gate space GS (reference) Figure 15 In the space between two adjacent insulating layers 120, a pair of gate electrodes 130A, including a first gate electrode 130XA and a second gate electrode 130YA separated from each other, can be formed. Therefore, the vertical height of the semiconductor device 100A can be relatively reduced, and defects attributable to collapse or falling during the manufacturing process of the semiconductor device 100A due to molding stacking can be reduced or prevented. Furthermore, because the gate insulating layer 152A includes a second protrusion 152YP, data loss can be prevented, and the reliability of the semiconductor device 100A can be improved.

[0061] Figure 7 A cross-sectional view of a semiconductor device 100B according to an exemplary embodiment of the present invention is shown.Figure 7 In the drawings, Figures 1 to 6 the same reference numbers can indicate the same components, and Figure 7 the description of features similar to those in Figures 1 to 6 may be omitted from the following.

[0062] Referring to Figure 7 , the cap insulating layer structure 140B can be between the first gate electrode 130X and the second gate electrode 130Y, and the cap insulating layer structure 140B can include a cap insulating layer 142B that substantially fills all of the space between the first gate electrode 130X and the second gate electrode 130Y. A top surface of the cap insulating layer 142B can contact a bottom surface of the second metal layer 134Y, and a bottom surface of the cap insulating layer 142B can contact a top surface of the first metal layer 134X. As shown in Figure 7 , sidewalls 142BS of the cap insulating layer 142B adjacent to the word line cut region WLC can be aligned with sidewalls of the first metal layer 134X and the second metal layer 134Y. In further embodiments, the sidewalls 142BS of the cap insulating layer 142B adjacent to the word line cut region WLC can be recessed inward (e.g., in a direction toward the channel structure 150) relative to the sidewalls of the first metal layer 134X and the second metal layer 134Y. In further embodiments, the sidewalls 142BS of the cap insulating layer 142B adjacent to the word line cut region WLC can be protruded outward (e.g., in a direction toward the common source line 180) relative to the sidewalls of the first metal layer 134X and the second metal layer 134Y.

[0063] In example embodiments, the cap insulating layer 142B can include a low-k insulating material. For example, the low-k insulating material can include a fluorosilicate glass (FSG), a carbon-doped silicon oxide (SIOC), a spin-on dielectric (SOD) material, or an ultra-low-k (ULK) material. For example, the cap insulating layer 142B can be formed using a low-k insulating material by an atomic layer deposition process or a chemical vapor deposition process. In further embodiments, the cap insulating layer 142B can include, for example, a silicon oxide, a silicon oxynitride, a silicon nitride, or the like.

[0064] In a process according to example embodiments, the sacrificial layer 310 (referring to Figure 14 ) can be removed through the channel hole 150H, the initial conductive barrier layer 132L (referring to Figure 16 ) and the initial metal layer 134L (referring to Figure 16 ) can be conformally formed on inner walls of the gate space GS (referring to Figure 15 ) in which the sacrificial layer 310 has been removed, and the cap insulating layer 142B can be formed to completely fill the remaining interior of the gate space GS. In this case, the cap insulating layer 142B can be formed to have a top surface that is substantially flush with a top surface of the second metal layer 134Y and a bottom surface that is substantially flush with a bottom surface of the first metal layer 134X.Figure 7 The semiconductor device 100B is described.

[0065] According to the semiconductor device 100B according to the embodiment of the present inventive concept, as an example, a pair of gate electrodes 130 including a first gate electrode 130X and a second gate electrode 130Y separated from each other can be formed in a gate space GS in which the sacrificial layer 310 has been removed, i.e., in a space between two adjacent insulating layers 120. Accordingly, a vertical height of the semiconductor device 100B can be relatively reduced, and occurrence of defects due to collapse or fall of the mold stack during a manufacturing process of the semiconductor device 100B can be reduced or prevented.

[0066] Figure 8 A cross-sectional view of a semiconductor device 100C according to an example embodiment of the present inventive concept is illustrated. In Figure 8 , the same reference numerals are used to refer to the same components, and a description of the components can be omitted from the following description for brevity. Figures 1 to 7 , the same reference numerals are used to refer to the same components, and a description of the components can be omitted from the following description for brevity. Figure 8 , the same reference numerals are used to refer to the same components, and a description of the components can be omitted from the following description for brevity. Figures 1 to 7 , the same reference numerals are used to refer to the same components, and a description of the components can be omitted from the following description for brevity.

[0067] Referring to Figure 8 , the first gate electrode 130XC can include a first metal layer 134XC, and the second gate electrode 130YC can include a second metal layer 134YC. In other words, in the semiconductor device 100C, the first conductive barrier layer 132X and the second conductive barrier layer 132Y included in the semiconductor device 100 described with reference to Figures 2 to 4 may be omitted. A top surface of the first metal layer 134XC can contact the cap insulating layer structure 140, and a bottom surface of the first metal layer 134XC can contact a top surface of the insulating layer 120 therebelow. Further, a top surface of the second metal layer 134YC can contact a bottom surface of the insulating layer 120 thereabove, and a bottom surface of the second metal layer 134YC can contact the cap insulating layer structure 140.

[0068] In an example embodiment, the first metal layer 134XC and the second metal layer 134YC can include any one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), cobalt (Co), tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), silicides thereof, and alloys thereof.

[0069] In a process according to an example embodiment, the sacrificial layer 310 (referring to Figure 14 ) can be removed through the channel hole 150H (referring to Figure 14 ), and the initial metal layer 134L (referring to Figure 16) can be formed conformally on the inner wall of the gate space GS (refer to Figure 15 ) in which the sacrificial layer 310 has been removed. In this case, the pair of gate electrodes 130C including the first gate electrode 130X and the second gate electrode 130Y separated from each other can be formed in the gate space GS in which one of the sacrificial layers 310 has been removed, that is, in the space between two adjacent insulating layers 120. The semiconductor device 100C described above can be manufactured by the following method. Figure 8

[0070] According to the semiconductor device 100C according to the embodiment of the idea of the present application, as an example, the pair of gate electrodes 130C including the first gate electrode 130X and the second gate electrode 130Y separated from each other can be formed in the gate space GS in which one of the sacrificial layers 310 has been removed, that is, in the space between two adjacent insulating layers 120. Therefore, the vertical height of the semiconductor device 100C can be relatively reduced, and the occurrence of defects due to collapse or fall of the mold stack during the manufacturing process of the semiconductor device 100C can be reduced or prevented.

[0071] Figure 9 A cross-sectional view of a semiconductor device 100D according to an example embodiment is shown. In Figure 9 , the same reference numerals as those in Figures 1 to 8 may denote the same components, and for brevity, the description of features similar to those in Figure 9 may be omitted from the following. Figures 1 to 8 With reference to

[0072] , the bottom gate electrode 130D can be between the lowermost two insulating layers 120. The bottom gate electrode 130D can substantially fill the entire space between the lowermost two insulating layers 120, and the bottom gate electrode 130D can have a thickness greater than that of each of the first gate electrode 130X and the second gate electrode 130Y in the pair of gate electrodes 130. Figure 9 The channel structure 150D can include a first gate insulating layer 152D1 on the sidewall of the channel hole 150H, a first channel layer 154D1 on the sidewall of the channel hole 150H, a second channel layer 154D2 at the bottom portion of the channel hole 150H, a second gate insulating layer 152D2 between the sidewall of the second channel layer 154D2 and the bottom gate electrode 130D, a filling insulating layer 156, and a conductive plug 158. The top surface of the second channel layer 154D2 can be at a level higher than that of the top surface of the bottom gate electrode 130D. The second channel layer 154D2 can include a semiconductor layer formed by using a selective epitaxial growth process from the main surface 110M of the substrate 110 exposed at the bottom portion of the channel hole 150H. The second gate insulating layer 152D2 can include silicon oxide formed by a thermal oxidation process, but is not limited thereto. The first gate insulating layer 152D1 and the first channel layer 154D1 can be similar to those described with reference to

[0073] Figures 2 to 4 ​​The gate insulating layer 152 and the channel layer 154 are described.

[0074] Figure 10 A cross-sectional view of a semiconductor device 100E according to an example embodiment of the present inventive concept is shown. In Figure 10 Figures 1 to 9 The same reference numerals are used in the drawings of the Figure 10 Figures 1 to 9 The description of features in the drawings of the

[0075] Referring to Figure 10 , the semiconductor device 100E can further include a first semiconductor layer 162 and a second semiconductor layer 164 sequentially disposed on the main surface 110M of the substrate 110, and a plurality of insulating layers 120 and a plurality of pairs of gate electrodes 130 can be alternately disposed on the second semiconductor layer 164. The first semiconductor layer 162 can include polysilicon doped with impurities or polysilicon not doped with impurities, and the second semiconductor layer 164 can also include polysilicon doped with impurities or polysilicon not doped with impurities. The first semiconductor layer 162 can serve as a common source line extension region and can be a portion corresponding to the common source line CSL in Figure 1 . The second semiconductor layer 164 can serve as a support layer to prevent a mold stack from falling or toppling in a process of removing a sacrificial layer for forming the first semiconductor layer 162.

[0076] The channel structure 150E can pass through the first semiconductor layer 162 and the second semiconductor layer 164 and extend to a level lower than the main surface 110M of the substrate 110. A portion in which the gate insulating layer 152E is split can be formed at a bottom of the channel structure 150E, and in the portion in which the gate insulating layer 152E is split, a sidewall 154W of the channel layer 154E can be surrounded by the first semiconductor layer 162. In addition, a bottom surface of the channel layer 154E can be surrounded by the gate insulating layer 152E and can not contact the substrate 110, but the present inventive concept is not limited thereto.

[0077] Figure 11 A cross-sectional view of a semiconductor device 200 according to an example embodiment of the present inventive concept is shown. In Figure 11 Figures 1 to 10 The same reference numerals are used in the drawings of the Figure 11 Figures 1 to 10 The description of features in the drawings of the

[0078] Referring to Figure 11 ​​​​The bottom substrate 210 can be at a lower vertical level than the substrate 110, in the bottom substrate 210, an active region (not shown) can be defined by an isolation layer 222 in the bottom substrate 210, and on the active region, a plurality of drive transistors 230T can be formed. The plurality of drive transistors 230T can include a drive circuit gate structure 232 and an impurity region 212 in portions of the bottom substrate 210 on both sides of the drive circuit gate structure 232.

[0079] On the bottom substrate 210, a plurality of wiring layers 242, a plurality of contact plugs 246 connecting each of the plurality of wiring layers 242 or between the plurality of wiring layers 242 and the drive transistor 230T, and a bottom interlayer insulating layer 250 covering the plurality of wiring layers 242 and the plurality of contact plugs 246 can be disposed.

[0080] The substrate 110 can be on the bottom interlayer insulating layer 250. On the substrate 110, a plurality of insulating layers 120, a plurality of pairs of gate electrodes 130, a cap insulating layer structure 140, and a channel structure 150 can be disposed.

[0081] Figures 12 to 26 A schematic view of a manufacturing method of a semiconductor device 100 according to an example embodiment of the present inventive concept is shown in accordance with a process sequence. Figures 12 to 26 is a cross-sectional view corresponding to a cross-section along Figure 2 line A1-A1' in Figures 12 to 26 is a cross-sectional view corresponding to a cross-section along Figures 1 to 11 line A1-A1' in The same reference numerals can denote the same components in

[0082] Figure 12 Referring to , a plurality of insulating layers 120 and a plurality of sacrificial layers 310 can be alternately formed on a main surface 110M of the substrate 110. In an example embodiment, the plurality of insulating layers 120 can include an insulating material such as silicon oxide or silicon oxynitride, and the plurality of sacrificial layers 310 can include, for example, silicon nitride, silicon oxynitride, or polysilicon doped with an impurity, etc.

[0083] Next, although not shown, a pad portion PAD (refer to Figure 2 ) can be formed by sequentially patterning the plurality of insulating layers 120 and the plurality of sacrificial layers 310 in the connection region CON. In an example embodiment, the pad portion PAD can be formed to have a stepped shape having a difference in a top surface level in the first direction (X direction) as previously described.

[0084] Next, a first top insulating layer 122 covering the uppermost sacrificial layer 310 and the pad portion PAD can be formed. The first top insulating layer 122 can include an insulating material such as silicon oxide and silicon oxynitride.

[0085] Referring to Figure 13 A mask pattern (not shown) can be formed on the first top insulating layer 122, and the word line cut opening 320H can be formed by etching a portion of the first top insulating layer 122, a portion of the plurality of insulating layers 120, and a portion of the plurality of sacrificial layers 310 using the mask pattern as an etching mask. Subsequently, the word line cut insulating layer 320 can be formed by using an insulating material inside the word line cut opening 320H.

[0086] Referring to Figure 14 The channel hole 150H can be formed by etching a portion of the first top insulating layer 122, a portion of the plurality of insulating layers 120, and a portion of the plurality of sacrificial layers 310. The channel hole 150H can extend to a level lower than the main surface 110M of the substrate 110.

[0087] Referring to Figure 15 The plurality of gate spaces GS can be formed at locations where the plurality of sacrificial layers 310 have been removed, by removing the plurality of sacrificial layers 310 exposed at the sidewalls of the channel hole 150H. The sidewalls of the word line cut insulating layer 320 can be exposed in the plurality of gate spaces GS. In an example embodiment, the removal process of the plurality of sacrificial layers 310 can be a wet etching process using a phosphoric acid solution as an etchant.

[0088] Referring to Figure 16 The initial conductive barrier layer 132L and the initial metal layer 134L can be sequentially formed on the inner walls of the channel hole 150H and the plurality of gate spaces GS. The initial conductive barrier layer 132L and the initial metal layer 134L can be conformally formed on the surfaces of the insulating layers 120 exposed at the inner walls of the channel hole 150H and the plurality of gate spaces GS, on the sidewalls of the word line cut insulating layer 320 exposed in the plurality of gate spaces GS, and on the first top insulating layer 122. The interiors of the channel hole 150H and the plurality of gate spaces GS are not completely filled.

[0089] Referring to Figure 17 The initial first cap insulating layer 142L can be formed on the inner walls of the channel hole 150H. The initial first cap insulating layer 142L can include an insulating material having a poor step coverage characteristic, and can fill a portion of the plurality of gate spaces GS communicating with the channel hole 150H. Accordingly, a portion of the plurality of gate spaces GS relatively far from the channel hole 150H can not be filled with the initial first cap insulating layer 142L, but can remain empty.

[0090] Referring to Figure 18The portion of the initial first cap insulating layer 142L disposed on (or over) the first top insulating layer 122 and on the inner wall of the channel hole 150H can be removed, and a plurality of first cap insulating layers 142 can be formed in the plurality of gate spaces GS. Accordingly, the initial metal layer 134L can be exposed again on the sidewall and the bottom portion of the channel hole 150H. In an example embodiment, the process for removing the portion of the initial first cap insulating layer 142L can be a wet etching process. In some embodiments, after the wet etching process, the plurality of first cap insulating layers 142 can include a recess 142R that is recessed inwardly with respect to the portion of the initial metal layer 134L on the sidewall of the channel hole 150H.

[0091] Referring to Figure 19 The portion of the initial metal layer 134L and the initial conductive barrier layer 132L on the inner wall of the channel hole 150H can be removed, and thus, the plurality of insulating layers 120 can be exposed on the inner wall of the channel hole 150H.

[0092] In an example embodiment, by performing a first wet etching process using a first etchant capable of removing the initial metal layer 134L, the portion of the initial metal layer 134L on the inner wall of the channel hole 150H can be first removed to expose the surface of the initial conductive barrier layer 132L. Next, by performing a second wet etching process using a second etchant capable of removing the initial conductive barrier layer 132L, the portion of the initial conductive barrier layer 132L on the inner wall of the channel hole 150H can be removed. However, the removal process of the portion of the initial conductive barrier layer 132L and the portion of the initial metal layer 134L is not limited to the above-described etching process.

[0093] For example, the portion of the initial conductive barrier layer 132L and the portion of the initial metal layer 134L covering the sidewall 120S of the insulating layer 120 on the inner wall of the channel hole 150H can be removed by a wet etching process, and the sidewall 120S of the insulating layer 120 can be exposed. In addition, the portion of the initial conductive barrier layer 132L and the portion of the initial metal layer 134L on the first top insulating layer 122 can be removed together, and the top surface of the first top insulating layer 122 can be exposed again.

[0094] Referring to Figure 20The blocking dielectric layer 152Z, the charge storage layer 152Y, and the tunneling dielectric layer 152X can be sequentially formed on the inner wall of the channel hole 150H to form the gate insulating layer 152. The gate insulating layer 152 can contact the sidewall of the first cap insulating layer 142 on the inner wall of the channel hole 150H, for example, the first protrusion 152ZP conforming to the shape of the recess 142R can be formed in the portion of the gate insulating layer 152 that contacts the recess 142R of the first cap insulating layer 142. However, the shape and size of the recess 142R and the first protrusion 152ZP are not limited to the shapes and sizes shown. Figure 20

[0095] Referring to Figure 21 , by performing an anisotropic etching process or a back-etching process on the gate insulating layer 152, the portion of the gate insulating layer 152 covering the bottom portion of the channel hole 150H can be removed. By the anisotropic etching process or the back-etching process, the portion of the substrate 110 exposed at the bottom portion of the channel hole 150H can be further removed to a certain depth.

[0096] Next, the channel layer 154 can be conformally formed on the inner wall of the channel hole 150H. The fill insulating layer 156 filling the remaining portion of the channel hole 150H can be formed by using an insulating material on the channel layer 154. By removing the portion of the channel layer 154 disposed in the top portion of the channel hole 150H and the portion of the fill insulating layer 156 disposed in the top portion of the channel hole 150H (and the portion of the gate insulating layer 152 disposed in the top portion of the channel hole 150H) via a back-etching process, and by filling the removed portion of the top portion of the channel hole 150H with a conductive material, the conductive plug 158 can be formed.

[0097] Referring to Figure 22 , a mask pattern (not shown) can be formed on the first top insulating layer 122 and the word line cut insulating layer 320 (refer to Figure 21 ), and a portion of the word line cut insulating layer 320 can be removed by using the mask pattern as an etching mask to form the word line cut opening 320HA. Next, by performing a wet etching process, the remaining portion of the word line cut insulating layer 320, the first top insulating layer 122, and the plurality of insulating layers 120 can be further removed by a certain thickness. The word line cut opening 320HA can be further extended laterally by the wet etching process, and the sidewall 120S of the insulating layer 120 can be recessed inwardly (e.g., in a direction toward the channel structure 150) relative to the sidewall of the initial conductive barrier layer 132L.

[0098] Referring to Figure 23 ​The portions of the initial metal layer 134L and the initial conductive barrier layer 132L on the inner wall of the word line cut opening 320HA can be removed, and thus, the plurality of gate spaces GS can be in communication with the word line cut opening 320HA and exposed at the word line cut opening 320HA.

[0099] In an example embodiment, by performing a third wet etching process using a third etchant capable of removing the initial conductive barrier layer 132L, the portions of the initial conductive barrier layer 132L on the inner wall of the word line cut opening 320HA can be removed first to expose the surface of the initial metal layer 134L. Next, by performing a fourth wet etching process using a fourth etchant capable of removing the initial metal layer 134L, the portions of the initial metal layer 134L on the inner wall of the word line cut opening 320HA can be removed. As a result, the portions of the initial conductive barrier layer 132L and the initial metal layer 134L on the inner wall of the word line cut opening 320HA around the gate space GS can be removed, and thus, the gate space GS can be in communication with or connected to the word line cut opening 320HA. However, the removal process of the portions of the initial conductive barrier layer 132L and the initial metal layer 134L is not limited to the above-described etching process.

[0100] For example, a portion of the initial metal layer 134L and a portion of the initial conductive barrier layer 132L, which extend in the vertical direction (Z direction) and are disposed on the sidewall of the word line cut insulation layer 320 (refer to FIG. 4A) among the initial metal layer 134L and the initial conductive barrier layer 132L can be removed, and thus, only the portions of the initial metal layer 134L and the initial conductive barrier layer 132L disposed on the top and bottom surfaces of the insulation layer 120 can remain. At the upper portion of one gate space GS, the initial metal layer 134L can be at a lower level than the initial conductive barrier layer 132L, and at the lower portion of one gate space GS, the initial metal layer 134L can be at a higher level than the initial conductive barrier layer 132L. Figure 21

[0101] ​For example, a portion of the initial conductive barrier layer 132L remaining on a top surface of a lower insulating layer 120 among two adjacent insulating layers 120 can be referred to as a first conductive barrier layer 132X, a portion of the initial metal layer 134L remaining on a top surface of the first conductive barrier layer 132X over the top surface of the lower insulating layer 120 can be referred to as a first metal layer 134X, a portion of the initial conductive barrier layer 132L remaining on a bottom surface of an upper insulating layer 120 among the two adjacent insulating layers 120 can be referred to as a second conductive barrier layer 132Y, and a portion of the initial metal layer 134L remaining on a bottom surface of the second conductive barrier layer 132Y under the bottom surface of the upper insulating layer 120 can be referred to as a second metal layer 134Y. Here, in one gate space GS between the two adjacent insulating layers 120, a first gate electrode 130X including the first conductive barrier layer 132X and the first metal layer 134X and a second gate electrode 130Y including the second conductive barrier layer 132Y and the second metal layer 134Y can be formed. Accordingly, the first gate electrode 130X and the second gate electrode 130Y can have a shape that is mirror-symmetrical with respect to each other based on an axis extending in a horizontal direction through a center of the gate space GS. In the memory cell region MCR, the first gate electrode 130X and the second gate electrode 130Y can be separated from each other in a vertical direction (Z direction).

[0102] Referring to Figure 24 The second cap insulating layer 146 can be formed on a top surface of the first top insulating layer 122 and on inner walls of the word line cut opening 320HA. The second cap insulating layer 146 can be formed by using an insulating material having a poor step coverage characteristic, and the second cap insulating layer 146 can fill a portion of the plurality of gate spaces GS that are communicated or connected with the word line cut opening 320HA. A certain region of the plurality of gate spaces GS that is relatively far from the word line cut opening 320HA can remain empty without being filled with the second cap insulating layer 146, and this empty region can be referred to as an air space 144. The air space 144 can denote a space defined between the first gate electrode 130X and the second gate electrode 130Y in a vertical direction (Z direction) and between the first cap insulating layer 142 and the second cap insulating layer 146 in a horizontal direction (X direction or Y direction). The shape and size of the air space 144 are not limited to those shown in the drawings. Here, the first cap insulating layer 142, the air space 144, and the second cap insulating layer 146 can be referred to as a cap insulating layer structure 140. Figure 24

[0103] Referring to Figure 25 ​The insulating spacer 182 can be formed on inner walls of the word line cut opening 320HA. In an example embodiment, the insulating spacer 182 can be formed to completely fill the word line cut opening 320HA on the second cap insulating layer 146. In another embodiment, unlike as shown, the insulating spacer 182 can be formed to have a relatively small thickness on the second cap insulating layer 146, and a portion of the word line cut opening 320HA can not be filled with the insulating spacer 182. Figure 25

[0104] Referring to Figure 26 , a mask pattern (not shown) can be formed on the insulating spacer 182, and a portion of the insulating spacer 182 can be removed by using the mask pattern as an etching mask to expose the main surface 110M of the substrate 110. By implanting impurities into the exposed substrate 110, the common source region 112 can be formed in a portion of the substrate 110 under the insulating spacer 182. Next, the common source line 180 can be formed by using a conductive material in the portion in which the insulating spacer 182 has been removed.

[0105] Referring again to Figure 3 , the second top insulating layer 124 can be formed on the first top insulating layer 122, and a bit line contact BLC electrically contacting the channel structure 150 via the conductive plug 158 can be further formed through the second top insulating layer 124. Next, a bit line BL connected to the bit line contact BLC and extending in the second direction (Y direction) can be further formed on the second top insulating layer 124.

[0106] The semiconductor device 100 can be completed by performing the above-described processes.

[0107] According to the manufacturing method of the above-described semiconductor device 100, the sacrificial layer 310 exposed by the channel hole 150H can be removed, and then the initial conductive barrier layer 132L and the initial metal layer 134L can be formed in the gate space GS from which the sacrificial layer 310 has been removed, a portion of the initial conductive barrier layer 132L and the initial metal layer 134L (i.e., a portion of the initial conductive barrier layer 132L and the initial metal layer 134L extending in the vertical direction) can be removed by using the channel hole 150H, and thereafter, another portion of the initial conductive barrier layer 132L and the initial metal layer 134L (i.e., a portion of the initial conductive barrier layer 132L and the initial metal layer 134L extending in the vertical direction) can be removed by using the word line cut opening 320HA. Thus, in the gate space GS in which one sacrificial layer 310 has been removed, i.e., in the space between two adjacent insulating layers 120, a pair of gate electrodes 130 including a first gate electrode 130X and a second gate electrode 130Y separated from each other can be formed.

[0108] ​Accordingly, the first gate electrode 130X and the second gate electrode 130Y can have relatively small thicknesses t11 and t12, respectively (refer to Figure 4 ), and a separation distance d11 between the first gate electrode 130X and the second gate electrode 130Y (refer to Figure 4 ) can be relatively small. Accordingly, a vertical height of the semiconductor device 100 can be relatively reduced, and occurrence of a defect due to collapse or fall of the mold stack during a manufacturing process of the semiconductor device 100 (e.g., during a removal process of the sacrificial layer 310) can be reduced or prevented.

[0109] Figure 27 and Figure 28 FIG. 1 illustrates a schematic diagram of a manufacturing method of a semiconductor device 100A according to an example embodiment of the present inventive concept.

[0110] First, a plurality of first cap insulating layers 142 can be formed in the plurality of gate spaces GS by performing a process described with reference to Figures 12 to 19 , and the plurality of insulating layers 120 can be exposed at inner walls of the channel holes 150HA.

[0111] With reference to Figure 27 , the initial conductive barrier layer 132L and the initial metal layer 134L exposed at the inner walls of the channel holes 150HA can be further etched in the lateral direction by performing a wet etching process. Accordingly, the sidewalls of the initial conductive barrier layer 132L and the sidewalls of the initial metal layer 134L can be recessed inward (e.g., in a direction toward the word line cut insulating layer 320) with respect to the sidewalls 120S of the plurality of insulating layers 120, and a recessed region 130R can be formed in a space in which the initial conductive barrier layer 132L and the initial metal layer 134L have been removed. In addition, the sidewalls of the initial conductive barrier layer 132L and the sidewalls of the initial metal layer 134L can be recessed inward (e.g., in a direction toward the word line cut insulating layer 320) with respect to the sidewalls of the first cap insulating layers 142.

[0112] In an example embodiment, by performing a first wet etching process using a first etchant capable of removing the initial metal layer 134L, a portion of the initial metal layer 134L on the inner walls of the channel holes 150HA can be first etched in the lateral direction, and then, by performing a second wet etching process using a second etchant capable of removing the initial conductive barrier layer 132L, a portion of the initial conductive barrier layer 132L on the inner walls of the channel holes 150HA can be removed in the lateral direction. However, the etching processes of the initial conductive barrier layer 132L and the initial metal layer 134L in the lateral direction are not limited to the above example.

[0113] With reference to Figure 28The barrier dielectric layer 152ZA, the charge storage layer 152YA, and the tunneling dielectric layer 152XA can be sequentially formed on the inner wall of the channel hole 150HA to form the gate insulating layer 152A. The gate insulating layer 152A can contact the side wall of the first cap insulating layer 142 on the inner wall of the channel hole 150H, and for example, a first protrusion 152ZP conforming to the shape of the recess 142R can be formed in a portion of the gate insulating layer 152A that contacts the recess 142R of the first cap insulating layer 142. Also, the gate insulating layer 152A can contact the side wall of the initial conductive barrier layer 132L and the initial metal layer 134L on the inner wall of the channel hole 150HA, and for example, a second protrusion 152YP conforming to the shape of the recessed region 130R can be formed in a portion of the gate insulating layer 152A that contacts the recessed region 130R of the initial conductive barrier layer 132L and the initial metal layer 134L. However, the shapes and sizes of the first protrusion 152ZP and the second protrusion 152YP are not limited to those shown in the drawings. Figure 28

[0114] Thereafter, the semiconductor device 100A can be completed by performing the processes described with reference to FIGS. 1A to 1E. Figures 21 to 26

[0115] According to the method of manufacturing the semiconductor device 100A according to the above-described example embodiment, occurrence of defects due to collapse or falling of the mold stack in the manufacturing processes of the semiconductor device 100A can be reduced or prevented. Also, because the gate insulating layer 152A includes the second protrusion 152YP, data loss can be prevented, and reliability of the semiconductor device 100A can be improved.

[0116] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

[0117] This application claims priority to Korean Patent Application No. 10-2019-0075225, filed on June 24, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.​​

Claims

1. A semiconductor device comprising: a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; a plurality of second gate electrodes surrounding the channel structure; and a cap insulating layer structure provided between the first gate electrodes and the second gate electrodes, wherein a first gate electrode among the plurality of first gate electrodes and a second gate electrode among the plurality of second gate electrodes are arranged between adjacent insulating layers among the plurality of insulating layers, the first gate electrode among the plurality of first gate electrodes and the second gate electrode among the plurality of second gate electrodes being spaced apart from each other along the first direction, wherein the first gate electrode includes a first metal layer arranged on a top surface of a lower insulating layer among the adjacent insulating layers, wherein the cap insulating layer structure includes a bottom surface contacting a top surface of the first metal layer. the cap insulating layer structure includes an air space, 2. The semiconductor device of claim 1, wherein, wherein the first gate electrode, a portion of the cap insulating layer structure, and the second gate electrode are sequentially arranged in the first direction.

3. The semiconductor device of claim 2, wherein the cap insulating layer structure includes: a first cap insulating layer surrounding portions of sidewalls of the channel structure between the first gate electrodes and the second gate electrodes; a second cap insulating layer arranged to surround edge portions of the first gate electrodes and the second gate electrodes and arranged between the first gate electrodes and the second gate electrodes, the edge portions of the first gate electrodes and the second gate electrodes both being adjacent to word line cut regions; and the air space is provided between the first cap insulating layer and the second cap insulating layer.

4. The semiconductor device of claim 3, wherein the first gate electrode further includes a first conductive barrier layer arranged between the top surface of the lower insulating layer among the adjacent insulating layers and the first metal layer, and the second gate electrode includes a second conductive barrier layer and a second metal layer sequentially arranged on a bottom surface of an upper insulating layer among the adjacent insulating layers.

5. The semiconductor device of claim 4, wherein the first metal layer contacts the first cap insulating layer and the second cap insulating layer, and wherein the first conductive barrier layer does not contact the first cap insulating layer. the first metal layer is directly arranged on the top surface of the lower insulating layer among the adjacent insulating layers, the second gate electrode includes a second metal layer that is directly arranged on a bottom surface of an upper insulating layer among the adjacent insulating layers, and 6. The semiconductor device of claim 3, wherein, a portion of the second cap insulating layer, the first cap insulating layer, and the air space are arranged between the first metal layer and the second metal layer. ​ ​ 7. The semiconductor device of claim 3, wherein the gate insulating layer surrounds an outer wall of the channel layer and extends in the first direction, and the gate insulating layer includes a sidewall and a plurality of first protrusions formed on the sidewall of the gate insulating layer and protruding outward.

8. The semiconductor device of claim 7, wherein the plurality of first protrusions protrude outward to be surrounded by the first cap insulating layer disposed between a respective pair of the adjacent insulating layers.

9. The semiconductor device of claim 7, wherein the gate insulating layer includes a plurality of second protrusions formed on the sidewall of the gate insulating layer and protruding outward, and wherein each of the plurality of second protrusions protrudes outward to be surrounded by a first gate electrode or a second gate electrode.

10. The semiconductor device of claim 9, wherein the gate insulating layer includes a charge storage layer, and the charge storage layer has a portion disposed within the plurality of second protrusions.

11. The semiconductor device of claim 1, wherein the first gate electrode further includes a first conductive barrier layer disposed between the top surface of the lower insulating layer among the adjacent insulating layers and the first metal layer, and the second gate electrode includes a second conductive barrier layer and a second metal layer sequentially disposed on a bottom surface of an upper insulating layer among the adjacent insulating layers, the cap insulating layer structure is a cap insulating layer having a sidewall that is inwardly recessed with respect to a sidewall of the plurality of insulating layers.

12. The semiconductor device of claim 11, wherein the cap insulating layer fills a space between a first gate electrode among the plurality of first gate electrodes and a second gate electrode among the plurality of second gate electrodes of each pair of the plurality of gate electrodes, wherein the cap insulating layer includes a top surface that respectively contacts a bottom surface of a second metal layer among the plurality of second gate electrodes and a bottom surface that respectively contacts a top surface of a first metal layer among the plurality of first gate electrodes, and the cap insulating layer includes a low-k insulating material.

13. A semiconductor device, comprising: a channel structure disposed on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers disposed on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of pairs of gate electrodes respectively disposed between adjacent insulating layers among the plurality of insulating layers, each pair of the plurality of pairs of gate electrodes including a first gate electrode and a second gate electrode spaced apart from each other; and a cap insulating layer structure surrounding the channel structure between the first gate electrode and the second gate electrode of each pair of the plurality of pairs of gate electrodes, the cap insulating layer structure covering edge portions of the plurality of pairs of gate electrodes, wherein the first gate electrode includes a first metal layer disposed on a top surface of a lower insulating layer among the adjacent insulating layers, wherein the cap insulating layer structure includes a bottom surface that contacts a top surface of the first metal layer.

14. The semiconductor device of claim 13, wherein a first gate electrode among the plurality of pairs of gate electrodes, a cap insulating layer structure among the cap insulating layer structures, and a second gate electrode among the plurality of pairs of gate electrodes are sequentially arranged in the first direction between each pair of the adjacent insulating layers.

15. The semiconductor device of claim 13, wherein the first gate electrode further includes a first conductive barrier layer arranged between the top surface of the lower insulating layer among the adjacent insulating layers and the first metal layer, and the second gate electrode includes a second conductive barrier layer and a second metal layer sequentially arranged on a bottom surface of an upper insulating layer among the adjacent insulating layers.

16. The semiconductor device of claim 13, wherein the cap insulating layer structure includes: a first cap insulating layer surrounding a portion of a sidewall of the channel structure between the first gate electrode and the second gate electrode of each of the plurality of pairs of gate electrodes; a second cap insulating layer arranged to surround an edge portion of the first gate electrode among the plurality of pairs of gate electrodes and an edge portion of the second gate electrode among the plurality of pairs of gate electrodes, the edge portion of the first gate electrode and the edge portion of the second gate electrode both being adjacent to a word line cut region; and an air space provided between the first cap insulating layer and the second cap insulating layer.

17. The semiconductor device of claim 16, wherein the second cap insulating layer covers edge portions of the adjacent insulating layers adjacent to the word line cut region.

18. A semiconductor device comprising: a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers being spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; a plurality of second gate electrodes surrounding the channel structure; and a cap insulating layer structure provided between the first gate electrodes and the second gate electrodes, wherein a first gate electrode among the plurality of first gate electrodes and a second gate electrode among the plurality of second gate electrodes are arranged between adjacent insulating layers among the plurality of insulating layers, the first gate electrode among the plurality of first gate electrodes and the second gate electrode among the plurality of second gate electrodes being spaced apart from each other in the first direction, the cap insulating layer structure including: a first cap insulating layer surrounding a portion of a sidewall of the channel structure between the first gate electrode and the second gate electrode; a second cap insulating layer arranged to surround an edge portion of the first gate electrode and an edge portion of the second gate electrode, the edge portion of the first gate electrode and the edge portion of the second gate electrode both being adjacent to a word line cut region; and an air space provided between the first cap insulating layer and the second cap insulating layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ the first gate electrode includes a first conductive barrier layer and a first metal layer sequentially arranged on a top surface of a lower insulating layer among the adjacent insulating layers, and wherein the first metal layer contacts the first cap insulating layer and the second cap insulating layer, and wherein the first conductive barrier layer does not contact the first cap insulating layer.

19. The semiconductor device of claim 18, wherein a sidewall of the first gate electrode adjacent to the word line cut region is recessed inward relative to a sidewall of the plurality of insulating layers adjacent to the word line cut region, and a sidewall of the second gate electrode adjacent to the word line cut region is recessed inward relative to the sidewall of the plurality of insulating layers.

Images