Capacitor and method for forming same, storage unit and memory

Abstract

A capacitor and a method for forming the same, a storage unit and a memory, wherein the capacitor comprises: a lower electrode; an upper electrode; a capacitor dielectric layer located between the lower electrode and the upper electrode, wherein the capacitor dielectric layer comprises a main dielectric layer and a sacrificial layer located between the main dielectric layer and the upper electrode. The performance of the capacitor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a capacitor and a method for forming the same, a storage unit and a memory. Background Art

[0002] Capacitors are important devices in semiconductor integrated circuits, and their performance has a significant impact on semiconductor integrated circuits. With the miniaturization of size, the use of high dielectric constant materials to replace traditional SiO2 materials as dielectric layers can not only maintain sufficient driving current, but also increase the actual physical thickness of the dielectric layer while maintaining the same equivalent oxide thickness (EOT), which can effectively suppress the quantum tunneling effect.

[0003] As a charge storage device in memory, capacitors have higher requirements for high capacitance and low leakage current. As the size of memory continues to shrink, existing high dielectric constant materials, such as ZrO x 、AlO x etc., as well as the existing stacking methods of high dielectric constant materials, such as ZrO x -AlO x -ZrO x , which can no longer meet the current memory requirements for high capacitance and low leakage current.

[0004] How to further increase the capacitance value while reducing the leakage current is a problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a capacitor and a method for forming the same, a storage unit and a memory, which can reduce leakage current on the basis of forming a high capacitance value.

[0006] In order to solve the above problems, the present invention provides a capacitor, comprising: a lower electrode; an upper electrode; a capacitor dielectric layer located between the lower electrode and the upper electrode, the capacitor dielectric layer comprising a main dielectric layer and a sacrificial layer located between the main dielectric layer and the upper electrode.

[0007] Optionally, the capacitor dielectric layer further includes a leakage current blocking layer located between the main dielectric layer and the upper electrode.

[0008] Optionally, the material of the sacrificial layer is an oxygen-containing high-K dielectric material.

[0009] Optionally, the material of the sacrificial layer includes at least one of zirconium oxide, titanium oxide, lanthanum oxide, hafnium oxide and tantalum oxide.

[0010] Optionally, the bandgap width of the material of the leakage current blocking layer is greater than or equal to the bandgap width of the material of the main dielectric layer.

[0011] Optionally, the material of the leakage current blocking layer includes at least one of aluminum oxide, magnesium oxide and silicon dioxide.

[0012] Optionally, the sacrificial layer is located between the leakage current blocking layer and the upper electrode.

[0013] Optionally, the thickness of the sacrificial layer is less than 1 nm, and the thickness of the leakage current blocking layer is less than 1 nm.

[0014] Optionally, the main dielectric layer includes a zirconium oxide layer, an aluminum oxide layer and a zirconium oxide layer stacked in sequence.

[0015] The technical solution of the present invention also provides a method for forming a capacitor, comprising: forming a lower electrode; forming a capacitor dielectric layer on the surface of the lower electrode, the capacitor dielectric layer comprising a main dielectric layer located on the surface of the lower electrode and a sacrificial layer located on the surface of the main dielectric layer; and forming an upper electrode on the surface of the capacitor dielectric layer.

[0016] Optionally, forming a capacitor dielectric layer on the surface of the lower electrode includes: forming a capacitor dielectric layer on the surface of the lower electrode by adopting a chemical vapor deposition process or an atomic layer deposition process.

[0017] Optionally, forming a capacitor dielectric layer on the surface of the lower electrode includes: forming a leakage current blocking layer on the surface of the main dielectric layer; and forming the sacrificial layer on the surface of the leakage current blocking layer.

[0018] Optionally, the bandgap width of the material of the leakage current blocking layer is greater than or equal to the bandgap width of the material of the main dielectric layer.

[0019] Optionally, the main dielectric layer includes a zirconium oxide layer, an aluminum oxide layer and a zirconium oxide layer stacked in sequence; the material of the leakage current blocking layer includes at least one of aluminum oxide, magnesium oxide and silicon dioxide; and the material of the sacrificial layer is an oxygen-containing high-k dielectric material.

[0020] The technical solution of the present invention also includes a storage unit, including: a capacitor as described in any one of the above items.

[0021] Optionally, it also includes: a substrate, in which a transistor having a source region and a drain region is formed, and in which an electrical contact portion connected to the source region or the drain region is also formed, the substrate exposes a surface of the electrical contact portion, and the lower electrode of the capacitor is connected to the source region or the drain region through the electrical contact portion.

[0022] Optionally, the longitudinal section of the lower electrode is U-shaped, and the U-shaped bottom of the lower electrode is in contact with the electrical contact portion.

[0023] The technical solution of the present invention further provides a memory, comprising: a storage array formed by a plurality of the above-mentioned storage units.

[0024] Optionally, the memory includes DRAM.

[0025] The capacitor dielectric layer of the capacitor of the present invention includes a sacrificial layer located between the main dielectric layer and the upper electrode, which can replace the main dielectric layer to be attacked by active ions, thereby protecting the main dielectric layer from the influence of active ions, thereby reducing leakage current and improving the capacitance value of the capacitor; and the capacitor also includes a leakage current blocking layer located between the main dielectric layer and the upper electrode, thereby blocking the leakage current channel between the upper electrode of the capacitor and the main dielectric layer, reducing the leakage current of the capacitor, so that the performance of the DRAM unit and memory having the above capacitor is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 3 A schematic diagram of the formation structure of a capacitor according to a specific embodiment of the present invention;

[0027] Figure 4 It is a structural schematic diagram of a capacitor according to another specific embodiment of the present invention;

[0028] FIG. 5A to FIG. 7 It is a structural schematic diagram of the formation process of a capacitor of the present invention. DETAILED DESCRIPTION

[0029] The specific implementation methods of the capacitor and its formation method, storage unit and memory provided by the present invention are described in detail below with reference to the accompanying drawings.

[0030] Please refer to Figures 1 to 3 , which is a structural schematic diagram of the formation process of a capacitor according to a specific embodiment of the present invention.

[0031] Please refer to Figure 1 , forming a lower electrode 101.

[0032] The lower electrode 101 is made of a conductive material, such as polysilicon, and may also include but not limited to metal materials such as Ti, Co, TiN, TiW, W, TiAl, TiAlN, and combinations thereof. When the capacitor is applied to DRAM (Dynamic Random Access Memory), the lower electrode 101 is preferably made of a metal material. In this specific embodiment, the material of the lower electrode 101 is TiN.

[0033] Please refer to Figure 2A capacitor dielectric layer 102 is formed on the surface of the lower electrode 101, and the capacitor dielectric layer 102 includes a main dielectric layer 1021 located on the surface of the lower electrode 101, a leakage current blocking layer 1022 located on the surface of the main dielectric layer 1021, and a sacrificial layer 1023 located on the surface of the leakage current blocking layer 1022.

[0034] The capacitor dielectric layer may be formed by chemical vapor deposition or atomic layer deposition, including sequentially forming the main dielectric layer 1021 , the leakage current blocking layer 1022 , and the sacrificial layer 1023 .

[0035] The thickness of the main dielectric layer 1021 is much greater than the thickness of the leakage current blocking layer 1022 and the sacrificial layer 1023, and determines the capacitance value of the entire capacitor. In some specific embodiments, the thickness of the main dielectric layer 1021 can be 3nm~10nm. The main dielectric layer 1021 usually uses a material with a higher dielectric constant, such as at least one of high-K dielectric materials such as zirconium oxide, aluminum oxide, and hafnium oxide. In this specific embodiment, the main dielectric layer 1021 includes a zirconium oxide layer 1021a, an aluminum oxide layer 1021b, and a zirconium oxide layer 1021c stacked in sequence, wherein the K value of the zirconium oxide layer 1021a and 1021c is high but the leakage rate is also high, and the K value of the aluminum oxide layer 1021b is low, but the leakage rate is low, so the main dielectric layer 1021 with a stacked structure can obtain a high K value and reduce the leakage rate. In other specific embodiments, the main dielectric layer 1021 can also use other dielectric materials. The zirconium oxide layer 1021a, the aluminum oxide layer 1021b and the zirconium oxide layer 1021c can be formed in sequence by chemical vapor deposition process. Considering the influence of the heat treatment process on the crystallization performance of the material, the thickness of the zirconium oxide layer 1021a close to the lower electrode 101 is usually larger. The crystallization performance of the zirconium oxide layer is different with different thicknesses, and the crystallization performance will affect the K value and the leakage rate. Therefore, the thickness of the zirconium oxide layers 1021a and 1021c can be reasonably adjusted to maximize the K value and reduce the leakage rate. In some specific embodiments, the thickness of the zirconium oxide layer 1021a can be 2nm~5nm, the thickness of the aluminum oxide layer 1021b can be less than 1nm, and the thickness of the zirconium oxide layer 1021c can be 1nm~4nm. The thickness of the leakage current blocking layer 1022 and the sacrificial layer 1023 can be less than 1nm.

[0036] The leakage current blocking layer 1022 is made of a material with a high bandgap width, so that free carriers are not likely to appear between the upper electrode 103 and the main dielectric layer 1021, thereby blocking the leakage current channel between the upper electrode 103 of the capacitor and the main dielectric layer 1021, and reducing the leakage current of the capacitor. Preferably, the bandgap width of the material of the leakage current blocking layer 1022 is greater than or equal to the bandgap width of the material of the main dielectric layer 1021.

[0037] In this specific embodiment, the material of the leakage current blocking layer 1022 is aluminum oxide. In other specific embodiments, the material of the leakage current blocking layer 1022 may also be at least one of aluminum oxide, magnesium oxide and silicon dioxide. The leakage current blocking layer 1022 may be a single-layer structure or a stacked structure composed of two or more layers of different materials.

[0038] The blocking effect of the leakage current blocking layer 1022 on the leakage current is independent of the thickness. In order to still be able to control the capacitance value of the capacitor through the main dielectric layer 1021 and avoid the leakage current blocking layer 1022 having a significant impact on the capacitance value, it is necessary to control the thickness of the leakage current blocking layer 1022. In some specific embodiments, the thickness of the leakage current blocking layer 1022 is less than 1nm. The leakage current blocking layer 1022 can be formed by an atomic layer deposition process, so that the thickness of the leakage current blocking layer 1022 can be accurately controlled.

[0039] In this specific embodiment, the sacrificial layer 1023 is formed on the surface of the leakage current blocking layer 1022. In other specific embodiments, the sacrificial layer 1023 may also be formed on the surface of the main dielectric layer 1021, and then the leakage current blocking layer 1022 is formed on the surface of the sacrificial layer 1023. In other specific embodiments, the sacrificial layer may not be formed.

[0040] The sacrificial layer 1023 is used to block the attack of ions generated in the subsequent process of forming the upper electrode on the main dielectric layer 1021. Usually, the materials of the main dielectric layer 1021 contain non-metallic ions, such as oxygen ions. The materials of the upper electrode 103 include but are not limited to TiN, TaN and Pt. Active ion byproducts are easily generated during the formation of the upper electrode. The active ions are usually highly active or more easily combined with other atoms in the main dielectric layer 1021, such as metal ions. The main dielectric layer 1021 is easily attacked by the active ions, so that the non-metallic ions in the main dielectric layer 1021 are replaced by the active ions, thereby causing the atomic structure of the main dielectric layer 1021 to change, thereby causing the leakage current to increase, and also causing the dielectric constant of the main dielectric layer 1021 to decrease, and the capacitance value of the capacitor to decrease.

[0041] The sacrificial layer 1023 is used to act as a material layer attacked by the byproducts of forming the upper electrode 103. Since the sacrificial layer 1023 is closer to the upper electrode, it is more easily attacked by the active ions of the byproducts of the upper electrode, thereby depleting the active ions in advance, so that the main dielectric layer 1021 is no longer attacked, thereby further reducing the leakage current.

[0042] The material of the sacrificial layer 1023 can be selected from materials with higher dielectric constants, especially oxygen-containing high-K dielectric materials, such as at least one of titanium oxide, lanthanum oxide, hafnium oxide and tantalum oxide. The sacrificial layer 1023 is susceptible to attack by active ions. In addition, it is also required that the sacrificial layer 1023 does not generate active ions that can attack the main dielectric layer 1021 during the formation process. In this specific embodiment, the material of the sacrificial layer 1023 is titanium oxide, which has higher adhesion with the subsequently formed upper electrode. TiH2 is usually used to react with oxygen-containing gas to form TiO2, and no active ions are generated during the reaction.

[0043] In order to prevent the sacrificial layer 1023 from affecting the capacitance of the capacitor, it is necessary to control the thickness of the sacrificial layer 1023. In some specific embodiments, the thickness of the sacrificial layer 1023 is less than 1 nm, and the sacrificial layer 1023 can be formed by an atomic layer deposition process, so that the thickness of the sacrificial layer 1023 can be accurately controlled.

[0044] Please refer to Figure 3 , an upper electrode 103 is formed on the surface of the sacrificial layer 1023 .

[0045] In this specific embodiment, the material of the upper electrode 103 is TiN, and the upper electrode 103 can be formed by chemical vapor deposition, atomic layer deposition, SFD (Sequential Flow Deposition) or ASFD (Advanced Sequential Flow Deposition) deposition. The reaction process uses TiCl4 and NH3 to react to form TiN, and active ions Cl ions are generated during the reaction. The zirconium ions in the zirconium oxide layer in the main dielectric layer 1021 are more likely to combine with Cl ions, so the main dielectric layer 1021 is easily attacked by Cl ions, and the Cl ions replace the oxygen ions in the zirconium oxide layer.

[0046] In this specific implementation, the material of the sacrificial layer 1023 is titanium oxide. The sacrificial layer 1023 replaces the main dielectric layer 1021 to be attacked by the Cl ions, thereby protecting the main dielectric layer 1021 from being affected.

[0047] The method for forming a capacitor in the above specific embodiment forms a sacrificial layer between the main dielectric layer and the upper electrode in the capacitor dielectric layer, which can replace the main dielectric layer to be attacked by active ions, thereby protecting the main dielectric layer from the influence of active ions, thereby reducing leakage current and increasing the capacitance value of the capacitor.

[0048] A leakage current blocking layer is further formed to block the leakage current path between the upper electrode of the capacitor and the main dielectric layer, thereby reducing the leakage current of the capacitor.

[0049] Please refer to Figure 4 , is a schematic structural diagram of a capacitor formed in another specific embodiment of the present invention.

[0050] In this specific embodiment, a main dielectric layer 1021, a sacrificial layer 1023 and an upper electrode 103 are sequentially formed on the surface of the lower electrode 101, and the main dielectric layer 1021, the sacrificial layer 1023 and the upper electrode 103 constitute a capacitor dielectric layer 102'. The specific formation method of the main dielectric layer 1021, the sacrificial layer 1023 and the upper electrode 103 is referred to the above specific embodiment, which will not be repeated here. This method forms a sacrificial layer 1023 between the main dielectric layer 1021 and the upper electrode 103, and the sacrificial layer 1023 can replace the main dielectric layer 1021 to be attacked by active ions, thereby protecting the main dielectric layer from the influence of active ions, thereby reducing leakage current and increasing the capacitance value of the capacitor.

[0051] A specific embodiment of the present invention further provides a capacitor formed by the above method.

[0052] Please refer to Figure 3 , which is a schematic structural diagram of a capacitor according to a specific embodiment of the present invention.

[0053] The capacitor includes a lower electrode 101 , an upper electrode 103 , and a capacitor dielectric layer 102 located between the lower electrode and the upper electrode.

[0054] The lower electrode 101 and the upper electrode 103 are both made of conductive materials, such as polysilicon, and may also include but are not limited to metal materials such as Ti, Co, TiN, TiW, W, TiAl, TiAlN, and combinations thereof. When the capacitor is applied to a DRAM memory, the lower electrode 101 and the upper electrode 103 are preferably made of metal materials.

[0055] The capacitor dielectric layer 102 includes a main dielectric layer 1021 and a leakage current blocking layer 1022 located between the main dielectric layer 1021 and the upper electrode 103 .

[0056] The thickness of the main dielectric layer 1021 is much greater than the thickness of the leakage current blocking layer 1022, which determines the capacitance value of the entire capacitor. The main dielectric layer 1021 is usually made of a material with a higher dielectric constant, such as at least one of zirconium oxide and aluminum oxide. In this specific embodiment, the main dielectric layer 1021 includes a zirconium oxide layer 1021a, an aluminum oxide layer 1021b and a zirconium oxide layer 1021c stacked in sequence. In other specific embodiments, the main dielectric layer 1021 can also be made of other dielectric materials.

[0057] The leakage current blocking layer 1022 is made of a material with a high bandgap width, so that free carriers are not likely to appear between the upper electrode 103 and the main dielectric layer 1021, thereby blocking the leakage current channel between the upper electrode 103 of the capacitor and the main dielectric layer 1021, and reducing the leakage current of the capacitor. Preferably, the bandgap width of the leakage current blocking layer 1022 is greater than or equal to the bandgap width of the main dielectric layer 1021.

[0058] In this specific embodiment, the material of the leakage current blocking layer 1022 is aluminum oxide. In other specific embodiments, the material of the leakage current blocking layer 1022 may also include at least one of aluminum oxide, magnesium oxide and silicon dioxide. The leakage current blocking layer 1022 may be a single-layer structure or a stacked structure composed of two or more layers of different materials.

[0059] The blocking effect of the leakage current blocking layer 1022 on leakage current is independent of its thickness. In order to still be able to control the capacitance value of the capacitor through the main dielectric layer 1021 and avoid the leakage current blocking layer 1022 having a significant impact on the capacitance value, it is necessary to control the thickness of the leakage current blocking layer 1022. In some specific embodiments, the thickness of the leakage current blocking layer 1022 is less than 1 nm.

[0060] In this specific embodiment, the capacitor dielectric layer 102 further includes a sacrificial layer 1023 located between the main dielectric layer 1021 and the upper electrode 103. The sacrificial layer 1023 is located between the leakage current blocking layer 1022 and the upper electrode 103. In other specific embodiments, the sacrificial layer 1023 may also be located between the main dielectric layer 1021 and the leakage current blocking layer 1022.

[0061] The sacrificial layer 1023 is used to block the attack of the ions generated during the formation of the upper electrode 103 on the main dielectric layer 1021. Usually, the materials of the main dielectric layer 1021 contain non-metallic ions, such as oxygen ions. Active ion byproducts are easily generated during the formation of the upper electrode 103. The active ions are usually highly active or more likely to combine with other atoms in the main dielectric layer 1021, such as metal ions. The main dielectric layer 1021 is easily attacked by the active ions, so that the non-metallic ions in the main dielectric layer 1021 are replaced by the active ions, thereby causing the atomic structure of the main dielectric layer 1021 to change, thereby causing the leakage current to increase, and also causing the dielectric constant of the main dielectric layer 1021 to decrease, and the capacitance value of the capacitor to decrease.

[0062] The sacrificial layer 1023 is used to act as a material layer attacked by byproducts of forming the upper electrode 103. Since the sacrificial layer 1023 is closer to the upper electrode 103, it is more easily attacked by the active ions of the byproducts of the upper electrode 103, thereby depleting the active ions in advance, so that the main dielectric layer 1021 is no longer attacked, thereby further reducing the leakage current.

[0063] In this specific embodiment, the material of the upper electrode 103 is TiN, which is usually deposited by chemical vapor deposition, atomic layer deposition, SFD (Sequential Flow Deposition) or ASFD (Advanced Sequential Flow Deposition), and the reaction process uses TiCl4 and NH3 to react to form TiN, and active ions Cl ions are generated during the reaction. The zirconium ions in the zirconium oxide layer in the main dielectric layer 1021 are more likely to combine with Cl ions, so the main dielectric layer 1021 is easily attacked by Cl ions, and the Cl ions replace the oxygen ions in the zirconium oxide layer.

[0064] The material of the sacrificial layer 1023 can be selected from materials with a higher dielectric constant, especially oxygen-containing high-K dielectric materials, such as at least one of titanium oxide, lanthanum oxide, hafnium oxide, and tantalum oxide. The sacrificial layer 1023 is susceptible to attack by active ions. In this specific embodiment, the material of the sacrificial layer 1023 is titanium oxide, and the sacrificial layer 1023 replaces the main dielectric layer 1021 to be attacked by the Cl ions, thereby protecting the main dielectric layer 1021 from being affected.

[0065] Furthermore, it is also required that the sacrificial layer 1023 does not generate active ions that can attack the main dielectric layer 1021 during the formation process. In this specific embodiment, the sacrificial layer 1023 is made of titanium oxide, which is usually formed by reacting TiH2 with oxygen-containing gas, and no active ions are generated during the reaction.

[0066] In order to prevent the sacrificial layer 1023 from affecting the capacitance of the capacitor, it is necessary to control the thickness of the sacrificial layer 1023. In some specific embodiments, the thickness of the sacrificial layer 1023 is less than 1 nm. Preferably, the total thickness of the leakage current blocking layer 1022 and the sacrificial layer 1023 is less than 1 nm.

[0067] In other specific implementations, the capacitor may also only include the leakage current blocking layer 1022 without forming the sacrificial layer 1023 .

[0068] The capacitor dielectric layer of the capacitor of the above-mentioned specific embodiment includes a leakage current blocking layer located between the main dielectric layer and the upper electrode, thereby blocking the leakage current channel between the upper electrode of the capacitor and the main dielectric layer, reducing the leakage current of the capacitor. In addition, the capacitor also includes a sacrificial layer located between the main dielectric layer and the upper electrode, which can replace the main dielectric layer to be attacked by active ions, thereby protecting the main dielectric layer from the influence of active ions, thereby reducing the leakage current and increasing the capacitance value of the capacitor.

[0069] Please refer to Figure 4 , is a schematic diagram of the structure of a capacitor according to another specific embodiment of the present invention. In this specific embodiment, the capacitor dielectric layer 102' between the lower electrode 101 and the upper electrode 103 of the capacitor includes a main dielectric layer 1021 and a sacrificial layer 1023. The sacrificial layer 1023 can replace the main dielectric layer 1021 to be attacked by active ions, thereby protecting the main dielectric layer 1021 from being affected by active ions, thereby reducing leakage current and increasing the capacitance value of the capacitor.

[0070] A specific embodiment of the present invention also provides a storage unit. The storage unit may include the capacitor described in the above specific embodiment, the leakage current of the capacitor is reduced and the capacitance value is increased, so that the performance of the storage unit is improved. The storage unit may be a DRAM unit, and the storage unit specifically includes: a transistor having a source region and a drain region, the transistor is arranged in the substrate, an electrical contact portion connecting the source region and the drain region is formed on the surface of the substrate, and the lower electrode of the capacitor is in contact with the source region or the drain region through the electrical contact portion.

[0071] A specific embodiment of the present invention further provides a memory, comprising a memory array composed of the above-mentioned multiple memory cells. The memory comprises a DRAM.

[0072] Please refer to FIG. 5A to FIG. 7 , which is a structural schematic diagram of the formation process of a capacitor according to a specific embodiment of the present invention.

[0073] Please refer to Figure 5A and Figure 5B, providing a substrate 400, the substrate 400 includes a substrate and a dielectric layer covering the substrate, a plurality of transistors with drain regions and source regions are formed in the substrate, and the transistors are arranged in an array; an electrical contact portion 401 is formed in the dielectric layer, and the dielectric layer exposes the surface of the electrical contact portion 401; the electrical contact portion 401 is connected to the source region and / or drain region of the transistor. Figure 5B For along Figure 5A Schematic cross-section of the secant line AA'.

[0074] A plurality of lower electrodes 420 arranged in an array are formed on the surface of the substrate 400. The lower electrodes 420 are cylindrical with an opening at the top, and the cross-sectional shape of the lower electrodes 420 in a direction perpendicular to the substrate 400 is U-shaped. The lower electrode 420 corresponding to each capacitor is connected to the electrical contact portion 401, and is electrically connected to the transistor corresponding to the capacitor through the electrical contact 401.

[0075] A support structure 410 is also formed on the substrate 400. The support structure 410 includes at least two support layers, which are used to support the lower electrode 420 to prevent the sidewall of the lower electrode 420 from collapsing. The support structure 410 includes a first support layer 411, a second support layer 412, and a third support layer 413. The third support layer 413 is located at the periphery of the top opening of the lower electrode 420, the second support layer 412 is located at the periphery of the middle part of the lower electrode 420, and the first support layer 411 is formed on the surface of the substrate 400 and is located at the periphery of the bottom of the lower electrode 420.

[0076] The method for forming the lower electrode 420 and the support structure 410 includes: forming alternately stacked support layers and spacer layers on the surface of the substrate 400, specifically including: a first support layer 411 formed on the surface of the substrate 400, a first spacer layer located on the surface of the first support layer 411, a second support layer 412 located on the surface of the first spacer layer, a second spacer layer located on the surface of the second support layer 412, and a third support layer 413 located on the surface of the second spacer layer. In other specific embodiments, the number of support layers and sacrificial layers can be increased to increase the height of the capacitor and further increase the capacitance value of the capacitor. The number of support layers can also be appropriately reduced, for example, only including the first support layer and the second support layer.

[0077] Then, a capacitor hole 430 is formed through the spacer layer and the support layer to expose the electrical contact portion 401; a lower electrode 420 is formed to cover the side wall of the capacitor hole 430; and the support layer and the spacer layer are etched to the surface of the first support layer 411 to form an opening 440 that at least exposes part of the spacer layer. The position of the opening 440 is shown in FIG. Figure 5AThe first sacrificial layer and the second sacrificial layer are removed along the opening 440 to expose a portion of the side wall of the lower electrode 420.

[0078] In a specific embodiment, the spacer layer and the support layer are made of silicon oxide and silicon nitride, respectively. When removing each spacer layer, a wet etching process can be used. The etching solution used includes a hydrofluoric acid solution. The corrosion rate of the spacer layer is much greater than the corrosion rate of the support layer. When the first spacer layer and the second spacer layer are completely removed, the first support layer 411, the second support layer 412 and the third support layer 413 are almost completely retained.

[0079] In this specific implementation, an opening 440 is formed between every three lower electrodes 420 of the capacitors. An opening 440 may also be formed between more or fewer lower electrodes 420 of the capacitors. Figure 5A Only the positions of some openings 440 are shown; in other specific implementations, the number of the openings 440 may be appropriately increased or decreased.

[0080] Figure 5B In the cross section, since an opening 440 is formed between two adjacent lower electrodes 420, the third supporting layer 413 and the second supporting layer 412 at the position of the opening 440 are removed, while in the area outside the opening 440, the third supporting layer 413 and the second supporting layer 412 are formed between the adjacent lower electrodes 420.

[0081] Please refer to Figure 6 A capacitor dielectric layer 421 and an upper electrode 422 are sequentially formed on the inner and outer surfaces of the lower electrode 420 .

[0082] The formation method and structure of the capacitor dielectric layer 421 can refer to the capacitor dielectric layer 102 in the above-mentioned specific embodiment (please refer to Figure 3 ) or capacitor dielectric layer 102' (please refer to Figure 4 ), which will not be elaborated here.

[0083] The capacitor dielectric layer 421 also covers the surfaces of the first supporting layer 411 , the second supporting layer 412 and the third supporting layer 413 .

[0084] Please refer to Figure 7 A conductive filling layer 501 and an interlayer dielectric layer 502 are formed on the surface of the upper electrode 422 .

[0085] The conductive filling layer 501 may be a doped germanium silicon layer, a doped polysilicon layer, etc. In this specific embodiment, the conductive filling layer 501 includes a boron-doped germanium silicon layer located on the surface of the upper electrode 422 and a boron-doped polysilicon layer covering the boron-doped germanium silicon layer. The conductive filling layer fills the gap between the upper electrodes 422.

[0086] The interlayer dielectric layer 502 may be planarized by a planarization process. The interlayer dielectric layer 502 may protect the storage unit below. Subsequently, an electrical connection structure connected to the upper electrode 422 may be formed in the interlayer dielectric layer 502 .

[0087] Please refer to Figure 7 , which is a structural diagram of a memory according to a specific implementation mode of the present invention.

[0088] The memory includes a substrate 400 and a plurality of capacitors arranged in an array on the substrate 400 .

[0089] The base 400 includes a substrate and a dielectric layer covering the substrate, a plurality of transistors having a drain region and a source region are formed in the substrate, and the transistors are arranged in an array; an electrical contact portion 401 is formed in the dielectric layer, and the dielectric layer exposes the surface of the electrical contact portion 401; the electrical contact portion 401 is connected to the source region and / or drain region of the transistor.

[0090] The capacitor includes a lower electrode 420 , a capacitor dielectric layer 421 covering a surface of the lower electrode 420 , and an upper electrode 422 covering a surface of the capacitor dielectric layer 421 .

[0091] The lower electrode 420 is cylindrical with an opening at the top, and has a U-shaped cross-section perpendicular to the substrate 400. The lower electrode 420 corresponding to each memory cell is connected to the electrical contact 401, and is electrically connected to the transistor corresponding to the memory cell through the electrical contact 401.

[0092] A support structure 410 is also formed on the substrate 400. The support structure 410 includes at least two support layers, which are used to support the lower electrode 420 to prevent the sidewall of the lower electrode 420 from collapsing. The support structure 410 includes a first support layer 411, a second support layer 412, and a third support layer 413. The third support layer 413 is located at the periphery of the top opening of the lower electrode 420, the second support layer 412 is located at the periphery of the middle part of the lower electrode 420, and the first support layer 411 is formed on the surface of the substrate 400 and is located at the periphery of the bottom of the lower electrode 420.

[0093] The capacitor dielectric layer 421 includes a main dielectric layer, and a leakage current blocking layer and a sacrificial layer located between the main dielectric layer and the upper electrode 422. For details, please refer to the capacitor dielectric layer 102 in the above-mentioned specific embodiment (please refer to Figure 3 , Figure 4The leakage current blocking layer can reduce the leakage current between the upper electrode 422 and the lower electrode 420, and the sacrificial layer can protect the main dielectric layer from being attacked by active ions generated during the formation of the upper electrode 422, thereby increasing the capacitance of the capacitor and reducing the leakage current.

[0094] In other specific implementations, only the sacrificial layer or only the leakage current blocking layer may be formed in the capacitor dielectric layer 421 .

[0095] The leakage current of the capacitor in the storage array of the memory is reduced and the capacitance value is increased, thereby improving the performance of the memory.

[0096] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A capacitor, characterized in that: include: Lower electrode; Upper electrode; A capacitor dielectric layer is located between the lower electrode and the upper electrode, the capacitor dielectric layer includes a main dielectric layer and a sacrificial layer located between the main dielectric layer and the upper electrode; the sacrificial layer is a material layer attacked by byproducts of forming the upper electrode, and the thickness of the sacrificial layer is less than 1nm.

2. The capacitor according to claim 1, characterized in that The capacitor dielectric layer further includes a leakage current blocking layer located between the main dielectric layer and the upper electrode.

3. The capacitor according to claim 1, characterized in that The material of the sacrificial layer is an oxygen-containing high-K dielectric material.

4. The capacitor according to claim 1, characterized in that The material of the sacrificial layer includes at least one of zirconium oxide, titanium oxide, lanthanum oxide, hafnium oxide and tantalum oxide.

5. The capacitor according to claim 2, characterized in that The bandgap width of the material of the leakage current blocking layer is greater than or equal to the bandgap width of the material of the main dielectric layer.

6. The capacitor according to claim 2, characterized in that The material of the leakage current blocking layer includes at least one of aluminum oxide, magnesium oxide and silicon dioxide.

7. The capacitor according to claim 2, characterized in that The sacrificial layer is located between the leakage current blocking layer and the upper electrode.

8. The capacitor according to claim 2, characterized in that The thickness of the leakage current blocking layer is less than 1 nm.

9. The capacitor according to claim 1, characterized in that The main dielectric layer includes a zirconium oxide layer, an aluminum oxide layer and a zirconium oxide layer which are stacked in sequence.

10. A method for forming a capacitor, characterized in that: include: forming a lower electrode; A capacitor dielectric layer is formed on the surface of the lower electrode, wherein the capacitor dielectric layer includes a main dielectric layer located on the surface of the lower electrode and a sacrificial layer located on the surface of the main dielectric layer; the sacrificial layer is a material layer attacked by byproducts of forming the upper electrode, and the thickness of the sacrificial layer is less than 1 nm; An upper electrode is formed on the surface of the capacitor dielectric layer.

11. The method for forming a capacitor according to claim 10, wherein: The forming of the capacitor dielectric layer on the surface of the lower electrode comprises: forming the capacitor dielectric layer on the surface of the lower electrode by adopting a chemical vapor deposition process or an atomic layer deposition process.

12. The method for forming a capacitor according to claim 10, wherein: The forming of the capacitor dielectric layer on the surface of the lower electrode comprises: forming a leakage current blocking layer on the surface of the main dielectric layer; and forming the sacrificial layer on the surface of the leakage current blocking layer.

13. The method for forming a capacitor according to claim 12, wherein: The bandgap width of the material of the leakage current blocking layer is greater than or equal to the bandgap width of the material of the main dielectric layer.

14. The method for forming a capacitor according to claim 12, wherein: The main dielectric layer includes a zirconium oxide layer, an aluminum oxide layer and a zirconium oxide layer stacked in sequence; the material of the leakage current blocking layer includes at least one of aluminum oxide, magnesium oxide and silicon dioxide; and the material of the sacrificial layer is an oxygen-containing high-k dielectric material.

15. A storage unit, characterized in that: include: A capacitor as claimed in any one of claims 1 to 9.

16. The storage unit according to claim 15, characterized in that Also includes: substrate; A transistor having a source region and a drain region is formed in the substrate; An electrical contact portion connected to the source region or the drain region is also formed in the substrate, the substrate exposes a surface of the electrical contact portion, and the lower electrode of the capacitor is connected to the source region or the drain region through the electrical contact portion.

17. The storage unit according to claim 16, characterized in that The longitudinal section of the lower electrode is U-shaped, and the U-shaped bottom of the lower electrode is in contact with the electrical contact portion.

18. A memory, characterized in that: include: A memory array formed by a plurality of memory cells as claimed in claim 16.

19. The memory according to claim 18, characterized in that: The memory includes DRAM.

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