Integrated multi-path power amplifier

Abstract

A multi-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peak amplifier FET), a combining node, and a shunt inductive circuit. The first and second amplifiers and the combining node structure are formed integral with a semiconductor die, and the shunt inductive circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt inductive circuit is electrically coupled between the combining node structure and a ground reference node. The shunt inductive circuit includes a shunt inductance (e.g., including one or more wire bonds and / or one or more spiral inductors) integrated with the semiconductor die. The multi-path amplifier can also include an integrated phase shifter / impedance inverter coupled between the outputs of the first and second transistors, and the integrated phase shifter / impedance inverter is configured to apply a 90 degree phase delay between intrinsic drains of the first and second transistors.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to multiple power amplifiers, and more specifically to multiple power amplifiers having output combination circuitry. Background Technology

[0002] For many years, Doherty power amplifiers (PAs) have been among the most popular amplifiers for cellular infrastructure applications. Because Doherty power PAs are well-suited for amplifying signals with a peak-to-average power ratio (PAPR), their use in future 5G infrastructure deployments is expected to continue in large numbers. However, despite their long history of use, traditional Doherty PA configurations are struggling to meet some of the new challenges associated with 5G deployments. These challenges include supporting communications over increasingly wider bandwidths with low-cost and increasingly compact amplifier devices, while simultaneously meeting stringent RF performance requirements regarding linearity, efficiency, and power gain. Summary of the Invention

[0003] According to one aspect of the present invention, a multiplexer is provided, comprising:

[0004] Semiconductor die;

[0005] The first transistor is integrally formed with the semiconductor die;

[0006] The second transistor is integrally formed with the semiconductor die;

[0007] A combined node structure, wherein the combined node structure is integrally formed with the semiconductor die, and wherein the outputs of the first transistor and the second transistor are electrically coupled to the combined node structure; and

[0008] A parallel inductor circuit electrically coupled between the combined node structure and the ground reference node, wherein the parallel inductor circuit includes a parallel inductor integrated with the semiconductor die.

[0009] According to one or more embodiments, the combined node structure is tightly electrically coupled to the output of the second transistor.

[0010] According to one or more embodiments, the parallel inductor circuit includes: a first integrated inductor, the first integrated inductor including a set of bonding wires, wherein each of the bonding wires has a first end and a second end respectively connected to a first bonding pad and a second bonding pad, the first bonding pad and the second bonding pad being exposed on the top surface of the semiconductor die.

[0011] According to one or more embodiments, the parallel inductor circuit further includes: a second integrated inductor, the second integrated inductor including one or more spiral inductors, the spiral inductors being integrally formed with the semiconductor die and being coupled in series with the first integrated inductor between the combined node structure and the ground reference node.

[0012] According to one or more embodiments, the parallel inductor circuit includes: one or more integrated inductors; and a capacitor electrically connected between the one or more integrated inductors and the ground reference node.

[0013] According to one or more embodiments, the multiplexer further includes: a radio frequency (RF) cold spot located between the one or more integrated inductors and the capacitor; and a video bandwidth circuit electrically coupled to the RF cold spot node.

[0014] According to one or more embodiments, the video bandwidth circuit includes a resistor, an inductor, and a capacitor coupled in series.

[0015] According to one or more embodiments, at least one of the resistor, the inductor, and the capacitor is integrated with the semiconductor die.

[0016] According to one or more embodiments, at least one of the resistor, the inductor, and the capacitor is implemented off-chip and electrically coupled to the RF cold spot node via wire bonding.

[0017] According to one or more embodiments, the second transistor is larger than the first transistor, and the first transistor has a first drain-source capacitance CdsM, which is smaller than the second drain-source capacitance CdsP of the second transistor.

[0018] According to one or more embodiments, the parallel inductor and the second drain-source capacitor resonate at a frequency below the operating frequency band of the multiplexer.

[0019] According to one or more embodiments, it further includes: an integrated phase shifter / impedance inverter coupled between the outputs of the first transistor and the second transistor, wherein the integrated phase shifter / impedance inverter is configured to apply a 90-degree phase delay between the intrinsic drains of the first transistor and the second transistor.

[0020] According to one or more embodiments, the integrated phase shifter / impedance inverter includes: a set of bonding wires, wherein each bonding wire in the set of bonding wires has a first end and a second end respectively connected to a first bonding pad and a second bonding pad, the first bonding pad and the second bonding pad being exposed on the top surface of the semiconductor die.

[0021] According to one or more embodiments, the integrated phase shifter / impedance inverter further includes: a transmission line integrally formed with the semiconductor die and coupled in series with the set of bonding wires.

[0022] According to one or more embodiments, the second transistor is larger than the first transistor, and the parallel inductor is configured to reduce the difference between the drain-source capacitance of the first transistor and the effective drain-source capacitance of the second transistor.

[0023] According to one or more embodiments, the semiconductor die includes a base semiconductor substrate having a bulk resistivity in the range of about 1,000 ohms / cm to about 100,000 ohms / cm or greater.

[0024] According to a second aspect of the present invention, a Dougherty amplifier is provided, comprising:

[0025] Main amplifier transistor;

[0026] A peak amplifier transistor, wherein the peak amplifier transistor is integrally formed with a semiconductor die;

[0027] A combined node structure, integrally formed with the semiconductor die, wherein the drain terminals of the main transistor and the peaking transistor are electrically coupled to the combined node structure; and

[0028] A parallel inductor circuit electrically coupled between the combined node structure and the ground reference node, wherein the parallel inductor circuit includes a parallel inductor integrated with the semiconductor die.

[0029] According to one or more embodiments, the parallel inductor includes one or more components integrated with the semiconductor die, wherein the one or more components are selected from a set of integrated bonding wires, one or more integrated spiral inductors, and one or more discrete inductors coupled to the top surface of the semiconductor die.

[0030] According to one or more embodiments, the parallel inductor circuit includes: one or more integrated inductors; and a capacitor electrically connected between the one or more integrated inductors and the ground reference node.

[0031] According to one or more embodiments, the Dougherty amplifier further includes: a radio frequency (RF) cold spot located between the one or more integrated inductors and the capacitor; and a video bandwidth circuit electrically coupled to the RF cold spot node.

[0032] According to one or more embodiments, the main amplifier transistor is integrally formed with the semiconductor die, and the Dougherty amplifier further includes an integrated phase shifter / impedance inverter coupled between the outputs of the main amplifier transistor and the peak amplifier transistor, wherein the integrated phase shifter / impedance inverter is configured to apply a 90-degree phase delay between the intrinsic drains of the main amplifier transistor and the peak amplifier transistor.

[0033] According to one or more embodiments, the Dougherty amplifier further includes a signal distributor integrated with the semiconductor die, wherein the signal distributor is configured to split the power of an input radio frequency (RF) signal into a main input signal provided to the main amplifier transistor and a peaked input signal provided to the peak amplifier transistor. Attached Figure Description

[0034] A more complete understanding of the subject matter can be derived by referring to the detailed embodiments and claims when considered in conjunction with the following figures, wherein the same reference numerals refer to similar elements throughout the figures.

[0035] Figure 1 This is a simplified schematic diagram of an integrated Dougherty power amplifier according to an example embodiment;

[0036] Figure 2 This is a top view of the Dougherty power amplifier integrated circuit (IC) according to an example embodiment;

[0037] Figure 3 This is a top view of a Dougherty power amplifier IC according to another example embodiment;

[0038] Figure 4 According to the example embodiment Figure 3 Side section view of the Dougherty amplifier IC along line 4-4;

[0039] Figure 5 This is a top view of a Dougherty amplifier device packaged in a high-power package according to an example embodiment;

[0040] Figure 6 This is a top view of a packaged Dougherty amplifier device coupled to a printed circuit board substrate according to an example embodiment; and

[0041] Figure 7 This is a flowchart of a method for manufacturing a Dougherty power amplifier IC and a packaged Dougherty amplifier device according to an example embodiment. Detailed Implementation

[0042] In some typical conventional Dougherty amplifiers, different semiconductor dies for the main amplifier and peak amplifier are packaged in a discrete power amplifier unit, which is coupled to a printed circuit board (PCB) that includes the rest of the Dougherty amplifier. For example, an input divider on the PCB splits the input radio frequency (RF) signal into a main input signal and a peaked input signal, which are supplied to the main amplifier and peak amplifier via input leads of the power amplifier unit. At the output side of the Dougherty amplifier, the amplified main signal and peaked signal are supplied by the power amplifier unit via separate output leads. Depending on whether the Dougherty amplifier has a non-inverting or inverting configuration, a phase shifter and impedance inverter are coupled to the PCB along either the main output path or the peaked output path. After the phase shifter / impedance inverter, the amplified main signal and peaked signal are combined together by a Dougherty combiner implemented on the PCB. In large-scale production environments, conventional Dougherty amplifiers exhibit various performance issues due to variations in the placement tolerances of the main power amplifier chip and peaking power amplifier chip, the length and height of the solder wires within the device, and the structural changes used to implement phase shifters / impedance inverters and combiners at the PCB level.

[0043] Embodiments of the subject matter of this invention include monolithic multiplexers, and in more specific embodiments, monolithic Dougherty power amplifiers having integrated first and second power transistors (e.g., a main power transistor and a peaking power transistor), an integrated phase shifter / impedance inverter, and an integrated signal combiner connected between the outputs (e.g., the drain terminals) of the first and second power transistors. More specifically, the phase shifter / impedance inverter and the signal combiner are implemented with conductive structures integrated with the same die as the first and second power transistors. As used herein, the term "monolithic" means with respect to a single semiconductor die (e.g., Figure 2-4 The dies 201 and 301 in the design are integrated or incorporated therein. When a component is referred to herein as being integrated with a die (e.g., ...), Figure 2-4 When the dies 201 and 301 in the die are "integratedly formed," it means that the component structure forms part of the die itself (e.g., the component is generated during the die manufacturing process and is physically positioned between the top and bottom surfaces of the die). For example, simply refer to... Figure 2-4FETs 226, 230, 246, 250, inductors 282', 282" and capacitor 284 are considered to be "integrated" with dies 201, 301. Conversely, when an assembly is referred to as being "integrated" with a die, it means that the assembly structure is "integrated" with the die, or that the assembly is attached to the die in a separate manner (e.g., attached to the surface of die 201, 301). For example, the wire bonding groups 261, 282 (where "group" means one or more) are considered to be "integrated" with dies 201, 301, as the terminology is used herein, because each wire in the wire bonding groups 261, 282 originates and arrives on the top surface of die 201, 301 (i.e., two wires of each wire). The ends are bonded to different bonding pads on the top surface of the die, and therefore each wire is “independent” within dies 201, 301. Conversely, wire groups 219, 290 are considered not “integrated” with dies 201, 301 because the wires in wire groups 219, 290 do not originate or arrive on dies 201, 301 (i.e., each wire has only one end bonded to a bonding pad on the top surface of the die). Additionally, discrete components coupled to the top surface of the die are also considered “integrated” with the die (e.g., passive or active components with separate input and output packages, which are physically and electrically attached to bonding pads exposed on the die surface, such as with solder or conductive adhesive).

[0044] As described above, embodiments of the Dougherty amplifier include an integrated signal combiner (or combined node structure) connected between the outputs of the main power transistor and the peaking power transistor. In some embodiments, the signal combiner is tightly electrically coupled to the drain terminal of the peaking transistor, where “tightly electrically coupled” as used herein means directly connected or electrically coupled through one or more conductive features (e.g., one or more integrated conductive traces or one or more vias) forming a conductive path with negligible total resistance (e.g., less than 5.0 ohms to 20 ohms) and no passive or active electrical components (e.g., discrete or integrated resistors, inductors, capacitors, or transistors). Because the signal combiner can be implemented very close to one or more intrinsic drains of one or more peaking amplifiers, a 90-0 Dougherty amplifier can be implemented. The 90-degree phase difference between the main amplifier output and the peaking amplifier output is provided by an analog quarter-wavelength transmission line with a CLC topology. The CLC topology includes the drain-source capacitances of the main transistor and the peaking transistor, and a tightly controllable inductor implemented between the main amplifier output and the Dougherty combined structure. In addition, according to various embodiments, the implementation of on-die parallel inductor (or parallel-L) circuitry can effectively compensate for parasitic drain-source capacitance of peak amplifier transistors that may otherwise limit performance.

[0045] Furthermore, the various embodiments can significantly reduce or eliminate device-to-device manufacturing variations associated with die placement, and can also reduce variations in wire length and height. Therefore, implementations of the various embodiments can enable the production of Dougherty amplifiers with more consistent RF performance.

[0046] The following and illustrated embodiments of the Dougherty amplifier IC correspond to a bidirectional Dougherty amplifier including a main amplifier and a peak amplifier. Although not explicitly shown, other embodiments may include an "N-directional" Dougherty power amplifier, where N > 2, and where the number of peak amplifiers is equal to N-1. Furthermore, while the example embodiments described below specifically relate to embodiments of Dougherty power amplifiers, the subject matter of the invention can be applied more generally to any type of multiplexer that can benefit from embodiments of the circuits and structures of the invention described herein. Therefore, the subject matter of the invention is not limited to applications only in Dougherty power amplifiers.

[0047] Figure 1 This is a simplified schematic diagram of a multi-channel Dougherty power amplifier 100 according to an exemplary embodiment. The Dougherty amplifier 100 includes an input node 102, an output node 194, a power divider 104 (or power splitter), a main amplification path 110, a peaking amplification path 111, a phase shifter / impedance inverter 160, a combination node structure 164, and an output parallel-L circuit 180. A load 196 can be coupled to the combination node structure 164 (e.g., through inductor 190 and output node 194) to receive amplified RF signals from the amplifier 100.

[0048] According to one embodiment, at least the main amplification path 110, peaking amplification path 111, phase shifter / impedance inverter 160, and combination node structure 164 are integrated with or incorporated therein with a single integrated circuit die 101 (i.e., the circuit is monolithic). In some other embodiments, the output parallel-L circuit 180 is also integrated with die 101, as discussed later. Figure 3 and 4 As depicted, in some embodiments, the power divider 104 may be implemented off-die, as shown by the solid-line rectangle surrounding amplification paths 110, 111, phase shifter / impedance inverter 160, and combined node structure 164, excluding the power divider 104. In such embodiments, the outputs 106, 108 of the power divider 104 may be electrically connected to the main path input 121 and the peaking path input 141, respectively. In other embodiments, and as discussed later... Figure 2 The power divider 104 is depicted (e.g., Figure 2The power divider 204 can alternatively be integrated with a die 101 having amplification paths 110, 111, a phase shifter / impedance inverter 160, and a combination node structure 164, as shown in the dashed rectangular box surrounding the power divider 104.

[0049] The Dougherty power amplifier 100 is considered a “bidirectional” Dougherty power amplifier, comprising a main amplifier 120 and a peak amplifier 140. The main amplifier 120 provides amplification along a main amplification path 110, and the peak amplifier 140 provides amplification along a peaking amplification path 111. In other embodiments, more than one peak amplifier may be implemented in parallel with the first peak amplifier 140 to produce an N-directional Dougherty power amplifier, where N > 2.

[0050] While the main amplifier 120 and peak amplifier 140 can be of equal size (e.g., a 1:1 main peak amplifier size ratio in a symmetrical Dougherty configuration), they can also be of unequal size (e.g., in various asymmetrical Dougherty configurations). In an asymmetrical bidirectional Dougherty amplifier configuration, the peak amplifier 140 is typically several times larger than the main power amplifier 120. For example, the peak amplifier 140 can be twice the size of the main power amplifier 120, giving it twice the current-carrying capacity. Asymmetrical main peak amplifier size ratios other than a 1:2 ratio can also be implemented.

[0051] Power divider 104 is configured to divide the power of the input RF signal received at input node 102 into a main portion and a peaked portion of the input signal. The main input signal is provided to the main amplification path 110 at power divider output 106, and the peaked input signal is provided to the peaked amplification path 111 at power divider output 108. During low-power mode operation, where only the main amplifier 120 supplies current to the load 196, power divider 104 supplies input signal power only to the main amplification path 110. During full-power mode operation, where both the main amplifier 120 and the peaked amplifier 140 supply current to the load 196, power divider 104 distributes the input signal power between amplification paths 110 and 111.

[0052] Power divider 104 can distribute the power of the input RF signal equally or unequally. For example, when the Dougherty amplifier 100 has an asymmetric Dougherty amplifier configuration where the size of the peak amplifier 140 is approximately twice the size of the main amplifier 120 (i.e., the Dougherty amplifier 100 has an asymmetric configuration with a peak-to-mass ratio of 1:2), power divider 104 can distribute the power such that approximately one-third of the input signal power is provided to the main amplification path 110 and approximately two-thirds of the input signal power is provided to the peak-to-mass amplification path 111. In other words, with a peak-to-mass ratio of 1:2, the peak amplifier 140 is approximately twice the size of the main amplifier 120, and power divider 104 is configured to produce a peaked input signal with a power approximately twice that of the main input signal.

[0053] Alternatively, in the case of a symmetrical Dougherty amplifier configuration (i.e., a main peaking size ratio of approximately 1:1), the power divider 104 can distribute the power such that approximately half of the input signal power is provided to the main amplification path 110 at the power divider output 106, and approximately half of the input signal power is provided to the peaking amplification path 111 at the power divider output 108.

[0054] Essentially, power divider 104 distributes the input RF signal supplied at input node 102 and amplifies the distributed signal along main amplifier path 110 and peak amplifier path 111, respectively. The amplified signals are then combined in phase at combination node structure 164. Importantly, phase coherence between main amplifier path 110 and peak amplifier path 111 is maintained across the band of interest (or operating band) to ensure that the amplified main signal and peaked signal arrive in phase at combination node structure 164, and thus ensure proper Dougherty amplifier operation. Figure 1 In the depicted Dougherty amplifier configuration (i.e., the non-reverse Dougherty configuration described below), the input phase delay circuit 109 is coupled between the power divider output 108 and the peak amplifier input 141. According to one embodiment, the input phase delay circuit 109 applies a phase delay of approximately 90 degrees to the peaked input signal before it is provided to the peak amplifier 140. For example, the input phase delay circuit 109 may include a quarter-wavelength transmission line, a lumped element delay circuit, or another suitable type of delay element or circuit with an electrical length of approximately 90 degrees.

[0055] Each of the main amplifier 120 and the peak amplifier 140 includes a single power transistor or multiple cascaded power transistors for amplifying RF signals conducted through amplifiers 120 and 140. As used herein, the term "transistor" means a field-effect transistor (FET) or another suitable type of transistor. For example, "FET" may be a metal-oxide-semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), an enhancement-mode or depletion-mode high electron mobility transistor (HEMT), or another type of FET. According to various embodiments, each of the power transistors in the main amplifier section 120 and the peak amplifier section 140 may be implemented, for example, using silicon-based FETs (e.g., LDMOS FETs), silicon-germanium (SiGe)-based FETs, or III-V FETs (e.g., HEMTs), such as gallium nitride (GaN) FETs (or another type of III-V transistor, including gallium arsenide (GaAs) FETs, gallium phosphide (GaP) FETs, indium phosphide (InP) FETs, or indium antimonide (InSb) FETs).

[0056] According to one embodiment, the main amplifier 120 is a two-stage amplifier comprising a relatively low-power preamplifier 126 and a relatively high-power final stage amplifier 130 connected in a cascaded arrangement between the main amplifier input 121 and the main amplifier output 134. In the cascaded arrangement of the main amplifiers, the output 127 of the preamplifier 126 is electrically coupled to the input 129 of the final stage amplifier 130. Similarly, the peak amplifier 140 is a two-stage amplifier comprising a relatively low-power preamplifier 146 and a relatively high-power final stage amplifier 150 connected in a cascaded arrangement between the peak amplifier input 141 and the peak amplifier output 154. In the cascaded arrangement of the peak amplifiers, the output 147 of the preamplifier 146 is electrically coupled to the input 149 of the final stage amplifier 150. In other embodiments, each of the main amplifier 120 and the peak amplifier 140 may be a single-stage amplifier, or may include two or more cascaded coupled amplifier stages. Input impedance matching networks 122, 142 (IMN) and interstage impedance matching networks 128, 148 (ISMN) can be implemented at the inputs 125, 145 of each preamplifier 126, 146 and between each preamplifier 126, 146 and each final stage amplifier 130, 150, respectively. In each case, the matching networks 122, 142, 128, 148 can increase the circuit impedance in an increasing manner toward the load impedance.

[0057] During operation of the Dougherty amplifier 100, the main amplifier 120 is biased to operate in Class AB mode, and the peak amplifier 140 is typically biased to operate in Class C mode. In some configurations, the peak amplifier 140 may be biased to operate in Class B or deep Class B mode. At low power levels, where the power of the input signal at node 102 is below the turn-on threshold level of the peak amplifier 140, amplifier 100 operates in low power mode, in which the main amplifier 120 is the only amplifier supplying current to the load 196. When the power of the input signal exceeds the threshold level of the peak amplifier 140, amplifier 100 operates in high power mode, in which both the main amplifier 120 and the peak amplifier 140 supply current to the load 196. At this time, the peak amplifier 140 provides active load modulation at the combined node structure 164, thereby allowing the current of the main amplifier 120 to continue to increase linearly.

[0058] As will be combined later Figure 2-4 To explain in more detail, in one embodiment, one or more resistor divider gate bias circuits 170, 170' can be used (e.g., Figure 2 , 3 The gate biasing of the main amplifier 120 and the peak amplifier 140 is performed by resistor divider gate biasing circuits 270, 270', wherein each resistor divider gate biasing circuit 170, 170' includes at least one resistor 173, 174, 173', 174' electrically coupled between the gate bias voltage inputs 171, 171' of each amplifier 126, 130, 146, 150 and the inputs 125, 129, 145, 149 (e.g., the gate terminals). The drain biasing of the preamplifiers 126, 146 can also be performed using a drain biasing circuit ( Figure 1 Not shown in the image, but... Figure 2 , 3 The circuit shown in Figure 278 is used to perform this operation.

[0059] In one embodiment, a parallel-L circuit 180 is coupled between the output 154 of the peak amplifier 140 and a ground reference (or a ground reference node). As previously described, the parallel-L circuit 180 is configured to compensate for the drain-source capacitance at the output 151 of the peaking final stage amplifier 150. In one embodiment, the parallel-L circuit 180 includes an inductor 182 and a capacitor 184 coupled in series between the output 154 of the peak amplifier 140 and the ground reference.

[0060] Additionally, embodiments of the subject matter of this invention may include a video bandwidth (VBW) circuit 186 coupled between the output 154 of the peak amplifier 140 and a ground reference. In a more specific embodiment, the VBW circuit 186 is coupled to a node (e.g., an “RF cold spot” node, or some other node) between the inductor 182 and capacitor 184 of the parallel-L circuit 180. As used herein, an “RF cold spot” node is a conductive node that can serve as a virtual ground reference voltage for RF electrical signals. In various embodiments, the inductor 182 and capacitor 184 of the VBW circuit 186 may be integrated with die 101, or the inductor 182 and / or capacitor 184 may be implemented off-chip. In either case, the VBW circuit 186 is configured to improve the low-frequency resonance (LFR) of the amplifier 100 caused by the interactions between the various circuits and structures of the amplifier 100 by presenting low impedance at the envelope frequency and / or high impedance at the RF frequency. From an RF matching perspective, the VBW circuit 186 can essentially be considered "invisible" because it primarily affects the impedance at the envelope frequency (i.e., the VBW circuit 186 provides termination for the signal energy at the envelope frequency of the amplifier 100).

[0061] The VBW circuit 186 can have any of a variety of configurations. In some embodiments, the VBW circuit 186 includes a series circuit of a resistor, an inductor, and a capacitor coupled between the peak amplifier output 154 (or some other point along the amplification paths 110, 111) and a ground reference. Although the VBW circuit 186 in Figure 1 While VBW circuit 186 is shown as coupled to a specific node, it can be coupled to another node, or multiple VBW circuits can be coupled to multiple points along each amplification path 110, 111. For example, VBW circuit 186 can be coupled between each output 127, 147 of preamplifiers 126, 146 and a ground reference, or VBW circuit 186 can be coupled between each output 131, 151 of final stage amplifiers 130, 150 and a ground reference, or VBW circuit 186 can be coupled between each input 125, 145 of preamplifiers 126, 146 and a ground reference.

[0062] The Dougherty amplifier 100 has a “non-inverting” load network configuration. In the non-inverting configuration, the input circuitry is configured such that the input signal supplied to the peak amplifier 140 is delayed by 90 degrees relative to the input signal supplied to the main amplifier 120 at the center operating frequency fo of amplifier 100. To ensure that the main input RF signal and the peaked input RF signal arrive at the main amplifier 120 and the peak amplifier 140 with a phase difference of approximately 90 degrees, as is essential for proper Dougherty amplifier operation, the input phase delay circuitry 109 applies a phase delay of approximately 90 degrees to the peaked input signal before it is supplied to the peak amplifier 140, as described above.

[0063] To compensate for the 90-degree phase delay difference between the main amplification path 110 and the peaking amplification path 111 at the inputs of amplifiers 120 and 140 (i.e., to ensure that the amplified signal arrives in phase at the combined node structure 164), the phase delay / impedance inverter circuit 160 is configured to apply an approximately 90-degree phase delay to the signal between the output of the main amplifier 120 and the combined node structure 164. Additionally, the phase delay / impedance inverter circuit 160 applies impedance inversion to the amplified RF signal along the main amplification path 110. In one embodiment, the phase delay / impedance inverter circuit 160 includes a plurality of components 161, 162 connected in series. For example, components 161, 162 may include combinations of wire bonding and integrated transmission lines, such as those used in combination. Figure 2-4 To be discussed in more detail.

[0064] Alternative embodiments of the Dougherty amplifier may have an “inverting” load network configuration. In this configuration, the amplifier is configured such that the input signal supplied to the main amplifier 120 is delayed by approximately 90 degrees relative to the input signal supplied to the peak amplifier 140 at the center operating frequency f0 of the amplifier 100, and the output phase delay / impedance inverter circuit is configured to apply approximately 90-degree phase delay and impedance inversion to the signal between the output of the peak amplifier 140 and the combined node structure.

[0065] The Dougherty amplifier 100 is "integrated," as the term is used herein, because at least the main amplifier 120 (e.g., including preamplifier 126 and final stage amplifier 130), peak amplifier 140 (including preamplifier 146 and final stage amplifier 150), phase delay / impedance inverter circuitry 160, and combination node structure 164 are integrated with a single IC die 101 (e.g., Figure 2-4 The individual IC die 101 may be referred to herein as an "integrated Dougherty amplifier die" or integrated therein with the dies 201, 301. According to one embodiment, all or part of the input and interstage impedance matching networks 122, 142, 128, 148 may also be integrated with the same IC die 101 (e.g., ...). Figure 2-4 The die 201, 301) is integrated or incorporated therein. Additionally, the distributor 104 can be integrated with the same IC die 101 (e.g., Figure 2 The die 201 is integrated or incorporated therein. Alternatively, all or part of the distributor 104 and / or input impedance matching networks 122, 142 may be implemented in one or more components different from the IC die including the main amplifier 120 and the peak amplifier 140. According to another embodiment, the resistor divider bias circuits 170, 170' are also integrated with the same IC die 101 as the main amplifier 120 and the peak amplifier 140 (e.g., Figure 2 , 3 The VBW circuit 186 is integrated with or incorporated into the same IC die 101 as the main amplifier 120 and the peak amplifier 140 (e.g., dies 201, 301), but in other embodiments, the biasing may be performed by a non-integrated circuit and structure. According to yet another embodiment, the VBW circuit 186 also incorporates the same IC die 101 as the main amplifier 120 and the peak amplifier 140 (e.g., dies 201, 301). Figure 2 , 3 The VBW circuit 186 may be integrated or incorporated therein with the die 201, 301, but in other embodiments, the VBW circuit 186 may be implemented using non-integrated circuits and structures.

[0066] Figure 2 and 3 These are top views of two example embodiments of the Dougherty power amplifier IC 200, 300 (or "Dougherty IC"). For better understanding, both should be viewed simultaneously. Figure 3 and Figure 4 , Figure 4 yes Figure 3 Side section view of Doherty 1C 300 along line 4-4. It should be noted that... Figure 2-4 The same or substantially similar elements are denoted by the same reference numerals. As used herein, the terms "integrated circuit die" and "IC die" mean a single, distinct semiconductor die (or semiconductor substrate) in which one or more circuit components (e.g., transistors, passive devices, etc.) are integrally formed and / or directly physically connected to produce a monolithic structure.

[0067] Doherty ICs 200 and 300 each include an entire Doherty amplifier integrated with or incorporated therein with a single semiconductor die 201 or 301 (e.g., Figure 1 The Dougherty amplifier 100) has a portion in which the semiconductor die has opposing input and output sides 210 / 211, 310 / 311 (e.g., Figure 2 and 3The generally rectangular perimeter defined by the bottom and top sides of the die 201, 301 and the opposing left and right sides 212 / 213, 312 / 313 extending between the input and output sides. The circuitry within each die 201, 301 is electrically connected to external circuitry via leads (e.g., leads 214, 216, 217, 219, 287, 294, 314, 315) positioned near the input and output sides 210 / 211, 310 / 311 of the die 201, 301 and via bonding wires (e.g., bonding wires 219, 290) connecting the leads on the die 201, 301 to bonding pads (e.g., bonding pads 202, 271, 271′, 278, 285, 302, 302′).

[0068] exist Figure 2 and 3 In the specific embodiments shown, each Dougherty amplifier IC 200, 300 includes the following circuitry integrated with or incorporating into semiconductor dies 201, 301: a two-stage main amplifier 220 (e.g., Figure 1 The main amplifier 120), and the two-stage peak amplifier 240 (e.g., Figure 1 Peak amplifier 140), phase shifter / impedance inverter circuit 260 (e.g., peak amplifier 140), phase shifter / impedance inverter circuit 260 Figure 1 Phase shifter / impedance inverter 160), combined node structure 264 (e.g., Figure 1 The combined node structure 164), resistor divider bias circuits 270, 270′ (for example, Figure 1 The resistor divider bias circuits 170, 170'), drain bias circuit 278, and parallel -L circuit 280 (e.g., Figure 1 Parallel-L circuit 180). Figure 2 The Doherty IC 200 also includes a power divider 204 (e.g., Figure 1 The power divider 104) and the input phase delay circuit 209 (e.g., Figure 1 Input phase delay circuit 109).

[0069] As in Figure 4 As most clearly seen, each semiconductor die 201, 301 includes a base semiconductor substrate 410 and a plurality of stacked layers 412 on the top surface of the base semiconductor substrate 410. In a particular example embodiment, the base semiconductor substrate 410 is a high-resistivity silicon substrate (e.g., a silicon substrate with a bulk resistivity in the range of about 1,000 ohms / cm to about 100,000 ohms / cm or greater). Alternatively, the base semiconductor substrate 410 may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a bulk resistivity up to 10...). 8The substrate can be a GaAs substrate with a resistivity of ohms / cm, or another suitable high-resistivity substrate. In other alternative embodiments, the base semiconductor substrate 410 can be any of a variety of variations of a GaN substrate or other III-V semiconductor substrates. The advantage of using a high-resistivity substrate is that, compared to amplifier ICs that do not use a high-resistivity substrate, such a substrate can enable various on-die circuits (e.g., on-die combined node structure 264 and other circuits) to exhibit relatively low losses.

[0070] Multiple stacked layers 412 may include, for example, multiple staggered dielectric layers, patterned conductive layers, and other conductive structures (e.g., conductive polysilicon structures). Portions of different patterned conductive layers and structures are electrically coupled to conductive vias (e.g., via 432). Additionally, conductive through-substrate vias (TSVs) (e.g., TSV 448) may provide a conductive path between the top and bottom surfaces of the base semiconductor substrate 410. The TSVs may be lined with or without dielectric material to insulate them from the base semiconductor substrate 410. According to one embodiment, a conductive layer 428 on or at the bottom surface of the base semiconductor substrate 410 serves as a ground reference node for the Dougherty IC 300. As used herein, "ground reference node" means a conductive feature integrally formed with semiconductor dies 201, 301, and said conductive feature is configured to be electrically coupled to an external conductive feature, which in turn may be electrically coupled to a ground reference voltage. Therefore, although... Figure 2-4 Not shown in the diagram, but when the Dougherty ICs 200 and 300 are finally packaged, the conductive layer 428 can be physically and electrically coupled to the ground node of the package substrate (e.g., Figure 5 (Flange 502). In other embodiments, the "ground reference node" may be an integrally formed conductive feature of the die 201, 301 other than the conductive layer 428 (e.g., the ground reference node may be a bonding pad, one or more ends of one or more conductive vias, or other integrally formed conductive features).

[0071] In the following description of the Dougherty IC 200, 300, reference will be made to various circuits including capacitors, inductors, and / or resistors. In various embodiments, the capacitor may be, for example, an integrated metal-insulator-metal (MIM) capacitor formed within a stacked layer (e.g., layer 412). Figure 2-4 The capacitor 284), discrete capacitors coupled to the top surfaces of dies 201 and 301, and / or other types of capacitors. Resistors can be, for example, integrated resistors (e.g., formed of polysilicon within stacked layer 412), or discrete resistors coupled to the top surfaces of dies 201 and 301. Inductors can be integrally formed spiral inductors (e.g., Figure 2-4The spiral inductor 282', 282" is formed by a patterned conductive layer and through-holes within a stacked layer (e.g., layer 412), or the inductor may be a discrete inductor or formed by bonding wires (e.g., Figure 2-4 Bonding wires 261, 282, 290), patterned conductive traces (e.g., Figure 2 , 3 The inductance is formed by bonding pads 262 and traces 263 or other inductor components.

[0072] exist Figure 2-4 In embodiments, each of the main amplifier 220 and the peak amplifier 240 includes a cascaded arrangement of two power transistors, including relatively low-power preamplifier transistors 226, 246 (e.g., Figure 1 The preamplifiers 126, 146) and the relatively high-power final stage amplifier transistors 230, 250 (e.g., Figure 1 The final stage amplifiers 130 and 150 are described herein as follows: each transistor includes one control terminal and two conductive terminals. For example, using FET-related terminology, "control terminal" refers to the gate terminal of the transistor, and the first and second conductive terminals refer to the drain and source terminals of the transistor (and vice versa). Although the following description may use terminology commonly used in conjunction with FET devices, the various embodiments are not limited to implementations utilizing FET devices, but are intended to be applicable to implementations utilizing bipolar junction transistor (BJT) devices or other suitable types of transistors.

[0073] Each transistor 226, 230, 246, 250 includes gate terminals 225, 229, 245, 249 (or control terminals), drain terminals 227, 231, 247, 251 (or first current-carrying terminals), and an uncoded source terminal (or second current-carrying terminal). In a specific embodiment, each transistor 226, 230, 246, 250 is an LDMOS FET, which includes an active region disposed between the gate terminal and the drain terminal. Each active region includes a plurality of elongated, parallel, and intersecting drain and source regions, wherein each drain region and each source region is a doped semiconductor region formed in a base semiconductor substrate (e.g., substrate 410). Due to their elongated shape, each set of adjacent drain and source regions and associated gate structures may be referred to as “transistor fingers,” and each transistor 226, 230, 246, 250 includes a plurality of parallel transistor fingers within the active region of the transistor (in Figure 2 and 3 (Used as vertical lines in the middle).

[0074] Variable conductivity channels (and drain drift regions in some embodiments) exist between adjacent source and drain regions. Conductive (e.g., polysilicon or metal) gate structures formed on a base semiconductor substrate (e.g., substrate 410) are coupled to each gate end 225, 229, 245, 249 on the channel regions and extend along the channel regions from each gate end 225, 229, 245, 249. Similarly, additional conductive (e.g., polysilicon) drain structures formed on the base semiconductor substrate (e.g., substrate 410) are coupled to each drain end 227, 231, 247, 251 on the drain regions and extend along the drain regions from each drain end 227, 231, 247, 251. The source region is electrically coupled to a conductive (e.g., polysilicon or metal) source contact, which in turn is coupled to a conductive TSV (e.g., ...) extending through the base semiconductor substrate (e.g., substrate 410) to connect with a conductive layer (e.g., layer 428) on the bottom surface of the base semiconductor substrate. Figure 4 (TSV 448). During operation, the voltage applied to the gate terminals 225, 229, 245, 249 modulates the conductivity of the variable conductive channel, thereby enabling current to flow between the source and drain regions (or ultimately between the conductive layer 428 and each drain terminal 227, 231, 247, 251).

[0075] The circuitry integrated into and coupled to the Dougherty IC 200 and 300 will now be described in more detail. First, refer to... Figure 2 The Doherty IC 200 includes an integrated power divider 204 (e.g., Figure 1 The power divider 104). More specifically, an input terminal 202 is configured to receive an input RF signal for amplification (e.g., Figure 1 The input node 102) is electrically connected to the distributor input 205 of the power divider 204 via a conductive path implemented in the stacked layer of the Dougherty IC200 (e.g., Figure 1 Input 105). Input 202 may include, for example, conductive bonding pads exposed on the top surface of die 201 and configured to attach one or more bonding wires 219. Alternatively, die 201 may be a flip-chip die, or the input may be exposed on the bottom surface of die 201, in which case input 202 may consist of conductive pads or other types of connections. These alternative configurations may also be applied to other terminals of the Dougherty IC 200 (e.g., terminals 271, 271', 278).

[0076] Power divider 204 (e.g., Figure 1 The power divider 104 is configured to divide the power of the input RF signal received at input terminal 202 into a main part and a peaked part of the input signal. (As in combination) Figure 1 As described, the power divider 204 is configured to split the power of an input RF signal received at input 202 into a primary portion (or "main input signal") and a peaked portion (or "peaked input signal") of the input signal. The main input signal is output at the power divider output 206 (e.g., Figure 1 The peaked input signal is generated at the output 106), and the peaked input signal is generated at the power divider output 208 (e.g., Figure 1 The power is generated at output 108). Similarly, as previously stated, power divider 204 can distribute power equally or unequally depending on the relative magnitudes of the main amplifier 220 and the peak amplifier 240. Figure 2 and 3 In one embodiment, the main amplifier 220 is approximately half the size of the peak amplifier 240 (i.e., the final stage amplifiers FETs 230 and 250 have a 1:2 size ratio, and the Dougherty amplifier is an asymmetric amplifier with a peak ratio of 1:2), and therefore the power divider 204 distributes the input RF signal such that approximately one-third of the input signal power is generated at the power divider output 206, and approximately two-thirds of the input signal power is generated at the power divider output 208. In other embodiments, the main amplifier 220 and the peak amplifier 240 may have different asymmetric size ratios. In yet another embodiment, the main amplifier 220 and the peak amplifier 240 may be equal in size (i.e., the final stage amplifiers FETs 230 and 250 have a 1:1 size ratio, and the Dougherty amplifier is a symmetric amplifier with a peak ratio of 1:1), in which case the power divider 204 can divide the power of the RF input signal into equal portions.

[0077] In one embodiment, input 205 has an input impedance of 50 ohms, but the input impedance may also be less than or greater than 50 ohms. According to one embodiment, power divider 204 has a Wilkinson-based design that essentially splits the power of the input signal received at input 205 into two signals (i.e., a main input signal and a peaked input signal), with the outputs 206 and 208 being in phase. In an alternative embodiment, power divider 204 may split the power of the input signal received at input 205 into two signals that are out of phase (e.g., 90 degrees out of phase).

[0078] The output 206 of power divider 204 is electrically connected to the input of main amplifier 220 via a conductive path implemented in the stacked layer of die 201. According to one embodiment, the output 208 of power divider 204 is connected to the input phase delay circuit 209 (e.g., ...). Figure 1The input phase delay circuit 209 and an additional conductive path implemented in the stacked layer of die 201 are electrically connected to the input of peak amplifier 240. The input phase delay circuit 209 is configured to apply a delay to the peaked input signal to ensure that the peaked input signal at the input of peak amplifier 240 has a phase difference of approximately 90 degrees with the main input signal at the input of main amplifier 220. According to one embodiment, the input phase delay circuit 209 is implemented with an integrated component, as indicated by the circuit diagram adjacent to circuit 209, which may include a π-configured phase delay circuit. For example, the phase delay circuit 209 may include an integrated inductor and an integrated parallel capacitor, a first end of which is coupled to the output 408 of distributor 204 and a second end of which is coupled to the input of peak amplifier 240, and the integrated parallel capacitor being coupled between each inductor end and a ground reference. In alternative embodiments, the input phase delay circuit 209 may be implemented using a transmission line (or wire bond) with a suitable electrical length (e.g., about 90 degrees or a smaller amount sufficient to produce the desired phase delay) or using some other delay circuit structure or configuration.

[0079] Now for reference Figure 3 The difference between the Dougherty IC 300 and the Dougherty IC 200 is that the Dougherty IC 300 does not include an integrated power divider (e.g., Figure 2 The power divider 204). Conversely, the input RF signal is coupled to the power divider of the external electrical system (e.g., the power divider of the external electrical system) by the Dougherti IC 300. Figure 6 The power is distributed by a power divider 630. The phase difference (e.g., about 90 degrees) between the main input signal and the peaked input signal is also applied by an external electrical system. The main input signal is provided to the main amplifier 220 via main input lead 314, solder wire 319 and bonding pad 302, and the peaked input signal is provided to the peak amplifier 240 via peaked input lead 315, solder wire 319' and bonding pad 302'.

[0080] Referring again to the two embodiments of the Dougherty IC 200, 300, in one embodiment, each of the main amplifier 220 and peak amplifier 240 may have a substantially similar configuration. According to one embodiment, each amplifier 220, 240 is a two-stage amplifier comprising relatively low-power preamplifiers 226, 246 (or preamplifier FETs) and relatively high-power final-stage amplifier transistors 230, 250 (or final-stage amplifier FETs) arranged in a cascaded configuration between amplifier inputs 221, 241 and combination node structure 264.

[0081] In the main amplifier 220, the input 221 of the amplifier 220 is connected to an input impedance matching network 222 (e.g., Figure 1The IMN 122) is coupled to the input 225 (e.g., the gate) of the preamplifier FET 226, and the output 227 (e.g., the drain) of the preamplifier FET 226 is connected through an interstage impedance matching network 228 (e.g., ...). Figure 1 The ISMN 128 is electrically coupled to the input 229 (e.g., the gate) of the final stage amplifier FET 230. Similarly, in the peak amplifier 240, the input 241 of the amplifier 240 is connected to the input impedance matching network 242 (e.g., the gate). Figure 1 The IMN 142) is coupled to the input 245 (e.g., the gate) of the preamplifier FET 246, and the output 247 (e.g., the drain) of the preamplifier FET 246 is connected to the interstage impedance matching network 248 (e.g., ...). Figure 1 ISMN 148 is electrically coupled to the input terminal 249 (e.g., the gate terminal) of the final stage amplifier FET 250. The source terminal of each of FETs 226, 230, 246, and 250 is electrically coupled to a ground reference (e.g., via TSV through the base semiconductor substrate 410). Figure 4 Bottom conductive layer 428).

[0082] In one embodiment, each preamplifier FET 226, 246 can be of equal size and can be configured to apply gain to the corresponding input RF signal in the range of about 15 dB to about 25 dB when the Dougherty IC 200, 300 operates in high-power mode (e.g., near compression), but when the Dougherty IC 200, 300 operates in low-power mode, only preamplifier FET 226 provides gain to its input signal. The final stage amplifier FETs 230, 250 are significantly larger than the preamplifier FETs 226, 246 (e.g., at least twice as large to apply at least twice the gain). In an asymmetric configuration, as... Figure 2 and 3 As shown, the final stage amplifier FETs 230 and 250 are of different sizes. Specifically, the final stage amplifier FET 250 of the peak amplifier 240 is approximately twice the size of the final stage amplifier FET 230 of the main amplifier 220, but the size ratio may also differ. In either case, when the Dougherty ICs 200 and 300 operate in high-power mode (e.g., near compression), each final stage amplifier FET 230 and 250 can be configured to apply gain to the corresponding input RF signal in the range of approximately 15 dB to approximately 25 dB; however, when the Dougherty ICs 200 and 300 operate in low-power mode, only the final stage amplifier FET 230 provides gain to its input signal.

[0083] According to one embodiment, the gate bias voltage of each of FETs 226, 230, 246, 250 is obtained through a resistor divider gate bias circuit 270, 270' (e.g., Figure 1 The resistor divider gate bias circuits 170 and 170' are provided. As previously mentioned, for proper operation of the Dougherty amplifier ICs 200 and 300, the main amplifier 220 is biased to operate in Class AB mode, and the peak amplifier 240 is typically biased to operate in Class C mode. Because the bias of the main amplifier 220 differs from that of the peak amplifier 240, the main amplifier resistor divider gate bias circuit 270 is different from (and not electrically connected to) the peak amplifier resistor divider gate bias circuit 270'.

[0084] In the illustrated embodiment, the main amplifier resistive divider gate bias circuit 270 includes a bias input terminal 271, resistors 273 and 274, and RF isolation circuits 275 and 276. Similarly, the peak amplifier resistive divider gate bias circuit 270' includes a bias input terminal 271', resistors 273' and 274', and RF isolation circuits 275' and 276'.

[0085] Terminals 271 and 271' may each include a conductive bonding pad exposed on the top surface of dies 201 and 301 and configured to attach one or more bonding wires. Input terminals 271 and 271' allow the main amplifier gate bias voltage to pass through the first bias lead 216 (e.g., ...). Figure 5 The peak amplifier gate bias voltage is supplied via the second bias lead 217 (e.g., lead 516), and the peak amplifier gate bias voltage can be supplied via the second bias lead 217 (e.g., lead 516). Figure 5 (517) supply.

[0086] Resistors 273, 274 or 273', 274' are electrically connected in series between input terminals 271, 271' and a ground reference. First resistors 273, 273' have a first terminal electrically coupled to input terminals 271, 271' and the gate terminals 225, 245 of preamplifier FETs 226, 246. The node between input terminals 271, 271' and resistors 273, 273' is electrically connected to the gate terminals 225, 245 of preamplifier FETs 226, 246, and an intermediate node (between resistors 273 / 273', 274 / 274') is electrically connected to the gate terminals 229, 249 of final stage amplifier FETs 230, 250. The resistance values ​​of resistors 273, 273', 274, and 274' are selected to segment the main preamplifier gate bias DC voltage or peaking preamplifier gate bias DC voltage supplied at input terminals 271, 271' (or at gate terminals 225, 245) to provide the desired DC bias voltage at gate terminals 229, 249. For example, resistors 273 / 273' and 274 / 274' can have equal or unequal resistance values ​​in the range of about 500 ohms to about 10,000 ohms, but resistors 273 / 273' and 274 / 274' can also have lower or higher resistance values.

[0087] To ensure that a significant amount of RF power is not lost through bias circuits 270, 270', the main amplifier 220 and peak amplifier 240 are decoupled (or isolated) from bias circuits 270, 270' via RF isolation circuits 275 / 275', 276 / 276'. More specifically, RF isolation circuits 275, 275' are electrically coupled between bias inputs 271, 271' and gates 225, 245, and RF isolation circuits 276, 276' are electrically coupled between resistors 273, 273' and gates 229, 249. According to one embodiment, each RF isolation circuit 275, 275', 276, 276' includes an integrated lumped element equivalent of a quarter-wavelength (λ / 4) transmission line having a reactive component resonating at the center operating frequency f0 of amplifiers 200, 300. Ideally, with this configuration, the bias circuits 270, 270' simulate infinite impedance at frequencies close to the center operating frequency, thereby isolating the bias circuits 270, 270' at these frequencies.

[0088] In addition to gate bias circuits 270, 270', each Dougherty amplifier IC 200, 300 may also include one or more drain bias circuits 277. According to one embodiment, the drain bias circuit 277 includes a bias input 278 and RF isolation circuits 279, 279'. Again, the bias input 278 may include conductive bonding pads exposed on the top surface of the die 201, 301 and configured to attach one or more bonding wires. Input 278 allows the drain bias voltage to pass through a third bias lead 218 (e.g., ...). Figure 5 (518) supply.

[0089] In one embodiment, input 278 is electrically connected to the drain terminals 227, 247 of each of the preamplifier FETs 226, 246 to supply the same DC drain bias voltage to each FET 226, 246. Again, to ensure that a significant amount of RF power is not lost through bias circuit 277, the main amplifier 220 and peak amplifier 240 are decoupled (or isolated) from bias circuit 277 via RF isolation circuits 279, 279'. More specifically, each RF isolation circuit 279, 279' is electrically coupled between input 278 and drain terminals 227, 247 of the preamplifier FETs 226, 246. Again, each RF isolation circuit 279, 279' may include an integrated lumped element equivalent of a quarter-wavelength (λ / 4) transmission line having a reactive component resonating at the center operating frequency f0. It should be noted that, in one embodiment, the drain bias voltage can be supplied to the final stage amplifier FETs 230, 250 via one or more device output leads (e.g., output lead 294) and the connection between the device output leads and the combination structure 264 (e.g., bond wire 290).

[0090] Returning to the amplification path of the main amplifier 220 and the peak amplifier 240, the outputs (i.e., drain terminals 231, 251) of each of the final stage amplifier FETs 230, 250 are electrically connected to the combination node structure 264 (e.g., Figure 1The combination node structure 264 is used to combine the amplified RF signals generated by each of the final-stage amplifier FETs 230, 250 into a single amplified output RF signal. According to one embodiment, the combination node structure 264 substantially corresponds to the drain terminal 251 of the final-stage peak amplifier FET 250. In practice, the combination node structure 264 can be implemented using a conductive structure tightly electrically coupled to the drain terminal 251 of the final-stage peak amplifier FET 250. Desiredly, the drain terminal 251 is connected to the combination node structure 264 with a conductive path having a negligible phase delay (i.e., a phase delay as close to zero as possible, such as 10 degrees or less), and in some embodiments, the drain terminal 251 may be an integrally formed part of the combination node structure 264. In other words, in some embodiments, the drain manifold of the final-stage peak amplifier FET 250 may form part of the combination node structure 264. The combined node structure 264 is also tightly electrically coupled to the bonding pad 281 exposed on the top surface of the dies 201, 301, and in some embodiments, the combined node structure 264 and the bonding pad 281 are the same conductive structure.

[0091] Conversely, the drain terminal 231 of the final stage main amplifier FET 230 passes through the phase delay / impedance inverter circuit 260 (e.g., Figure 1 The phase delay / impedance inverter circuit 260 is coupled to the combination node structure 264 (or drain terminal 251). The phase delay / impedance inverter circuit 260 is configured to compensate for the 90-degree phase delay difference between the main amplification path and the peaking amplification path at the inputs of amplifiers 220 and 240 (i.e., ensuring that the amplified signal arrives in phase at the combination node structure 264). Therefore, the phase delay / impedance inverter circuit 260 is configured to apply approximately a 90-degree phase delay to the signal between the drain terminal 231 of the final-stage main amplifier FET 230 and the combination node structure 264. Additionally, the phase delay / impedance inverter circuit 260 applies impedance inversion to the amplified RF signal generated by the final-stage main amplifier FET 230.

[0092] In one embodiment, the phase delay / impedance inverter circuit 260 includes a plurality of components 261, 262, 263 connected in series (e.g., Figure 1 Components 161 and 162). Figure 2 and 3In specific example embodiments, components 261-263 include one or more bond wires 261 (first inductor), bonding pads 262 (second inductor), and integrated transmission lines 263 (third inductor) connected in series between the drain terminal 231 of the final-stage main amplifier FET 230 and the combination node structure 264. In other embodiments, the multiple components 261-263 may be coupled in series in different orders, or more, fewer, or different components may be used to implement the phase delay / impedance inverter circuit 260. For example, some alternative embodiments of the phase delay / impedance inverter circuit 260 may include bond wires only or transmission lines only. Other alternative embodiments may include integrated or discrete inductors and / or other components.

[0093] According to one embodiment, the phase delay / impedance inverter circuit 260 has a CLC (capacitor-inductor-capacitor) topology between drain terminals 231 and 251. The first (parallel) capacitor includes the drain-source capacitance C of the final stage FET 230 of the main amplifier. dsM In some embodiments, this first (parallel) capacitance can be increased by additional capacitance provided by one or more additional parallel capacitors (e.g., MIM capacitors, not shown), which are connected at the drain terminal 231 of the final stage FET of the main amplifier to a die ground reference (e.g., ...). Figure 4 The conductive layer 428) and C dsM Parallel ground coupling. Ideally, for a symmetrical Dougherty amplifier, the capacitance of the additional parallel capacitor should be chosen such that C... dsM The combined capacitance with the other parallel capacitors is approximately equal to the drain-source capacitance C of the final-stage peak amplifier FET 250. dsP For example Figure 2 and 3 The asymmetric Dougherty amplifier shown has a drain-source capacitance C of the final stage main amplifier FET 230. dsM It can be designed with a drain-source capacitance C lower than that of the final-stage peak amplifier FET 250. dsP In the asymmetric Dougherty amplifier embodiment, C dsM The combined capacitance with other parallel capacitors (if included) should be designed such that: 1) the transmission path (or "pseudo-transmission line") between the final stage main amplifier FET 230 and the final stage peak amplifier FET 250 provides approximately 90 degrees of phase shift at the center operating frequency; and 2) the following:

[0094]

[0095]

[0096] Where freq is the center operating frequency (f0), L DC is the inductance of the conductive path between the drain terminal 231 of the final stage FET 230 of the main amplifier and the drain terminal 251 of the final stage peak amplifier FET 250. DS It is the output capacitance of the final stage main amplifier FET 230 and / or the final stage peak amplifier FET 250, and Z C It is the characteristic impedance of the pseudo-transmission line between the drain terminal 231 of the final-stage main amplifier FET 230 and the drain terminal 251 of the final-stage peak amplifier FET 250. For example, in one embodiment, C dsM The parallel combination with other parallel capacitors can have a combined capacitance value in the range of about 3 pF to about 10 pF (e.g., about 5 pF to about 6 pF) at a center operating frequency of about 2.0 GHz, but the center operating frequency and / or combined capacitance can also be lower or higher.

[0097] In the CLC topology of the phase delay / impedance inverter circuit 260, the inductance is provided by a series combination of bond wires 261, bonding pads 262, and transmission lines 263. One or more bond wires 261 each have a first end connected to a first bonding pad 265 (which is in turn tightly electrically coupled to the drain terminal 231 of the final stage main amplifier FET) and a second end connected to a bonding pad 262 (hereinafter referred to as the "inter-inductor node"), wherein both bonding pads 262 and 265 are integrally formed with and exposed beneath the top surfaces of dies 201 and 301. Bond pad 262 is electrically coupled to the first end of transmission line 263, and the second end of transmission line 263 is electrically coupled to the combined node structure 264 (and / or drain terminal 251). Transmission lines 263 can be, for example, made from the stacked layers of dies 201 and 301 (e.g., Figure 4 The transmission line 263 is implemented by patterning one or more conductive layers of the stacked layer 412, and thus the transmission line 263 is integrally formed with the dies 201, 301. According to one embodiment, the series combination of the bonding wire 261, the bonding pad 262 and the transmission line 263 has a combined inductance of about 0.8 nanohenries (nH) to about 1.2 nH at a center operating frequency of about 2.0 GHz, but the center frequency and / or the combined inductance may also be lower or higher.

[0098] Finally, the second (parallel) capacitor in the CLC topology of the phase delay / impedance inverter circuit 260 is approximately equal to the drain-source capacitance C of the final-stage peak amplifier FET 250. dsP Subtract a portion of C compensated by the parallel inductance (e.g., by parallel inductors 282, 282', 282"). dsP As will be explained below. In other words, the second parallel capacitor can be A × C dsP This indicates that A < 1.0, and (1.0 - A) × C dsPThis is equivalent to the negative capacitance provided by the parallel inductor (e.g., parallel inductors 282, 282', 282"). In one embodiment, at a center operating frequency of approximately 2.0 GHz, C dsP The capacitor has a capacitance value in the range of about 5pF to about 10pF (e.g., about 7pF to about 8pF), but the center frequency and / or capacitance may also be lower or higher.

[0099] In summary, the 90-degree phase difference between drain terminal 231 and drain terminal 251 (or combined node 264) is provided by a phase delay / impedance inverter circuit 260 with a CLC topology, wherein the topology includes a first parallel capacitor (e.g., by C...). dsM And possibly additional parallel capacitors are provided), series inductor circuit (e.g., provided by bonding wire 261, bonding pad 262 and transmission line 263) and second parallel capacitor (e.g., provided by A×C dsP Provided, where A < 1.0).

[0100] The RF signals amplified by the main amplification path and the peaking amplification path are combined substantially in phase at the combination node 264, as previously described, to produce an amplified output RF signal. In one embodiment, the combination node 264 is connected via multiple bonding wires 290 (e.g., Figure 1 The inductor 190 is electrically connected to the output lead 294 (e.g., Figure 1 The output RF signal, amplified, is thus transmitted from the combination node 264 to the output lead 294 via the bond wire 290. According to one embodiment, the bond wire 290 is configured to have a relatively low inductance, such as an inductance value in the range of about 20 picohens (pH) to about 70 pH (e.g., about 60 pH), but the inductance value can also be smaller or larger. Desiredly, the bond wire 670 is designed such that the inductance value of the bond wire 670 is as low as possible.

[0101] According to one embodiment, in one embodiment, the parallel-L circuit 280 (e.g., Figure 1 The parallel-L circuit 180) is coupled to the drain terminal 251 (or combination node 264) of the final stage peak amplifier to the die ground reference (e.g., Figure 4 Between the conductive layer 428). As previously described, the parallel-L circuit 280 is configured to compensate (e.g., resonate out) the drain-source capacitance at the drain terminal 251 of the final-stage peak amplifier FET 250. In one embodiment, the parallel-L circuit 280 includes a parallel inductor (e.g., between the drain terminal 251 of the final-stage peak amplifier FET 250 and a ground reference) coupled in series. Figure 1 The inductor 182) and parallel capacitor (e.g., Figure 1The parallel capacitor (capacitor 184) is configured to provide a low-impedance ground path for very low-frequency signal energy (e.g., DC) and a high-impedance ground path for signal energy in the operating bands of amplifiers 200 and 300. In alternative embodiments, the parallel-L circuit may alternatively be coupled between the drain terminal 231 of the final stage main amplifier and the die ground reference, or the parallel-L circuit may be coupled between both drain terminals 231 and 251 and the die ground reference.

[0102] In one embodiment, the parallel inductance of the parallel-L circuit 280 is implemented using one or more bonding wires 282 series coupled to one or more integrally formed inductors 282′, 282″. Each of the bonding wires 282 representing the first integrated inductor has a first end connected to a first bonding pad 281 (which is in turn tightly electrically coupled to the combination node 264 and the drain terminal 251 of the final stage peak amplifier) ​​and a second end connected to a bonding pad 283 (hereinafter referred to as the "inter-inductor node"), wherein both bonding pads 281, 283 are connected to dies 201, 30 The top surface of 1 is integrally formed and exposed thereunder. Essentially, the set of bond wires 282 can be considered an inductor, wherein one or more first ends of bond wires 282 correspond to a first end of an inductor, and one or more second ends of bond wires 282 correspond to a second end of an inductor. In alternative embodiments, more or fewer bond wires may be used to implement the first inductor. In other alternative embodiments, the set of bond wires 282 may be replaced by one or more discrete inductors, wherein the first and second ends are connected to different bonding pads exposed on the top surfaces of dies 201, 301.

[0103] Integrated inductors 282' and 282" representing a second inductance are coupled in parallel between inductor internode 283 and second conductive node 285. In one embodiment, the second conductive node 285 may be an RF cold spot node. More specifically, each of the integrated inductors 282' and 282" includes a stacked structure of dies 201 and 301 (e.g., Figure 4 An integrally formed spiral inductor is formed from portions of one or more layers of stacked layers 412, wherein a first end (or end portion) of each spiral inductor is coupled to an inter-inductor node 283, and a second end (or end portion) of each spiral inductor is coupled to a node 285. In an alternative embodiment, two parallel-coupled integrated inductors 282', 282" can be replaced by a single integrated inductor, two or more parallel-coupled integrated inductors, or one or more discrete inductors coupled to the top surface of dies 201, 301.

[0104] As used herein, the “operating band” or “band of operation” for amplifiers 200 and 300 refers to a frequency range defined by the lower and higher -3dB cutoff frequencies. According to one embodiment, the parallel inductor of the parallel-L circuit has an inductance value selected such that the parallel inductor and drain-source capacitance CdsP of the final-stage peak amplifier FET 250 resonate at frequencies below the operating band of amplifiers 200 and 300. For example, the parallel inductor and CdsP may resonate at frequencies at least 300 MHz below the operating band of amplifiers 200 and 300 (e.g., the resonant frequency of the parallel inductor and CdsP may be 300-500 MHz below the operating band, but the resonant frequency may also be higher or lower). As a specific, non-limiting example, when the center operating frequency f0 of amplifiers 200 and 300 is 2.0 GHz and the operating bandwidth between the lower cutoff frequency of 1.8 GHz and the upper cutoff frequency of 2.2 GHz is 400 MHz, the resonant frequency of the parallel inductor and CdsP can be 300-500 MHz or more lower than the lower cutoff frequency (e.g., the resonant frequency can be between 1.3 GHz and 1.5 GHz, but it can also be lower or higher). In other embodiments, the center operating frequency can be less than or greater than 2.0 GHz, the operating bandwidth can be narrower or wider, and therefore, the parallel inductor value can be selected to resonate with the CdsP at different frequencies below the corresponding operating bandwidth.

[0105] By reducing the difference between the effective drain-source capacitances of the final-stage main amplifier transistor 230 and the peak amplifier transistor 250, the parallel inductance of the parallel-L circuit substantially improves the quality of the combined node structure 264 (e.g., improves Zopt and Zmod at the center operating frequency). More specifically, since amplifiers 200 and 300 are asymmetric Dougherty amplifiers, the drain-source capacitance (CdsP) of the final-stage peak amplifier transistor 250 is greater than the drain-source capacitance (CdsM) of the final-stage main amplifier transistor 230. For example, when the peaking size ratio is approximately 1:2, the drain-source capacitance of the final-stage peak amplifier transistor 250 can be approximately 50-80% greater than the drain-source capacitance (CdsM) of the final-stage main amplifier transistor 230 (e.g., for a 1:2 asymmetry ratio, CdsM can be approximately 3.7 pF and CdsP can be approximately 4.9 pF). The parallel inductor of the parallel-L circuit is configured to reduce the difference between the drain-source capacitance CdsM of the final-stage main amplifier FET 250 and the effective drain-source capacitance of the final-stage peak amplifier FET 230. In some embodiments, the parallel inductor is configured such that the effective drain-source capacitance of the final-stage peak amplifier FET 250 is approximately equal to the drain-source capacitance of the final-stage main amplifier FET 230 (or equal to the effective capacitance of the final-stage main amplifier FET, provided that another parallel inductor is tightly electrically coupled to the drain of the final-stage main amplifier FET).

[0106] By utilizing the parallel-L circuit 280 to resonate at least some of the drain-source capacitances of the final-stage peak amplifier transistor 250, the effective drain-source capacitances of the main final-stage amplifier transistor 230 and the peaked final-stage amplifier transistor 250 are made essentially equal (or the difference between them is significantly reduced), which improves the quality of the combined node structure 264. In other words, the total parallel inductance provided by one or more bonding wires 282 and series coupling arrangement of inductors 282′, 282″ is selected to resonate at least some of the drain-source capacitance of the final-stage peak amplifier transistor 250. For example, in the given examples of amplifiers 200, 300 with an asymmetry ratio of 1:2, CdsM of approximately 3.7pF and CdsP of approximately 4.9pF, the parallel-L circuit 280 with a total parallel inductance of approximately 5nH can reduce the effective drain-source capacitance of the final-stage peak amplifier transistor 250 (i.e., the drain-source capacitance changed by the parallel inductance) from 4.9pF to approximately 3.7pF (i.e., equal to the value of the drain-source capacitance of the final-stage main amplifier transistor 230).

[0107] Factors influencing the selection of the total parallel inductance include, for example, the asymmetry ratio between the main amplifier transistor 230 and the peak amplifier transistor 250 (and thus the drain-source capacitance difference between transistors 230 and 250), the power level of the amplifier, and the center operating frequency of amplifiers 200 and 300. Generally, as the asymmetry ratio, center operating frequency, and / or power level increase, the selected total parallel inductance decreases, and conversely, as the asymmetry ratio, center operating frequency, and / or power level decreases, the selected total parallel inductance increases. For example, for a 30-watt amplifier 200, 300 with an asymmetry ratio of 1:2 and a center frequency f0 of approximately 2 GHz, the total parallel inductance provided by a series coupling arrangement of one or more solder wires 282 and inductors 282', 282" can range from approximately 1 nH to approximately 10 nH (e.g., approximately 5 nH), but the total parallel inductance can also be lower or higher. All other things being equal, if the center operating frequency is increased to 4 GHz, the selected total parallel inductance can be reduced to approximately half the value of the 2 GHz amplifier. Alternatively, all other things being equal, if the power level is reduced to 15 watts, the selected total parallel inductance can be approximately twice that of the 2 GHz amplifier.

[0108] According to one embodiment, a portion of the total parallel inductance of the parallel-L circuit 280 is provided by one or more bond wires 282, and another portion of the total parallel inductance is provided by integrated inductors 282′, 282”. In some embodiments, the portion of the total parallel inductance provided by one or more bond wires 282 may be between about 20% and about 80% of the total parallel inductance of the parallel-L circuit 280. For example, for amplifiers 200, 300 with a center operating frequency of about 2 GHz, the inductance value of the first inductor provided by one or more bond wires 282 may be in the range of about 0.5 nH to about 9.5 nH, and the second inductance provided by the parallel-coupled integrated inductors 282′, 282” may be in the range of about 0.5 nH to about 9.5 nH. Although specific example ranges and values ​​are provided above, in other embodiments, the inductance value of any one of elements 282, 282', 282" and / or the total inductance value of all elements 282, 282', 282" may be less than or greater than the ranges given above.

[0109] In one embodiment, the parallel capacitance of the parallel-L circuit 280 is implemented using an integrally formed capacitor 284. In one embodiment, the capacitor 284 has a first end electrically coupled to node 285 (or plate) and electrically coupled to a die ground reference (e.g., Figure 4 The second end (or plate) of the conductive layer 428). According to one embodiment, the capacitor 284 may include, for example, a stacked layer on the dies 201, 301 (e.g., Figure 4 One or more MIM capacitors are formed within layer 412. Alternatively, capacitor 284 may be integrally formed on the base semiconductor substrate (e.g., Figure 4 Within a substrate 410, vertical and / or horizontal conductive layers (e.g., polysilicon) are separated by a dielectric material. In other embodiments, capacitor 284 may be a discrete capacitor coupled to the surfaces of dies 201, 301. In other alternative embodiments, node 285 may be coupled to bonding pads, capacitor 284 may be connected to a substrate other than dies 201, 301, and bonding wires may be used to electrically couple the bonding pads (or node 285) to the external capacitor 284. Regardless of the method, according to one embodiment, the capacitance value of capacitor 284 is in the range of about 500 pF to about 2000 pF, but the capacitance value of capacitor 284 may also be lower or higher.

[0110] although Figure 2-4The illustrated embodiment of the parallel-L circuit 280 includes a series-coupled circuit comprising specific components in a particular series sequence (i.e., wire bonding 282, integrated inductors 282', 282" and integrated capacitor 284). However, other embodiments may include different implementations of the parallel-L circuit 280, including different series arrangements of components, different physical types of components, additional components or fewer components. As a non-limiting example, different series arrangements may include one or more integrated inductors (e.g., inductors 282' and / or 282") having a first end directly electrically connected to the drain terminal 251 and a second end coupled to an inductor indirect bonding pad (e.g., bonding pad 283), and the different series arrangements may additionally include one or more wire bonding lines (e.g., wire bonding 282) having a first end coupled to an inductor indirect bonding pad and a second end coupled to node 285. Other embodiments of the parallel-L circuit 280 may include wire bonding only or integrated inductors only. Additionally, the physical components of the inductors in the parallel-L circuit 280 may include any combination of inductor components selected from one or more integrally formed inductors, one or more sets of bonded wires, and / or one or more discrete inductors. Furthermore, the inductor components of the parallel-L circuit 280 may be interconnected using any series and / or parallel arrangement to achieve the desired total inductance value of the parallel inductors in the parallel-L circuit 280. Similarly, the physical components of the capacitors in the parallel-L circuit may include any combination of capacitor components selected from one or more integrally formed capacitors and / or one or more discrete capacitors. Furthermore, the capacitor components of the parallel-L circuit 280 may be interconnected using any series and / or parallel arrangement to achieve the desired total capacitance value of the parallel capacitors in the parallel-L circuit 280.

[0111] As previously described, embodiments of the Dougherty amplifier ICs 200 and 300 may also include one or more video bandwidth (VBW) circuits 286 coupled between the combined node structure 264 and a ground reference (e.g., Figure 1 VBW circuit 186). In Figure 2 and 3 In the illustrated embodiment, VBW circuit 286 is electrically coupled to node 285 in parallel-L circuit 280. According to one embodiment, and as shown in the circuit diagram adjacent to VBW circuit 286, VBW circuit 286 may include a series circuit comprising multiple components, and more specifically, components series coupled at node 285 to a ground reference (e.g., ...). Figure 4The resistors (or resistors), inductors (or inductors), and capacitors (or capacitors) between layers 428. In other embodiments, one or more VBW circuits 286 may be coupled to one or more different nodes (e.g., one or more drain terminals 231, 251, one or more gate terminals 225, 245, or other locations). Multiple VBW circuits may also be coupled at multiple points along each amplification path.

[0112] In some embodiments, some or all of the components of VBW circuit 286 may be integrated or integrally formed with dies 201 and 301, and / or some or all of the components of VBW circuit 286 may be discrete components connected to the top surface of dies 201 and 301. Alternatively, only some of the components of VBW circuit 286 (e.g., resistors and / or inductors) may be integrally formed with or connected to dies 201 and 301, while other components (e.g., capacitors) may be implemented off-chip and electrically connected via conductive connections (e.g., wire bonding). In other embodiments, substantially all of the VBW circuitry may be implemented off-chip (i.e., all or part of VBW circuit 296 may be provided with circuitry not integrated with dies 201 and 301). For example, in an alternative embodiment, node 285 may be electrically connected to lead 287 (e.g., by wire bonding, as shown), and all or part of VBW circuit 286 (i.e., at least one of the resistors, inductors, and / or capacitors of VBW circuit) may be implemented using external circuitry coupled to lead 287.

[0113] Dougherty power amplifier ICs 200 and 300, and more specifically, dies 201 and 301, can be packaged and / or incorporated into larger electrical systems in a variety of ways. For example, Dougherty dies 201 and 301 can be packaged in molded or cavity power device packages (e.g., Figure 5 The Dougherty dies 201 and 301 may be encapsulated in a surface-mount package, such as a leadless package (e.g., a dual-plane leadless (DFN) or quad-plane leadless (QFN) package). In other embodiments, the Dougherty dies 201 and 301 may be directly mounted to the surface of a module or PCB substrate.

[0114] By example Figure 5 This is a top view of a Dougherty amplifier device 500 according to an example embodiment, the Dougherty amplifier device 500 including a Dougherty die 501 (e.g., encapsulated in a high-power discrete device package 504) Figure 2 201 or Figure 3 Die 301). Die 501 includes the following integrated circuits: main amplifier (e.g., Figure 2 , 3The main amplifier 220), peak amplifier (e.g., Figure 2 , 3 Peak amplifier 240), phase shifter / impedance inverter circuit (e.g., Figure 2 , 3 Phase shifter / impedance inverter 260), combined node structure (e.g., Figure 2 , 3 Combination node structure 264) and parallel-L circuit (e.g., Figure 2 , 3 Parallel-L circuit 280). In some embodiments, die 501 may also include an integrated signal distributor (e.g., Figure 2 The signal distributor 204) and / or VBW circuit (e.g., Figure 2 , 3 The VBW circuit 286), while in other embodiments, the signal distributor and / or VBW circuit may be implemented outside the die and / or outside the device 500.

[0115] Package 504 includes a plurality of conductive input signal and bias leads 514, 516, 517, 518 (e.g., leads 214, 216, 217, 218, 314, 315) and at least one output lead 594 (e.g., ...). Figure 2 , 3 (lead 294). In some embodiments, package 504 may also include one or more additional bias or other leads. For example, package 504 may include VBW lead 587 (e.g., Figure 2 , 3 The VBW lead 587 facilitates electrical connection between die 501 and one or more components of a VBW circuit mounted to a PCB or other substrate (not shown) on which package 504 is mounted. Input signal and bias leads 514, 516, 517, 518 are located on the input side of package 504, and at least one output lead 594 and VBW lead 587 (if included) are located on the output side of package 504. In one embodiment, the input side of Dougherty die 501 (e.g., ...) Figure 2 , 3 The input side 210 is close to and parallel to the input side of the device package 504.

[0116] According to one embodiment, package 504 includes a package substrate, such as a conductive flange 530, to which a Dougher die 501 (e.g., using conductive epoxy, solder, brazing, sintering, or other conductive connection methods) is physically and electrically connected. Finally, package 504 includes non-conductive structural features or materials, such as molding compound and / or other insulating materials, which hold leads 514, 516, 517, 518, 587, 594 and flange 530 in an orientation fixed relative to each other.

[0117] Conductive connections, such as conductive wires, electrically connect the input signal and bias voltage bonding pads (or terminals) on die 501 to conductive leads 514, 516, 517, and 518 on the input side of package 504. For example, one or more first bonding wires 519 can electrically connect the input RF signal lead 514 to the corresponding input terminal (e.g., ...). Figure 2 The first bonding pad of the input terminal 202) and the input RF signal lead 514 can be used to transmit the input RF signal to the Dougher die 501. In the signal distributor (e.g., Figure 2 In alternative embodiments where the distributor 204 is not implemented in die 501, separate leads (e.g., Figure 3 Leads 314 and 315 can be used to provide the main RF signal and peaked RF signal to two bonding pads on die 501, wherein the first bonding pad corresponds to the input of the main amplifier (e.g., Figure 2 The second bonding pad corresponds to the input terminal 302 of the peak amplifier (e.g., the input terminal 302), and the second bonding pad corresponds to the input terminal of the peak amplifier (e.g., the input terminal 302 of the peak amplifier). Figure 2 Input terminal 302'). As mentioned above... Figure 2 The bias circuit on the Dougherty die 501 discussed (e.g., Figure 2 , 3 The bias circuits 270, 270', 277) can be electrically connected to the bias leads 516-518 via additional solder wires (unnumbered). Figure 2 , 3 The bias leads 216-218). According to one embodiment, the output of the Dougherty die 501 (and more specifically, Figure 2 , 3 The combined node structure 264) uses multiple bonding lines (e.g., Figure 2-4 The solder wire 290 is electrically connected to the output lead 594.

[0118] In some embodiments, leads 514, 516-518, 587, 594 and flange 530 may form part of a lead frame. To complete the encapsulation during device manufacturing, after the attachment of die 501 and the interconnection of the leads with the bonding wires between the leads and die 501, the inner ends of die 501, leads 514, 516-518, 587, 594, the bonding wires, and the upper and side surfaces of flange 530 may be sealed with non-conductive (e.g., plastic) molding materials 540, 542. Figure 5 Only a portion is shown to avoid obscuring the internal components of device 500. Molding materials 540 and 542 define the boundaries of device 500, from which leads 514, 516-518, 587, and 594 protrude, and the molding materials 540 and 542 also define the top surface of device 500. The bottom surface of device 500 is partially defined by molding material 540 and partially by the bottom surface of flange 530. Therefore, when properly coupled to a system substrate (e.g., Figure 6 When using PCB 610, flange 530 can be used (e.g., via...) Figure 4 The bottom conductive layer 428) transmits the ground reference to the die 501 and can also be used as a heat sink for the device 500.

[0119] In similar but different embodiments, having Figure 5 The leads 514, 516-518, 587, and 594 shown can be replaced with solder pads of a leadless package. The flange 530 and the solder pads can be re-formed into a lead frame, with the die 501 and the solder wires attached to the lead frame, and the assembly can be re-sealed with a non-conductive molding compound to form a leadless surface mount device (e.g., a DFN or QFN device).

[0120] In other embodiments, the package 504 may be a cavity package. In this embodiment, the flange 530 may have a larger boundary, which is equal to or approximately equal to the boundary of the device 500. A non-conductive insulator (e.g., ceramic, plastic, or other material) having a frame shape may be attached to the top surface of the flange, leads 514, 516-518, 587, 594 may be placed on the non-conductive insulator with attached bonding wires, and a cap (not shown) may be placed over the frame opening to enclose the internal components of the device 500 within the cavity.

[0121] although Figure 5A Dougherty amplifier device 500 is shown, comprising a single Dougherty amplifier die 501 and corresponding leads. However, other embodiments of the Dougherty amplifier device may include multiple Dougherty amplifier dies placed side-by-side (e.g., multiple instances of dies 201, 301, 501), with corresponding sets of leads associated with each die. Using such a device, output RF signals from multiple Dougherty amplifier dies can be combined (e.g., on a PCB to which the Dougherty amplifier device is coupled), for example, using a 3-dB coupler or other means.

[0122] Ultimately, the Dougherty amplifier unit 500 is integrated into a larger electrical system (e.g., a power transmitter array in a cellular base station). For example, as... Figure 6 As shown, the Dougherty amplifier device 620 can be coupled to a system substrate (such as a single-layer or multi-layer PCB 601) to enable the Dougherty amplifier device 620 (e.g., Figure 5 The device 500 is incorporated into the amplifier system 600. In one embodiment, the Dougherty amplifier device 620 includes a plurality of input-side leads 610 and output leads 694 (e.g., Figure 2-5 Leads 294, 594), which are configured to have conductive features on PCB 601 and a die enclosed within device 620 (e.g., Figure 2 , 3 The bias voltage and RF signal are transmitted between the dies 201 and 301.

[0123] In one embodiment, PCB 601 may be a single-layer or multi-layer PCB, and multiple components are coupled to PCB 601. According to one embodiment, a conductive coin 602 (or other feature) is embedded within PCB 601, and the top and bottom surfaces of the conductive coin 602 are exposed to the top and bottom surfaces of PCB 601, respectively. Dougherty amplifier device 620 (e.g., Figure 5 The device 500 is connected to the conductive coin 602. More specifically, the bottom surface of the Dougherty amplifier device 620 (e.g., Figure 5 The bottom of the flange 530 can be physically and electrically connected to the top surface of the conductive coin 602. The conductive coin 602 can then be electrically connected to the system ground, and the bottom surface of the coin 602 can be physically connected to the system heat sink. Therefore, the conductive coin 602 can be used as a ground reference and heat sink for the amplifier system 600.

[0124] In a typical configuration, amplifier system 600 includes an input RF connector 603 and an output RF connector 604 coupled to PCB 601, which are respectively configured to receive an input RF signal from an RF signal source and generate an amplified output RF signal for transmission to a load (e.g., ...). Figure 1The load 196 may be a cellular antenna coupled to connector 604.

[0125] PCB 601 includes multiple conductive paths 605, 606, 607, and 640 electrically coupled between input and output RF connectors 603 and 604 and the Dougherty amplifier device 620. Additional conductive paths 616, 617, 618, and 642 can be used to transfer DC gate and drain bias voltages from bias voltage connectors 650, 651, and 652 to device 620. For example, conductive paths and features 605-607, 616-618, 640, and 642 can be formed from patterned portions of the top conductive layer, bottom conductive layer, and / or one or more internal conductive layers (if included) of PCB 601.

[0126] In the illustrated embodiment, a first conductive path 605 electrically connects an input RF connector 603 to an input of a signal distributor 630, which is configured to split the input RF signal transmitted via path 605 into a first RF signal and a second RF signal (e.g., corresponding to a main input RF signal and a peaked input RF signal). The first and second RF signals are generated at two outputs of the signal distributor 630 and are transmitted to a first RF input lead 614 and a second RF input lead 615 of a Dougherty amplifier device 620 via a second conductive path 606 and a third conductive path 607, respectively. According to one embodiment, the signal distributor 630 generates the first and second RF signals such that they have a phase difference of approximately 90 degrees. In other embodiments, the phase difference may be applied by circuitry different from that of the signal distributor 630.

[0127] The Dougherty amplifier device 620 in the illustrated embodiment corresponds to including a Dougherty amplifier die (e.g., Figure 3 The device of the Dougherty amplifier die 301, wherein the Dougherty amplifier die does not include an integrated signal distributor (e.g., Figure 2 The signal distributor 204). Conversely, in the illustrated embodiment, the input RF signal is split into a first RF signal and a second RF signal (e.g., a main RF signal and a peaked RF signal) using a signal distributor 630. In an alternative embodiment, the Dougherty amplifier device 620 may include a Dougherty amplifier die (e.g., Figure 2 The Dougherty die 201), the Dougherty amplifier die including an integrated signal distributor (e.g., Figure 2 In the case of distributor 204, signal distributor 630 can be excluded from system 600, and input RF connector 603 can be directly connected to a single input lead (e.g., lead 214, 614) via a single conductive path.

[0128] As discussed in detail above, the Dougherty amplifier die (e.g., within the Dougherty amplifier assembly 620) Figure 2-5 The dies 201, 301, and 501 amplify one or more input RF signals to output a signal at lead 694 (e.g., ...). Figure 2-5 An amplified output RF signal is generated at leads 294 and 594. An additional conductive path 640 on PCB 601 electrically connects the output RF signal lead 694 of the Dougherty amplifier device 620 to the output RF connector 604. Therefore, during operation of system 600, the amplified RF signal generated by the Dougherty amplifier device 620 is transmitted to the output RF connector 604 via conductive path 640.

[0129] As previously mentioned, Dougherty amplifier dies (e.g., Figure 2-5 The dies 201, 301, and 501 may or may not include integrated VBW circuitry (e.g., Figure 2 , 3 VBW circuit 286). In Figure 6 In the illustrated embodiment, the Dougherty amplifier die within the Dougherty amplifier device 620 does not include integrated VBW circuitry. Instead, the Dougherty amplifier device 620 includes VBW leads 687 (e.g., Figure 2-5 The VBW leads 287 and 587, and the VBW circuit 686 implemented on PCB 601. For example, the VBW circuit 686 may include a resistor, an inductor, and a capacitor series coupled between the VBW lead 687 and a ground reference.

[0130] Figure 7 This refers to the manufacture of a Dougherty power amplifier die according to an example embodiment (e.g., Figure 2-5 Doherty amplifier chips 201, 301, 501), and packaged Doherty amplifier devices (e.g., Figure 5 The device 500) and the Dougherty amplifier system (e.g., Figure 6 A flowchart of a method for a system 600. The method can be implemented in block 702 by forming an amplifier die (e.g., ...). Figure 2-5 Starting with dies 201, 301, and 501, the amplifier die includes an integrated main amplifier (e.g., Figure 2 , 3 The main amplifier 220), and the integrated peak amplifier (e.g., Figure 2 , 3 Peak amplifier 240), integrated phase shifter / impedance inverter circuit (e.g., Figure 2 , 3 Phase shifter / impedance inverter 260), integrated combined node structure (e.g., Figure 2 , 3Combination node structure 264) and integrated parallel-L circuit (e.g., Figure 2 , 3 Parallel-L circuit 280). Additionally, the amplifier die may include an integrally formed or integrated power divider (e.g., Figure 2 The allocator 204), the matching network (e.g., Figure 2 , 3 IMN222, 242, ISMN 228, 248), bias circuits (e.g., Figure 2 , 3 Bias circuits 270, 270', 277), and one or more VBW circuits (e.g., Figure 2 , 3 (VBW circuit 286) and / or other integrated components. In alternative embodiments, some of the circuits and components mentioned above may be implemented on a substrate different from that of the amplifier die.

[0131] In box 704, integrated bonding wires are coupled between the bonding pads of the die (e.g., Figure 2 , 3 The bonding wires 261, 282) and / or coupling discrete components to the top surface of the die to complete the Dougherty amplifier die (e.g., Figure 2-5 Doherty amplifier chips 201, 301, and 501.

[0132] Then, the Dougherty amplifier die (e.g., Figure 2-5 The Dougherty amplifier die (201, 301, 501) can be packaged in frame 706. As previously mentioned, the Dougherty amplifier die can be packaged in a molded or cavity package. Alternatively, the Dougherty amplifier die can be attached as a bare die to a system substrate (e.g., a module or PCB substrate). When packaged in a molded package (e.g., Figure 5 When packaged in a cavity package (504), the Dougherty amplifier die can be connected to the conductive flange of the lead frame, and wire bonding can be coupled between the input, output, and bias leads of the lead frame and the appropriate bonding pads of the Dougherty amplifier die, and the flange, leads, and Dougherty amplifier die can be sealed in molding material. When packaged in a cavity package, the insulator frame can be attached to the top surface of the conductive flange, the Dougherty amplifier die can be connected to the top surface of the flange in the frame opening, the input, output, and bias leads can be connected to the top surface of the insulator frame, wire bonding can be coupled between the input, output, and bias leads and the appropriate bonding pads of the Dougherty amplifier die, and caps can be applied to the flange, insulator frame, leads, wire bonding, and Dougherty amplifier die to enclose the Dougherty amplifier die in a cavity.

[0133] In box 708, the amplifier system (e.g., Figure 6System 600) can be used by using a Doherty amplifier device (e.g., Figure 5 The device 500 (or in some embodiments, a bare die) is attached to a system substrate, such as a PCB (e.g., Figure 6 (PCB 601). More specifically, the bottom surface of the Dougherty amplifier device can be connected to a conductive coin (e.g., Figure 6 Coin 602) is used to provide a ground reference and heat sink for the device, and the input, output, and bias leads of the device can be connected to the corresponding conductive paths of the system substrate (e.g., Figure 6 Paths 605-607, 616-618, 640.

[0134] According to one embodiment, in block 710, additional components (e.g., Figure 6 The distributor 630 and / or VBW circuit 686) can be coupled to the system substrate (e.g., Figure 6 The amplifier system is then completed using PCB 601. The method can then conclude.

[0135] The embodiment includes a multiplexer comprising a semiconductor die, a first transistor integrally formed with the semiconductor die, a second transistor integrally formed with the semiconductor die, a combined node structure integrally formed with the semiconductor die, and a parallel inductor circuit. The outputs of the first transistor and the second transistor are electrically coupled to the combined node structure. The parallel inductor circuit is electrically coupled between the combined node structure and a ground reference node, and the parallel inductor circuit includes a parallel inductor integrated with the semiconductor die.

[0136] According to another embodiment, the parallel inductor circuit includes a first integrated inductor comprising a set of bonding wires, wherein each bonding wire has a first end and a second end respectively connected to a first bonding pad and a second bonding pad exposed on the top surface of the semiconductor die. According to yet another embodiment, the parallel inductor circuit further includes a second integrated inductor comprising one or more spiral inductors integrally formed with the semiconductor die and coupled in series with the first integrated inductor between the combined node structure and the ground reference node.

[0137] According to another embodiment, the parallel inductor and the second drain-source capacitor resonate at a frequency below the operating band of the multiplexer.

[0138] According to another embodiment, the multiplexer further includes an integrated phase shifter / impedance inverter coupled between the outputs of the first transistor and the second transistor, wherein the integrated phase shifter / impedance inverter is configured to apply a 90-degree phase delay between the intrinsic drains of the first transistor and the second transistor.

[0139] Another embodiment includes a Dougherty amplifier with a main amplifier transistor, a peak amplifier transistor integrally formed with a semiconductor die, a combined node structure integrally formed with a semiconductor die, and a parallel inductor circuit electrically coupled between the combined node structure and a ground reference node. The drain terminals of the main transistor and the peak amplifier transistor are electrically coupled to the combined node structure, and the parallel inductor circuit includes a parallel inductor integrated with the semiconductor die.

[0140] According to another embodiment, the parallel inductor includes one or more components integrated with the semiconductor die, wherein the one or more components are selected from a set of integrated bonding wires, one or more integrated spiral inductors, and one or more discrete inductors coupled to the top surface of the semiconductor die.

[0141] According to another embodiment, the main amplifier transistor is integrally formed with the semiconductor die, and the Dougherty amplifier further includes an integrated phase shifter / impedance inverter coupled between the outputs of the main amplifier transistor and the peak amplifier transistor, wherein the integrated phase shifter / impedance inverter is configured to apply a 90-degree phase delay between the intrinsic drains of the main amplifier transistor and the peak amplifier transistor.

[0142] The connecting lines shown in the various figures included herein are intended to illustrate exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be limiting, and the terms “first,” “second,” and other such numerical terms relating to structures do not imply a sequence or order unless the context clearly indicates otherwise.

[0143] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., that has a given signal, logic level, voltage, data mode, current, or quantity. Furthermore, two or more nodes can be implemented using a single physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even if received or output at a common node).

[0144] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless explicitly stated otherwise, "connected" means that one element is directly and not necessarily mechanically linked to (or directly connected to) another element. Similarly, unless explicitly stated otherwise, "coupled" means that one element is directly or indirectly and not necessarily mechanically connected to (or directly or indirectly connected to) another element via electrical or other means. Therefore, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0145] As used herein, “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary or illustrative is not necessarily to be construed as preferred or superior to other embodiments. Furthermore, it is not intended to be construed as being bound by any represented or implied theory presented in prior art, background art, or detailed description.

[0146] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing one or more of the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including known and foreseeable equivalents at the time of filing this patent application.

Claims

1. A multiplexer, characterized in that, include: Semiconductor die; The first transistor is integrally formed with the semiconductor die; The second transistor is integrally formed with the semiconductor die; A combined node structure is integrally formed with the semiconductor die, wherein the outputs of the first transistor and the second transistor are electrically coupled to the combined node structure; as well as A parallel inductor circuit, electrically coupled between the combined node structure and the ground reference node, wherein the parallel inductor circuit includes a parallel inductor integrated with the semiconductor die. The parallel inductor circuit includes: A first integrated inductor, comprising a set of bonding wires, wherein each bonding wire has a first end and a second end respectively connected to a first bonding pad and a second bonding pad, the first bonding pad and the second bonding pad being exposed on the top surface of the semiconductor die, and The second integrated inductor includes one or more spiral inductors, which are integrally formed with the semiconductor die and are coupled in series with the first integrated inductor between the combined node structure and the ground reference node.

2. The multiplexer according to claim 1, characterized in that, The combined node structure is tightly electrically coupled to the output of the second transistor.

3. The multiplexer according to claim 1, characterized in that, The parallel inductor circuit includes: One or more integrated inductors; and A capacitor, which is electrically connected between the one or more integrated inductors and the ground reference node.

4. The multiplexer according to claim 3, characterized in that, In addition, including: Radio frequency (RF) cold spot node, the RF cold spot node being located between the one or more integrated inductors and the capacitor; and A video bandwidth circuit, which is electrically coupled to the radio frequency cold spot node.

5. The multiplexer according to claim 4, characterized in that, The video bandwidth circuit includes: Resistors, inductors, and capacitors coupled in series.

6. The multiplexer according to claim 5, characterized in that, At least one of the resistor, the inductor, and the capacitor is integrated with the semiconductor die.

7. The multiplexer according to claim 5, characterized in that, At least one of the resistor, the inductor, and the capacitor is implemented off-chip and electrically coupled to the RF cold spot node via wire bonding.

8. A Dougherty amplifier, characterized in that, include: Main amplifier transistor; A peak amplifier transistor, wherein the peak amplifier transistor is integrally formed with a semiconductor die; A combined node structure is integrally formed with the semiconductor die, wherein the drain terminals of the main amplifier transistor and the peak amplifier transistor are electrically coupled to the combined node structure; as well as A parallel inductor circuit, electrically coupled between the combined node structure and the ground reference node, wherein the parallel inductor circuit includes a parallel inductor integrated with the semiconductor die. The parallel inductor circuit includes: A first integrated inductor, comprising a set of bonding wires, wherein each bonding wire has a first end and a second end respectively connected to a first bonding pad and a second bonding pad, the first bonding pad and the second bonding pad being exposed on the top surface of the semiconductor die, and The second integrated inductor includes one or more spiral inductors, which are integrally formed with the semiconductor die and are coupled in series with the first integrated inductor between the combined node structure and the ground reference node.

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