Hybrid driver with low output pad capacitance

Abstract

Embodiments of the present application relate to a hybrid driver with low output pad capacitance. The hybrid driver receives complementary high-speed input data signals and paired low-speed input data signals, selects a pair of input data signals from the paired input data signals, and drives output data signals on a first output node and a second output node based on the selected pair of input data signals. The hybrid driver includes a first driver circuit and a second driver circuit coupled to the first output node and the second output node, respectively. Each driver circuit includes a first series transistor and a second series transistor coupled between a first supply voltage node and a reference voltage node, wherein the interconnection of the first series transistor and the second series transistor is coupled to a corresponding first output node or a second output node. Each first driver circuit and the second driver circuit include a third transistor coupled in parallel with the corresponding first transistor. In response to the corresponding low-speed input data signal, each first transistor and the third transistor couples the corresponding output node in parallel to the second supply voltage node.

Description

Technical Field

[0001] The present application is generally directed to output drivers and, more particularly, to a hybrid transmitter or driver for providing low-speed signals and high-speed differential signals with reduced output pad capacitance. Background Art

[0002] Conventional hybrid drivers include high-speed differential signaling circuits for providing high-speed differential signals, such as scalable low voltage signals (SLVS), in a high-speed operating mode. These high-speed differential signals are provided on paired output pads. The hybrid driver also includes a low-speed signaling circuit system coupled to these output pads. In the low-speed operating mode, the low-speed signaling circuit system provides low-speed signals, such as low-voltage complementary metal oxide semiconductor (LVCMOS) signals, on the output pads. A hybrid driver that provides this type of dual signaling functionality is required under a variety of communication standards, such as embedded universal serial bus (eUSB) specifications or standards, which require the driver to provide low-speed low-voltage signals (such as LVCMOS signals) and high-speed differential signals (such as SLVS signals). Therefore, the driver must include LVCMOS circuit systems and SLVS circuit systems coupled in parallel to drive the output pads in both high-speed and low-speed operating modes. This combination of SLVS circuitry and LVCMOS circuitry coupled in parallel to the output pads increases the capacitance of each of these output pads, which adversely affects the performance of hybrid driver 100 in high-speed operating modes because the SLVS circuitry is very sensitive to variations in output pad capacitance. Accordingly, a need exists for improved hybrid drivers. Summary of the Invention

[0003] Embodiments of the present invention are directed to hybrid transmitters or drivers for transmitting signals via various standards, such as eUSB, that require both low-speed, low-voltage CMOS (LVCMOS) signaling and high-speed differential signaling, such as scalable low-voltage signaling (SLVS). However, rather than simply using parallel-coupled LVCMOS and SLVS circuitry, embodiments of the present invention utilize simplified circuitry that provides the required dual signaling functionality while reducing the capacitance of the driver's output pads that provide these signals. This reduced capacitance improves the high-speed operation of the hybrid driver's SLVS circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For a better understanding of the present disclosure, embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which:

[0005] Figure 1 is a schematic diagram of a hybrid driver for providing high-speed signals and low-speed signals with reduced output pad capacitance according to a first embodiment of the present disclosure;

[0006] Figure 2 is a schematic diagram of a hybrid driver for providing high-speed signals and low-speed signals with reduced output pad capacitance according to another embodiment of the present disclosure; and

[0007] Figure 3 The invention includes a Figure 1 and Figure 2 Functional block diagram of an electronic system of one or more hybrid drive electronic devices. DETAILED DESCRIPTION

[0008] Figure 1 FIG1 is a schematic diagram of a hybrid driver 100 for providing high-speed differential output signals and low-speed output signals with reduced capacitance on output pads OUTP, OUTN according to a first embodiment of the present disclosure. Rather than simply coupling high-speed and low-speed driver circuits in parallel to these output pads OUTP, OUTN as in conventional hybrid drivers, hybrid driver 100 according to an embodiment of the present disclosure includes simplified circuitry that provides the required dual signaling functionality while reducing capacitance at each output pad OUTP, OUTN and thereby improving the high-speed operation of the hybrid driver, as will be described in more detail below.

[0009] In this description, certain details are set forth in conjunction with the described embodiments to provide a full understanding of the present disclosure. However, it will be understood by those skilled in the art that embodiments of the present invention may be practiced without these specific details. In addition, it will be understood by those skilled in the art that the present disclosure is not limited to the example embodiments described herein, and it will also be understood that various modifications, equivalents and combinations of the disclosed embodiments, and components of such embodiments are within the scope of the present disclosure. Although not explicitly described below, embodiments comprising less than all components of any described embodiment may also be within the scope of the present invention. In order to avoid unnecessarily obscuring the present invention, the operation of well-known components and / or processes is not shown or described in detail below. Finally, in this application, even if the detailed operation of such components may be different in various embodiments, common components in the described embodiments are given the same figure marks or descriptors.

[0010] As used herein, the terms "high speed" and "low speed" are used with respect to the data rate of associated signals. Accordingly, the data transmission rate of the high-speed differential signal discussed herein is greater than the data transmission rate of the low-speed signal. For example, the high-speed differential signal can be a signal transmitted according to low voltage differential signaling (LVDS) (such as scalable low voltage signaling (SLVS)), wherein such a signal can have a data transmission rate of, for example, 6 Gb / s (Gps). The low-speed signal herein can, for example, be a low voltage complementary metal oxide semiconductor (LVCMOS) signaling with a data transmission rate of, for example, 12 Mb / s (Mbps). These signaling types for high-speed differential signaling and low-speed signaling are merely examples, and these signals are not limited to these specific types of signaling in the embodiments of the present invention.

[0011] When operating in high-speed mode, the hybrid driver 100 receives high-speed differential input data signals HS_INP and HS_INN and drives corresponding high-speed differential output data signals on output pads OUTP and OUTN. Those skilled in the art will appreciate that the high-speed differential input signals HS_INP and HS_INN and the output signals are complementary signals. When operating in low-speed mode, the hybrid driver 100 receives independent low-speed data input signals CMOS_INP_DP and CMOS_INP_DN and drives corresponding low-speed data output signals on output pads OUTP and OUTN. The CMOS_INP_DP and CMOS_INP_DN signals can be independently selected in low-speed mode, as will be described in detail below.

[0012] The hybrid driver 100 includes two driver circuits 102A and 102B, wherein the driver circuit 102A receives high-speed differential input signals HS_INP, HS_INN and low-speed data input signals CMOS_INP_DP, and drives the output pad OUTP in response to these signals. Similarly, the driver circuit 102B receives high-speed differential input signals HS_INP, HS_INN and low-speed data input signals CMOS_INP_DN, and drives the output pad OUTN in response to these signals. Each driver circuit 102A, 102B includes a high-speed differential driver circuit 103A, 103B having a first transistor 104A, 104B, which is coupled in series with a first resistor R1 between a first supply voltage node 105 receiving a first supply voltage VDRV or a second supply voltage VPDRV and the corresponding output nodes OUTP, OUTN. Figure 1 In FIG, a first supply voltage node receiving a supply voltage VDRV or VPDRV is shown as VDRV / VPDRV. Figure 1In an embodiment, the second transistors 106A, 106B are coupled in series with the second resistor R2 between the output nodes OUTP, OUTN and a reference voltage node receiving a reference voltage GND. The supply voltage VDRV / VPDRV depends on the operating mode of the hybrid driver 100. In a high-speed operating mode, the first supply voltage node receives a first supply voltage VDRV, which in one embodiment has a value of 400 millivolts (mv). In a low-speed operating mode, the first supply voltage node receives a second supply voltage VPDRV, which in one embodiment has a value of 1.2 volts. Figure 1 In the embodiment of FIG. 5 , the first transistors 104A, 104B and the second transistors 106A, 106B are NMOS transistors.

[0013] Each driver circuit 102A, 102B further includes a low-speed driver circuit 108A, 108B, wherein each low-speed driver circuit has a third transistor 110A, 110B coupled in parallel with the corresponding first transistor 104A, 104B. Figure 1 In the embodiment, the third transistors 110A and 110B are PMOS transistors. The single third transistors 110A and 110B are the only additional components coupled to the output nodes OUTP and OUTN to provide the hybrid driver 100 with low-speed operating mode functionality. The single third transistors 110A and 110B do not add significant capacitance to each output node OUTP and OUTN, thereby improving the operation of the hybrid driver 100 in the high-speed operating mode. Conventional hybrid drivers couple the output of a separate low-speed driver to each output node OUTP and OUTN to drive these nodes in the low-speed operating mode. These conventional drivers include multiple components coupled to each output pad OUTP and OUTN, and these multiple components add capacitance to the output nodes OUTP and OUTN, which is important for the data transmission rate required by the high-speed differential signals transmitted by the hybrid driver 100.

[0014] Each low-speed driver circuit 108A, 108B further includes a pass gate 112A, 112B having an output node coupled to the control node of the corresponding third transistor 110A, 110B, and an input node coupled to receive the corresponding drive control signal PDRV_INN_L, PDRV_INN_R. The control node of each pass gate 112A, 112B receives a corresponding select signal SEL_DP.ZOUT, SEL_DN.ZOUT to control activation and deactivation of the pass gate. As will be appreciated by those skilled in the art, in response to activating the select signal SEL_DP.ZOUT, SEL_DN.ZOUT corresponding to the pass gate 112A, 112B, the pass gate couples the corresponding input node and output node together. In response to deactivating the select signal SEL_DP.ZOUT, SEL_DN.ZOUT corresponding to the pass gate, each pass gate 112A, 112B isolates the corresponding input and output nodes.

[0015] The low speed driver circuits 108A, 108B each further include a fourth transistor 114A, 114B coupled between a second supply voltage node 115 receiving the second supply voltage VPDRV and a control node of the third transistor 110A, 110B. Figure 1 In the embodiment of the present invention, the fourth transistors 114A, 114B are PMOS transistors. Each of the fourth transistors 114A, 114B receives a corresponding selection signal SEL_DP.ZOUT, SEL_DN.ZOUT on a control node and is used to turn off the third transistor when the pass gates 112A, 112B are disabled. More specifically, in Figure 1 In one embodiment, when select signals SEL_DP.ZOUT and SEL_DN.ZOUT are low, pass gates 112A and 112B are turned off, isolating the corresponding drive control signals PDRV_INN_L and PDRV_INN_R from third transistors 110A and 110B. In the absence of fourth transistors 114A and 114B, control nodes 110A and 110B of the third transistors would float when pass gates 112A and 112B are turned off. In this case, low select signals SEL_DP.ZOUT and SEL_DN.ZOUT turn on corresponding fourth transistors 114A and 114B, driving the control nodes of corresponding third transistors 110A and 110B to approximately the second supply voltage VPDRV, thereby turning off the third transistors.

[0016] Each driver circuit 102A, 102B also includes a corresponding logic circuit 115A, 115B coupled to the high-speed differential driver circuit 103A, 103B and the low-speed driver circuit 108A, 108B. Each logic circuit 115A, 115B receives first and second high-speed differential input signals HS_INP, HS_INN, and also receives a corresponding one of the low-speed input signals CMOS_INP_DP, CMOS_INP_DN. A mode select signal SEL_DP, SEL_DN is applied to each logic circuit 115A, 115B and has a value indicating either a high-speed operating mode or a low-speed operating mode. Each logic circuit 115A, 115B also receives an enable signal ZOUT to disable or enable the corresponding driver circuit 102A, 102B.

[0017] When the mode select signals SEL_DP and SEL_DN indicate a high-speed operating mode, logic circuits 115A and 115B generate drive control signals PDRV_INN_L and PDRV_INN_R, and also generate drive control signals PDRV_INP_L and PDRV_INP_R for activating and deactivating first transistors 104A and 104B and second transistors 106A and 106B in response to first and second high-speed differential input signals HS_INP and HS_INN. In high-speed mode, enable signal ZOUT is also activated to enable driver circuits 102A and 102B, and mode select signals SEL_DP and SEL_DN are also activated, as will be described in more detail below. These activated select signals SEL_DP and SEL_DN turn on fourth transistors 114A and 114B, thereby deactivating third transistors 110A and 110B. Therefore, in this high-speed mode, the logic circuits 115A and 115B generate drive control signals PDRV_INN_L, PDRV_INN_R, PDRV_INP_L, and PDRV_INP_R, which are used to control the activation and deactivation of transistors 104A, 104B, 106A, and 106B in response to the high-speed differential input signals HS_INP and HS_INN, thereby driving the corresponding high-speed differential output signals on the output pads OUTP and OUTN.

[0018] When the mode select signals SEL_DP and SEL_DN indicate a low-speed operating mode, the logic circuits 115A and 115B generate drive control signals PDRV_INN_L, PDRV_INN_R, PDRV_INP_L, and PDRV_INP_R for activating and deactivating the first and third transistors 104A and 104B in parallel or activating the second transistors 106A and 106B in response to the corresponding low-speed input signals CMOS_INP_DP and CMOS_INP_DN. The level or value of each CMOS_INP_DP and CMOS_INP_DN signal determines whether the logic circuits 115A and 115B activate the corresponding second transistors 106A and 106B or the corresponding first and third transistors 104A and 104B in parallel, 110A and 110B, as will be described in more detail below.

[0019] exist Figure 1 In the embodiment of the present invention, the logic circuits 115A and 115B will now be described in more detail. Each of the logic circuits 115A and 115B includes a pair of inverting multiplexers 116A, 118A, 116B, and 118B for selecting between high-speed differential input signals HS_INP and HS_INN and low-speed input signals CMOS_INP and CMOS_INN in response to corresponding mode selection signals SEL_DP and SEL_DN. Each low-speed input signal CMOS_INP and CMOS_INN is applied directly to one input of the multiplexers 116A and 116B and is applied to the input of the multiplexers 118A and 118B through corresponding inverters 119A and 119B. In response to the SEL_DP and SEL_DN signals, the inverting multiplexers 116A, 118A and 116B, 118B provide a selected set of complementary input signals HS_INP, HS_INN and CMOS_INP, CMOS_INN to drive the AND gates 120A, 122A and 120B, 122B, thereby driving the gates of the first transistors 104A, 106A and the second transistors 104B, 106B. Each of the AND gates 120A, 120B, 122A, 122B receives the enable signal ZOUT along the output of a corresponding one of the inverting multiplexers 116A, 116B, 118A, 118B and generates drive control signals PDRV_INP_L, PDRV_INN_L, PDRV_INP_R, and PDRV_INN_R to control the corresponding transistors 104A, 104B, 106A, 106B and 110A, 110B based on the selected input signals HS_INP, HS_INN or CMOS_INP, CMOS_INN, as will be described in more detail below. Figure 1As shown, the inverting multiplexers 116A, 116B, 118A, 118B and the AND gates 120A, 120B, 122A, 122B are powered by the second supply voltage VPDRV.

[0020] The operation of driver circuit 102A in high-speed and low-speed operating modes will now be described in greater detail. The operation of driver circuit 102A to generate a high-speed differential output signal on output pads OUTP is identical to the operation of driver circuit 102B to generate a complementary high-speed differential output signal on output pads OUTN, and therefore, only the operation of driver circuit 102A will be described in greater detail below. Similarly, in low-speed operating mode, driver circuit 102B operates in the same manner as driver circuit 102A, and therefore, only the operation of driver circuit 102A will be described in greater detail below. In low-speed mode, input signals CMOS_INP_DP and CMOS_INP_DN are independent signals, rather than complementary signals as in high-speed mode, and therefore, both input signals can be high, both low, or have different voltage levels corresponding to different logic states.

[0021] In the high-speed operating mode of driver circuit 102A, mode select signal SEL_DP is low, causing inverting multiplexers 116A and 118A to select high-speed differential input signals HS_INP and HS_INN. Enable signal ZOUT is high, enabling AND gates 120A and 122A, and select signal SEL_DP.ZOUT is low, thereby turning off pass gate 112A and turning on fourth transistor 114A. Fourth transistor 114A drives the control node of third transistor 110A high, thereby turning off transistor 110A. Thus, as will now be described in greater detail, in the high-speed operating mode, first transistor 104A and second transistor 106A drive output pad OUTP in response to the level or value of input signals HS_INP and HS_INN. Also in the high-speed operating mode, as previously described, first supply voltage VDRV is provided to first power supply node 105.

[0022] In response to the low mode selection SEL_DP, inverting multiplexers 116A and 118A select high-speed differential input signals HS_INP and HS_INN. Multiplexers 116A and 118A provide inverted input signals HS_INP and HS_INN at their respective outputs. For the initial description of the operation of driver circuit 102A, it is assumed that the input signals HS_INP and HS_INN are high and low, respectively. Multiplexer 116A drives its output low accordingly because the HS_INP signal is high, and AND gate 122A receives this low output and the high ZOUT signal and accordingly drives the drive control signal PDRV_INN_L low at its output, thereby turning off transistor 106A. At the same time, because the HS_INN signal is low, multiplexer 118A drives its output high. Therefore, AND gate 120A receives the high output and high ZOUT signals from multiplexer 118A and accordingly drives the drive control signal PDRV_INP_L high at its output, turning on transistor 104A, thereby driving the output pad OUTP high to the first supply voltage VDRV.

[0023] In high-speed mode, when input signals HS_INP and HS_INN have complementary levels, i.e., low and high, driver circuit 102A operates as follows. Because the HS_INP signal is low, multiplexer 116A drives its output high, and AND gate 122A accordingly receives this high output and the high ZOUT signal and accordingly drives drive control signal PDRV_INN_L high at its output, turning on transistor 106A and thereby driving output pad OUTP to reference voltage GND via the turned-on transistor 106A. Simultaneously, because the HS_INN signal is high, multiplexer 118A drives its output low. Consequently, AND gate 120A receives the low output and the high ZOUT signal from multiplexer 118A and accordingly drives drive control signal PDRV_INP_L low at its output, thereby turning off transistor 104A.

[0024] In the low-speed operating mode of driver circuit 102A, mode select signal SEL_DP is high, causing inverting multiplexers 116A and 118A to select the low-speed input signal CMOS_INP_DP. Assuming driver circuit 102A provides the low-speed output signal on output pad OUTP, enable signal ZOUT is again high, enabling AND gates 120A and 122A. In the low-speed mode, select signal SEL_DP.ZOUT is now high, turning on pass gate 112A and turning off fourth transistor 114A. Accordingly, drive control signal PDRV_INN_L is provided through the turned-on pass gate 112A, thereby controlling third transistor 110A, as will be described in more detail below. As previously discussed, and as will now be described in more detail, in the low-speed mode, in response to the level or value of input signal CMOS_INP_DP, first transistor 104A and third transistor 110A drive output node OUTP in parallel, or second transistor 106A drives output pad OUTP. Also in the low speed operation mode, as described above, the second power supply voltage VPDRV is provided to the first power supply node 105 .

[0025] In response to the high mode select SEL_DP, inverting multiplexers 116A, 118A select the low-speed input signal CMOS_INP_DP, which is applied directly to multiplexer 116A and applied to multiplexer 118A through inverter 119A. Multiplexers 116A and 118A provide the corresponding inverted input signal CMOS_INP_DP and its complement at their respective outputs. For the initial description of the operation of driver circuit 102A, it is assumed that the input signal CMOS_INP_DP is high. Because the CMOS_INP_DP signal is high, multiplexer 116A drives its output low accordingly, and AND gate 122A receives this low output and the high ZOUT signal and accordingly drives the drive control signal PDRV_INN_L low at its output, thereby turning off transistor 106A.

[0026] At the same time, because the CMOS_INP_DP signal is high, multiplexer 118A drives its output high, which is inverted by inverter 119A and then inverted again by inverting multiplexer 118A to provide a high output from the multiplexer. Consequently, AND gate 120A receives the high output and high ZOUT signal from multiplexer 118A and, in response, drives the drive control signal PDRV_INP_L high at its output, thereby turning on transistor 104A. Additionally, the drive control signal PDRV_INN_L from AND gate 122A is supplied via the turned-on pass gate 112A to drive the control node of transistor 110A. The drive control signal PDRV_INN_L from AND gate 122A is low, thereby turning on transistor 110A. Therefore, when the CMOS_INP_DP signal is high, both transistors 110A and 104A are turned on to drive the output pad OUTP in parallel high to the second supply voltage VPDRV.

[0027] The operation of driver circuit 102A will now be described when input signal CMOS_INP_DP is low. In this case, because the CMOS_INP_DP signal is low, multiplexer 116A accordingly drives its output high. AND gate 122A receives this high output and the high ZOUT signal and accordingly drives drive control signal PDRV_INN_L high at its output, turning on transistor 106A and thereby driving output pad OUTP to reference voltage GND via the turned-on transistor 106A. Simultaneously, because the CMOS_INP_DP signal is low, multiplexer 118A drives its output low, which is inverted by inverter 119A and then further inverted by inverting multiplexer 118A to provide a low output from the multiplexer. Consequently, AND gate 120A receives the low output and the high ZOUT signal from multiplexer 118A and accordingly drives drive control signal PDRV_INP_L low at its output, thereby turning off transistor 104A. In addition, the drive control signal PDRV_INN_L from AND gate 122A is also provided through the turned-on pass gate 112A to drive the control node of transistor 110A. In this case, the drive control signal PDRV_INN_L from AND gate 122A is high, thereby turning off transistor 110A. Therefore, when the CMOS_INP_DP signal is low, both transistor 110A and transistor 104A are turned off, and transistor 106A is turned on, driving the output pad OUTP low to the reference voltage GND.

[0028] Now the operation of driver circuit 102A in high-speed operation mode and low-speed operation mode has been described in detail. The operation of driver circuit 102B is the same as that of driver circuit 102A, so it is not described in detail again. In addition, driver circuit 102B operates in high-speed mode in a complementary manner, so driver circuits 102A and 102B provide high-speed differential signals as complementary signals on output pads OUTP and OUTN. Therefore, in high-speed mode, if driver 102A drives output pad OUTP to high, driver 102B drives output pad OUTN to low, and vice versa, when driver 102A drives output pad OUTP to low, driver 102B drives output pad OUTN to high. In low-speed operation mode, low-speed input signals CMOS_INP_DP and CMOS_INP_DN are independent, rather than the complementary signals mentioned above. In this mode, drivers 102A, 102B operate as described above for driver 102A to drive corresponding output pads OUTP, OUTN based on the values ​​of corresponding received low-speed input signals CMOS_INP_DP and CMOS_INP_DN.

[0029] Figure 2 FIG. 3 is a schematic diagram of a hybrid driver 200 according to another embodiment of the present invention, wherein the hybrid driver 200 has reduced output pad capacitance on the output pads OUTP and OUTN. Figure 1 The drive 100, and in addition Figure 2 In addition to the PMOS transistors 210A-1 and 210B-1 in the embodiment, Figure 2 All components 202 to 218 correspond to Figure 1 Components 102 to 118 in. Figure 2 In the embodiment of FIG. 1 , the PMOS transistors 210A- 1 and 210B- 1 are coupled between the first supply voltage node 205 receiving the supply voltage VDRV / VPDRV and the output nodes OUTP and OUTN. Figure 1 The overall operation of the hybrid driver 200 and the individual operations of the components 202 to 218 are different from the PMOS transistors 210A, 210B, which are coupled across the drive transistors 204A, 204B. Figure 1 The corresponding components of the hybrid drive 100 are the same, and therefore, for the sake of brevity, will not be described in detail.

[0030] Figure 3 is a functional block diagram of an electronic system 300 including electronic devices 301 and 302, each of which includes a circuit according to an embodiment of the present invention. Figure 1 and Figure 2One or more of the hybrid drivers 100, 200. In one embodiment, the electronic devices 301, 302 are coupled via a communication link 303 that is an embedded universal serial bus (eUSB) communication link. In this embodiment, during the handshake process between the electronic devices 301, 302, the hybrid drivers 100, 200 drive the high-speed differential output signal or the low-speed output signal through the eUSB communication link 303. More specifically, the handshake process according to the eUSB standard is initiated when the USB cable is physically connected between the two electronic devices 301, 302. The handshake process exchanges information between the electronic devices 301, 302 to determine the capabilities of the two devices, and determines the signaling parameters of the high-speed differential output signal generated by the hybrid driver 100, 200 on the output pads OUTP, OUTN, so as to communicate with the eUSB receiver ( Figure 3 In the electronic device 301 , the communication subsystem 304 includes the hybrid drivers 100 and 200 and also includes a USB receiver for receiving signals from the hybrid drivers 100 and 200 in the electronic device 302 via the USB communication link 303 .

[0031] As an example, in Figure 3 The eUSB standard is used in an electronic system 300 that involves hybrid drivers 100, 200 included in electronic devices 301, 302. Embodiments of the hybrid driver programs 100, 200 are not limited to use in the eUSB standard, and in other embodiments of the present disclosure, the hybrid drivers described herein are used to generate output data signals for communication according to other communication standards. Figure 3 In the embodiment of FIG, electronic device 301 includes processing circuitry 305 that controls the overall operation of electronic device 301 and also executes applications or "apps" 306 that provide specific functionality to a user of electronic device 301. Electronic device 301 may be any type of electronic device, such as a smartphone, a wearable electronic device such as a heart rate or activity monitor, a laptop or tablet computer, etc. Figure 3 In an example embodiment, the electronic device 301 includes a power management subsystem 308 coupled to the processing circuit system 2304, and will typically include a battery for powering the electronic device and a control circuit system for controlling power-related operating modes of the electronic device (such as battery charging, power saving mode, etc.).

[0032] Electronic device 301 further includes visual components such as touch screen 310, which has a touch display (not shown) such as a liquid crystal display (LCD), and a touch panel (not shown) attached to or forming an integral part of the touch display. In operation, touch screen 310 senses a user's touch on electronic device 301 and provides the sensed touch information to processing circuit system 305, thereby allowing the user to interface with and control the operation of the electronic device. Processing circuit system 305 also controls touch screen 310 to display desired visual content on the touch display portion of the touch screen.

[0033] The electronic device 301 further includes a data storage portion or memory 312 coupled to the processing circuitry 305 for storing and retrieving data, including application programs 306 and other software executed on the processing circuitry and used by the electronic device 301 during operation. Examples of typical types of memory 312 include solid-state memory such as DRAM, SRAM, and FLASH, solid-state drives (SSDs), phase-change RAM (PCRAM), and may include any other type of memory suitable for the desired functionality of the electronic device 301.

[0034] Input devices 314 are coupled to processing circuitry 305 and may include a keypad (whether implemented through touch screen 310 or separately), a pressure sensor, an accelerometer, a microphone, a keyboard, a mouse, a digital camera for capturing still and video images, and other suitable input devices. Output devices 316 are coupled to processing circuitry 305 and may include, for example, audio output devices such as speakers, printers, vibration devices, etc. Communication subsystem 304 coupled to processing circuitry 305 includes a Figure 3 The hybrid drive 100, 200 of the exemplary embodiment of the present invention may include appropriate eUSB circuitry and may also include other types of communication circuitry, such as Wi-Fi, GPS, cellular, and Bluetooth circuitry, for providing corresponding functionality to the electronic device 301. These other types of communication circuitry may also be included with the hybrid drive 100, 200. Of course, the specific type and number of input devices 314, output devices 316, communication subsystem 304, and even the specific functionality of power management subsystem 308 will depend on the type of electronic device 301, which may be any appropriate type of electronic device.

[0035] Unless the context requires otherwise, throughout the specification and claims, the word "including" and variations such as "comprising" and "having" should be construed as having an open and inclusive meaning, i.e., "including but not limited to." Furthermore, throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0036] As used in this specification and the appended claims, the singular forms "a," "an," and "the" may include plural referents unless the content clearly dictates otherwise. It should also be noted that the word "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise.

[0037] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. A hybrid drive comprising: a high-speed differential driver circuit comprising a first transistor coupled between a first supply voltage node and a first output node, and a second transistor coupled between the first output node and a reference voltage node; a low-speed driver circuit comprising a third transistor coupled in parallel with the first transistor; as well as a logic circuit coupled to the high-speed differential driver circuit and the low-speed driver circuit, the logic circuit being configured to receive a first high-speed differential input signal and a second high-speed differential input signal, a first low-speed input signal, and a mode selection signal having a value indicating a high-speed operating mode or a low-speed operating mode; and the logic circuit being configured to generate a first gate control signal in response to the mode selection signal indicating the high-speed operating mode, the first gate control signal activating the first transistor in response to the first high-speed differential input signal and deactivating the second transistor and the third transistor in response to the second high-speed differential input signal; and the logic circuit being configured to generate a second gate control signal in response to the mode selection signal indicating the low-speed operating mode, activating the second transistor in response to the low-speed input signal having a low level and activating the first transistor and the third transistor in response to the low-speed input signal having a high level. 2 . The hybrid driver of claim 1 , wherein the first transistor and the second transistor comprise NMOS transistors, and the third transistor is a single PMOS transistor. 3 . The hybrid driver of claim 2 , wherein the first supply voltage node is configured to receive a first supply voltage, and wherein the logic circuit includes a second supply voltage node configured to receive a second supply voltage, the second supply voltage being greater than the first supply voltage.

4. The hybrid driver according to claim 3, wherein the logic circuit further comprises: a first inverting multiplexer having a first input configured to receive the first high-speed differential input signal, a second input configured to receive the first low-speed input signal, a control input configured to receive the mode select signal, and an output; an inverter configured to receive the first low-speed input signal and having an output; a second inverting multiplexer having a first input configured to receive the second high-speed differential input signal, a second input configured to receive the output of the inverter, a control input configured to receive the mode select signal, and an output; a first AND gate having a first input coupled to the output of the first inverting multiplexer, a second input configured to receive an enable signal, and an output coupled to a control node of the second transistor; as well as A second AND gate has a first input coupled to the output of the second inverting multiplexer, a second input configured to receive the enable signal, and an output coupled to a control node of the first transistor.

5. The hybrid driver according to claim 4, wherein the low-speed driver circuit further comprises: a pass gate having a first signal node coupled to the output of the first AND gate, a second signal node coupled to the control node of the third transistor, and a control node configured to receive a second select signal; as well as A fourth transistor is coupled between the control node of the third transistor and the second supply voltage node and has a control node configured to receive the second selection signal. The hybrid driver of claim 5 , wherein the fourth transistor comprises a PMOS transistor. 7 . The hybrid driver of claim 1 , wherein the high-speed differential driver circuit further comprises a first resistor coupled between the first transistor and the first supply voltage node, and a second resistor coupled between the second transistor and the reference voltage node. 8 . The hybrid driver of claim 1 , wherein the high-speed differential driver circuit comprises a low-voltage differential signal driver circuit, and the first high-speed differential input signal and the second high-speed differential input signal comprise low-voltage differential signals. 9 . The hybrid driver of claim 8 , wherein the low voltage differential signal comprises a scalable low voltage signal. 10 . The hybrid driver of claim 9 , wherein the first low-speed input signal comprises a low-voltage CMOS signal. 11 . The hybrid driver of claim 10 , wherein the scalable low voltage signal is a 6 Gbps data signal, and the low voltage CMOS signal is a 12 Mbps data signal.

12. A hybrid driver configured to receive a pair of high-speed differential input data signals and a pair of low-speed input data signals, and configured to select a pair of input data signals from the pair of input data signals and drive output data signals on a first output node and a second output node based on the selected pair of input data signals, the hybrid driver comprising a first driver circuit and a second driver circuit coupled to the first output node and the second output node, respectively, each of the first driver circuit and the second driver circuit comprising a first series transistor and a second series transistor coupled between a supply voltage node and a reference voltage node, an interconnection between the first series transistor and the second series transistor coupled to the corresponding first output node or the second output node, and each of the first driver circuit and the second driver circuit comprising a third transistor coupled in parallel with the first series transistor, the third transistor configured to couple the corresponding first output node or the second output node, connected in parallel with the corresponding first series transistor, to a second supply voltage node in response to the selected low-speed input data signal and the value of the corresponding low-speed input data signal. The hybrid driver is configured to receive a first selection signal and a second selection signal, and is configured to drive the first output node in response to a corresponding one of the paired low-speed input data signals only when the first selection signal is high, and is configured to drive the second output node in response to a corresponding one of the paired low-speed input data signals only when the second selection signal is high. 13 . The hybrid driver of claim 12 , wherein each of the first and second series transistors comprises an NMOS transistor, and each of the third transistors comprises a single PMOS transistor.

14. The hybrid driver of claim 12, wherein the pair of high-speed differential input data signals are low-voltage differential signals, and wherein the pair of low-speed input data signals are independent low-voltage CMOS signals.

15. A method for a hybrid drive, comprising: In high-speed differential signaling operation mode, In response to a first high-speed differential input signal, coupling the first output node to a first supply voltage node through a first switching element, or to a reference voltage node through a second switching element; as well as In response to a second high-speed differential input signal, coupling the second output node to the first supply voltage node through a third switching element, or to the reference voltage node through a fourth switching element; In low-speed signaling operation mode, In response to a first low-speed input signal, coupling the first output node in parallel to a second supply voltage node through the first switching element and through a fifth switching element, or coupling the first output node to the reference voltage node through the second switching element; as well as In response to a second low-speed input signal, the second output node is coupled in parallel to the second supply voltage node through the third switching element and through the sixth switching element, or to the reference voltage node through the fourth switching element. 16 . The method of claim 15 , wherein the first high-speed differential input signal and the second high-speed differential input signal comprise low voltage differential signals. 17 . The method of claim 16 , wherein each of the first low-speed input signal and the second low-speed input signal comprises a low-voltage CMOS signal. 18 . The method of claim 15 , the second supply voltage node receiving a second supply voltage having a magnitude greater than a magnitude of a first supply voltage on the first supply voltage node.

19. The method of claim 18, wherein the amplitude of the first supply voltage is 400 millivolts and the amplitude of the second supply voltage is 1.2 volts.

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