Cross-point array memory in a nonvolatile dual in-line memory module

Abstract

An indication of a loss of power may be received at a crosspoint array memory dual inline memory module (DIMM) operational component of a memory subsystem. The crosspoint array memory DIMM operational component includes a volatile memory component and a nonvolatile crosspoint array memory component. In response to receiving the indication of the loss of power, a type of write operation for the nonvolatile crosspoint array memory component of the crosspoint array memory DIMM operational component is determined based on characteristics of the memory subsystem. Data stored at the volatile memory component of the crosspoint array memory DIMM operational component is retrieved and the data is written to the nonvolatile crosspoint array memory component of the crosspoint array memory DIMM operational component using the determined type of write operation.

Description

Technical Field

[0001] The present disclosure relates generally to memory subsystems, and more particularly, to cross-point array memory in a non-volatile dual in-line memory module (DIMM). Background Art

[0002] The memory subsystem may be a storage system, such as a solid-state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0005] Figure 2A An example architecture of a dual in-line memory module (DIMM) having a cross-point array memory according to some embodiments of the present disclosure is described.

[0006] Figure 2B An example architecture of a DIMM with a cross point array memory according to some other embodiments of the present disclosure is described.

[0007] Figure 3 is a flowchart of an example method of performing a save operation according to some embodiments of the present disclosure.

[0008] Figure 4 is a flow chart of an example method of performing a restore operation according to some embodiments of the present disclosure.

[0009] Figure 5 is a flowchart of an example method of performing a pre-save operation according to some embodiments of the present disclosure.

[0010] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure are directed to a memory subsystem that includes a crosspoint array memory in a nonvolatile dual inline memory module (DIMM). The memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), or nonvolatile dual inline memory modules (NVDIMMs), etc. In some embodiments, the memory subsystem may be a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem, and may request to retrieve data from the memory subsystem. For example, the host system may utilize the DIMMs of the memory subsystem as a cache memory.

[0012] Conventional DIMMs may include static dynamic random access memory (SDRAM) to store data accessed by a host system. SDRAM may be a volatile memory. Therefore, when a conventional DIMM experiences a loss of power or a condition that results in a loss of power for a certain amount of time (e.g., during a restart), then the data stored at the SDRAM may be lost. Therefore, conventional DIMMs may include flash memory to store data at the SDRAM in the event of a power loss. When the DIMM loses power, the data at the SDRAM may be stored at the flash memory. For example, a write operation may be performed to write the data at the SDRAM to the flash memory. Since the flash memory is a non-volatile memory, then when the DIMM experiences a power loss, the data may still be stored at the flash memory. Subsequently, when power is returned to the DIMM, the data stored at the flash memory may be written back to the SDRAM for use by the host system.

[0013] In the case of power loss, due to the inherent disadvantages of flash memory, using flash memory to store data from the SDRAM of the DIMM can take an extended amount of time to write the data to the flash memory to copy the data from the SDRAM. Therefore, when experiencing power loss, there may not be enough time to save the data stored at the SDRAM to the flash memory. Similarly, when power is restored to the DIMM, there may be additional downtime for the host system when the data is being restored from the flash memory to the SDRAM. In addition, the performance of the write operation and the read operation of the flash memory can utilize a larger amount of energy or power to read or write data from the flash memory. Therefore, it is necessary to use a larger backup power supply in conjunction with a conventional DIMM that includes flash memory as a non-volatile memory. In addition, the flash memory may have a more limited persistence. For example, before the data stored at the flash memory can no longer be reliably stored at the flash memory, a specific number of write operations and / or read operations can be performed at the flash memory. Therefore, the life of the DIMM including the flash memory can also be limited by the persistence of the flash memory.

[0014] Aspects of the present disclosure address the above and other deficiencies by using a cross-point array memory in a DIMM. In some embodiments, the cross-point array memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. For example, a bit '0' or '1' may be determined based on the resistance value of a particular memory cell of the cross-point array memory. The cross-point array memory may be a non-volatile memory contained in a DIMM that is used to store data from an SDRAM of the DIMM in the event of a power loss. For example, a host system may provide a signal to a DIMM containing a cross-point array memory. When an indication of a power loss is received or expected, the host system may transmit a save command to the DIMM. In response, the DIMM may perform a save operation to retrieve data from the SDRAM and store the data at the cross-point array memory. In addition, when power is returned to the DIMM, a restore operation may be performed to retrieve data from the cross-point array memory and store the data at the SDRAM of the DIMM. After the data is restored to the SDRAM, the DIMM may prepare the cross-point array memory for the next save operation by resetting the data value at the location where the data was previously stored.

[0015] Advantages of the present disclosure include, but are not limited to, a reduction in the amount of time to store data from an SDRAM to a cross point array memory and the amount of time to restore data from a cross point array memory to an SDRAM. Thus, a host system associated with a DIMM having a cross point array memory may spend less time operating on data stored at the DIMM when power is returned to the DIMM. Additionally, because the performance of read operations and write operations on the cross point array memory may utilize less energy, a smaller backup energy or power supply may be used in conjunction with or in the DIMM. Furthermore, the cross point array memory may have a higher durability and may therefore store data from more write operations without causing the data to become unreliable. Thus, a DIMM using a cross point array memory may have a longer life span or usage time.

[0016] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media, such as memory components 112A-112N. The memory components 112A-112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0017] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0018] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. Furthermore, the memory cells of the memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to cells of a memory component used to store data.

[0019] The memory system controller 115 (hereinafter referred to as the "controller") can communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory components 112A to 112N, and other such operations. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0020] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 may additionally include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0021] The memory subsystem 110 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A to 112N.

[0022] The memory subsystem 110 includes a cross-point array memory DIMM operation component 113 (e.g., an integrated circuit having SDRAM and a cross-point array memory). In some embodiments, the controller 115 includes at least a portion of the cross-point array memory DIMM operation component 113. For example, the controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in a local memory 119 for performing the operations described herein.

[0023] The memory subsystem 110 receives power from a main power source. In addition, in the event of a power failure at the main power source, the memory subsystem 110 includes or is connected to a backup power source. In response to the power failure, a cross-point array memory DIMM operation component 113 of the memory subsystem 110 may receive an indication of a power loss due to the main power source. In response, the cross-point array memory DIMM operation component 113 may save data. On the other hand, in response to detecting power restoration at the main power source, the cross-point array memory DIMM operation component 113 may restore the saved data in response to power restoration. The cross-point array memory DIMM operation component 113 may also pre-save data when normal power is supplied from the main power source in order to shorten the time required to save data in the event of a power failure. Further details regarding the operation of the cross-point array memory DIMM operation component 113 are described below.

[0024] Figure 2A 2 is an example system architecture for a cross-point array memory DIMM operation component 113 for storage operation according to some embodiments of the present disclosure. As shown, the DIMM controller 230 may include a host system channel 251 that provides signals to the cross-point array memory DIMM operation component 113. The DIMM controller 230 may be connected to a volatile memory component 210 (e.g., SDRAM), a non-volatile cross-point array memory component 220. The volatile memory component 210 stores data used or accessed by the host system 120. The non-volatile cross-point array memory component 220 stores data from the volatile memory component 210 that may be lost, for example, due to a power loss. The volatile memory component 210 and the non-volatile cross-point array memory component 220 may correspond to Figure 1 Media 112A to 112N in.

[0025] The DIMM controller 230 monitors input signals from the host system channel 251. If the crossbar DIMM controller 230 detects a power loss signal or a save command, a save operation may be performed by transferring data from the volatile memory component 210 to the non-volatile cross point array memory component 220. For example, the DIMM controller 230 may read data stored at the volatile memory component 210 via the volatile memory channel 255. The DIMM controller 230 may determine to save data to the non-volatile cross point array memory using a pre-scan write operation or a forced write operation by communicating via the non-volatile memory channels 257A / 257B. Figure 3 Operation 330 of FIG. 1 is used to describe details regarding the pre-scan write operation and the forced write operation.

[0026] The DIMM controller 230 may use the non-volatile memory channel 253 to retrieve characteristics of the memory subsystem 110 in order to determine which write operation to use for the save operation. For example, the DIMM controller 230 may access a power controller or a backup power supply via the non-volatile memory channel 253 to obtain the energy level of the backup power supply. The backup power supply may be connected to the memory subsystem 110 and supply backup power to the memory subsystem 110 during the save operation to be performed by the cross point array memory DIMM operation component 113, but not during normal operation or other operations performed when the host system 120 utilizes data stored at the volatile memory component 210. For normal operation, the main power supply may provide power to the memory subsystem 110. The DIMM controller 230 may also access a database or volatile memory component 210 via the non-volatile memory channel 253, which has metadata of the data stored at the volatile memory component 210. The metadata may include information about the data of the volatile memory component 210, such as the amount of data stored at the volatile memory component 210, or a classification of the data (e.g., a priority type), and other information of the data stored at the volatile memory component 210. The DIMM controller 230 may then determine which write operation to perform based on the characteristics of the memory subsystem 110 collected via the non-volatile memory channel 253.

[0027] In some embodiments, the DIMM controller 230 may perform a pre-save operation to enable faster execution of the save operation. For example, when the main power supply operates properly, the DIMM controller 230 may begin transferring some of the data stored at the volatile memory component 210 to the non-volatile cross-point array memory component 220. Figure 5 To describe more details about the pre-save operation.

[0028] Figure 2Bis an example of a system architecture of a cross-point array memory DIMM operation component 113 for recovery operations according to some embodiments of the present disclosure. Figure 2A In the system architecture of the present invention, the cross-point array memory DIMM operation component 113 includes a DIMM controller 230, which is connected to the volatile memory component 210 and the non-volatile cross-point array memory component 220. The host system channel 271 of the DIMM controller 230 can provide a power signal or a recovery command from the host system 120 to the DIMM controller 230. The host system channel 271 can be connected to Figure 2A In response to detecting the return of the power signal, the DIMM controller 230 may perform a recovery operation to transfer data from the nonvolatile cross point array memory component 220 to the volatile memory component 210. For example, the DIMM controller 230 may read data stored in the nonvolatile cross point array memory component 220 via the nonvolatile memory channel 273 and write data to the volatile memory component 210 via the volatile memory channel 275. The volatile memory channel 275 may be the same as the volatile memory channel 273. Figure 2A After completing the write operation on the volatile memory component 210, the DIMM controller 230 may reset the nonvolatile cross point array memory component 220 via another nonvolatile memory channel 277. The nonvolatile memory channels 273 and 277 may be the same channel as the volatile memory channel 255. Figure 2A The nonvolatile memory channels 257A and 257B are the same channel. Figure 4 Describes further details about the restore operation.

[0029] Figure 3 300 is a flowchart of an example method 300 of performing a save operation according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The crosspoint array memory DIMM operation component 113 is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0030] like Figure 3As shown, at operation 310, the processing device receives an indication of power loss. For example, the processing device or DIMM controller 230 may detect a power loss signal generated from the host system 120 via the host system channel 251 of the cross point array memory DIMM operation component 113. The power loss signal may be at a low signal level (e.g., asserted to a value of '0'). The power loss signal may indicate that the host system 120 intends to power down, or may indicate a failure or anticipated failure of a main power supply that supplies energy to the memory subsystem 110 and / or the host system 120. The processing device may process the power loss as a save command from the host system 120 to initiate a save operation so that data stored at the volatile memory component 210 may be written to the non-volatile cross point array memory component 220.

[0031] The processing device determines the characteristics of the memory subsystem 110 at operation 320. For example, the processing device may determine the characteristics of the backup power supply that provides backup power to the memory subsystem 110 for the save operation to be performed by the cross point array memory DIMM operation component 113. The processing device may determine the energy level of the backup power supply (i.e., how much energy is left). In another example, the processing device may determine the characteristics of the data stored in the volatile memory component 210 that will be saved in the non-volatile cross point array memory component 220. Specifically, the processing device may determine the size of the data stored in the volatile memory component 210, or the amount of data to be transferred to the non-volatile cross point array memory component 220. In addition, the processing device may identify the classification of data blocks of the data stored in the volatile memory component 210. The data blocks may be classified into high priority and low priority depending on the data stored. For example, the high priority data blocks may include user data (e.g., data generated by a user of the host system 120) or any other data that is important (more difficult to recover) to the operation of the host system 120. Low priority data blocks may have non-user data, such as metadata of user data or any other data that is less detrimental to (or easier to recover from) the operation of the host system 120. The processing device may classify data blocks of the volatile memory component 210 based on their metadata.

[0032] At operation 330, the processing device, in response to receiving the indication of the power loss, determines the type of write operation for the non-volatile cross point array memory component 220 based on the characteristics of the memory subsystem 110. There may be a plurality of write operations available for execution on the non-volatile cross point array memory component 220 of the cross point array memory DIMM operation component 113. Examples of such write operations include, but are not limited to, pre-scan write operations and force write operations.

[0033] The pre-scan write operation may write data to the non-volatile cross point array memory component 220 based on a comparison between a data block of data from the volatile memory and a data block previously stored at the non-volatile cross point array memory component 220. For example, when the previous data was written to the non-volatile cross point array memory component 220, such a data block may store the value previously written to the data block. The value previously written to the data block of the previous data may still exist at the non-volatile cross point array memory component 220 because no erase operation is performed on the non-volatile cross point array memory component 220. In some embodiments, such a data block may store the same value as the value previously reset (e.g., zero), such as with respect to Figure 4 The pre-scan write operation 430 is described in detail. The pre-scan write operation may include a pre-read operation. The pre-read operation may first identify the locations (or data blocks) in the non-volatile cross point array memory component 220 to be written, and may read the data currently stored at these locations in the non-volatile cross point array memory component 220. Each data block of data to be stored (e.g., data from the volatile memory component 210) will have a corresponding data block in the non-volatile cross point array memory component 220. The pre-scan write operation may also include a comparison operation followed by the pre-read operation. For example, if a particular data block at the non-volatile cross point array memory component 220 currently stores data that matches a corresponding data block of data from the volatile memory component 210, then the processing device may determine not to write the data corresponding to the data block of data from the volatile memory component 210 to the data block at the non-volatile cross point array memory component 220 because the data currently stored at the non-volatile cross point array memory component 220 matches the particular data block of the volatile memory component 210. Otherwise, if the specific data block at the nonvolatile cross point array memory component 220 currently stores data that does not match the corresponding data block of the data from the volatile memory component 210, a write operation may be performed at the specific data block of the nonvolatile cross point array memory component 220. For example, a voltage signal may be applied to the specific data block of the nonvolatile cross point array memory component 220 to change the value of the data stored at the specific data block. Thus, in the pre-scan write operation, for a data block that includes a data value that is different from the data value of the corresponding data block from the volatile memory component 210, the processing device writes data to the data block of the nonvolatile cross point array memory component 220.

[0034] On the other hand, the forced write operation does not perform a pre-read operation and / or a comparison operation. Rather, the forced write operation may apply a voltage to each data block of the non-volatile cross point array memory component 220 that will store data from the volatile memory component 210. For example, the forced write operation may apply a voltage to the data block to set a value of '0', and another voltage may be applied to another data block to set a value of '1'. Thus, the forced write operation may write the entire data of the volatile memory component 210 to the non-volatile cross point array memory component 220. In some embodiments, the pre-scan write operation may be performed in less time and may consume less power, while the forced write operation may consume more time and more power. However, the forced write operation may be considered to result in more reliable data storage because each data block is being written to store data, regardless of the data stored, and the corresponding data block becomes more susceptible to errors (e.g., errors caused by drift in the voltage threshold used to store data over time). Therefore, when there is sufficient backup power and / or time to complete the save operation, the processing device may determine to use a forced write operation to obtain better reliability of the data.

[0035] In some embodiments, the processing device may be set as a default to write data from the volatile memory component 210 to the non-volatile cross-point array memory component 220 by using a pre-scan write operation for a save operation. In another embodiment, in certain circumstances, the processing device may selectively perform a forced write operation in place of the pre-scan write operation. For example, if there is more than enough power in the backup power supply of the memory subsystem 110 to perform a save operation, the processing device may use a forced write operation to obtain better reliability of the data. The processing device may determine whether the energy level of the backup power supply meets an energy level threshold. The energy level threshold may be based on a specific energy level sufficient to write data from the volatile memory component 210 to the non-volatile cross-point array memory component 220. The specific energy level may also indicate an energy level of the backup power supply that is sufficient for the processing device to perform a forced write operation. If the energy level of the backup power supply exceeds a specific energy level set as a threshold, the processing device may determine to use a forced write operation. Otherwise, the processing device may perform a pre-scan write operation.

[0036] As another example, the processing device may determine to use a forced write operation when the amount of data stored in the volatile memory component 210 to be written to the non-volatile cross point array memory component 220 does not exceed a specific data size. Because a forced write operation takes longer than a pre-scan write operation, the processing device may perform a forced write operation when the forced write operation can be completed for the amount of data stored in 210. It is assumed that there is sufficient spare energy available for a save operation using a forced write operation. Therefore, the processing device may apply a data size threshold to control when data is written to the non-volatile cross point array memory component 220 by performing a forced write operation.

[0037] The processing device may also determine which write operation to use based on the classification of the data blocks from the volatile memory component 210. For example, the processing device may use a forced write operation to store data blocks classified as high priority, and use a pre-scan write operation to store other data blocks classified as low priority. The high priority data blocks may store user data (e.g., data generated by a user of the host system 120) or any other data that is important to the operation of the host system 120 (or more difficult to recover), and the low priority data blocks may include non-user data, such as metadata of the user data or any other data that is less detrimental to the operation of the host system 120 (or more easily recoverable).

[0038] The processing device may further consider the amount of energy that can be supplied by the backup power supply. If the backup power is insufficient to write some data blocks using a forced write operation, the processing device may determine to perform a pre-scan write operation on data blocks classified as low priority, while determining to perform a forced write operation on data blocks classified as high priority.

[0039] At operation 340, the processing device retrieves data stored at the volatile memory component 210. For example, a read operation is performed on the volatile memory component 210. Then, at operation 350, the processing device writes the retrieved data to the non-volatile cross-point array memory component 220 by using a write operation of the determined type. For example, a pre-scan write operation or a force write operation may be performed as described above with respect to operation 330. The processing device may further keep a record of which data block from the volatile memory component 210 is written to which data block of the non-volatile cross-point array memory component 220.

[0040] In some embodiments, when writing from the volatile memory component 210, the data may be written to the non-volatile cross-point array memory component 220 sequentially. For example, the save operation may save the data from the volatile memory component 210 in consecutive or adjacent memory cells or data block locations. Thus, when reading data from the non-volatile cross-point array memory component 220 during a recovery operation, interference mechanisms may be reduced. For example, the data in consecutive memory cells may be read in a streaming manner. In the same or alternative embodiments, multiple cursors may be used to write data from the volatile memory component 210 to the non-volatile cross-point array memory component 220. For example, the volatile memory component 210 may include multiple data channels in which data may be retrieved from the volatile memory component 210. Each channel may be used to provide data to a specific cursor, which writes the data to a specific data block location of the cross-point array memory.

[0041] Figure 4 4 is a flowchart of an example method 400 of performing a recovery operation according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The crosspoint array memory DIMM operation component 113 is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0042] At operation 410, the processing device receives an indication of a return of power. For example, the processing device may detect the return of a power signal generated from the host system 120 via the host system channel 271 of the cross point array memory DIMM operation component 113. The return of the power signal may be a high signal level (e.g., asserted to a value of '1'). Also, the return of the power signal may indicate a return or expected return of power from a main power source of the memory subsystem 110 and / or the host system 120. The processing device may process the return of the power signal as a restore command from the host system 120 to initiate a restore operation of data stored at the non-volatile cross point array memory component 220 to the volatile memory component 210.

[0043] In response to receiving the indication of power return, the processing device retrieves data from the nonvolatile cross point array memory component 220 and writes the data to the volatile memory component 210 at operation 420. At operation 430, the processing device resets the data blocks of the nonvolatile cross point array memory component 220 that store the data written to the volatile memory component 210. For example, the processing device may determine which data blocks in the nonvolatile cross point array memory component 220 have been written for a previous save operation. The processing device may refer to the record that maps the data blocks of the volatile memory component 210 to the data blocks in the nonvolatile cross point array memory component 220 in the save operation (as mentioned with respect to operation 350). The processing device may then write the same data value (e.g., data value '0') to the data blocks of the nonvolatile cross point array memory component 220 that store the data written to the volatile memory component 210. In some embodiments, the processing device may perform a force write operation on these data blocks of the nonvolatile cross point array memory component 220. The processing device may apply a voltage to these data blocks of the nonvolatile cross-point array memory component 220 to set the value '0'. When subsequent values ​​are stored at the memory cells of the data blocks, setting the value of each of the memory cells to the value '0' may result in a better threshold voltage distribution for the memory cells. In some embodiments, the processing device may use a pre-scan write operation on these data blocks of the nonvolatile cross-point array memory component 220 in order to reset the data values. The processing device may additionally reset other data blocks of the nonvolatile cross-point array memory component 220 that have not yet stored data written to the volatile memory component 210.

[0044] After the nonvolatile cross-point array memory element 220 has been reset, the processing device may receive an indication of a power loss, which triggers a Figure 3 In response, the processing device may perform a pre-scan write operation as a default to save the data stored at the volatile memory component 210 to the non-volatile cross point array memory component 220 .

[0045] Figure 5 is a flow chart of an example method 500 for performing a pre-save operation according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1The crosspoint array memory DIMM operation component 113 is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0046] The pre-save operation may be performed by writing some of the data stored at the volatile memory component 210 to the non-volatile cross point array memory component 220 during normal operation of the cross point array memory DIMM operation component 113. In this way, the time required for the save operation may be reduced because some of the data stored at the volatile memory component 210 may be stored at the non-volatile cross point array memory component 220 before the save operation is performed. As described with respect to operation 430, the pre-save operation may be performed after the non-volatile cross point array memory component 220 has been reset.

[0047] At operation 510, the processing device determines a subset of data blocks for a pre-save operation at the volatile memory component 210. For example, the processing device may begin performing the pre-save operation from data blocks that were stored earlier (i.e., older data) in the volatile memory component 210. In another example, the processing device may select data blocks that are least frequently accessed by the host system 120.

[0048] The processing device retrieves the determined subset of data blocks from the volatile memory component 210 at operation 520. The processing device then writes the subset of data blocks to the non-volatile cross-point array memory at operation 530 based on a first type of write operation. For example, the first type of write operation may be performed when power is supplied from the main power supply to the memory subsystem 110 and / or the host system 120. In some embodiments, the first type of write operation may be a forced write operation that is performed on the subset of data blocks of the volatile memory component 210 to obtain better reliability of the subset of data blocks when stored at the non-volatile cross-point array memory. In other embodiments, the first type of write operation may be a pre-scan write operation. The processing device may perform the write operation as a background process that does not interfere with the operation of the host system 120. The processing device may also keep a record of which data blocks from the volatile memory component 210 have been transferred to the non-volatile cross-point array memory component 220.

[0049] When some blocks of data of the volatile memory component 210 are stored at the nonvolatile cross point array memory component 220, the processing device receives an indication of a power loss at operation 540, similar to the indication of the power loss with respect to Figure 3 In response, the processing device saves the remaining data blocks from the volatile memory component 210 to the non-volatile cross point array memory component 220 based on a second type of write operation at operation 550. The second type of write operation may be different from the first type of write operation. For example, the first type of write operation may be a force write operation, and the second type of write operation may be a pre-scan write operation. The processing device may determine the remaining data blocks based on a record retained from a pre-save operation. The remaining data blocks of the volatile memory component 210 are data blocks that have not been written to the non-volatile cross point array memory component 220 during the pre-save operation. In some embodiments, the processing device may perform a save operation at operation 550, such as with respect to Figure 4 described.

[0050] Figure 6 An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to execute the operation of the controller (for example, execute the operating system to implement the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a cloud computing infrastructure or environment.

[0051] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" will also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0052] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0053] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for implementing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate via a network 620.

[0054] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0055] In one embodiment, the instructions 626 include executing a component corresponding to a cross-point array DIMM operation (eg, Figure 1 The cross-point array DIMM operation component 113 of the present invention is a cross-point array DIMM operation component 113 of the present invention. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0056] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is an operation that requires physical control of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0058] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as but not limited to any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0059] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0060] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0061] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A storage system, comprising: volatile memory components; non-volatile cross-point array memory components; as well as a processing device operatively coupled to the volatile memory component and the nonvolatile cross-point array memory component to perform the following operations: receiving an indication of a loss of power to the system; determining an energy level of a backup power supply for the system by determining how much energy is remaining in the backup power supply for the system, wherein the backup power supply provides backup power to the system in response to the power loss; in response to receiving the indication of the loss of power to the system, determining a type of write operation from a plurality of types of write operations for the nonvolatile cross point array memory component based on whether the energy level of the backup power source satisfies an energy level threshold; retrieving data stored at the volatile memory component; as well as The retrieved data is written to the non-volatile cross point array memory component using the determined type of write operation.

2. The memory system of claim 1 , wherein the plurality of types of write operations for the nonvolatile cross point array memory component comprises: a pre-scan write operation that writes the retrieved data to the non-volatile cross point array memory component based on a comparison between a data block of the retrieved data and other data blocks stored at the non-volatile cross point array memory component; as well as A write operation is forced that writes each block of the retrieved data stored in the volatile memory component to the nonvolatile cross point array memory component.

3. The memory system of claim 1, wherein the energy level threshold is based on an energy level sufficient to write the retrieved data to the nonvolatile cross point array memory component.

4. The memory system according to claim 2, wherein in order to write the data stored in the volatile memory component to the nonvolatile cross point array memory component by using the pre-scan write operation, the processing device further performs the following operations: determining one or more data blocks of the non-volatile cross point array memory component where the data stored in the volatile memory component is to be written; comparing data from each of the one or more blocks of data from the nonvolatile cross point array memory component with data from a corresponding block of the data retrieved from the volatile memory component; determining a subset of the one or more data blocks of the nonvolatile cross point array memory component having data that is different than data of a corresponding data block of the volatile memory component; as well as Data of corresponding data blocks stored in the volatile memory component are written to the subset of the one or more data blocks of the non-volatile cross point array memory component.

5. The storage system of claim 1, wherein the system is a Dual In-line Memory Module (DIMM).

6. A method of operating a memory subsystem, comprising: receiving an indication of a loss of power to a memory subsystem including a volatile memory component and a nonvolatile cross point array memory component; determining an energy level of a backup power supply for the memory subsystem by determining how much energy is left in the backup power supply for the memory subsystem, wherein the backup power supply provides backup power to the memory subsystem in response to the power loss; in response to receiving the indication of the loss of power to the memory subsystem, determining a type of write operation from a plurality of types of write operations for the nonvolatile cross point array memory component based on whether the energy level of the backup power source satisfies an energy level threshold; retrieving data stored at the volatile memory component; as well as The retrieved data is written, by the processing means, to the non-volatile cross point array memory component by using the determined type of write operation.

7. The method of claim 6, wherein the plurality of types of write operations for the nonvolatile cross point array memory component comprises: a pre-scan write operation that writes the retrieved data to the non-volatile cross point array memory component based on a comparison between a data block of the retrieved data and other data blocks stored at the non-volatile cross point array memory component; as well as A write operation is forced that writes each block of the retrieved data stored in the volatile memory component to the nonvolatile cross point array memory component.

8. The method of claim 6, wherein the energy level threshold is based on an energy level sufficient to write the retrieved data to the nonvolatile cross point array memory component.

9. The method of claim 7, wherein writing the data stored in the volatile memory component to the nonvolatile cross point array memory component by using the pre-scan write operation comprises: determining one or more data blocks of the non-volatile cross point array memory component where the data stored in the volatile memory component is to be written; comparing data from each of the one or more blocks of data from the nonvolatile cross point array memory component with data from a corresponding block of the data retrieved from the volatile memory component; determining a subset of the one or more data blocks of the nonvolatile cross point array memory component having data that is different than data of a corresponding data block of the volatile memory component; as well as Data of corresponding data blocks stored in the volatile memory component are written to the subset of the one or more data blocks of the non-volatile cross point array memory component.

10. The method of claim 6, wherein the memory subsystem is a dual in-line memory module (DIMM).

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