Methods, apparatuses, devices, and media for accessing data

Abstract

According to embodiments of the present disclosure, a method, device, equipment and computer readable storage medium for accessing data are provided, which are related to the field of computer. The method for accessing data comprises obtaining an identification of a virtual function corresponding to a virtual machine of a computing device and an address related to data in a memory to be accessed by the virtual machine, the identification of the virtual function and the address being determined based on an access request received from the virtual machine of the computing device. The method further comprises determining a range of a storage resource in the memory corresponding to the virtual machine based on the identification. The method further comprises determining whether the address is within the range. The method further comprises accessing the data related to the address in response to determining that the address is within the range. The access method controls the virtual machine to access the memory through a memory management unit on a system on chip, which not only reduces the hardware resources, but also reduces the software overhead and improves the efficiency.

Description

Technical Field

[0001] The embodiments of this disclosure are primarily related to the field of computers, and more specifically, to methods, apparatus, devices, and media for accessing data. Background Technology

[0002] With the rapid development of cloud computing, modern data centers often use virtualization technology to improve the utilization of server physical resources. The separation of virtual machine software and hardware allows for better software management, fault detection, and system maintenance. Virtualization technology enables a single physical server to run multiple virtual servers, thereby improving server utilization and significantly reducing cloud computing deployment costs.

[0003] Artificial intelligence (AI) computing is widely used in cloud computing, leading to the massive deployment of various GPUs and AI accelerator cards. These accelerator cards can quickly support virtualization through Single Root I / O Virtualization (SR-IOV) technology. However, many problems need to be solved in using accelerator cards to support virtual machines. Summary of the Invention

[0004] According to an example embodiment of this disclosure, a scheme for accessing data is provided.

[0005] In a first aspect of this disclosure, a method for accessing data is provided. The method includes obtaining an identifier of a virtual function corresponding to a virtual machine of a computing device and an address relating to data in memory to be accessed by the virtual machine, the identifier of the virtual function and the address being determined based on an access request received from the virtual machine of the computing device; determining a range of storage resources in the memory corresponding to the virtual machine based on the identifier; determining whether the address is within the range; and accessing the data associated with the address in response to determining that the address is within the range.

[0006] In a second aspect of this disclosure, an apparatus for accessing data is provided. The apparatus includes an acquisition module configured to acquire an identifier of a virtual function corresponding to a virtual machine of a computing device and an address relating to data in memory to be accessed by the virtual machine, the identifier of the virtual function and the address being determined based on an access request received from the virtual machine of the computing device; a range determination module configured to determine a range of storage resources in memory corresponding to the virtual machine based on the identifier; an address comparison module configured to determine whether the address is within the range; and a first access module configured to access the address-related data in response to determining that the address is within the range.

[0007] In a third aspect of this disclosure, an electronic device is provided, including one or more processors; and a storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the method according to a first aspect of this disclosure.

[0008] In a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to a first aspect of this disclosure.

[0009] In a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method according to a first aspect of this disclosure.

[0010] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0012] Figure 1 A schematic diagram of an example environment 100 for accessing data according to an embodiment of the present disclosure is shown;

[0013] Figure 2 A flowchart of a method 200 for accessing data according to an embodiment of the present disclosure is shown;

[0014] Figure 3 A flowchart of a method 300 for accessing data according to an embodiment of the present disclosure is shown;

[0015] Figure 4 A schematic diagram of an example environment 400 for processing data according to an embodiment of the present disclosure is shown;

[0016] Figure 5 A schematic block diagram of an apparatus 500 for accessing data according to an embodiment of the present disclosure is shown;

[0017] Figure 6 A block diagram of a computing device 600 capable of implementing various embodiments of the present disclosure is shown. Detailed Implementation

[0018] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0019] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0020] Currently, effectively supporting virtualization using System-on-Chip (SoC) chips such as GPUs and AI accelerator cards faces significant challenges. SoCs often employ Memory Management Units (MMUs) to support memory virtualization. However, when using MMUs for memory virtualization, multiple MMU modules need to be instantiated on-chip due to the numerous computing units present. This approach not only requires substantial hardware resources but also incurs significant overhead due to the need for software to maintain multiple page tables and perform related consistency operations.

[0021] According to embodiments of this disclosure, an improved scheme for accessing data is proposed. In this scheme, firstly, an identifier of the virtual machine and a logical address of the data to be accessed, associated with an access request received from a virtual machine in a computing device, are determined. Then, based on the identifier, a range of storage resources in the memory on the system-on-a-chip (SoC) corresponding to the virtual machine is determined. When the address falls within this range, the data associated with that address is accessed through address translation. By using a memory management unit (MMU) on the SoC to translate memory addresses from different virtual machines into actual physical addresses for access, without needing to set up a MMU and associated page tables for each computing unit, memory access can be achieved with fewer hardware resources and less software overhead, effectively meeting the virtualization requirements of SoCs in cloud computing.

[0022] Figure 1 A schematic diagram of an example environment 100 for accessing data according to an embodiment of the present disclosure is shown. Figure 1As shown, environment 100 includes host 102 and system-on-a-chip (SoC) chip 104. Host 102 can be various types of computing devices capable of running virtual machines 106. Example computing devices include, but are not limited to, personal computers, server computers, handheld or laptop devices, mobile devices (such as mobile phones, personal digital assistants (PDAs), media players, etc.), multiprocessor systems, consumer electronics, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices.

[0023] In some embodiments, host 102 supports PCIe functionality. Alternatively or additionally, host 102 also supports I / O devices, such as network interfaces, through single root I / O virtualization (SR-IOV) to improve the utilization of I / O devices.

[0024] Virtual machine 106 runs on host 102. Virtual machine 106 refers to an application execution environment created by a specific application on the hardware platform of a physical machine. Users can run applications and interact with it through this environment as if using a physical machine. When creating virtual machine 106, a certain amount of resources are typically allocated from host 102, which hosts virtual machine 106, through a manager for the virtual machine 106 to use during operation. These resources can be any available resources used to run virtual machine 106, such as computing resources (e.g., CPU, GPU, FPGA, etc.), storage resources (e.g., memory, storage disks, etc.), and network resources (e.g., network interface cards, etc.). Figure 1 The inclusion of virtual machines 106 in host 102 is merely illustrative of this disclosure and not a specific limitation thereof. Host 102 can be configured with any number of virtual machines as needed.

[0025] Environment 100 also includes a system-on-a-chip (SoC) 104 communicatively coupled to host 102. A system-on-a-chip (SoC) refers to a complete system integrated on a single chip, specifically a system or product formed by combining multiple integrated circuits with specific functions on a single chip, containing a complete hardware system and its embedded software. For example, AI accelerator cards or various GPUs can be implemented using SoC 104. Besides the aforementioned AI accelerator cards and various GPUs, those skilled in the art can implement all suitable systems using SoC as needed.

[0026] The System-on-Chip (SoC) 104 supports single-root I / O virtualization, making it appear as multiple independent physical devices. Therefore, the SoC 104 supports physical functions (PF) and virtual functions (VF). Physical functions are full-featured Peripheral Component Interconnect (PCIe) functions that support single-root I / O virtualization. Physical functions are discovered, managed, and configured like ordinary PCIe devices. Virtual functions are lightweight PCIe functions associated with physical functions. Each virtual function is decoupled from a physical function. Virtual functions can be assigned to virtual machines.

[0027] The system-on-chip 104 also includes a PCIe interface, which, when receiving an access request from the virtual machine 106, determines the identifier of the virtual function corresponding to the virtual machine 106 and the logical address (e.g., Advanced Extensible Interface (AXI) address) of the data to be accessed in the memory 112 connected to the memory controller 110 based on the address information in the access request.

[0028] The system-on-a-chip 104 includes a memory management unit 108 and a memory controller 110. The memory management unit 108 controls access to the memory controller 110. Based on the received virtual function identifier, the memory management unit 108 can determine the range of storage resources of the memory 112 connected to the memory controller 110 corresponding to the virtual function identifier or the virtual machine 106.

[0029] The memory management unit 108 can also determine whether the received logical address is within the address range. If it is within the address range, the physical address corresponding to the logical address can be accessed. If it is not within the address range, an error message is returned.

[0030] In some embodiments, the memory management unit 108 includes a register. The register stores a memory block table. The memory block table stores multiple entries, each entry recording a virtual function identifier and the range of the actual physical address space corresponding to that virtual function identifier. Alternatively or additionally, the storage space of the memory 112 connected to the memory controller 110 is divided into multiple blocks, and the block table also stores information on whether the block corresponding to the virtual function identifier is valid, the starting number information of the block corresponding to the virtual function, and the size of the block, i.e., how many blocks there are.

[0031] In some embodiments, if the system-on-chip 104 supports four virtual functions and the memory 112 connected to the memory controller 110 has a storage space of 16GB, then each virtual function can correspond to 4GB of storage space. Alternatively or additionally, in order to ensure address consistency seen by the virtual machines, each virtual function sees an address space of 0-4GB.

[0032] The memory controller 110 is used to store data in the memory 112. The memory 112 connected to the memory controller 110 includes, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR), Random Access Memory (RAM), High Bandwidth Memory (HBM), Erasable Programmable Read-Only Memory (EEPROM), Flash Memory or other memory technologies, or any other non-transmission medium that can be used to store the required information and can be accessed by the host 102.

[0033] The above description, with reference to reference 1, illustrates a schematic diagram of an example environment 100 for accessing data according to an embodiment of the present disclosure. The following is in conjunction with... Figure 2 A flowchart describing a method 200 for accessing data according to an embodiment of the present disclosure.

[0034] like Figure 2 As shown, at box 202, the memory manager obtains the identifier of the virtual function corresponding to the virtual machine of the computing device and the address of the data in the memory that the virtual machine wants to access. The identifier and address of the virtual function are determined based on the access request received from the virtual machine of the computing device. For example, Figure 1 The System-on-Chip (SoC) 104 receives an access request from the virtual machine 106 of the host 102. This request is for accessing data in memory 112 via the SoC 104. Upon receiving the request, the interface unit of the SoC 104 determines, based on the request (e.g., address information in the request), the virtual function identifier associated with the virtual machine 106 and the address of the data to be accessed in memory 112 (e.g., an Advanced Extensible Interface (AXI) address). This virtual function identifier and address are then transmitted to the memory management unit 108.

[0035] At box 204, the memory management unit determines the range of storage resources in the memory corresponding to the virtual machine based on the identifier. For example, Figure 1 The memory management unit 108 determines the range of storage resources in the memory 112 corresponding to the virtual machine 106 based on the identifier. Alternatively or additionally, the memory management unit 108 determines the range of storage resources corresponding to the identifier of the virtual function based on the identifier of the virtual function.

[0036] In some embodiments, the memory management unit 108 includes a register that stores a mapping relationship between the virtual function identifier and the storage resources of the memory 112 connected to the memory controller 110. Alternatively or additionally, the register stores a memory block table containing multiple entries, each entry recording a virtual function identifier and the range of the actual physical address space corresponding to that virtual function identifier.

[0037] In some embodiments, the memory block table of the register or the aforementioned mapping relationship can only be modified through the physical functions of the system-on-chip 104. When the memory management unit 108 receives a request transmitted through physical functions for setting or modifying the mapping relationship between the identifier and the range of storage resources, the mapping relationship is stored or modified in the register associated with the memory controller 110.

[0038] The above method modifies the memory block table or mapping relationship stored in the registers only through physical functions, while keeping the registers inaccessible to virtual functions. This ensures that the memory block table or mapping relationship of the registers can only be accessed by the virtual machine manager, and not by the virtual machine itself. In this way, each virtual machine can only access its allocated memory space, and cannot access beyond its bounds or modify the memory block table, thus achieving physical isolation of the virtual machines and making access operations safe and reliable.

[0039] In box 206, the memory management unit determines whether the address is within the range. For example, Figure 1 The memory management unit 108 checks whether the address is within the range.

[0040] At box 208, in response to determining that the address is within range, the memory management unit accesses the data associated with that address. This data access process will be described below. Figure 3 Provide a detailed description.

[0041] If the memory management unit determines that the address is out of range, it will return an error message. In some embodiments, this error message indicates a decoding error. This operation prevents the virtual machine from accidentally accessing storage space that should not be accessed.

[0042] Using the above method, virtual machines can access the memory on the system-on-a-chip (SoC). By implementing virtual machine access to memory addresses through a memory management unit located on the SoC, this process requires minimal hardware resources, has low software overhead, and effectively meets the virtualization requirements of SoCs in cloud computing.

[0043] above Figure 2 A flowchart of a method 200 for accessing data according to embodiments of the present disclosure is described below. Figure 3 The exemplary process for accessing address-related data in box 208 of method 200 is described in detail below. Figure 3 A flowchart of a method 300 for accessing data according to an embodiment of the present disclosure is shown.

[0044] like Figure 3 As shown in box 302, the memory management unit determines the starting physical address of the storage resource based on the identifier. For example, Figure 1The memory management unit 108 can determine the starting physical address of the storage resource corresponding to the virtual machine 106 or the virtual function based on the identifier of the virtual function.

[0045] At box 304, the memory management unit determines the physical memory address corresponding to the address based on the starting physical address and the address. For example, Figure 1 The memory management unit 108 determines the actual physical address of the data in the memory 112 connected to the memory controller 110 based on the determined physical starting address of the memory resource and the logical address determined based on the access request.

[0046] At box 306, the memory management unit accesses data corresponding to physical memory addresses. For example, Figure 1 The memory management unit 110 in the memory controller 110 accesses data in the memory 112 connected to the memory controller 110 based on the actual physical address obtained.

[0047] Data access is achieved by translating addresses from different virtual machines into actual physical addresses, enabling different virtual machines to access memory addresses without requiring page tables for each computing unit, thus reducing software resource overhead.

[0048] under Figure 4 A schematic diagram of an example environment 400 for processing data according to an embodiment of the present disclosure is shown. This example environment 400 is... Figure 1 A specific example of example environment 100.

[0049] like Figure 4 As shown, the example environment 400 includes a host 102, a system-on-a-chip 104, a memory management unit 108, and a memory controller 110. Figure 1 The details have been described in detail in the previous section, so they will not be described in detail here.

[0050] The host 102 also includes a CPU 406 and a memory 408. The CPU 406 is the central processing unit of the host 102, which controls the operation of virtual machines in the host 102. The memory 408 stores the data and programs required to run the virtual machines. The host 102 also includes a PCIe interface 410, which supports PCIe functionality. The host 102 is connected to the system-on-a-chip 104 through the PCIe interface 410.

[0051] The system-on-chip 104 also supports PCIe functionality and the Advanced Extensible Interface (AXI) protocol, and is connected to the host 102 via an interface module 412. This interface module includes a PCIe interface 412, a master AXI interface 416, and a slave AXI interface 418. When the interface module 412 receives an access request from a virtual machine on the host 102, it determines the virtual function identifier and AXI address corresponding to the virtual machine based on the address information in the access request. The virtual function identifier and AXI address are transmitted to the memory management unit 108 via the internal bus 420. The memory management unit 108 contains a register 424. The register 424 stores a memory block table. Each entry in the block table stores a virtual function identifier and the range of memory resources corresponding to that virtual function identifier. The memory management unit 108 uses this table to determine whether the received AXI address is out of bounds. If it is not out of bounds, the actual physical address corresponding to the AXI address is determined using the address information stored in the register 424.

[0052] If the data is out of bounds, an error message will be returned indicating a decoding error. The memory block table stored in register 424 can only be modified through physical functions; the virtual machine cannot access register 424 through virtual functions, ensuring physical isolation of the virtual machine and making it more secure.

[0053] In some embodiments, if the system-on-chip 104 supports a maximum of 4 Virtual Functions (VFs), and the memory 112 has a space of 16MB, but actually supports 3 Virtual Function VFs, then the 3 VFs are allocated 16MB of space in a (2:1:1) ratio, starting at address 0xC000_0000. The block table would then be:

[0054]

[0055] Wherein, Id represents the virtual function identifier, Vld indicates whether the block is valid (1 for valid, 0 for invalid), base represents the starting number of the block, ranging from 0 to (2*VF_MAX_NUM-1), and size represents the size of the block, the number of granularities, also ranging from 0 to (2*VF_MAX_NUM-1), where VF_MAX_NUM represents the maximum number of supported virtual functions (VFs). To improve flexibility, the finer granularity is half the average value, i.e., 1 / (2*VF_MAX_NUM), with a granularity of 1 / 8 (i.e., VF_MAX_NUM = 4).

[0056] The above example illustrates a physical function corresponding to three virtual functions VF0-VF2. Further, when VF0-VF2 correspond to three virtual machines VM0-VM2: VM0 accesses memory controller 110 via VF0. When VF_id = 0, the valid addresses for AXI are 0xC000_0000 to 0xC07F_FFFF. When VM0 accesses address 0xC080_0000 via VF0, the main AXI interface 416 outputs VF_id = 0, and the AXI address is 0xC080_0000. The memory management unit 108 checks this as out of bounds and returns an error message. VM1 accesses memory controller 110 via VF1. When VF_id = 1, the valid addresses for AXI are 0xC000_0000 to 0xC03F_FFFF (corresponding to physical addresses 0xC080_0000 to 0xC0BF_F). VM2 accesses memory controller 110 via VF2, VF_id = 2, the valid address of AXI is 0xC000_0000~0xC03F_FFFF (corresponding to physical address 0xC0C0_0000~0xC0FF_FFFF); VM2 accesses address 0xC060_0000 via VF2, then the main AXI interface 416 will output VF_id = 2, the address of AXI is 0xC060_0000, the memory management unit 108 checks that it is out of bounds and returns an error message; the virtual machine manager VMM / monitor accesses register 424 of memory management unit 108, its address is 0xFFFF_0020, then the main AXI interface 416 will output PF = 1, the address of AXI is 0xFFFF_0020.

[0057] Figure 5 A schematic block diagram of an apparatus 500 for processing data according to an embodiment of the present disclosure is shown. The apparatus 500 may be included in... Figure 1 and Figure 4 The memory management unit 108 is either located in or implemented as a memory management unit 108. For example... Figure 5 As shown, device 500 includes an acquisition module 502 configured to acquire an identifier of a virtual function corresponding to a virtual machine of a computing device and an address related to data in memory to be accessed by the virtual machine, the identifier of the virtual function and the address being determined based on an access request received from the virtual machine of the computing device. Device 500 also includes a range determination module 504 configured to determine a range of storage resources in memory corresponding to the virtual machine based on the identifier. Device 500 further includes an address comparison module 506 configured to determine whether the address is within the range. Device 500 also includes a first access module 508 configured to access data related to the address in response to determining that the address is within the range.

[0058] In some embodiments, the device 500 further includes a return module configured to return an error message in response to determining that the address is out of range.

[0059] In some embodiments, the error message indicates a decoding error.

[0060] In some embodiments, the first access module 508 includes a starting physical address determination module configured to determine the starting physical address of the storage resource based on an identifier; a physical storage address determination module configured to determine the physical storage address corresponding to the address based on the starting physical address and the address; and a second access module configured to access the data corresponding to the physical storage address.

[0061] In some embodiments, the apparatus 500 further includes a storage module configured to store the mapping in a memory-related register in response to receiving a request transmitted via physical functions for setting a mapping relationship between an identifier and a range of storage resources.

[0062] In some embodiments, the device 500 is on a system-on-a-chip (SoC) that is communicatively coupled to the computing device.

[0063] Figure 6 A schematic block diagram of an electronic device 600 that can be used to implement embodiments of the present disclosure is shown. Device 600 can be used to implement... Figure 1 and Figure 4 The memory management unit 108 is included. As shown, the device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 602 or loaded from storage unit 608 into random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0064] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of monitors, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0065] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as methods 200 and 300. For example, in some embodiments, methods 200 and 300 may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of methods 200 and 300 described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform method 600 by any other suitable means (e.g., by means of firmware).

[0066] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload programmable logic devices (CPLDs), and so on.

[0067] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0068] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0069] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0070] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for accessing data, comprising: Obtain the identifier of the virtual function corresponding to the virtual machine of the computing device and the address related to the data in the memory to be accessed by the virtual machine, wherein the identifier of the virtual function and the address are determined based on the access request received from the virtual machine of the computing device; Based on the identifier and the mapping relationship between the identifier and the range of storage resources in the memory, the range of storage resources in the memory corresponding to the virtual machine is determined; Determine whether the address is within the specified range; as well as In response to determining that the address is within the range, the data associated with the address is accessed; as well as In response to receiving a request to modify the mapping relationship via a physical function of a system-on-a-chip (SoC) chip, the mapping relationship is modified via the physical function, and the mapping relationship is accessible only by the virtual machine manager and not by the virtual machine.

2. The method according to claim 1, further comprising: In response to determining that the address is not within the range, an error message is returned.

3. The method of claim 2, wherein the error message indicates a decoding error.

4. The method of claim 1, wherein accessing data related to the address comprises: Based on the identifier, determine the starting physical address of the storage resource; Based on the starting physical address and the address, determine the physical storage address corresponding to the address; and Access the data corresponding to the physical storage address.

5. The method according to claim 1, further comprising: In response to receiving a request transmitted via the physical function to set the mapping relationship, the mapping relationship is stored in a register associated with the memory.

6. The method of claim 1, wherein the method is performed at the system-on-chip (SoC) chip communicatively coupled to the computing device.

7. An apparatus for accessing data, comprising: The acquisition module is configured to acquire an identifier of a virtual function corresponding to a virtual machine of a computing device and an address related to the data in the memory to be accessed by the virtual machine, the identifier of the virtual function and the address being determined based on an access request received from the virtual machine of the computing device. The range determination module is configured to determine the range of storage resources in the memory corresponding to the virtual machine based on the identifier and the mapping relationship between the identifier and the range of storage resources in the memory; The address comparison module is configured to determine whether the address is within the range; as well as A first access module is configured to access the data associated with the address in response to determining that the address is within the range; as well as The modification module is configured to respond to receiving a request to modify the mapping relationship via a physical function of a system-on-a-chip (SoC) chip, wherein the mapping relationship is accessible only by the virtual machine manager and not by the virtual machine.

8. The apparatus according to claim 7, further comprising: The return module is configured to return an error message in response to determining that the address is not within the range.

9. The apparatus of claim 8, wherein the error message indicates a decoding error.

10. The apparatus of claim 7, wherein the first access module comprises: The starting physical address determination module is configured to determine the starting physical address of the storage resource based on the identifier; The physical storage address determination module is configured to determine the physical storage address corresponding to the address based on the starting physical address and the address; as well as The second access module is configured to access the data corresponding to the physical storage address.

11. The apparatus of claim 7, further comprising: The storage module is configured to store the mapping relationship in a register associated with the memory in response to receiving a request for setting the mapping relationship transmitted via the physical function.

12. The apparatus of claim 7, wherein the apparatus is on the system-on-a-chip (SoC) chip communicatively coupled to the computing device.

13. An electronic device, the device comprising: One or more processors; as well as A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the method as described in any one of claims 1-6.

14. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any one of claims 1-6.

15. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-6.

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