Two-dimensional scalable universal storage format for data storage devices

Abstract

In various aspects, the present disclosure describes one or more techniques for use with a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a plurality of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format based on the performance capabilities of the storage region using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format. The controller applies the modified storage format to the storage region.

Description

Technical Field

[0001] The present disclosure, in various embodiments, relates to data storage devices. More specifically, the present disclosure relates to a two-dimensional scalable universal storage format for data storage devices. Background Art

[0002] A data storage device, such as a solid-state device (SSD) or a hard disk drive (HDD), may include non-volatile memory (NVM). The NVM may include one or more flash memory devices, such as NAND flash memory. Due to the high error rates that occur when reading or writing data from NAND flash memory, error correction procedures (e.g., error correction codes (ECC) and algorithms) may be used to improve SSD reliability and data integrity. However, in some cases, the manner in which the error correction procedures are applied to NAND flash memory may degrade the performance and endurance of the SSD. Summary of the invention

[0003] One aspect of the present disclosure provides a data storage device. In one example, the data storage device includes a non-volatile memory (NVM) and a processor coupled to the NVM. The processor is configured to: apply a default storage format to a storage area of ​​the NVM, wherein the default storage format configures the storage area into a plurality of distinct storage areas logically arranged along a horizontal dimension and a vertical dimension; modify the default storage format based on the performance capability of the storage area using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format; and apply the modified storage format to the storage area.

[0004] Another aspect of the present disclosure provides a data storage device. In one example, the data storage device includes: a component for applying a default storage format to a storage area of ​​a NVM, the default storage format configuring the storage area as a plurality of distinct storage areas logically arranged along a horizontal dimension and a vertical dimension; a component for modifying the default storage format based on the performance capability of the storage area using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format; and a component for applying the modified storage format to the storage area.

[0005] Another aspect of the present disclosure provides a method for operating a data storage device. In one example, the method includes: applying a default storage format to a storage area of ​​a NVM, the default storage format configuring the storage area into a plurality of distinct storage areas logically arranged along a horizontal dimension and a vertical dimension; modifying the default storage format based on performance capabilities of the storage area using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format; and applying the modified storage format to the storage area.

[0006] Another aspect of the present disclosure provides a data storage device. In one example, the data storage device includes an NVM and a processor coupled to the NVM. The processor is configured to: apply a first storage format to a page of a block in the NVM, wherein the storage format configures the page as a first number of logical pages; determine a second storage format of the page when a bit error rate of the page exceeds a threshold, wherein the second storage format configures the page as a second number of logical pages, the second number of logical pages being less than the first number of logical pages; and apply the second storage format to the page.

[0007] Another aspect of the present disclosure provides a data storage device. In one example, the data storage device includes: a component for applying a first storage format to a page of a block in an NVM, wherein the storage format configures the page as a first number of logical pages; a component for determining a second storage format of the page when a bit error rate of the page exceeds a threshold, wherein the second storage format configures the page as a second number of logical pages, the second number of logical pages being less than the first number of logical pages; and a component for applying the second storage format to the page.

[0008] Another aspect of the present disclosure provides a method for operating a data storage device. In one example, the method includes: applying a first storage format to a page of a block in an NVM, wherein the storage format configures the page as a first number of logical pages; determining a second storage format for the page when a bit error rate of the page exceeds a threshold, wherein the second storage format configures the page as a second number of logical pages, the second number of logical pages being less than the first number of logical pages; and applying the second storage format to the page.

[0009] Another aspect of the present disclosure provides a data storage device. In one example, the data storage device includes a NVM and a processor coupled to the NVM. The processor is configured to: monitor a bit error rate of a plurality of storage areas of the NVM, each of the plurality of storage areas having a storage format; identify one or more storage areas of the plurality of storage areas having a bit error rate exceeding a threshold; and dynamically scale the storage format of the one or more of the plurality of storage areas to reduce the bit error rate of the one or more of the plurality of storage areas.

[0010] Another aspect of the present disclosure provides a data storage device. In one example, the data storage device includes: a NVM including a plurality of storage areas; a component for monitoring a bit error rate of the plurality of storage areas of the NVM, each of the plurality of storage areas having a storage format; a component for identifying one or more storage areas of the plurality of storage areas having a bit error rate exceeding a threshold; and a component for dynamically scaling the storage format of the one or more of the plurality of storage areas to reduce the bit error rate of the one or more of the plurality of storage areas.

[0011] Another aspect of the present disclosure provides a method for operating a data storage device. In one example, the method includes: monitoring a bit error rate of a plurality of storage areas of a NVM, each of the plurality of storage areas having a storage format; identifying one or more storage areas of the plurality of storage areas having a bit error rate exceeding a threshold; and dynamically scaling the storage format of the one or more of the plurality of storage areas to reduce the bit error rate of the one or more of the plurality of storage areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following contains a more detailed description with reference to specific embodiments shown in the accompanying drawings. It should be understood that these drawings depict only certain embodiments of the disclosure and are not to be considered limiting of its scope. The disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of a system including an exemplary data storage system according to aspects of the present disclosure.

[0014] Figure 2 An SSD is shown communicating with a host device according to aspects of the present invention.

[0015] Figure 3 A first example of storage space allocation applicable to pages of a non-volatile memory (NVM) according to aspects of the present invention is shown.

[0016] Figure 4 A second example of storage space allocation applicable to pages of an NVM according to aspects of the present invention is shown.

[0017] Figure 5 An example storage format that may be applied by a storage format control device to a page of an NVM is shown.

[0018] Figure 6 An example of a horizontally scaled single-level cell (SLC) storage format applicable to a page of an NVM according to aspects of the present invention is shown.

[0019] Figure 7An example of a horizontally scaled SLC storage format applicable to a page of an NVM according to aspects of the present invention is shown.

[0020] Figure 8 (including Figures 8A to 8E ) shows an example of a storage format of an NVM according to aspects of the present invention.

[0021] Fig. 9 An exemplary diagram is shown indicating an example storage format applicable to pages of an NVM according to aspects of the present invention.

[0022] Figure 10 (including Fig. 10A and 10B ) illustrates an example magnetic storage medium according to one or more aspects of the present disclosure.

[0023] Fig.11 An embodiment of a device according to one or more aspects of the present disclosure is shown.

[0024] Fig.12 An exemplary operation for use with a controller of an SSD is generally outlined.

[0025] Fig.13 An exemplary operation for use with a controller of an SSD is generally outlined.

[0026] Fig.14 An exemplary operation for use with a controller of an SSD is generally outlined. DETAILED DESCRIPTION

[0027] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features will become apparent by reference to the drawings and the following detailed description. The description of the elements in each figure may refer to the elements of the preceding figures. Like numbers in the drawings may refer to like elements, including alternative embodiments of similar elements.

[0028] Overview

[0029] A data storage system such as a solid-state device (SSD) may include a data storage management system to improve the performance and endurance of non-volatile memory (NVM) (e.g., NAND flash memory) used in the data storage system. For example, the data storage management system may apply a specific error correction code (ECC) rate when storing a set of data bits (also referred to as user bits). This may be achieved by adding a number of parity bits (also referred to as ECC bits) to the set of user bits to form a codeword. For example, n ECC bytes may be added to m data bytes to produce a codeword having m+n bytes. The parity bits in the codeword may be used to correct erroneous user bits in the codeword.

[0030] In some data storage management systems, the ECC rate is fixed during the life of the data storage system (also referred to as fixed ECC (FECC)). This FECC may be designed to deliver a specified sector failure rate (SFR) for the bit error rate (BER) of the NVM at end of life. For example, the end of life of the NVM may be limited by the BER of a portion of the NVM (e.g., a page in a NAND flash block). In addition, the end of life of the NVM may be limited by several outlier regions of the NVM (e.g., NAND flash blocks). For example, such an outlier region of the NVM may include one or more NAND flash blocks having a BER that exceeds the average BER of most (or all) NAND flash blocks in the NVM. Due to the high fail bit count (FBC) of the outlier region, these outlier regions of the NVM are unlikely to be recovered with the default FECC applied by the data storage management system. The FBC indicates the count of erroneous user bits (also referred to as failed user bits), such as bits whose values ​​are erroneously changed when being stored or during a write or read operation.

[0031] In some scenarios, advanced wear-leveling algorithms may swap out or retire outlier areas of NVM (e.g., NAND flash blocks identified as bad blocks). However, this may impair overprovisioning in the data storage system and may compromise the overall performance and durability of the data storage system.

[0032] To address these issues, the present disclosure provides a two-dimensional scalable universal storage format for a data storage system. In one aspect, this may be embodied in a data storage device comprising a non-volatile memory (NVM) and a processor coupled to the NVM. The processor may be configured to: apply a default storage format to a storage area of ​​the NVM, the default storage format configuring the storage area as a number of distinct storage areas logically arranged along a horizontal dimension and a vertical dimension; modify the default storage format based on the performance capability of the storage area using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format; and apply the modified storage format to the storage area. In one aspect, the performance capability may relate to BER, and the data storage device may apply scaling to the storage area in the NVM to achieve a BER that prevents one or more storage areas from being considered unavailable, thereby improving the durability of the NVM. In addition, by reducing the storage format of a storage area (e.g., a page) to improve the reliability of the page, it can be appreciated that the read / write performance (e.g., decoding speed) of the page may also be improved. The method provided herein may be applied to both solid-state devices (SSDs) and hard disk drives (HDDs).

[0033] Sample data storage system

[0034] Figure 11 shows an embodiment of a data storage system 100, which includes a host device 102 and a data storage device 104 communicatively coupled to the host device 102. Although the data storage device 104 can be an SSD or an HDD, it will be directed to Figure 1 The host device 102 (e.g., a host computer) 102 provides a command for transferring data between the host device 102 and the SSD 104 to the SSD 104. For example, the host device 102 may provide a write command for writing data to the SSD 104 to the SSD 104, or provide a read command for reading data from the SSD 104 to the SSD 104. The host device 102 may be any system or device having a need for data storage or retrieval and a compatible interface for communicating with the SSD 104. For example, the host device 102 may be a computing device, a personal computer, a portable computer, a workstation, a server, a personal digital assistant, a digital camera, a digital phone, etc.

[0035] SSD 104 includes a host interface 106, a controller 108, an optional memory 110, and a non-volatile data storage device 112 (also referred to as NVM 112). Host interface 106 is coupled to controller 108 and facilitates communication between host device 102 and controller 108. In addition, controller 108 is coupled to memory 110 and NVM 112. NVM 112 may be, for example, NAND flash memory or a magnetic storage medium.

[0036] The host interface 106 may be any type of communication interface, such as an integrated drive electronics (IDE) interface, a universal serial bus (USB) interface, a serial peripheral (SP) interface, an advanced technology attachment (ATA) interface, a small computer system interface (SCSI), an IEEE 1394 (FireWire) interface, etc. In some aspects, the host device 102 includes the SSD 104 (e.g., the host device 102 and the SSD 104 are implemented as a single component). In other embodiments, the SSD 104 is located remotely from the host device 102 or is included in a remote computing system that is communicatively coupled to the host device 102. For example, the host device 102 may communicate with the SSD 104 via a wireless communication link.

[0037] Controller 108 controls the operation of SSD 104. In various embodiments, controller 108 receives commands from host device 102 via host interface 106 and executes the commands to transfer data between host device 102 and NVM 112. Figure 1As shown in , the controller 108 may include a storage format control device 116. For example, the storage format control device 116 may be configured to apply one or more storage formats to the NVM 112 according to the aspects described in detail herein. The term storage format as used herein may refer to the configuration of distinct storage areas logically arranged along horizontal and vertical dimensions. In some examples, each of the distinct storage areas can be used to store codewords including data bits and parity bits (e.g., ECC bits). In some examples, the storage format may define the ECC strength, codeword structure, and / or media format type to be used when generating and storing codewords. For example, the ECC strength may be quantified in terms of parity overhead. For example, the codeword structure may refer to a combination of data payload and ECC strength.

[0038] Controller 108 may perform internal operations such as garbage collection operations, data integrity operations, and wear leveling operations. Controller 108 may include any type of processing device, such as a microprocessor, microcontroller, embedded controller, logic circuit, software, firmware, etc., for controlling the operation of SSD 104.

[0039] In some embodiments, some or all of the functions described herein as being performed by controller 108 may instead be performed by another element of SSD 104. For example, SSD 104 may include a microprocessor, a microcontroller, an embedded controller, logic circuits, software, firmware, or any kind of processing device for performing one or more of the functions described herein as being performed by controller 108. In some embodiments, one or more of the functions described herein as being performed by controller 108 are instead performed by host device 102. In some embodiments, some or all of the functions described herein as being performed by controller 108 may instead be performed by another element, such as a controller in a hybrid drive that includes both non-volatile memory elements and magnetic storage elements.

[0040] The memory 110 may be any memory, computing device, or system capable of storing data. For example, the memory 110 may be a random access memory (RAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), a flash memory device, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. In various embodiments, the controller 108 uses the memory 110 or a portion thereof to store data during data transfer between the host device 102 and the NVM 112. For example, the memory 110 or a portion of the memory 110 may be a cache memory. In one aspect, the data storage system 100 is configured to be used with a fast non-volatile memory (NVMe) system, wherein the NVM data storage controller (e.g., the controller 108) is configured to control access to NVM devices (e.g., 112) such as NAND memory devices (hereinafter, "NAND") using the NVMe protocol. The NVMe system is a scalable host controller interface for use with system SSDs using Peripheral Component Interconnect Express (PCI) (PCIe). See, for example, the NVM Express Standard, Revision 1.3a, October 24, 2017. However, at least some of the features described herein are applicable to other data storage devices, drives, systems, or protocols.

[0041] Figure 2 A solid state device (SSD) 200 is shown communicating with a host device 202 in accordance with aspects of the present invention. Figure 2 As shown in FIG. 2 , SSD 200 may include controller 206 and NVM 208. Controller 206 may include storage format control device 204. NVM 208 may include one or more NAND blocks, such as NAND block 0 210, NAND block 1 212, and NAND block n-1 214. Figure 2 2, each NAND block may include several pages. For example, NAND block 0 210 may include page 0 216, page 1 218, and page m-1 220, NAND block 1 212 may include page 0 222, page 1 224, and page m-1 226, and NAND block n-1 214 may include page 0 228, page 1 230, and page m-1 232.

[0042] Figure 2Each page (e.g., page 0 216) in the NVM 208 may represent a group of memory cells (also referred to as a word line). In some aspects of the present disclosure, the storage format control device 204 may configure the media format type of the memory cells of the pages in the NVM 208. For example, the storage format control device 204 may configure the media format type of the memory cells of the pages in the NVM 208 to be a single-level cell (SLC) type (e.g., the memory cells of the page may store one bit per cell (1 BPC)), a multi-level cell (MLC) type (e.g., the memory cells of the page may store two bits per cell (2 BPC)), a triple-level cell (TLC) type (e.g., the memory cells of the page may store three bits per cell (3 BPC)), a fractional-level cell type (e.g., the memory cells of the page may store 3.5 bits per cell (3.5 BPC)), or a quad-level cell (QLC) type (e.g., the memory cells of the page may store four bits per cell (4 BPC)).

[0043] In some aspects of the present disclosure, SSD 200 may contain Figure 2 200 (e.g., in different NAND flash memory chips). For example, NVM 208 may include thousands of NAND blocks per block (e.g., n≥1000) and hundreds of pages (e.g., m≥100). Each NVM (e.g., NVM 208), block (e.g., block 0 210), and page (e.g., page 0 216) may have its own unique error correction code (ECC) requirement to maximize its usefulness to SSD 200. This ECC requirement may be determined based on the performance capabilities of the associated data storage area (e.g., NVM array, block, page, etc.) in SSD 200. For example, the performance capabilities (also referred to as states or conditions) of a page or block may be determined based on one or more performance metrics of the storage area. In some aspects, the one or more performance metrics may include at least one of a bit error rate (BER), a bit error count, a number of program-erase cycles, an error correction code (ECC) decoding latency, a program duration, an erase cycle duration, or a read sense duration. For example, BER may vary depending on one or more physical parameters including, but not limited to, semiconductor process variations, wafer location, word line, media format type (e.g., SLC, MLC, TLC, QLC), program-erase cycles, and disturb effects. For example, read sensing duration may refer to the time period required to detect information stored in a memory cell (e.g., a voltage level corresponding to a bit value or sequence of bit values) during a read operation.

[0044] Aspects described herein may enable each data storage region (e.g., NVM array, block, and / or page) of NVM 208 to have a unique ECC strength, codeword structure, and / or media format type. In some aspects of the present disclosure, storage format control device 204 may select the most appropriate storage format for a data storage region (e.g., block, page, etc.) to meet minimum (e.g., worst case) endurance and reliability requirements for the data storage region and a range within the data storage region.

[0045] In some aspects of the present disclosure, the storage format control device 204 may determine the performance capabilities (e.g., BER) of the data storage regions in the SSD 200. In some aspects of the present disclosure, the storage format control device 204 may apply a two-dimensional scalable storage format to the data storage regions. The two-dimensional scalable storage format may enable adaptation of the storage format (e.g., including both ECC and media format types) according to the requirements of each data storage region (e.g., block, page, etc.) and the individual ranges and requirements within each data storage region. In some aspects of the present disclosure, the storage format control device 204 may select a storage format that maximizes the data payload storage space of the data storage region at the expense of the durability of the data storage region.

[0046] Figure 3 2 shows a first example of a memory space allocation 300 that can be applied to a page of an NVM according to aspects of the present invention. For example, the storage format control device 204 can apply the memory space allocation 300 to a page (e.g., page 0 216) of a block (e.g., block 0 210) in the NVM 208. Figure 3 As shown, the page size 302 of the page may be L bytes. Figure 3 As further shown in FIG. 1 , M bytes of the available L bytes may be allocated for storing data payload (e.g., indicated as Figure 3 The payload area 304 in the L bytes may be allocated for storing parity information (eg, indicated as Figure 3 3,904 bytes may be allocated to the parity region 306 (e.g., LM=N=3,904). In one example, the page size 302 may be 36,672 bytes (e.g., L=36,672). In this example, 32,768 bytes may be allocated to the payload region 304 (e.g., M=32,768), and the remaining 3,904 bytes may be allocated to the parity region 306 (e.g., LM=N=3,904).

[0047] Figure 4A second example of a storage space allocation 400 that can be applied to a page of an NVM according to aspects of the present invention is shown. For example, the storage format control device 204 can apply the memory space allocation 400 to a page (e.g., page 1 224) of a block (e.g., block 1 212) in the NVM 208. In one example, the page size 402 of the page can be 37,952 bytes (e.g., L=37,952). In this example, 32,768 bytes can be allocated to the payload area 404 (e.g., M=32,768), and the remaining 5,184 bytes can be allocated to the parity area 406 (e.g., LM=N=5,184). It should be noted that although Figure 4 The page size in the instance 402 is greater than Figure 3 302 in the example of , but the size of the payload areas 304 and 404 can be equal. Therefore, for a given payload area, the memory space allocation 400 can provide a parity area (e.g., parity area 406) that is larger than the parity area 306 in the memory space allocation 300. Therefore, in some aspects of the present disclosure, the memory space allocation 400 can provide improved error correction capabilities relative to the memory space allocation 300.

[0048] Figure 5 An example storage format 500 is shown that can be applied by the storage format control device 204 to a page of NVM (e.g., NAND). For example, the storage format 500 can set the media format type of the memory cells of the page to the SLC media format type. In one example, the storage format 500 can be applied to a memory cell having a storage medium ... Figure 3 The memory space allocation 300 discussed herein is a page of an NVM. For example, the page size 502 of the page may be L bytes. Figure 5 As shown in , the storage format control device 204 can divide the L bytes of the page to form eight groups of equal size. In the aspects described herein, each group can be referred to as a logical page (LP). Figure 5, L bytes (e.g., memory cells configured to store a page of L bytes) are partitioned to form logical page 0 508, logical page 1 510, logical page 2 512, logical page 3 514, logical page 4 516, logical page 5 518, logical page 6 520, and logical page 7 522. For example, each logical page may include a data payload region (e.g., data payload regions 524, 526, 528, 530, 532, 534, 536, 538) having a length 504 of A bytes and a corresponding parity region (e.g., parity regions 540, 542, 544, 546, 548, 550, 552, 554) having a length 506 of B bytes. Thus, in this example, the sum of the eight data payload areas 540, 542, 544, 546, 548, 550, 552, 554 (eg, (8) x (A bytes)) may be equal to Figure 3 Accordingly, the sum of the eight parity check areas 540, 542, 544, 546, 548, 550, 552, 554 (eg, (8) x (B bytes)) may be equal to Figure 3 The total number of available bytes in a page (eg, indicated herein as L bytes) may be expressed as (8)(A bytes)+(8)(B bytes).

[0049] In one example, see Figure 5 , if the page size 502 is 36,672 bytes (e.g., L=36,672), each data payload area (e.g., data payload areas 524, 526, 528, 530, 532, 534, 536, 538) may have 4,096 bytes (e.g., A=4096), and each corresponding parity area (e.g., parity areas 540, 542, 544, 546, 548, 550, 552, 554) may have 488 bytes (e.g., B=488). Accordingly, in this example, the total number of available bytes in a page (e.g., indicated herein as L bytes) may be expressed as (8)(4096 bytes)+(8)(488 bytes)=36,672 bytes.

[0050] In another example, see Figure 5, if the page size 502 is 37,952 bytes (e.g., L=37,952), each data payload area (e.g., data payload areas 524, 526, 528, 530, 532, 534, 536, 538) may have 4,096 bytes (e.g., A=4096), and each corresponding parity area (e.g., parity areas 540, 542, 544, 546, 548, 550, 552, 554) may have 648 bytes (e.g., B=648). Accordingly, in this example, the total number of available bytes in a page (e.g., indicated herein as L bytes) may be expressed as (8)(4096 bytes)+(8)(648 bytes)=37,952 bytes.

[0051] Figure 6 6 shows an example of a horizontally scaled SLC storage format 600 that can be applied to a page of an NVM (e.g., NAND) according to aspects of the present invention. For example, the SLC storage format 600 can be applied to a page of an NVM (e.g., NAND) having a Figure 3 The memory space discussed is allocated 300 to the pages of the NVM. Figure 6 In the example shown in FIG. 1 , the storage format control device 204 can divide the L bytes of the page to form seven groups of equal size (also referred to as logical pages (LP)). Figure 6 In the example of , L bytes (e.g., memory cells configured to store a page of L bytes) are divided to form logical page 0 608, logical page 1 610, logical page 2 612, logical page 3 614, logical page 4 616, logical page 5 618, and logical page 6 620. For example, each logical page may include a data payload region (e.g., data payload regions 622, 624, 626, 628, 630, 632, 634) having a length 604 of A bytes and a corresponding parity region (e.g., parity regions 636, 638, 640, 642, 644, 646, 648) having a length 606 of B bytes.

[0052] In one example configuration, the page size 602 may be the same as Figure 5 502 in . For example, page size 602 may be 36,672 bytes (eg, L=36,672). In this example, Figure 6 Each data payload area in (e.g., data payload areas 622, 624, 626, 628, 630, 632, 634) may be configured to be Figure 5 The same size as the data payload area (e.g., data payload area 524) in FIG. Figure 6Each data payload area in the page (e.g., data payload areas 622, 624, 626, 628, 630, 632, 634) may have 4,096 bytes (e.g., A=4096). The remaining 8,000 bytes in the page (e.g., L-7(A)=36,672 bytes-7(4096) bytes=8,000 bytes) may be used to store parity information. Therefore, in this example, each corresponding parity area (e.g., parity areas 636, 638, 640, 642, 644, 646, 648) may have approximately 1,142 bytes (e.g., B=(8,000 bytes) / 7≈1,142 bytes).

[0053] It should be noted that the data payload areas in the horizontally scaled SLC storage format 600 (e.g., data payload areas 622, 624, 626, 628, 630, 632, 634) and the data payload areas in the SLC storage format 500 (e.g., data payload areas 524, 526, 528, 530, 532, 534, 536, 538) are equal in size. However, because the horizontally scaled SLC storage format 600 includes one less logical page than the SLC storage format 500, the horizontally scaled SLC storage format 600 provides larger parity areas for each data payload area (e.g., parity areas 636, 638, 640, 642, 644, 646, 648) as compared to the parity areas in the SLC storage format 500 (e.g., parity areas 540, 542, 544, 546, 548, 550, 552, 554).

[0054] Figure 7 An example of a horizontally scaled single-level cell (SLC) storage format 700 that can be applied to a page of an NVM (e.g., a NAND device) according to aspects of the present invention is shown. For example, the SLC storage format 700 can be applied to a page of an NVM (e.g., a NAND device) having a Figure 4 The memory space discussed is allocated 400 to the pages of the NVM. Figure 7 In the example shown in FIG. 1 , the storage format control device 204 can divide the L bytes of the page to form nine groups of equal size (also referred to as logical pages (LP)). Figure 7In the example of , L bytes (e.g., memory cells configured to store a page of L bytes) are divided to form logical page 0 708, logical page 1 710, logical page 2 712, logical page 3 714, logical page 4 716, logical page 5 718, logical page 6 720, logical page 7 722, and logical page 8 724. For example, each logical page may include a data payload region (e.g., data payload regions 726, 728, 730, 732, 734, 736, 738, 740, 742) having a length 704 of A bytes and a corresponding parity region (e.g., parity regions 744, 746, 748, 750, 752, 754, 756, 758, 760) having a length 706 of B bytes.

[0055] In one example configuration, the page size 702 may be the same as Figure 5 502 in . For example, page size 702 may be 37,952 bytes (eg, L=37,952). In this example, Figure 7 Each data payload area in (e.g., data payload areas 726, 728, 730, 732, 734, 736, 738, 740, 742) may be configured to be Figure 5 The same size as the data payload area (e.g., data payload area 524) in FIG. Figure 7 Each data payload area in the page (e.g., data payload areas 726, 728, 730, 732, 734, 736, 738, 740, 742) may have 4,096 bytes (e.g., A=4096). The remaining 1,088 bytes in the page (e.g., L-9(A)=37,952 bytes-9(4096) bytes=1,088 bytes) may be used to store parity information. Therefore, in this example, each respective parity area (e.g., parity areas 744, 746, 748, 750, 752, 754, 756, 758, 760) may have approximately 120 bytes (e.g., B=(1,088 bytes) / 9≈120 bytes).

[0056] It should be noted that the data payload areas in the horizontally scaled SLC storage format 700 (e.g., data payload areas 726, 728, 730, 732, 734, 736, 738, 740, 742) and the data payload areas in the SLC storage format 500 (e.g., data payload areas 524, 526, 528, 530, 532, 534, 536, 538) are equal in size. However, because the horizontally scaled SLC storage format 700 includes one more logical page than the SLC storage format 500, the horizontally scaled SLC storage format 700 provides a smaller parity area for each data payload area (e.g., parity areas 744, 746, 748, 750, 752, 754, 756, 758, 760) as compared to the parity areas in the SLC storage format 500 (e.g., parity areas 540, 542, 544, 546, 548, 550, 552, 554).

[0057] Figure 8 (including Figures 8A to 8E ) shows an example of a storage format of a NVM according to aspects of the present invention. In some aspects of the present disclosure, Fig. 8A 800 may be an example of a default storage format 800 applied to a page in an NVM. As previously described, a page in an NVM may represent a group of memory cells (also referred to as a word line), and the page size 802 of the page may be L bytes. Fig. 8A As shown in the example configuration of , L bytes of a page (e.g., memory cells of a page) can be divided to form eight groups of equal size, such as a first group 806 (also referred to as group 0) and an eighth group 808 (also referred to as group 8). In addition, in the default storage format 800, each memory cell of a page can be configured as a quad-level cell (QLC). Accordingly, each memory cell can store four bits. Fig. 8A , each of the four bits stored at the memory cells of the group can correspond to a different logical page (LP). For example, the first bit of the memory cells in the first group 806 can correspond to the lower logical page 0 (LP0), the second bit of the memory cells in the first group 806 can correspond to the middle logical page 0 (MP0), the third bit of the memory cells in the first group 806 can correspond to the upper logical page 0 (UP0), and the fourth bit of the memory cells in the first group 806 can correspond to the top logical page 0 (TP0).

[0058] In the default storage format 800, a portion of the available storage space in each logical page may be allocated for storing data bits (also referred to as a data payload area), while the remaining portion of the available storage space in each logical page may be allocated for storing parity information (also referred to as a parity area). In some aspects of the present disclosure, the parity information may include parity bits (also referred to as error correction code (ECC) bits). In some aspects of the present disclosure, each logical page in the default storage format 800 may have the same length, such as length 804. In one example, similar to Figure 5 In the configuration of FIG. 8 , if the page size 802 is 36,672 bytes (e.g., L=36,672), each logical page may include a data payload area of ​​4,096 bytes (e.g., A=4096) and a corresponding parity area of ​​488 bytes (e.g., B=488). Accordingly, in this example, the total number of available bytes in each row of the logical page (e.g., row 810) may be expressed as (8)(4096 bytes)+(8)(488 bytes)=36,672 bytes.

[0059] Fig. 8A The default storage format 800 in the embodiment of the present invention can be viewed as having two dimensions. For example, the first dimension (also referred to as the horizontal dimension) of the default storage format 800 can refer to the number of logical pages in each row (e.g., row 807) of the default storage format 800. The second dimension (also referred to as the vertical dimension) of the default storage format 800 can refer to the number of logical pages in each column (e.g., logical pages LP0, MP0, UP0, and TP0 in column 809) of the default storage format 800. Although the terms horizontal dimension and vertical dimension as used herein may seem to imply that the two dimensions are the same, the horizontal dimension and vertical dimension are the same as the horizontal dimension. Figures 8A to 8E , but they refer only to the first and second dimensions of the storage region as scalable features of the storage region. The first or horizontal dimension can refer to the number of logical pages in a page consisting of a preselected number of multi-level storage cells. The second or vertical dimension can refer to the number of storage levels in one of the multi-level storage cells. Therefore, as used herein, horizontal dimension scaling can refer to scaling the number of logical pages used in a given page. On the other hand, as used herein, vertical dimension scaling can refer to scaling the number of bits used per storage cell in a given page. As referred to herein Figures 8B to 8E As described, the default storage format 800 is scalable in the horizontal and / or vertical dimensions depending on the storage reliability and endurance requirements of each storage component in the NVM.

[0060] In some aspects of the present disclosure, the storage format control device 204 may scale the default storage format 800 in the horizontal dimension by increasing or decreasing the number of logical pages in each row of the default storage format 800. In some aspects, the storage format control device 204 may maintain the size of the data payload in each logical page while scaling (e.g., increasing or decreasing) the default storage format 800 in the horizontal dimension. In some aspects, the storage format control device 204 may scale the default storage format 800 in the vertical dimension to increase or decrease the number of bits stored in each memory cell. In some aspects, as described herein, the storage format control device 204 may combine both horizontal and vertical scaling when changing the storage format of a page in the NVM to achieve finer granularity of storage. In these aspects, the storage format control device 204 may configure the storage format of the page to achieve maximum storage efficiency of the page while extending the endurance (also known as persistence) of the NVM.

[0061] Figure 8B An example of a horizontally scaled storage format 810 of pages in a NVM according to aspects of the present invention is shown. Figure 8B As shown in the example of , the controller may shrink (e.g., reduce) the number of logical pages in each row of the default storage format 800. For example, the storage format control device 204 may shrink the horizontal dimension of the default storage format 800 to include seven logical pages (e.g., LP0 to LP6) in each row, as shown in FIG. Figure 8B In one aspect, the storage format control device 204 can be similar to the horizontally scaled storage format 810 of FIG. Figure 6 This horizontal scaling is performed in the manner of the described example. Because each row (e.g., row 807) of the horizontally scaled storage format 810 includes one less logical page than the default storage format 800, the size 812 of each logical page in the horizontally scaled storage format 810 can be larger than the size 804 of each logical page in the default storage format 800. The larger size 812 of each logical page in the horizontally scaled storage format 810 can enable each logical page to include a larger parity area of ​​data payload than each logical page of the default storage format 800. In some aspects of the present disclosure, the payload area in each logical page of the default storage format 800 can be equal to the payload area in each logical page of the horizontally scaled storage format 810.

[0062] Therefore, in some aspects of the present disclosure, the storage format control device 204 may be as follows: Figure 8B The default storage format 800 is shown scaled down in the horizontal dimension to reduce the ECC code rate. For example, the ECC code rate of a logical page can be reduced by increasing the parity region of a given data payload in the logical page (eg, increasing the number of ECC parity bits).

[0063] In the horizontally scaled storage format 810, it should be noted that the storage format control device 204 has not applied any vertical scaling relative to the default storage format 800. Therefore, similar to the default storage format 800, each memory cell of the page is QLC. Accordingly, each memory cell of the page can store four bits. Figure 8B , each of the four bits in the memory cell can correspond to a different logical page. For example, the first bit of the memory cells in the first group 814 can correspond to the lower page 0 (LP0), the second bit of the memory cells in the first group 814 can correspond to the middle page 0 (MP0), the third bit of the memory cells in the first group 814 can correspond to the upper page 0 (UP0), and the fourth bit of the memory cells in the first group 814 can correspond to the top page 0 (TP0).

[0064] Figure 8C 800 of a NVM according to aspects of the present invention. As previously described, a page in the NVM may represent a group of memory cells (also referred to as a word line), and the page size 802 of the page may be L bytes. In some aspects, the storage format control device 204 may shrink (e.g., reduce) the vertical dimension of the default storage format 800 by configuring each memory cell as a triple-level cell (TLC). Accordingly, as Figure 8C As shown, each memory cell can store three bits. Figure 8C As further shown in FIG. 8 , each of the three bits stored at the memory cell can correspond to a different logical page (LP). For example, the first bit of the memory cells in the first group 824 can correspond to a lower logical page 0 (LP0), the second bit of the memory cells in the first group 824 can correspond to a middle logical page 0 (MP0), and the third bit of the memory cells in the first group 824 can correspond to an upper logical page 0 (UP0).

[0065] In the vertically scaled storage format 820, it should be noted that the storage format control device 204 has not applied any horizontal scaling relative to the default storage format 800. Therefore, in some aspects of the present disclosure, the size 822 of each logical page in the vertically scaled storage format 820 may be equal to the size 804 of each logical page in the default storage format 800.

[0066] Fig.8D An example of a horizontally and vertically scaled storage format 830 of an NVM according to aspects of the present invention is shown. Fig.8DAs shown in the example of , the storage format control device 204 can reduce (e.g., decrease) the number of logical pages in each row of the default storage format 800. For example, the storage format control device 204 can reduce the horizontal dimension of the default storage format 800 to include seven logical pages (e.g., LP0 to LP6) in each row, as shown in FIG. Fig.8D In one aspect, the storage format control device 204 can be similar to the storage format control device 204 with respect to the horizontal and vertical scaling of the storage format 830. Figure 6 This horizontal scaling is performed in the manner of the described example. Because each row of the horizontally and vertically scaled storage format 830 contains one less logical page than the default storage format 800, the size 832 of each logical page in the horizontally and vertically scaled storage format 830 can be larger than the size 804 of each logical page in the default storage format 800. The larger size 832 of each logical page in the horizontally and vertically scaled storage format 830 can enable each logical page to contain a larger parity area of ​​data payload than each logical page of the default storage format 800. In some aspects of the present disclosure, the payload area in each logical page of the default storage format 800 can be equal to the payload area in each logical page of the horizontally scaled storage format 830.

[0067] like Fig.8D As further shown in FIG. 8 , the storage format control device 204 can also reduce (e.g., decrease) the vertical dimension of the default storage format 800 by configuring each memory cell as a triple-level cell (TLC). Fig.8D As shown, each memory cell can store three bits. Fig.8D , each of the three bits stored at the memory cells can correspond to a different logical page (LP). For example, the first bit of the memory cells in the first group 834 can correspond to the lower logical page 0 (LP0), the second bit of the memory cells in the first group 834 can correspond to the middle logical page 0 (MP0), and the third bit of the memory cells in the first group 834 can correspond to the upper logical page 0 (UP0). It should be understood that, for example, by reducing the vertical dimension of the storage format 800, the reliability of the associated data storage area can be improved.

[0068] Fig. 8E An example of a horizontally and vertically scaled storage format 840 of an NVM according to aspects of the present invention is shown. Fig. 8E As shown in the example of , the storage format control device 204 may enlarge (e.g., increase) the number of logical pages in each row of the default storage format 800. For example, the storage format control device 204 may enlarge the horizontal dimension of the default storage format 800 to include nine logical pages (e.g., LP0 to LP8) in each row, as shown in FIG. Fig. 8EIn one aspect, the storage format control device 204 can be similar to the storage format control device 204 with respect to the horizontal and vertical scaling of the storage format 840. Figure 7 This horizontal scaling is performed in the manner of the described example. Because each row of the horizontally and vertically scaled storage format 840 includes one more logical page than the default storage format 800, the size 842 of each logical page in the horizontally and vertically scaled storage format 840 can be smaller than the size 804 of each logical page in the default storage format 800. The smaller size 842 of each logical page in the horizontally and vertically scaled storage format 830 can produce each logical page having a parity area with a smaller data payload than each logical page of the default storage format 800. In some aspects of the present disclosure, the payload area in each logical page of the default storage format 800 can be equal to the payload area in each logical page of the horizontally scaled storage format 840.

[0069] like Fig. 8E As further shown in FIG. 8 , the storage format control device 204 can also reduce (e.g., decrease) the vertical dimension of the default storage format 800 by configuring each memory cell as a TLC media format type. Fig. 8E As shown, each memory cell can store three bits. Fig. 8E , each of the three bits stored at the memory cells can correspond to a different logical page (LP). For example, the first bit of the memory cells in the first group 844 can correspond to the lower logical page 0 (LP0), the second bit of the memory cells in the first group 844 can correspond to the middle logical page 0 (MP0), and the third bit of the memory cells in the first group 844 can correspond to the upper logical page 0 (UP0).

[0070] As described herein, the storage format control device 204 may perform horizontal scaling for pages in the NVM relative to a default storage format (e.g., the default storage format 800) to implement different storage formats. In one example, the storage format control device 204 may perform horizontal scaling to implement a storage format that includes fewer logical pages with larger parity regions than the default storage format (e.g., the storage format 810). In another example, the storage format control device 204 may perform horizontal scaling to implement a storage format that includes more logical pages with smaller parity regions than the default storage format (e.g., the storage format 840). Because horizontal scaling may increase or decrease the size of the parity region of the data payload in each logical page, the storage format control device 204 may perform horizontal scaling to implement a desired ECC format type for the pages in the NVM.

[0071] In one example configuration, a default storage format (e.g., storage format 800) obtained by dividing the L bytes of a page into eight logical pages may be identified as an 8 / 8ECC format type. Other storage formats achieved by horizontally scaling this default storage format may be identified as x / 8ECC format types, where x represents the number of logical pages resulting from the horizontal scaling operation. For example, a storage format including nine logical pages (e.g., x=9) in each row (e.g., row 846) may be identified as an 8 / 8ECC format type. Fig. 8E The storage format 840 in FIG. 840 may be referred to as having a 9 / 8 ECC format type. As another example, a storage format including seven logical pages (eg, x=7) in each row (eg, row 838) may be referred to as having a 9 / 8 ECC format type. Fig.8D The storage format 830 in may be referred to as having a 7 / 8 ECC format type.

[0072] According to aspects described herein, an x / 8 ECC format type (where x<8) can improve the storage reliability of pages in NVM at the expense of storage efficiency. In other words, the number of parity bits of a page can be increased while the data storage capacity of the page can be reduced (e.g., due to a reduction in the number of logical pages). Figure 6 This scenario is observed in the example of the horizontally scaled SLC storage format 600 shown. In addition, the x / 8 ECC format type (where x>8) can increase the storage efficiency of pages in the NVM at the expense of storage reliability. In other words, the data storage capacity of the page can be increased (e.g., due to the increase in the number of logical pages), while the number of parity bits of the page can be reduced. Figure 7 This scenario is observed in the example of the horizontally scaled SLC storage format 700 shown in FIG.

[0073] Fig. 9 An exemplary diagram 900 is shown indicating an example storage format applicable to a page of an NVM (e.g., an NVM such as NAND) according to aspects of the present disclosure. In some aspects of the present disclosure, the storage format control device 204 may select and / or apply the storage format control device 204 described herein with respect to Fig. 9 An example storage format is described.

[0074] like Fig. 9, the storage format control device 204 may select the storage format of a page in the NVM by configuring the media format type of the memory cells of the page and / or the ECC format type applied to the page. In some aspects, for example, the storage format control device 204 may configure the media format type of the memory cells of the page to be an SLC type 902 (e.g., the memory cells of the page may store one bit per cell (1 BPC)), an MLC type 904 (e.g., the memory cells of the page may store two bits per cell (2 BPC)), a TLC type 906 (e.g., the memory cells of the page may store three bits per cell (3 BPC)), a fractional level cell type 908 (e.g., the memory cells of the page may store 3.5 bits per cell (3.5 BPC)), or a QLC type 910 (e.g., the memory cells of the page may store four bits per cell (4 BPC)). In some aspects, for example, the storage format control device 204 may select the 9 / 8ECC format type 912, the 8 / 8ECC format type 914, the 7 / 8ECC format type 916, or the 6 / 8ECC format type 918. As described herein, the 8 / 8ECC format type 914 may represent a default storage format type (e.g., the default storage format type 800).

[0075] An exemplary diagram 900 indicates the possible number of logical pages that may be configured in a page of an NVM for a given media format type and an ECC format type. In some aspects of the present disclosure, the number of logical pages indicated in diagram 900 may refer to logical pages that include the same data payload size (e.g., a data payload size of 4096 bytes). In some aspects of the present disclosure, the number of logical pages in different columns of diagram 900 may refer to logical pages that include parity regions of different sizes (e.g., due to horizontal scaling as described herein). In a first example, referring to diagram 900, if the storage format control device 204 configures the media format type of the memory cells of the page to a QLC type 910 and applies an 8 / 8 ECC format type 914, the page may include 32 logical pages. This configuration may represent the default storage format 800 discussed previously with reference to FIG. 8. For example, it can be seen that the default storage format 800 includes four rows, each row containing eight logical pages (e.g., 4×8=32 logical pages). In a second example, referring to diagram 900, if the storage format control device 204 configures the media format type of the memory cells of the page as the SLC type 902 and applies the 9 / 8ECC format type 912, the page may include nine logical pages. According to aspects described herein, the parity region included in each of the nine logical pages of the second example may be smaller than the parity region included in each of the 32 logical pages of the first example.

[0076] In some aspects of the present disclosure, the storage format control device 204 may select a storage format for one or more pages of the NVM based on one or more criteria. In one aspect, the criteria may include one or more performance metrics of the page. For example, the one or more criteria may include a bit error rate (BER), a bit error count, a number of program-erase cycles, an ECC decoding delay, a program duration, an erase cycle duration, a read sense duration, and / or any other data that may indicate the reliability and / or endurance of the storage medium (e.g., a page of the NVM).

[0077] In one example embodiment, the criteria for selecting the storage format of the page may be based on the BER of the page, and the storage format control device 204 may apply the storage format according to the BER of the page. The storage format control device 204 may obtain the BER of the page by decoding the codeword stored in the page and determining the number of failed bits (e.g., error bits) in the codeword. The storage format control device 204 may then determine the ratio of the number of failed bits to the number of bits in the codeword to obtain the BER. In some aspects of the present disclosure, the storage format control device 204 may monitor (e.g., track) the BER of one or more pages in the NVM 208.

[0078] In one example, the storage format control device 204 may apply a first storage format when the BER exceeds a first threshold, and apply a second storage format when the BER exceeds a second threshold, and so on. The storage format control device 204 may select a storage format with lower storage efficiency and / or a more robust ECC format as the BER of the page increases. For example, the storage format control device 204 may monitor the BER of pages configured in a default storage format. In one example, the default storage format may be Fig. 8A The default storage format in 800. Accordingly, see Fig. 9 , the page may be configured with a QLC media format type 910 and an 8 / 8ECC format type 914. Therefore, see Fig. 9 , a page may include 32 logical pages. In this example, if the BER of the page exceeds the first threshold, the storage format control device 204 may horizontally reduce the default storage format to the 7 / 8ECC format type 914 to improve storage reliability. Fig. 9 , a page may include 28 logical pages. Continuing with this example, if the BER of the page still exceeds the first threshold, the storage format control device 204 may further reduce the storage format horizontally to the 6 / 8ECC format type 914 to further improve storage reliability. Fig. 9 , a page may include 24 logical pages. If the BER of the page continues to exceed the first threshold, the storage format control device 204 may vertically reduce the storage format by configuring the memory cells of the page as TLC type 906. Therefore, see Fig. 9, a page may include 18 logical pages. While maintaining the same ECC format type (e.g., 6 / 8ECC format type 918), by converting the memory cells of the page from QLC type 910 to TLC type 906, the page may be more robust and resilient to errors,

[0079] In some aspects of the present disclosure, the first threshold previously described may be set to a BER that represents the maximum BER that a storage region may have in order to be considered as an available storage region (e.g., a good block in NAND). In other words, a storage region having a BER exceeding this maximum BER may be considered unavailable (e.g., a bad block in NAND). Therefore, the previously described method may enable storage regions in an NVM (e.g., NVM 208) to achieve a BER that prevents the one or more storage regions from being considered unavailable, thereby improving the durability of the NVM. In addition, by reducing the storage format of the page as previously described to improve the reliability of the page, it can be appreciated that the read / write performance (e.g., decoding speed) of the page may also be improved.

[0080] In some aspects of the present disclosure, the storage format control device 204 can track the BER of the page in real time. In these aspects, the storage format control device 204 can dynamically select and apply the appropriate storage format to the page based on the current value of the BER based on the aspects described herein.

[0081] In some aspects of the present disclosure, the storage format control device 204 may be configured to select a storage format of a page that provides the greatest storage efficiency. Fig. 9 , if the first storage format (e.g., the storage format applying the fractional hierarchical unit media format type 908 and the 8 / 8ECC format type 914) can provide 28 logical pages and the second storage format (e.g., the storage format applying the TLC type 906 and the 9 / 8ECC format type 912) can provide 27 logical pages, the storage format control device 204 can prefer to apply the first storage format. For example, the fractional hierarchical unit media format type 908 can be applied by using full sequence reading and advanced signal processing technology.

[0082] In some aspects of the present disclosure, the storage format control device 204 may be configured to select the storage format that provides the most program-erase cycles for the page. For example, in these aspects, if the second storage format in the previous example provides more program-erase cycles for the page than the first storage format, the storage format control device 204 may select the second storage format. Therefore, by selecting the second storage format that provides a larger number of program-erase cycles, the storage format control device 204 can increase the endurance of the page.

[0083] As previously described, aspects of the present invention can improve the performance and durability of NVM. The horizontal and / or vertical dimensions of the storage format described herein can allow each storage region (e.g., page, block, etc.) of NVM 208 to have a unique ECC strength, codeword structure, and / or media storage type. The storage format control device 204 can determine the most appropriate storage format for the data storage region to meet the persistence and reliability requirements of the data storage region. The storage format control device 204 can further determine the storage format of each storage region to maximize user data during the life of the NVM 208.

[0084] For example, if one or more pages of a block in a NAND begins to perform below an acceptable level such that the controller of the NAND will consider the block as a bad block, the disclosed storage format control device 204 can apply aspects described herein to improve the performance (e.g., storage reliability) of the one or more pages. Due to the improved performance, the block may no longer be considered a bad block (e.g., the controller 206 may continue to use the block), and therefore, the endurance of the storage device may be increased.

[0085] In some aspects of the present disclosure, the techniques described herein may be applied during the manufacturing phase of a data storage system (e.g., an SSD). For example, a storage format control device (e.g., storage format control device 204) may identify one or more regions of NVM that are deemed unusable (e.g., one or more bad blocks in NAND), and may apply a scaled storage format to enable use of such one or more regions of NVM.

[0086] Figure 10 (including Fig. 10A and 10B ) illustrates an example magnetic storage medium 1002 according to one or more aspects of the present disclosure. Fig. 10A A top view of an example magnetic storage medium 1002 according to one or more aspects of the present disclosure is shown. For example, the magnetic storage medium 1002 may be implemented in a hard disk drive (HDD), and the magnetic storage medium 1002 may spin when data is written to (or read from) the magnetic storage medium 1002. In some examples and as shown in FIG. 10, the magnetic storage medium 1002 may be configured to store information on one or more concentric circular tracks (e.g., tracks 1004, 1006). The density of information (e.g., bits) stored along the tracks may be expressed as bits per inch (BPI), and the density of tracks in the magnetic storage medium 1002 may be expressed as tracks per inch (TPI).

[0087] Fig. 10BA conceptual diagram of tracks of an example magnetic storage medium 1002 is shown in accordance with one or more aspects of the present disclosure. In the conceptual diagram, the tracks (e.g., 1004, 1006) have been redrawn as straight lines separated by track intervals. In this embodiment, the BPI may indicate the number of bits that can be stored along a track having a track length of one inch (e.g., first length 1008), and the TPI may indicate the number of tracks within a radial length of one inch (e.g., second length 1010) as measured along the radius of the magnetic storage medium 1002.

[0088] In some aspects of the present disclosure, a data storage system (eg, an HDD) may apply the example storage formats and / or scaling operations described herein to a magnetic storage medium (eg, magnetic storage medium 1002). Fig. 8A 1002, a first dimension (also referred to as a horizontal dimension) of the default storage format 800 may correspond to a tangential direction of the magnetic storage medium 1002, wherein the tangential direction (e.g., along the first length 1008) includes a number of bits that can be stored along a portion of a track (e.g., a BPI) on the magnetic storage medium 1002. A second dimension (also referred to as a vertical dimension) of the default storage format 800 may correspond to a radial direction of the magnetic storage medium 1002, wherein the radial direction (e.g., along the second length 1010) includes a number of tracks based on TPI values ​​that can be stored along a given length of a portion of the magnetic storage medium 1002. Accordingly, the data storage system may perform the horizontal dimension scaling described herein by increasing or decreasing (e.g., controlling) the BPI of the magnetic storage medium 1002, and / or may perform the vertical dimension scaling described herein by increasing or decreasing (e.g., controlling) the TPI of the magnetic storage medium 1002. In some examples, the data storage system may define a number of distinct storage areas (e.g., also referred to as sectors) on the magnetic storage medium 1002, wherein each distinct storage area includes a portion of a number of tracks. The data storage system may increase the storage capacity of each distinct storage region by increasing the TPI of the magnetic storage medium 1002 , and may decrease the storage capacity of each distinct storage region by decreasing the TPI of the magnetic storage medium 1002 .

[0089] An example HDD configured to scale the storage format may implement shingled magnetic recording (SMR). Shingled magnetic recording (SMR) technology achieves an increase in area density compared to contemporary drives using conventional magnetic recording (CMR) technology. Physically, this can be done by sequentially writing data and then overlapping (or "shingling") the data with another data track. By repeating this process, more data tracks can be placed on each magnetic surface. Conventional magnetic recording leaves gaps between recording tracks on the HDD to account for track misalignment (TMR) budgets. These separations affect area density because portions of the disk are not fully utilized. Shingled magnetic recording removes the gaps between tracks by sequentially writing tracks in an overlapping manner, forming a pattern similar to tiles on a roof.

[0090] Due to the shingled format of SMR, data streams are typically organized and written to the media sequentially. Although the methods of SMR implementation may be different, data is typically written to the media sequentially. Therefore, if a particular track needs to be modified or rewritten, the entire track "band" (area) is rewritten. Because the modified data may be located below another "tile" of data, direct modification may not be allowed, which is different from traditional CMR drives. In the case of SMR, the entire row of tiles above the modified track needs to be rewritten in the process. Therefore, SMR technology has some similarities with flash memory, and can also benefit from the methods described in this article for adjusting the granularity of the storage format implemented in NVM.

[0091] In some examples, a data storage system (e.g., an SSD 104 reconfigured as a data storage system that may include solid-state storage components and / or magnetic storage components) may implement shingled magnetic recording (SMR) such that previously described tracks (e.g., tracks 1004, 1006) on the magnetic storage medium 1002 at least partially overlap, which may further increase the storage density (e.g., area density) of the magnetic storage medium 1002. In these examples, the data storage system may perform the horizontal dimension scaling described herein by increasing or decreasing the bit density along the tracks, and / or may perform the vertical dimension scaling described herein by increasing or decreasing the track density in the radial direction across the tracks. As discussed above with respect to embodiments involving SSDs and flash memories, scaling may be based on the performance capabilities of the storage region to obtain a modified storage format. The performance capabilities may be determined based on one or more performance metrics of the storage region, such as a bit error rate (BER), in a storage region (e.g., a sector or zone) of the magnetic media of the HDD. In some cases, some bands (or zones) may exhibit specific behavioral characteristics with respect to area density (TPI*BPI), including an impact on BER. Thus, some consumer applications may require trading BER capability for area density, for example.The present disclosure contemplates a possible approach to presenting tradeoffs between drivers and between regions within a given driver during manufacturing.

[0092] The present disclosure describes a systematic approach for improving the maximum efficiency of SSD / HDD and for extending the durability of SSD / HDD. In some aspects of the present disclosure, such a systematic approach may include using horizontal scaling, vertical scaling, and / or some combination of horizontal scaling and vertical scaling to adjust the granularity of the storage format implemented in NVM. According to various aspects of the present invention, the processes and devices described herein can enable the reuse of areas of NVM that would otherwise be considered unusable in a data storage system (e.g., bad blocks in NAND flash memory). In some aspects of the present disclosure, the reuse of these areas may include writing data to these areas and / or reading data from these areas. In some scenarios, the reuse of these areas can improve the over-design of storage space in the data storage system, which can improve the performance of the data storage system.

[0093] Example Device

[0094] Fig.11An embodiment of an apparatus 1100 according to one or more aspects of the present disclosure is shown. The apparatus 1100 may be embodied or implemented within a controller, an SSD, a solid state drive, a host device, an NVM device, a NAND die, or some other type of device that supports data storage. In various embodiments, the apparatus 1100 may be embodied or implemented within a computing device, a personal computer, a portable device or workstation, a server, a personal digital assistant, a digital camera, a digital phone, an entertainment device, a medical device, or any other electronic device that stores data.

[0095] Device 1100 includes a communication interface 1102, a storage medium 1104, an NVM (e.g., an NVM memory circuit) 1108, and a processing circuit 1110 (e.g., at least one processor and / or other suitable circuit). These components can be connected via a signaling bus or other suitable components (generally composed of Fig.11 The signaling bus may include any number of interconnecting buses and bridges depending on the specific application and overall design constraints of the processing circuit 1110. The signaling bus links the various circuits together such that each of the communication interface 1102, the storage medium 1104, and the NVM 1108 are coupled to and / or in electrical communication with the processing circuit 1110. The signaling bus may also link together various other circuits (not shown), such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0096] The communication interface 1102 provides a component for communicating with other devices through a transmission medium. In some embodiments, the communication interface 1102 includes a circuit and / or programming design (e.g., a program) suitable for facilitating the bidirectional information transmission relative to one or more devices in the system. In some embodiments, the communication interface 1102 may be configured to be used for communication based on wire. For example, the communication interface 1102 may be a bus interface, a send / receive interface, or a signal interface of some other type, including a driver, a buffer, or other circuits for outputting and / or obtaining signals (e.g., outputting signals from an integrated circuit and / or receiving signals into an integrated circuit). The communication interface 1102 serves as an example of a component for receiving and / or a component for transmitting.

[0097] NVM 1108 may represent one or more non-volatile memory devices. In some embodiments, NVM 1108 and storage medium 1104 are implemented as a common memory component. NVM 1108 may also be used to store data manipulated by processing circuit 1110 or some other component of device 1100.

[0098] Storage media 1104 may represent one or more computer-readable, machine-readable, and / or processor-readable devices for storing programming such as processor-executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information. Storage media 1104 may also be used to store data that is manipulated by processing circuitry 1110 when executing programming. Storage media 1104 may be any available media that can be accessed by a general or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other media capable of storing, containing, or carrying programming.

[0099] By way of example and not limitation, storage medium 1104 may include a magnetic storage device (e.g., a hard disk, a floppy disk, a magnetic stripe), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, stick, or key drive), a random access memory (RAM), a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), registers, a removable disk, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. Storage medium 1104 may be embodied in an article of manufacture (e.g., a computer program product). By way of example, a computer program product may include a computer-readable medium in packaging material. In view of the above, in some embodiments, storage medium 1104 may be a non-transitory (e.g., tangible) storage medium. For example, storage medium 1104 may be a non-transitory computer-readable medium that stores computer-executable code including code to perform operations as described herein.

[0100] Storage medium 1104 may be coupled to processing circuit 1110 such that processing circuit 1110 may read information from and write information to storage medium 1104. That is, storage medium 1104 may be coupled to processing circuit 1110 such that storage medium 1104 is at least accessible by processing circuit 1110, including instances where at least one storage medium is integral to processing circuit 1110 and / or instances where at least one storage medium is separate from processing circuit 1110 (e.g., resident in device 1100, external to device 1100, distributed across multiple entities, etc.).

[0101] The programming stored by the storage medium 1104, when executed by the processing circuit 1110, causes the processing circuit 1110 to perform one or more of the various functional and / or process operations described herein. For example, the storage medium 1104 may include configurations for regulating operations at one or more hardware blocks of the processing circuit 1110 and for utilizing the communication interface 1102 to communicate wirelessly using its corresponding communication protocol.

[0102] The processing circuitry 1110 is generally adapted for processing, including the execution of such programming stored on the storage medium 1104. As used herein, the terms "code" or "programming" shall be interpreted broadly to include, without limitation, instructions, instruction sets, data, code, code segments, program code, programs, programming, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable programs, threads of execution, programs, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0103] The processing circuit 1110 is arranged to obtain, process and / or send data, control data access and storage, issue commands, and control other desired operations. The processing circuit 1110 may include a circuit configured to implement the desired programming provided by an appropriate medium in at least one instance. For example, the processing circuit 1110 may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable programming. The examples of the processing circuit 1110 may include a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic components, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may include a microprocessor as well as any conventional processor, controller, microcontroller, or state machine. The processing circuit 1110 may also be implemented as a combination of computing components, such as a combination of a controller and a microprocessor, a combination of multiple microprocessors, one or more microprocessors in combination with an ASIC and a microprocessor, or any other number of different configurations. These examples of the processing circuit 1110 are for illustration, and other suitable configurations within the scope of the present disclosure are also contemplated.

[0104] According to one or more aspects of the present disclosure, the processing circuit 1110 may be adapted to perform any or all of the features, processes, functions, operations, and / or routines of any or all of the devices described herein. For example, the processing circuit 1110 may be configured to perform operations relative to Figure 11-13 As used herein, the term "adapted to" with respect to processing circuitry 1110 may refer to processing circuitry 1110 being configured, employed, implemented and / or programmed to perform specific processes, functions, operations and / or routines, one or more of which, in accordance with the various features described herein.

[0105] The processing circuit 1110 may be a dedicated processor, such as an application specific integrated circuit (ASIC), which serves as a processor for executing the combined Figure 11-13The processing circuit 1110 serves as an example of a means for sending and / or a means for receiving. In various embodiments, the processing circuit 1110 may at least partially provide and / or incorporate the above-mentioned means for sending and / or receiving. Figure 1 The functionality described by controller 108 or SSD 104.

[0106] According to at least one example of the apparatus 1100, the processing circuit 1110 may include one or more of the following: a circuit / module 1120 for applying a default storage format, a circuit / module 1122 for modifying the default storage format, a circuit / module 1124 for applying a modified storage format, a circuit / module 1126 for monitoring a bit error rate of a storage area, a circuit / module 1128 for associating a storage area with a modified storage format, and a circuit / module 1130 for storing data in a data storage device. In various embodiments, the circuit / module 1120 for applying a default storage format, the circuit / module 1122 for modifying the default storage format, the circuit / module 1124 for applying a modified storage format, the circuit / module 1126 for monitoring a bit error rate of a storage area, the circuit / module 1128 for associating a storage area with a modified storage format, or the circuit / module 1130 for storing data in an NVM may be provided at least in part and / or incorporated with the above-described circuit / modules. Figure 1 In some aspects of the present disclosure, the circuit / module 1122 for modifying the default storage format may be configured to scale the default storage format 1122 as described herein (e.g., perform horizontal dimension scaling and / or vertical dimension scaling) to provide a scaled storage format. Accordingly, in these aspects, the term modified storage format may be used interchangeably with the term scaled storage format.

[0107] As mentioned above, the program stored by the storage medium 1104, when executed by the processing circuit 1110, causes the processing circuit 1110 to perform one or more of the various functions and / or process operations described herein. For example, the program may cause the processing circuit 1110 to perform the various functions and / or process operations described herein in various embodiments with respect to Figure 11-13 The various functions, steps and / or processes described herein. Fig.11As shown in , the storage medium 1104 may include one or more of the following codes: code 1140 for applying a default storage format, code 1142 for modifying the default storage format, code 1144 for applying a modified storage format, code 1146 for monitoring a bit error rate of a storage region, code 1148 for associating a storage region with a modified storage format, or code 1150 for storing data in an NVM. In various embodiments, code 1140 for applying a default storage format, code 1142 for modifying the default storage format, code 1144 for applying a modified storage format, code 1146 for monitoring a bit error rate of a storage region, code 1148 for associating a storage region with a modified storage format, and code 1150 for storing data in an NVM may be executed or otherwise used to provide the functionality described herein for the circuit / module 1120 for applying a default storage format, the circuit / module 1122 for modifying the default storage format, the circuit / module 1124 for applying a modified storage format, the circuit / module 1126 for monitoring a bit error rate of a storage region, the circuit / module 1128 for associating a storage region with a modified storage format, and the circuit / module 1130 for storing data in an NVM.

[0108] First example process

[0109] Fig.12 Process 1200 is shown according to some aspects of the present disclosure. Process 1200 may occur within a processing circuit (e.g., processing circuit 1010 of FIG. 10 ), which may be located in a controller, an SSD, a solid-state drive, a host device, an NVM device, a NAND die, or some other suitable device. Of course, in various aspects within the scope of the present disclosure, process 1200 may be implemented by any suitable device capable of supporting memory-related operations. It should be understood that Fig.12 A box indicated by a dotted line in the figure represents an optional box.

[0110] At block 1202, the device applies a default storage format to a storage region of the NVM. The default storage format may configure the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. In one example, the NVM may be a NAND device, and the storage region may be a page or block in the NAND device. In another example, the NVM may include a magnetic storage medium, and the storage region may include at least a portion of the magnetic storage medium. In some aspects, the default storage format may configure the storage region as a number of distinct storage regions by dividing the storage region (e.g., a page in the NAND) into a number of distinct storage regions (e.g., logical pages).

[0111] At box 1204, the device modifies (e.g., scales) a default storage format based on the performance capability of the storage region using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format (also referred to as a scaled storage format). In some aspects, the performance capability of the storage region is determined based on one or more performance metrics of the storage region. In some aspects, the one or more metrics include at least one of the following: bit error rate, bit error count, number of program-erase cycles, error correction code (ECC) decoding latency, programming duration, erase cycle duration, or read sensing duration. In some aspects, the horizontal dimension scaling includes controlling the number of parity bits available for each of the distinct storage regions, and the vertical dimension scaling includes controlling the number of bits that can be stored by each memory cell of the storage region. In some aspects, the combination of horizontal dimension scaling and vertical dimension scaling reduces the storage efficiency of the storage region and increases the reliability and durability of the storage region. In some aspects, the modified storage format is configured to increase at least one of the durability of the storage region of the NVM or the reliability of the storage region of the NVM relative to the default storage format.

[0112] At block 1206, the device applies the modified storage format to the storage area.

[0113] At block 1208, the device stores the data in the storage area based on the modified storage format.

[0114] In some aspects, processes according to the teachings herein may include any combination of the above operations.

[0115] Second example process

[0116] Fig.13 Process 1300 is shown according to some aspects of the present disclosure. Process 1300 may occur within a processing circuit (e.g., processing circuit 1010 of FIG. 10 ), which may be located in a controller, an SSD, a solid-state drive, a host device, an NVM device, a NAND die, or some other suitable device. Of course, in various aspects within the scope of the present disclosure, process 1300 may be implemented by any suitable device capable of supporting memory-related operations. It should be understood that Fig.13 A box indicated by a dotted line in the figure represents an optional box.

[0117] At block 1302, a device applies a first storage format to pages of a block in an NVM. The storage format may configure the pages into a first number of logical pages.

[0118] At box 1304, the device determines a second storage format for the page when the bit error rate of the page exceeds a threshold. The second storage format can configure the page as a second number of logical pages, which is less than the first number of logical pages. In some aspects, the second number of logical pages has a higher ECC rate than the first number of logical pages. In some aspects, the second storage format reduces the number of bits that can be stored in each memory cell of the page relative to the first storage format. In some aspects, each of the first number of logical pages and each of the second number of logical pages are configured to store approximately the same amount of data. In some aspects, each of the second number of logical pages is allocated more ECC bits relative to each of the first number of logical pages.

[0119] At block 1306 , the device applies the second storage format to the page.

[0120] At block 1308 , the device stores the data in the page based on the second storage format.

[0121] At block 1310, the device determines a third storage format for the page when the bit error rate of the page exceeds a second threshold. The third storage format configures (e.g., divides) the page into a third number of logical pages, the third number of logical pages being less than the second number of logical pages. In some aspects, the third number of logical pages has a higher ECC rate than the second number of logical pages.

[0122] At block 1312 , the device stores the data in the pages based on the third storage format.

[0123] In some aspects, processes according to the teachings herein may include any combination of the above operations.

[0124] Third example process

[0125] Fig.14 Process 1400 is shown according to some aspects of the present disclosure. Process 1400 may occur within a processing circuit (e.g., processing circuit 1010 of FIG. 10 ), which may be located in a controller, an SSD, a solid-state drive, a host device, an NVM device, a NAND die, or some other suitable device. Of course, in various aspects within the scope of the present disclosure, process 1400 may be implemented by any suitable device capable of supporting memory-related operations. It should be understood that Fig.14 A box indicated by a dotted line in the figure represents an optional box.

[0126] At block 1402, a device monitors a bit error rate of a plurality of storage regions of a NVM, each of the plurality of storage regions having a storage format. In some aspects, each of the plurality of storage regions is approximately equal in size.

[0127] At block 1404 , the device identifies one or more storage regions of the plurality of storage regions having a bit error rate exceeding a threshold.

[0128] At box 1406, the device dynamically scales the storage format of the one or more of the multiple storage areas to reduce the bit error rate of the one or more of the multiple storage areas. In some aspects, the scaled storage format reduces the storage efficiency of the one or more of the multiple storage areas to increase the reliability of the one or more of the multiple storage areas. In some aspects, the scaled storage format reduces the storage efficiency of the one or more of the multiple storage areas to increase the number of parity bits available for the one or more of the multiple storage areas. In some aspects, the first storage area of ​​the one or more of the multiple storage areas has a first scaled storage format, and the second storage area of ​​the one or more of the multiple storage areas has a second scaled storage format, wherein the first scaled storage format is different from the second scaled storage format.

[0129] At block 1408 , the device associates the first storage area with the first scaled storage format and the second storage area with the second scaled storage format.

[0130] At block 1410 , the device stores first data in a first storage area based on a first scaled storage format.

[0131] At block 1412 , the device stores the second data in the second storage area based on the second scaled storage format.

[0132] In some aspects, processes according to the teachings herein may include any combination of the above operations.

[0133] Additional aspects

[0134] The examples set out herein are provided to illustrate the specific concepts of the present disclosure. The equipment, devices or components described above may be configured to perform one or more of the methods, features or steps described herein. Those of ordinary skill in the art will appreciate that these are essentially illustrative only, and other examples may fall within the scope of the present disclosure and the appended claims. Based on the teachings of this article, those of skill in the art should appreciate that the aspects disclosed herein may be implemented independently of any other aspects, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement an apparatus or practice a method. In addition, by using other structures, functionality or structure and functionality other than one or more of the aspects described herein or different from one or more of the embodiments described herein, this apparatus may be implemented or this method may be practiced.

[0135] Aspects of the present disclosure have been described above with reference to schematic flow charts and / or schematic block diagrams of methods, devices, systems, and computer program products according to embodiments of the present disclosure. It should be understood that each frame of the schematic flow charts and / or schematic block diagrams and the combination of frames in the schematic flow charts and / or schematic block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor or other programmable data processing device of a computer to produce a machine, so that instructions executed via a processor or other programmable data processing device create components for implementing the functions and / or actions specified in the frames of one or more schematic flow charts and / or schematic block diagrams.

[0136] The subject matter described herein can be implemented in hardware, software, firmware or any combination thereof. Thus, the terms "function", "module", etc. used herein may refer to hardware, which may also include software and / or firmware components for implementing the described features. In an exemplary embodiment, the subject matter described herein may be implemented using a computer-readable medium having computer-executable instructions stored thereon, which controls the computer to perform the functionality described herein when executed by a computer (e.g., a processor). Examples of computer-readable media suitable for implementing the subject matter described herein include non-transitory computer-readable media, such as disk memory devices, chip memory devices, programmable logic devices, and application-specific integrated circuits. In addition, the computer-readable medium implementing the subject matter described herein may be located on a single device or computing platform, or may be distributed on multiple devices or computing platforms.

[0137] It should also be noted that in some alternative embodiments, the functions mentioned in each block may not occur in the order mentioned in the figure. For example, depending on the functionality involved, the two blocks shown continuously can actually be performed substantially simultaneously, or the blocks can sometimes be performed in reverse order. Other steps and methods can be conceived, which are equivalent to one or more blocks or parts thereof of the drawings shown in function, logic or effect. Although various arrow types and line types can be used in flow charts and / or block diagrams, it should be understood that they do not limit the scope of the corresponding embodiments. For example, an arrow can indicate a waiting or monitoring cycle of unspecified duration between the listed steps of the depicted embodiment.

[0138] The various features and processes described above can be used independently of each other, or can be combined in different ways. All possible combinations and sub-combinations are expected to fall within the scope of the present disclosure. In addition, certain methods, events, states or process blocks can be omitted in some embodiments. The methods and processes described herein are also not limited to any specific sequence, and the blocks or states associated therewith can be performed in other appropriate sequences. For example, the tasks or events described can be performed in an order different from the order disclosed specifically, or multiple tasks or events can be combined in a single block or state. Example tasks or events can be performed serially, in parallel or in some other suitable manner. Tasks or events can be added to or removed from the disclosed example embodiments. The example systems and components described herein can be configured differently from what is described. For example, elements can be added to, removed from or rearranged compared to the disclosed example embodiments.

[0139] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0140] As used herein, the terms "about the same" or "about equal" mean any of the same, equal, up to 1% different, up to 5% different, or up to 10% different. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspect" does not require that all aspects include the discussed feature, advantage, or mode of operation.

[0141] Although the above description includes many specific embodiments of the present invention, these should not be interpreted as limitations on the scope of the present invention, but should be interpreted as examples of its specific embodiments. Therefore, the scope of the present invention should not be determined by the illustrated embodiments, but should be determined by the attached claims and their equivalents. In addition, references to "one embodiment", "embodiment" or similar language throughout this specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearance of the phrases "in one embodiment", "in an embodiment" and similar language throughout this specification may, but not necessarily, all refer to the same embodiment, but refer to "one or more but not all embodiments", unless otherwise explicitly stated.

[0142] The terms used herein are only used to describe the purpose of specific aspects, and do not wish to limit various aspects. As used herein, the singular form "one" and "described" are intended to also include plural forms (i.e., one or more), unless the context clearly indicates otherwise. Unless otherwise clearly stated, the enumerated list of items does not mean that any or all items are mutually exclusive and / or mutually inclusive. It should be further understood that, unless otherwise clearly stated, the terms "include", "comprise", "have", and its variants used herein refer to "including but not limited to". That is, these terms can specify the existence of stated features, integers, steps, operations, elements or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components or their groups. In addition, it should be understood that, unless otherwise clearly stated, the word "or" has the same meaning as the Boolean operator "OR", that is, it covers the possibility of "any" and "all", and is not limited to "XOR" ("XOR"). It should also be understood that, unless otherwise clearly stated, the symbol " / " between two adjacent words has the same meaning as "or". Additionally, phrases such as "connected to," "coupled to," or "in communication with," are not limited to direct connections unless expressly stated otherwise.

[0143] Any reference to an element using names such as "first", "second" etc. herein does not generally limit the amount or order of those elements. In fact, these names can be used as a convenient method to distinguish two or more elements or element instances in this article. Therefore, the reference to the first and second elements does not mean that only two elements can be used here, or that the first element must precede the second element in a certain way. And, unless otherwise specified, a group of elements may include one or more elements. In addition, the term "at least one of a, b or c" or "a, b, c or any combination thereof" used in the description or claims means "a or b or c, or any combination of these elements". For example, this term can include a or b or c, or a and b, or a and c, or a and b and c, or 2a or 2b or 2c, or 2a and b, etc.

[0144] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), confirming, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, selecting, choosing, establishing, and the like.

Claims

1. A data storage device, comprising: Non-volatile memory NVM; a processor coupled to the NVM and configured to: applying a default storage format to a storage area of ​​the NVM, the default storage format configuring the storage area into a plurality of distinct storage areas logically arranged along a horizontal dimension and a vertical dimension; measuring a performance metric of the storage region, the performance metric representing a duration of a storage operation applied to the storage region; determining, based on the performance metric, whether the storage area is operating below a threshold performance level; In response to determining that the storage region is operating below a threshold performance level, modifying the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling to obtain a modified storage format; applying the modified storage format to the storage area, thereby reconfiguring the storage area; as well as The data is stored in the storage area according to the modified storage format. 2 . The data storage device of claim 1 , wherein the storage operation comprises at least one of a read operation, a program operation, an error correction operation, or an erase operation.

3. The data storage device of claim 2, wherein the performance metric comprises at least one of: an error correction code (ECC) decoding duration, a programming duration, an erase cycle duration, or a read sensing duration.

4. A data storage device according to claim 1, wherein the processor is further configured to apply the horizontal dimension scaling by controlling the number of parity bits available for each of the different storage regions, and the processor is further configured to apply the vertical dimension scaling by controlling the number of bits that can be stored by each memory cell of the storage region.

5. The data storage device of claim 1, wherein the processor is further configured to select the combination of horizontal dimension scaling and vertical dimension scaling to reconfigure the storage region so that the storage region no longer operates below the threshold performance level.

6. The data storage device of claim 1, wherein the processor is further configured to modify the default storage format using a combination of vertical scaling and horizontal scaling sets to increase total data storage over the life of the storage area.

7. The data storage device of claim 1, wherein the NVM comprises a NAND device, and the storage area is a page or a block in the NAND device.

8. The data storage device of claim 1, wherein the NVM comprises a magnetic storage medium and the storage area includes at least a portion of the magnetic storage medium.

9. A data storage device according to claim 8, wherein the processor is further configured to apply the horizontal dimension scaling by controlling the number of bits per inch (BPI) stored in one or more tracks of at least one portion of the magnetic storage medium, and wherein the processor is further configured to apply the vertical dimension scaling by controlling the number of tracks per inch (TPI) used for at least one portion of the magnetic storage medium.

10. The data storage device of claim 9, wherein the processor is further configured to store information on the magnetic storage medium using shingled magnetic recording.

11. A method of operating a data storage device, comprising: applying a first storage format to pages of a block in a non-volatile memory NVM, wherein the first storage format configures the pages as a first number of logical pages having a first number of parity bits; measuring a performance metric for the page, the performance metric representing a duration of a storage operation applied to the page; determining whether the page has an unused storage area based on the performance metric; In response to determining that the page has an unused storage area, determining a second storage format for the page, wherein the second storage format configures the page as a second number of logical pages having a second number of parity bits; as well as applying the second storage format to the page, thereby reconfiguring the page; as well as The data is stored in the page according to the second storage format.

12. The method of claim 11, wherein the performance metric comprises at least one of an error correction code (ECC) decoding duration, a programming duration, an erase cycle duration, or a read sensing duration.

13. The method of claim 11, wherein the determining the second storage format further comprises selecting the second number of logical pages and the second number of parity bits such that the pages no longer have unused storage areas.

14. The method of claim 11, wherein the determining the second storage format further comprises configuring the page to employ a fractional hierarchical unit media format.

15. The method of claim 11, wherein each of the second number of logical pages is allocated more error correction code (ECC) bits relative to each of the first number of logical pages.

16. The method of claim 11, wherein said determining said second storage format further comprises selecting said second number of logical pages and said second number of parity bits to increase total data storage over a lifetime of said pages.

17. The method of claim 11, wherein the storage operation comprises at least one of a read operation, a program operation, an error correction operation, or an erase operation.

18. A data storage device comprising: A non-volatile memory NVM including a plurality of storage areas; means for monitoring a performance metric indicative of a duration of storage operations applied within the plurality of storage areas of the NVM, each of the plurality of storage areas having a storage format including a media format and an error correction code format (ECC format); means for identifying one or more storage areas of the plurality of storage areas wherein the performance metric is below a threshold performance level; as well as Means for dynamically scaling the storage format of the one or more storage areas of the plurality of storage areas by modifying a combination of the media format and the ECC format so the performance metric no longer falls below the threshold performance level.

19. The data storage device of claim 18, wherein the means for dynamically scaling the storage format comprises means for selecting a combination of the media format and the ECC format such that each of the plurality of storage regions no longer falls below the threshold performance level.

20. The data storage device of claim 18, wherein the means for dynamically scaling the storage format comprises means for configuring the storage format to include a fractional hierarchical unit media format.

21. The data storage device of claim 18, wherein the means for dynamically scaling the storage format comprises means for selecting a combination of the media format and the ECC format to increase total data storage over the life of the one or more of the plurality of storage areas.

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