Method for producing a diode

Abstract

The present disclosure relates to a method for producing a diode. A circuit is provided, comprising at least one bipolar transistor and at least one variable capacitance diode. A method is used to manufacture the circuit, wherein the bipolar transistor and the variable capacitance diode are produced together on a common substrate.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority to French patent application No. 1907150, filed on June 28, 2019, the entire contents of which are incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to methods for producing electronic components, and more particularly, to methods for producing variable capacitance diodes (also known as varactors or varactors). Background Art

[0004] A varactor is an electronic dipole provided with two terminals, between which a pn junction is formed.

[0005] When the varactor is subjected to direct polarization, the varactor has an operation similar to a conventional diode, ie when a certain voltage threshold is exceeded, the varactor switches on.

[0006] If, on the other hand, a reverse polarization voltage is applied between the terminals of a varactor, the varactor differs from a conventional diode in the off state in that the varactor behaves not like an open circuit in theory but like a capacitor. In practice, a similar capacitance phenomenon also occurs for a reverse biased conventional diode, but to a lesser extent.

[0007] While this capacitance phenomenon is avoided as much as possible in the case of conventional diodes, it is encouraged as much as possible in the case of varactor diodes.

[0008] There is a need in the art to increase the capacitance of current variable capacitance diodes. There is a need for further improved methods that enable the production of variable capacitance diodes. Summary of the invention

[0009] One embodiment addresses all or some of the disadvantages of known varactors and methods of producing the same.

[0010] One embodiment provides a method for jointly producing at least one bipolar transistor and at least one variable capacitance diode on the same (ie, common or shared) substrate.

[0011] According to one embodiment, the diode comprises a pn junction comprising: a first region of a first conductivity type; and a second region of a second conductivity type; the second region and the intrinsic base of the bipolar transistor being made during the same step.

[0012] According to one embodiment, the second region is made flush with an extrinsic collector region constituting the first region.

[0013] According to one embodiment, the second region is produced by epitaxy.

[0014] According to one embodiment, the diode includes a third region of the first conductivity type, the third region being interposed between the first region and the second region.

[0015] According to one embodiment, said third region and the intrinsic collector of said transistor are made during the same step.

[0016] According to one embodiment, the third region is formed by epitaxy.

[0017] According to one embodiment, the first conductivity type is n and the second conductivity type is p.

[0018] According to one embodiment, the first conductivity type is p and the second conductivity type is n.

[0019] According to one embodiment, the diode comprises a varactor having a hyperabrupt pn junction.

[0020] One embodiment provides the described method, which has the following steps: providing a substrate, having a first sinker and a second sinker in at least a first non-intrinsic collector region on the inner side of the substrate, and having a third sinker in at least a second non-intrinsic collector region on the inner side of the sinker; forming a stack having a first layer, a second layer, a third layer and a fourth layer from the upper surface of the substrate; forming a first opening and a second opening in the second layer, the third layer and the fourth layer; producing a first spacer inside the first opening and the second opening; and making a third opening and a fourth opening in the first layer.

[0021] One embodiment provides the described method, which has the following steps: depositing a fifth layer and a sixth layer on the side of the upper surface; protecting the first area of ​​the sixth layer by the area of ​​the seventh layer; removing the sixth layer, except for the first area of ​​the sixth layer and the second and third areas of the sixth layer; removing the area of ​​the seventh layer; removing the area of ​​the fifth layer that is not covered; depositing an eighth layer on the side of the upper surface; removing the eighth layer, except for the area of ​​the eighth layer covered by the area of ​​the ninth layer, and removing the first area of ​​the sixth layer; removing a part of the area of ​​the fourth layer that is not covered and removing the area of ​​the ninth layer; separating the first and second areas of the tenth layer by the first and second areas Respectively protect future diodes and future transistors, and remove unprotected parts of the first, second and third areas of the third and fourth layers; remove parts of the area of ​​the first layer that is not covered, and remove the first and second areas of the tenth layer; produce a second spacer filled in a right angle on the side of the upper surface; and produce a first contact, a second contact and a third contact on the first, second and third sinker areas, respectively, produce a third contact on the first deposit, produce a fourth contact on the first part of the area of ​​the second layer, produce a fifth contact on the second part of the area of ​​the second layer and produce a sixth contact on the area of ​​the eighth layer.

[0022] One embodiment provides the method having the steps of filling the third opening with a second deposit and with the first deposit, and filling the fourth opening with a third deposit and a fourth deposit.

[0023] One embodiment provides the method having the steps of filling the third opening with the first deposit and filling the fourth opening with a fifth deposit.

[0024] One embodiment provides an electronic circuit comprising at least one variable capacitance diode and at least one bipolar transistor obtained using the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The foregoing features and advantages as well as other features and advantages will be described in detail in the following description of specific embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0026] Figures 1 to 18 Successive steps of an embodiment of a method for producing a varactor are schematically shown in cross section; and

[0027] Fig.19 The variation curve of the characteristics of the varactor diode obtained using the embodiment of the method is shown. DETAILED DESCRIPTION

[0028] In the various drawings, similar features have been denoted by similar reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties.

[0029] For the sake of clarity, only the operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, the method for preparing the substrate is not described in detail.

[0030] Unless otherwise specified, when referring to two elements being connected together, it means a direct connection without any intermediate elements other than conductors, and when referring to two elements being coupled together, it means the two elements may be connected or they may be coupled via one or more other elements.

[0031] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.), or orientation qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the figure.

[0032] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "in the order of" mean within 10%, preferably within 5%.

[0033] The following Figures 1 to 18 The sequential steps of an embodiment of a method for producing a varactor 100, a variable capacitance diode 100 or a varistor 100 are illustrated. According to this embodiment, the varactor 100 is co-integrated with a heterojunction bipolar transistor (HBT) 300, here a transistor 300 of the BiCMOS (bipolar CMOS) type. In other words, the described embodiment enables the bipolar transistor 300 and the varactor 100 to be produced on the same (common or shared) substrate and jointly.

[0034] For simplicity, the following Figures 1 to 18 The disclosure uses an example of a method in which a single variable capacitance diode 100 and a single bipolar transistor 300 are jointly made. However, it is to be understood that the method can be extended to jointly produce any number of bipolar transistors 300 and any number of variable capacitance diodes 100 on the same substrate, which numbers can be different.

[0035] Figure 1The steps of an exemplary embodiment of a method for producing a varactor are schematically shown in cross section.

[0036] According to this embodiment, a substrate 500, for example composed of a single crystal silicon wafer, is provided. Figure 1 In the embodiment, the substrate 500 has a first extrinsic collector region 520 and a second extrinsic collector region 522. For example, these extrinsic collector regions 520 and 522 are formed by performing a very high dose ion implantation operation (approximately 10 15 at / cm 2 ), and then an epitaxial growth operation is performed on a thickness of about 0.4μm.

[0037] exist Figure 1 In the embodiment, the substrate 500 also has first isolation substrates 510, 512 and 514, such as deep trench isolation (DTI). These deep isolation trenches 510, 512 and 514 extend vertically from the upper surface 502 of the substrate 500. Figure 1 The trenches 510, 512 and 514 in FIG. 5 define two locations laterally in the substrate 500 from left to right:

[0038] - A first location (HA-varicap), included between trench 510 and trench 512 (at Figure 1 ), where the variable capacitance diode 100 needs to be produced, hereinafter referred to as the "diode position"; and

[0039] - A second location (HBT), included between trench 512 and trench 514 (at Figure 1 ), at which position it is desired to produce a bipolar transistor 300, hereinafter referred to as the "transistor position".

[0040] exist Figure 1 , deep isolation trenches 510, 512, and 514 of substrate 500 separate two extrinsic collector regions 520 and 522. Regions 520 and 522 extend vertically from the upper surface 502 of substrate 500 to a depth less than the depth of deep isolation trenches 510, 512, and 514. More specifically:

[0041] - a first extrinsic collector region 520 at the diode location, interposed between the deep isolation trenches 510 and 512; and

[0042] A second extrinsic collector region 522 , located at the transistor site, is inserted between the deep isolation trenches 512 and 514 .

[0043] Therefore, if Figure 1, the first extrinsic collector region 520 and the second extrinsic collector region 522 are separated from each other by a common isolation trench, in the present case a deep isolation trench 512. For example, these regions 520 and 522 are obtained by ion implantation of ions of a dopant element of a first conductivity type, for example n-type (e.g. phosphorus or arsenic) below the upper surface 502 of the substrate 500. The first extrinsic collector region 520 and the second extrinsic collector region 522 then have an increasingly stronger concentration of the dopant element as they move away from the upper surface 502 of the substrate 500.

[0044] According to a preferred embodiment, a region 5200 (at Figure 1 The ion implantation of the dopant element of the first conductivity type (here n-type) is performed by implanting arsenic ions (AS) with an energy of 130 keV. + ions) to obtain a 6x10 13 at / cm 2 Surface doping of magnitude.

[0045] Likewise, a region 5220 (at Figure 1 The ion implantation that enables the formation of regions 5200 and 5220 is preferably performed simultaneously.

[0046] The substrate 500 further comprises second isolation structures 530 , 532 and 534 (STI—shallow trench isolation). These shallow isolation trenches 530 , 532 and 534 extend vertically from the upper surface 502 of the substrate 500 to a depth that is less than the depth of the regions 520 and 522 .

[0047] In the diode position, trenches 530 and 532 abut or are adjacent to region 5200 of region 520. Thus, trenches 530 and 532 are located on both sides of region 5200 (at Figure 1 , grooves 530 and 532 are adjacent to the left and right sides of region 5200, respectively).

[0048] In the transistor position, trench 534 is adjacent to region 5220 of region 522 (at Figure 1 , trench 534 is next to the left side of region 5220). Shallow isolation trenches 530, 532, and 534 have a depth of approximately 300 nm, preferably equal to 300 nm.

[0049] The substrate 500 also has a first sinker region 540, a second sinker region 542, and a third sinker region 544 (N sinker region) extending vertically from the upper surface 502 of the substrate 500 to a depth greater than the depth of the regions 5200, 5220 and less than the depth of the regions 520 and 522. These sinker regions 540, 542, and 544 have a first conductivity type, here, n-type.

[0050] In the diode position, the first sinker region 540 is inserted between the deep isolation trench 510 and the shallow isolation trench 530 (at Figure 1 , trenches 510 and 530 are beside the left and right sides of the sinker region 540, respectively). The second sinker region 542 is inserted between the shallow isolation trench 532 and the deep isolation trench 512 (at Figure 1 , trench 532 and trench 512 are next to the left and right sides of sinker region 542 , respectively). Thus, first sinker region 540 and second sinker region 542 make it possible to contact first extrinsic collector region 520 from upper surface 502 of substrate 500 .

[0051] In the transistor position, the third sinker region 544 is inserted between the deep isolation trench 512 and the shallow isolation trench 534 (at Figure 1 , trench 512 and trench 534 are next to the left and right sides of sinker region 544 , respectively). Thus, third sinker region 544 makes it possible to contact second extrinsic collector region 522 from upper surface 502 of substrate 500 .

[0052] In the rest of the description, Figures 2 to 18 The described embodiment of the method only includes performing operations above the upper surface 502 of the substrate 500. Therefore, throughout the method, Figures 2 to 18 The substrate 500 is preferably connected with Figure 1 The disclosed substrate 500 is the same. For the sake of simplicity, the substrate 500 will not be described in detail in the following figures.

[0053] Figure 2 A further step of an embodiment of a method for producing a varactor diode is schematically shown in cross section, the varactor diode being composed of Figure 1 The disclosed structure is made.

[0054] During this step, a first stack 700 of four consecutive layers superimposed on one another is deposited over the entire upper surface 502 of the substrate 500. This first stack 700 has more particularly:

[0055] a first layer 710 made of oxide (eg silicon oxide), completely covering the upper surface 502 of the substrate 500;

[0056] a second layer 712 made of polysilicon having a second conductivity type (here, p-type), completely covering the upper surface of the first layer 710;

[0057] a third layer 714 made of an oxide (for example, the same oxide as that constituting the first layer 710 ), completely covering the upper surface of the second layer 712 ; and

[0058] A fourth layer 716 made of nitride (eg silicon nitride) completely covers the upper surface of the third layer 714 .

[0059] According to this embodiment, the layers 710, 712, 714 and 716 making up the stack 700 have different thicknesses. For example:

[0060] - the first layer 710 has a thickness comprised between 30 nm and 70 nm, preferably of the order of 50 nm, more preferably equal to 50 nm;

[0061] - the second layer 712 has a thickness comprised between 20 nm and 60 nm, preferably approximately 40 nm, more preferably equal to 40 nm;

[0062] the third layer 714 has a thickness comprised between 2 nm and 8 nm, preferably approximately 5 nm, more preferably equal to 5 nm; and

[0063] The fourth layer 716 has a thickness comprised between 20 nm and 60 nm, preferably of the order of 40 nm, more preferably equal to 40 nm.

[0064] exist Figure 2 Layers 710 , 712 , 714 , and 716 of stack 700 are not shown to scale.

[0065] Figure 3 A further step of an embodiment of a method for producing a varactor diode is schematically shown in cross section, the varactor diode being composed of Figure 2 The disclosed structure is made.

[0066] During this step, the stack 700 is locally etched to be vertically aligned with the regions 5200 and 5220 and to be etched to a depth flush with the upper surface of the first layer 710. This is equivalent to forming through the fourth layer 716, the third layer 714 and the second layer 712: a first vertical opening 720 located in the diode position; and a second vertical opening 722 located in the transistor position.

[0067] According to a preferred embodiment, the width of the first opening 720 is smaller than the width of the region 5200, and the width of the second opening 722 is smaller than the width of the region 5222. The first opening 720 and the second opening 722 are substantially centered relative to the regions 5200 and 5220, respectively.

[0068] exist Figure 3 In the example of FIG. 7 , the second layer 712 is divided into a first region 7120, a second region 7122, and a third region 7124. More specifically, the regions 7120 and 7122 are located on both sides of the opening 720 (in Figure 3 , region 7120 is located on the left side of opening 720 and region 7122 is located on the right side of opening 720); and regions 7122 and 7124 are located on both sides of opening 722 (in Figure 3 , region 7122 is located on the left side of opening 722 and region 7124 is located on the right side of opening 722).

[0069] Still in Figure 3 In the example of FIG. 7 , the third layer 714 is divided into a first region 7140, a second region 7142, and a third region 7144. More specifically, regions 7140 and 7142 are located on both sides of the opening 720 (in Figure 3 , region 7140 is located on the left side of opening 720 and region 7142 is located on the right side of opening 720); and regions 7142 and 7144 are located on both sides of opening 722 (in Figure 3 , region 7142 is located on the left side of opening 722 and region 7144 is located on the right side of opening 722).

[0070] Still in Figure 3 In the example of FIG. 7 , the fourth layer 716 is divided into a first region 7160, a second region 7162, and a third region 7164. More specifically, regions 7160 and 7162 are located on both sides of the opening 720 (in Figure 3 , region 7160 is located on the left side of opening 720 and region 7162 is located on the right side of opening 720); and regions 7162 and 7164 are located on both sides of opening 722 (in Figure 3 , region 7162 is located on the left side of opening 722 and region 7164 is located on the right side of opening 722).

[0071] Thus, the second regions 7122, 7142, and 7162 of the layers 712, 714, and 716 are respectively inserted between the two openings 720 and 722. Figure 3 Throughout the steps described, the first layer 710 remains intact.

[0072] Figure 4 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Figure 3 The disclosed structure is made.

[0073] During this step, first spacers 730, 732, 734 and 736 are created inside the previously made openings 720 and 722 in the stack 700. The spacers 730 and 732 completely abut the side walls of the opening 720. Likewise, the spacers 734 and 736 completely abut the side walls of the opening 722. More specifically, in Figure 4 In the figure: the spacer 730 completely covers the sides of the first area 7120, 7140 and 7160 of the layers 712, 714 and 716 constituting the inner wall of the opening 720; the spacer 732 completely covers the sides of the second area 7122, 7142 and 7162 of the layers 712, 714 and 716 constituting the inner wall of the opening 720; the spacer 734 completely covers the sides of the second area 7122, 7142 and 7162 of the layers 712, 714 and 716 constituting the inner wall of the opening 722; and the spacer 736 completely covers the sides of the third area 7124, 7144 and 7164 of the layers 712, 714 and 716 constituting the inner wall of the opening 722.

[0074] Spacers 730 and 732 are discontinuous, that is, they only partially cover the free upper surface of the first layer 710 at the bottom of the first opening 720. Similarly, spacers 734 and 736 are discontinuous, that is, they only partially cover the free upper surface of the first layer 710 at the bottom of the second opening 722.

[0075] The first spacers 730 , 732 , 734 , and 736 are flush with upper surfaces of the first region 7160 , the second region 7162 , and the third region 7164 of the fourth layer 716 .

[0076] These first spacers 730, 732, 734 and 736 are made of nitride (e.g., the same nitride as that forming the fourth layer 716). If applicable, it can be considered that the spacer 730 is formed on the entire sidewall of the opening 720 (at Figure 4 , the first region 7160 of the fourth layer 716 extends over the left side wall of the opening 720; the spacer 732 extends over the other entire side wall of the opening 720 (in Figure 4 The second region 7162 of the fourth layer 716 extends over the right side wall of the opening 720; the spacer 734 extends over the entire side wall of the opening 722 (in Figure 4 , the second region 7162 of the fourth layer 716 extends over the left side wall of the opening 722); and the spacer 736 extends over the other entire side wall of the opening 722 (in Figure 4 , a third region 7164 of the fourth layer 716 extends above the right side wall of the opening 722.

[0077] Figure 5A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Figure 4 The disclosed structure is made.

[0078] During this step, the first layer 710 is locally etched to a depth flush with the areas 5200 and 5220 of the upper surface 502 of the substrate 500 through the openings 720 and 722. This is equivalent to forming in the first layer 710: a third vertical opening 724 extending from the opening 720 at the location of the diode; and a fourth vertical opening 726 extending from the opening 722 at the location of the transistor.

[0079] According to the present embodiment, the width of the third opening 724 is greater than the width of the first opening 720 and the width of the fourth opening 726 is greater than the width of the second opening 722. The width of the third opening 724 is preferably equal to the width of the region 5200 of the first extrinsic collector region 520. Likewise, the width of the fourth opening 726 is preferably equal to the width of the region 5220 of the second extrinsic collector region 522. The third opening 724 and the fourth opening 726 are approximately centered relative to the regions 5200 and 5220, respectively.

[0080] In other words, this is equivalent to extending the first opening 720 and the second opening 722, respectively, by the third opening 724 and the fourth opening 726 made in the first layer 710. Thus, deoxidation (i.e., removal of oxide) is performed from a portion of the upper surface 502 of the substrate 500, wherein the first region 5200 and the second region 5220 of the extrinsic collector regions 520 and 522 are flush. The oxide is preferably locally removed by a wet etching method.

[0081] exist Figure 5 In the example of FIG. 7 , the first layer 710 is divided into a first region 7100, a second region 7102, and a third region 7104. More specifically, the regions 7100 and 7102 are located on both sides of the opening 724 (at Figure 5 , region 7100 is located on the left side of opening 724 and region 7102 is located on the right side of opening 724); and regions 7102 and 7104 are located on both sides of opening 726 (in Figure 5 , region 7102 is located on the left side of opening 726 and region 7104 is located on the right side of opening 726).

[0082] Therefore, the second region 7102 of the first layer 710 is inserted between the two openings 724 and 726 .

[0083] Figure 6 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Figure 5 The disclosed structure is made.

[0084] During this step, the third opening 724 is completely filled (filled): by the first deposit 750, forming a region 750 covering the entire upper surface of the region 5200 belonging to the first extrinsic collector region 520; and by the second deposit 752, forming a region 752 covering the entire upper surface of the first deposit 750.

[0085] Likewise, during this step, the fourth opening 726 is completely filled: by the third deposit 754 , covering the entire upper surface of the region 5220 belonging to the second extrinsic collector region 522 ; and by the fourth deposit 756 , covering the entire upper surface of the third deposit 754 .

[0086] In this example: the first deposit 750 and the second deposit 752 are inserted between the first region 7100 and the second region 7102 of the first layer 710 ; and the third deposit 754 and the fourth deposit 756 are inserted between the second region 7102 and the third region 7102 of the first layer 710 .

[0087] exist Figure 6 , the first deposit 750 and the second deposit 752 together have a total thickness substantially equal to the thickness of the regions 7100, 7102, and 7104 of the first layer 710, preferably equal to the thickness of the regions 7100, 7102, and 7104 of the first layer 710. Similarly, in Figure 6 , the third deposit 754 and the fourth deposit 756 together have a total thickness substantially equal to the thickness of regions 7100 , 7102 , and 7104 of the first layer 710 , preferably equal to the thickness of regions 7100 , 7102 , and 7104 of the first layer 710 .

[0088] In other words, the first deposit 750 and the third deposit 754 each have a thickness less than the regions 7100, 7102, and 7104 of the first layer 710. Figure 6 The second deposit 752 and the fourth deposit 756 illustrated in FIG. 7 also each have a thickness that is less than the regions 7100 , 7102 , and 7104 of the first layer 710 .

[0089] The first deposit 750 is approximately two times thinner than the second deposit 752, preferably two times thinner than the second deposit 752. Likewise, the third deposit 754 is approximately two times thinner than the fourth deposit 756, preferably two times thinner than the fourth deposit 756.

[0090] The first deposit 750, the second deposit 752, the third deposit 754 and the fourth deposit 756 are Figure 6 and the following Figures 7 to 18Not shown to scale.

[0091] In this example, the thickness of deposits 750 and 754 is approximately 16.7 nm, preferably equal to 16.7 nm. In this example, the thickness of deposits 752 and 756 is approximately 33.3 nm, preferably equal to 33.3 nm.

[0092] The first deposit 750 and the third deposit 754 are made of a doped material having a first conductivity type (here, n-type). These first deposit 750 and the third deposit 754 are preferably made of the same material as the regions 5200 and 5220 constituting the first extrinsic collector region 520 and the second extrinsic collector region 522 .

[0093] The second deposit 752 and the fourth deposit 756 are made of a doped material having a second conductivity type (here, p-type). These second deposits 752 and the fourth deposit 756 are preferably made of the same material as the material constituting the second layer 712, except that the second deposit 752 and the fourth deposit 756 are preferably made of a single crystal material, while the second layer 712 is made of a polycrystalline material.

[0094] Therefore, the second deposit 752 forms a first pn junction together with the first deposit 750 located at the diode position. Similarly, the fourth deposit 756 forms a second pn junction together with the third deposit 754 located at the transistor position.

[0095] Deposits 750, 752, 754 and 756 are preferably produced epitaxially (in other words, they are obtained by epitaxial growth). In particular: first deposit 750 and third deposit 754 can be produced simultaneously; second deposit 752 and fourth deposit 756 can be produced simultaneously after deposits 750 and 754 have been produced.

[0096] Thus, a very sharp interface is obtained between the first deposit 750 and the second deposit 752. This makes it possible to ensure that the first pn junction is characterized by a dopant profile that changes very sharply near this interface. This is then called a "sudden" pn junction, in other words, a pn junction that has a sudden dopant profile near the interface.

[0097] Likewise, a very sharp interface is thus obtained between the third deposit 754 and the fourth deposit 756. This makes it possible to ensure that the second pn-junction is characterized by a dopant profile that varies very sharply in the vicinity of this interface (“abrupt” pn-junction).

[0098] According to this embodiment, both the region 5220 of the second extrinsic collector region 522 and the third deposit 754 constitute the intrinsic collector of the future bipolar transistor 300. The fourth deposit 756 in turn constitutes the intrinsic base of the future bipolar transistor 300.

[0099] Figure 7 Another variant of an embodiment of a method for producing a varactor and a bipolar transistor is schematically shown in cross section, the varactor and the bipolar transistor being composed of Figure 5 The disclosed structure is made.

[0100] This variation is related to Figure 6 The main difference of the disclosed steps is that the third opening 724 and the fourth opening 726 here are completely filled (or filled up) by the fifth deposit 752' and the sixth deposit 756', respectively. These deposits 752' and 756' preferably have the same properties as the second deposit 752 and the fourth deposit 756 described previously. Therefore, the fifth deposit 752' forms a region 752' having the same properties as the region 752. In other words, this is equivalent to a situation in which the first deposit 750 and the third deposit 754 are not produced and the third opening 724 and the fourth opening 726 are completely filled by the second deposit 752 and the fourth deposit 756, respectively.

[0101] Thus, according to this variant, the deposits 752' and 756' cover the entire upper surface of the regions 5200 and 5220 belonging to the first extrinsic collector region 520 and the second extrinsic collector region 522, respectively. Figure 7 Middle: the fifth deposit 752 ′ is inserted between the first region 7100 and the second regions 7100 and 7102 of the first layer 710 ; and the sixth deposit 756 ′ is inserted between the second region 7102 and the third region 7104 of the first layer 710 .

[0102] exist Figure 7 , the fifth deposit 752' has a substantially equivalent Figure 6 The thickness of the first deposit 750 and the second deposit 752 is the total thickness. Figure 7 , the sixth deposit 756' has a substantially equivalent Figure 6 The thickness of the third deposit 754 and the fourth deposit 756 is the total thickness of the third deposit 754 and the fourth deposit 756. Figure 7 The fifth deposit 752' and the sixth deposit 756' shown in FIG. Figure 6 The thicknesses of the second deposit 752 and the fourth deposit 756 are shown in .

[0103] Here, the deposits 752' and 756' have a thickness substantially equal to the thickness of the regions 7100, 7102 and 7104 of the first layer 710. In this example, the thickness of the deposits 752' and 756' is approximately 50 nm, preferably equal to 50 nm.

[0104] The fifth deposit 752' and the sixth deposit 756' are composed of a doping material having a second conductivity type (here, p-type). These fifth deposit 752' and the sixth deposit 756' are preferably composed of a doping material having a second conductivity type (here, p-type). Figure 6 The second deposit 752 and the fourth deposit 756 are disclosed to be composed of the same material.

[0105] Therefore, the fifth deposit 752' forms a first pn junction with the first extrinsic collector region 520 located at the diode position. Likewise, the sixth deposit 756' forms a second pn junction with the second extrinsic collector region 522 located at the transistor position.

[0106] More specifically, according to a preferred embodiment, in which the first extrinsic collector region 520 and the second extrinsic collector region 522 have regions 5200 and 5220, respectively: the fifth deposition 752' forms a first pn junction together with the region 5200 of the first extrinsic collector region 520; and the sixth deposition 756' forms a second pn junction together with the region 5220 of the second extrinsic collector region 522.

[0107] According to this variant, the sixth deposit 756 ′ thus in turn constitutes the intrinsic base of the future bipolar transistor 300 . The region 5220 of the second extrinsic collector region 522 constitutes the intrinsic collector of the future bipolar transistor 300 .

[0108] The fifth deposit 752 ′ and the sixth deposit 756 ′ are preferably produced by epitaxy (in other words, they are obtained by epitaxial growth).

[0109] Relative to about Figure 6 The embodiment shown in the figure has the advantage that this variant does not have the operations of producing the first deposit 750 and the third deposit 754. The total number of steps of the method is thus reduced, thereby reducing the time allocated for its implementation.

[0110] Still in this variant, a marked interface is obtained between the fifth deposit 752' and the region 5200, that is to say between the fifth deposit 752' and the first extrinsic collector region 520. This makes it possible to ensure that the first pn is characterized by a dopant profile that varies very significantly near this interface (abrupt pn junction).

[0111] A marked interface is also obtained between the sixth deposit 756' and the region 5200, that is to say between the sixth deposit 756' and the first extrinsic collector region 520. This makes it possible to ensure that the second pn junction is characterized by a dopant profile that varies very significantly near this interface (abrupt pn junction).

[0112] It is assumed in the following that no selection is made in the embodiment of the method described. Figure 7 However, for the case where the first deposit 750 and the third deposit 754 do not exist, that is, when the third opening 724 and the fourth opening 726 are respectively formed by Figure 7 When the disclosed deposits 752' and 756' are filled (or filled only with deposits 752 and 756, respectively), adjustments to the steps are within the capabilities of those skilled in the art based on the information provided below.

[0113] Figure 8 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Figure 6 (or alternatively, Figure 7 ) is made of the disclosed structure.

[0114] During this step, the upper surface 502 of the substrate 500 (at Figure 8 Depositing on the structure on one side of the substrate 70 at the top of the substrate 70: a fifth layer 760 composed of an oxide (for example, the same oxide as that constituting the first layer 710); and a sixth layer 762 composed of polycrystalline silicon (poly-Si) or preferably amorphous silicon (a-Si);

[0115] More specifically, the fifth layer 760 covers: the first region 7160, the second region 7162 and the third region 7164 of the fourth layer 716; the upper surface and free side surfaces of the first spacers 730, 732, 734 and 736; the free upper surface of the second deposit 752; and the free upper surface of the fourth deposit 756.

[0116] The sixth layer 762 completely covers the fifth layer 760. This sixth layer 762 is a sacrificial layer making it possible to protect certain parts of the structure during the method for the co-production of the variable capacitance diode 100 and the bipolar transistor 300.

[0117] The fifth layer 760 and the sixth layer 762 do not completely fill the first opening 720 and the second opening 722. In other words, these layers 760 and 762 have a total thickness that is strictly less than: half of the distance separating the first spacers 730 and 732 located at the diode position; and half of the distance separating the first spacers 734 and 736 located at the transistor position.

[0118] In other words, the first opening 720 is partially filled by the second spacers 730 and 732 and by the fifth layer 760 and the sixth layer 762, thereby forming a fifth opening 720′ corresponding to the reduced opening 720. Likewise, the second opening 722 is partially filled by the second spacers 734 and 736 and by the fifth layer 760 and the sixth layer 762, thereby forming a sixth opening 722′ corresponding to the reduced opening 722.

[0119] According to this embodiment, the layers 760 and 762 have different thicknesses. In this example: the thickness of the fifth layer 760 is between 2 nm and 6 nm, preferably about 4 nm, more preferably equal to 4 nm; and the thickness of the sixth layer 762 is between 30 nm and 70 nm, preferably about 50 nm, more preferably equal to 50 nm.

[0120] exist Figure 8 Layers 760 and 762 are not shown to scale.

[0121] Fig. 9 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Figure 8 The disclosed structure is made.

[0122] During this step, the future variable capacitance diode 100 is protected for the following steps. This protection is produced, for example, by a first operation consisting in depositing a seventh layer 770 made of photoresist over the entire upper surface of the sixth layer 762 (only a portion 7700 of the seventh layer 770 remains at the end of this step and only this portion is visible), the seventh layer 770 having a sufficient thickness to fill the fifth opening 720 ′; a second operation consisting in exposing this seventh photoresist layer 770 by means of a mask; and a third operation consisting in removing the exposed portion of the seventh layer 770 by etching, thereby leaving only a region 7700 of this layer 770 (not exposed) in the diode position.

[0123] Region 7700 of seventh layer 770 covers a region of sixth layer 762 that is flush with region 5200 of first extrinsic collector region 520. Fig. 9 , the region 7700 is T-shaped. The vertical bar of the T completely fills (or fills) the fifth opening 720', while the horizontal bar of the T extends (or extends) over the portion of the upper surface of the sixth layer 762 adjacent to the fifth opening 720'.

[0124] Fig.10 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig. 9The disclosed structure is made.

[0125] In this step, an etching operation is performed, for example, by a dry etching method (e.g., plasma etching) to remove most of the unprotected areas of the sixth layer 762. Preferably, anisotropic etching is performed so that the etching preferably (or selectively, or mainly) causes the horizontal areas of the sixth layer 762 to disappear relative to the vertical areas of the sixth layer 762.

[0126] In the diode position, region 7700 of seventh layer 770 covers vertical regions of sixth layer 762 (these regions are located within fifth opening 720' which is completely filled by region 7700). Still in the diode position, horizontal regions of sixth layer 762 not covered by region 7700 are thus removed.

[0127] In the transistor position, the vertical areas of the sixth layer 762 are not covered (these areas are located inside the sixth opening 722', which is completely free). Still in the transistor position, the horizontal areas of the sixth layer 762 are thus mainly removed. The vertical areas of the sixth layer 762 are also removed. The removal of the sixth layer 762 by etching is controlled so that only two areas of the sixth layer 762, the second area 7622 and the third area 7624, are retained inside the sixth opening 722'.

[0128] Next, the region 7700 is removed from the seventh layer 770. The region 7700 is Fig.10 Not shown in FIG. 7 , since region 7700 is removed at the end of the above-described etching step.

[0129] As in Fig.10 , only the first region 7620 of the sixth layer 762, which is located flush with the region 7700 of the seventh layer 770, is retained in the diode position. Only the second region 7622 and the third region 7624 of the sixth layer 762 are retained in the transistor position. These second regions 7622 and third regions 7624 of the sixth layer 762 respectively constitute the two first parts 7622 and 7624 of the second spacers 780 and 782 to be formed (in Fig.10 ), so as to produce a bipolar transistor 300.

[0130] exist Fig.10 In the example of FIG. 1 , the first portions 7622 and 7624 of the second spacers 780 and 782 approximately have a “quarter circle” shape. These portions 7622 and 7624 are located on both sides of the interior of the sixth opening 722′ (at Fig.10 In the future, the spacer (780, Fig.11 ) portion 7622 is located on the left side of the inner side of the opening 722', and the future spacer (782, Fig.11) is located on the right side of the inner side of the opening 722'). The portions 7622 and 7624 are discontinuous, that is, they only partially cover the free upper surface of the fifth layer 760 at the bottom of the sixth opening 722'.

[0131] Still in Fig.10 In the example of FIG. 1 , the first portions 7622 and 7624 of the spacers 780 and 782 are such that: the first portion 7622 of the spacer 780 partially covers the inner vertical wall of the sixth opening 722′ (at Fig.10 and the first portion 7624 of the spacer 782 partially covers the other inner vertical wall of the sixth opening 722' (in Fig.10 , portion 7624 partially covers the right wall of opening 722').

[0132] Fig.11 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.10 The disclosed structure is made.

[0133] During this step, areas of the fifth layer 760 that are not covered by the remaining areas of the sixth layer 762 are removed. Portions of the upper surface of the first area 7160, the second area 7162 and the third area 7164 of the fourth layer 716 are thus deoxidized (i.e., the oxide is removed). The oxide is preferably locally removed by a wet etching method.

[0134] Thus, the following remain: the first area 7600 of the fifth layer 760 covered by the first area 7620 of the sixth layer 762; the second area 7602 of the fifth layer 760 covered by the second area 7622 of the sixth layer 762; and the third area 7604 of the fifth layer 760 covered by the third area 7624 of the sixth layer 762.

[0135] The second region 7602 and the third region 7604 of the fifth layer 760 are L-shaped. These second regions 7602 and the third regions 7604 of the fifth layer 760 constitute two second portions 7602 and 7604 of the second spacers 780 and 782, respectively, so as to produce the bipolar transistor 300. Fig.11 In the example: the spacer 780 is composed of the first part 7622 (the second region 7622 of the sixth layer 762) and the second part 7602 (the second region 7602 of the fifth layer 760); and the spacer 782 is composed of the first part 7624 (the third region 7624 of the sixth layer 762) and the second part 7604 (the third region 7604 of the fifth layer 760).

[0136] Fig.12A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.11 The disclosed structure is made.

[0137] During this step, on one side of the upper surface 502 of the substrate 500 (at Fig.12 The eighth layer 764 is deposited on the structure on the top of the substrate 750 (in FIG. 1 ), and the eighth layer 764 is made of a doped material having a first conductivity type (here, n-type). The eighth layer 764 is preferably made of the same material as the first deposition 750 and the third deposition 754.

[0138] More specifically, the eighth layer 764 covers: the free upper surfaces of the first region 7160, the second region 7162 and the third region 7164 of the fourth layer 716; the upper surfaces of the first spacers 734 and 736; the free surface of the first region 7600 of the fifth layer 760; the free surface of the first region 7620 of the sixth layer 762; and the free surfaces of the second spacers 780 and 782, in other words, the free surfaces of the second region 7602 and the third region 7604 of the fifth layer 760 and the free surfaces of the second region 7622 and the third region 7624 of the sixth layer 762.

[0139] The eighth layer 764 preferably has sufficient thickness to completely fill (or fill up) the fifth opening 720' and the sixth opening 722'. For example, the eighth layer 764 has a thickness between 60nm and 140nm, preferably about 100nm, and more preferably equal to 100nm.

[0140] Fig.13 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.12 The disclosed structure is made.

[0141] During this step, the future bipolar transistor 300 is protected for the following steps. This protection is produced, for example, by: a first operation, comprising: Fig.13 The invention further comprises the steps of: depositing a ninth layer 772 composed of a photoresist (not shown) (only a portion 7720 of the ninth layer 772 remains at the end of this step and only this portion is visible); a second operation, comprising exposing the ninth photoresist layer 772 through a mask; and a third operation, comprising removing the exposed portion of the ninth layer 772 by etching and etching layer 764, thereby keeping only an area 7720 (unexposed) of the ninth layer 772 and an area 7640 (protected by area 7720) of the eighth layer 764 in the transistor position.

[0142] For example, to obtain the region 7640, the etching of the eighth layer 764 is performed by dry etching (e.g., plasma etching). For example, the region 7640 is centered relative to the sixth opening 722'. In this example, the region 7640 has a width greater than the width of the region 5220 of the second extrinsic collector region 522.

[0143] According to this embodiment, the etching operation of layers 772 and 764 is extended until the first region 7620 ( Fig.12 The second region 7622 and the third region 7624 of the sixth layer 762 are in turn protected by the region 7720 of the ninth layer 772 and by the region 7640 of the eighth layer 764, and these regions 7622 and 7624 remain intact at the end of etching.

[0144] Region 7640 of the eighth layer 764 is connected to the fourth deposit 756, that is, to the intrinsic base of the bipolar transistor 300. Region 7640 is doped with a conductivity type other than the intrinsic base 756 (here, region 7640 is n-type and base 756 is p-type). Region 7640 of the eighth layer 764 then constitutes the emitter of the bipolar transistor 300.

[0145] Fig.14 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.13 The disclosed structure is made.

[0146] During this step, the region 7720 of the ninth layer 772 is removed, and then the first region 7160, the second region 7162, and the third region 7164 of the fourth layer 716 that are not covered are etched. Thus, the etching operation removes portions of the regions 7160, 7162, and 7164 that are not protected by the first region 7600 of the fifth layer 760 or by the region 7640 of the eighth layer 764.

[0147] Therefore, in this example, only: a portion 71600 of the first area 7160 of the fourth layer 716 located flush with the first area 7600 of the fifth layer 760; a first portion 71620 of the second area 7162 of the fourth layer 716 located flush with the first area 7600 of the fifth layer 760; a second portion 71622 of the second area 7162 of the fourth layer 716 located flush with the area 7640 of the eighth layer 764; and a portion 71640 of the third area 7164 of the fourth layer 716 located flush with the area 7640 of the eighth layer 764 are retained.

[0148] Fig.15A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.14 The disclosed structure is made.

[0149] During this step, the future variable capacitance diode 100 and the future bipolar transistor 300 are protected for the following steps. These protections are done, for example, by a first operation consisting of depositing a tenth layer 774 (only portions 7740 and 7742 of the tenth layer 774 are left at the end of this step and only this portion is visible) on the structure on one side of the upper surface 502 of the substrate 500, the tenth layer consisting of photoresist; a second operation consisting of exposing this tenth photoresist layer 774 through a mask; and a third operation consisting of removing the exposed portions of the tenth layer 774 by etching, so as to keep only the first region 7740 and the second region 7742 (not exposed) of this layer 774 in the diode position and in the transistor position, respectively.

[0150] exist Fig.15 , only these first regions 7740 and second regions 7742 of the tenth layer 774 are shown.

[0151] In this example, the first region 7740 of the tenth layer 774 covers: the first region 7600 of the fifth layer 760; the free side of a portion 71600 of the first region 7160 of the fourth layer 716; the free side of the first portion 71620 of the second region 7162 of the fourth layer 716; the free upper surface of a portion 71400 of the first region 7140 of the third layer 714; and the free upper surface of the first portion 71420 of the second region 7142 of the third layer 714.

[0152] Still in this example, the second region 7742 of the tenth layer 774 covers: the region 7640 of the eighth layer 764; the free side of the second portion 71622 of the second region 7162 of the fourth layer 716; the free side of the portion 71640 of the third region 7164 of the fourth layer 716; the free upper surface of the second portion 71422 of the second region 7142 of the third layer 714; and the free upper surface of the portion 71440 of the third region 7144 of the third layer 714.

[0153] Next, regions of the second layer 712 and the third layer 714 that are not located flush with the first region 7740 and the second region 7742 of the tenth layer 774 are etched. In other words, partial regions of the second layer 712 and the third layer 714 that are not covered by the regions 7740 and 7742 are removed.

[0154] Thus, retained in the diode position are: portion 71400 of the first region 7140 of the third layer 714; portion 71200 of the first region 7120 of the second layer 712; first portion 71420 of the second region 7142 of the third layer 714; and first portion 71220 of the second region 7122 of the second layer 712.

[0155] Thus similarly, retained in the transistor position are: the second portion 71422 of the second region 7142 of the third layer 714; the second portion 71222 of the second region 7122 of the second layer 712; the portion 71440 of the third region 7144 of the third layer 714; and the portion 71240 of the third region 7124 of the second layer 712.

[0156] Portions 7122 and 71240 are connected to the fourth deposit 756, that is, to the intrinsic base of the bipolar transistor 300. These portions 71222 and 71240 are doped with the same type as the fourth deposit 756 (here p-type) and thus constitute the extrinsic base of the bipolar transistor 300.

[0157] Fig.16 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.15 The disclosed structure is made.

[0158] During this step, the first region 7740 and the second region 7742 of the tenth layer 774 are removed (these regions 7740 and 7742 are not Fig.16 ). Next, the uncovered oxide, ie, the uncovered portions of the first region 7100, the second region 7102, and the third region 7104 of the first layer 710, is removed.

[0159] exist Fig.16 In the example, the following are thus retained in the diode position: a portion 71000 of the first region 7100 of the first layer 710, which is located flush with a portion 71200 of the first region 7120 of the second layer 712; a first portion 71020 of the second region 7102 of the first layer 710, which is located flush with a first portion 71220 of the second region 7122 of the second layer 712; an element 714000 of a portion 71400 of the first region 7140 of the third layer 714, which is located flush with a portion 71600 of the first region 7160 of the fourth layer 716; and an element 714200 of a first portion 71420 of the second region 7142 of the third layer 714, which is located flush with a first portion 71620 of the second region 7162 of the fourth layer 716.

[0160] Similarly, still according to this example, what remains in the transistor position are: the second portion 71022 of the second region 7102 of the first layer 710, which is located flush with the second portion 71222 of the second region 7122 of the second layer 712; the portion 71040 of the third region 7104 of the first layer 710, which is located flush with the portion 71240 of the third region 7124 of the second layer 712; the element 714220 of the second portion 71422 of the second region 7142 of the third layer 714, which is located flush with the second portion 71622 of the second region 7162 of the fourth layer 716; and the element 714400 of the portion 71440 of the third region 7144 of the third layer 714, which is located flush with the portion 71640 of the third region 7164 of the fourth layer 716.

[0161] Fig.17 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.16 The disclosed structure is made.

[0162] During this step, a deposition is performed in a position forming a right angle above the upper surface 502 of the substrate 500. This deposition is made of a nitride, for example the same nitride that constitutes the fourth layer 716. A third spacer is thus formed, called a "MOS spacer".

[0163] exist Fig.17In the example of FIG. 5 , more specifically in the diode position, a spacer 7400 is formed that partially fills a right angle formed by the upper surface 502 of the substrate 500 and the free side surfaces of the portions 71000 and 7120 of the first regions 7100 and 7120 of the first and second layers 710 and 712, respectively; a spacer 7402 that partially fills a right angle formed by the upper surface 502 of the substrate 500 and the free side surfaces of the first portions 71020 and 71220 of the second regions 7102 and 7122 of the first and second layers 710 and 712, respectively; a spacer 7420 that partially fills a right angle formed by the upper surface of the portion 71200 of the first region 7120 of the second layer 712 and the portion 71400 of the first region 7140 of the third layer 714. The right angle formed by the upper surface of the first portion 71220 of the second region 7122 of the second layer 712 and the first portion 71420 of the second region 7142 of the third layer 714 and the free side surface of the first portion 71620 of the second region 716 of the fourth layer 716 is partially filled; the spacer 7440 partially fills the right angle formed by the upper surface of the second deposit 752 and the free side surface of the spacer 730; and the spacer 7442 partially fills the right angle formed by the upper surface of the second deposit 752 and the free side surface of the spacer 732.

[0164] Still in Fig.17 In the example of FIG. 5 , more specifically in the transistor position, a spacer 7460 is formed partially filling a right angle formed by the upper surface 502 of the substrate 500 and by free side surfaces of second portions 71022 and 71222 of the second regions 7102 and 7122 of the first layer 710 and the second layer 712, respectively; a spacer 7462 is formed partially filling a right angle formed by the upper surface 502 of the substrate 500 and by free side surfaces of portions 71040 and 71240 of the third regions 7104 and 7124 of the first layer 710 and the second layer 712, respectively; a spacer 7480 is formed partially filling a right angle formed by the second layer 712 a right angle formed by the upper surface of the second portion 71222 of the second region 7122 of the second layer 712, the element 714220 of the second portion 71422 of the second region 7142 of the third layer 714, and the free side surface of the second portion 71622 of the second region 7162 of the fourth layer 716; and a spacer 7482, partially filling the right angle formed by the upper surface of the portion 71240 of the third region 7124 of the second layer 712, the element 714400 of the portion 71440 of the third region 7144 of the third layer 714, and the free side surface of the portion 71640 of the third region 7164 of the fourth layer 716.

[0165] MOS spacers 7400, 7402, 7420, 7422, 7440, 7442, 7460, 7462, 7480, and 7482 are Fig.17 These MOS spacers 7400, 7402, 7420, 7422, 7440, 7442, 7460, 7462, 7480 and 7482 are approximately "quarter circle" shaped. Fig.17 Not shown to scale.

[0166] exist Fig.17 In the example of FIG. 1 , in the diode position: spacer 7400 partially covers the upper surface of shallow isolation trench 530, completely covers the free side surface of portion 71000 and partially covers the free side surface of portion 71200; spacer 7402 partially covers the upper surface of shallow isolation trench 532, completely covers the free side surface of portion 71020 and partially covers the free side surface of portion 71220; spacer 7420 partially covers the upper surface of portion 71200, completely covers the free side surface of element 714000 free side surface and partially covers the free side surface of portion 71600; spacer 7422 partially covers the upper surface of portion 71220, completely covers the free side surface of element 714200 and partially covers the free side surface of portion 71620; spacer 7440 partially covers the upper surface of the second deposit 752 and partially covers the free side surface of spacer 730; and spacer 7442 partially covers the upper surface of the second deposit 752 and partially covers the free side surface of spacer 732.

[0167] Still in Fig.17 In the example, in the transistor position: spacer 7460 partially covers the upper surface of shallow isolation trench 534 and partially covers the free side surface of portion 71022; spacer 7462 partially covers the upper surface of deep isolation trench 514 and partially covers the free side surface of portion 71040; spacer 7480 partially covers the upper surface of portion 71222, completely covers the free side surface of element 714220 and partially covers the free side surface of portion 71622; and spacer 7482 partially covers the upper surface of portion 71240, completely covers the free side surface of element 714400 and partially covers the free side surface of portion 71640.

[0168] Fig.18 A further step of an embodiment of a method for producing a varactor and a bipolar transistor comprising a varactor diode and a bipolar transistor is schematically shown in cross section. Fig.17 The disclosed structure is made.

[0169] During this step, the contact reactive elements of the variable capacitance diode 100 and of the bipolar transistor 300 are created. These contact reactive elements are obtained, for example, by silicide of the free horizontal surfaces of the structure that do not belong to the deep or shallow isolation trenches.

[0170] More specifically, in the diode position: contact reaction element 7900 is formed in line with first sinker region 540 ; contact reaction element 7902 is formed in line with second sinker region 542 ; and contact reaction element 7920 is formed in line with region 5200 of first extrinsic collector region 520 .

[0171] The contact reaction element 7900 is composed of a horizontal portion 7900H and a vertical portion 7900V that completely cover the upper surface of the first sink area 540. The contact reaction element 7902 is composed of a horizontal portion 7902H and a vertical portion 7902V that completely cover the upper surface of the second sink area 542. The contact reaction element 7920 is composed of a horizontal portion 7920H and a vertical portion 7920V that cover the free upper surface of the second deposit 752.

[0172] Similarly, in the transistor position: a contact reaction element 7940 is formed consistent with the third sink region 544; a contact reaction element 7960 is formed consistent with the free upper surface of the second portion 71222 of the second region 7122 of the second layer 712; a contact reaction element 7962 is formed consistent with the free upper surface of the portion 71240 of the third region 7124 of the second layer 712; and a contact reaction element 7980 is formed consistent with the region 7640 of the eighth layer 764.

[0173] The contact reaction element 7940 is composed of a horizontal portion 7940H and a vertical portion 7940V that completely cover the upper surface of the third sink area 544. The contact reaction element 7960 is composed of a horizontal portion 7960H and a vertical portion 7960V that completely cover the free upper surface of the portion 71222. The contact reaction element 7962 is composed of a horizontal portion 7962H and a vertical portion 7962V that completely cover the free upper surface of the portion 71240. The contact reaction element 7980 is composed of a horizontal portion 7980H and a vertical portion 7980V that completely cover the free upper surface of the region 7640.

[0174] The respective vertical portions 7900V, 7902V, 7920V, 7940V, 7960V, 7962V and 7980V of the contact reaction elements 7900, 7902, 7920, 7940, 7960, 7962 and 7980 are substantially perpendicular to the horizontal portions 7900H, 7902H, 7920H, 7940H, 7960H, 7962H and 7980H and are approximately centered relative to these same horizontal portions. In other words, the contact reaction elements 7900, 7902, 7920, 7940, 7960, 7962 and 7980 are in the form of an inverted T.

[0175] In the diode position, both contact-reactive elements 7900 and 7902 are connected to the first extrinsic collector region 520 through the first sinker region 540 and the second sinker region 542, respectively. The first extrinsic collector region 520 is in turn connected to the first deposit 750 through its region 5200. In the example where the first deposit 750 is n-doped, the contact-reactive elements 7900 and 7902 thus constitute the cathode contact (or terminal) of the varactor 100.

[0176] The contact reactive element 7920 is directly connected to the second deposit 752. In the example where the second deposit 752 is p-doped, the contact reactive element 7920 thus constitutes the anode contact (or terminal) of the varactor 100.

[0177] In the transistor position, the contact-reactive element 7940 is connected to the second extrinsic collector region 522 via the third sinker region 544. This second extrinsic collector region 522 is in turn connected via its region 5220 to the third deposit 754, which constitutes the intrinsic collector of the bipolar transistor 300. The contact-reactive element 7940 thus constitutes the collector contact (or terminal) of the bipolar transistor 300.

[0178] The contact-reactive elements 7960 and 7962 are connected to a second portion 71222 of the second region 7122 of the second layer 712 and a portion 71240 of the third region 7124 of the second layer 712, respectively. These portions 71222 and 71240, which constitute the extrinsic base of the bipolar transistor 300, are in turn connected to the fourth deposit 756, which constitutes the intrinsic base of the bipolar transistor 300. The contact-reactive elements 7960 and 7962 thus constitute the base contacts (or terminals) of the bipolar transistor 300.

[0179] The contact-reactive element 7980 is directly connected to the region 7640 of the eighth layer 764, which constitutes the emitter of the bipolar transistor 300. The contact-reactive element 7980 thus constitutes the emitter (or terminal) of the bipolar transistor 300.

[0180] Already about Figures 1 to 18 The sequential steps of the method of the embodiment are described, which has the advantage of enabling the variable capacitance diode 100 and the bipolar transistor 300 to be produced simultaneously (commonly). Therefore, this reduces the manufacturing steps of the diode 100 and the transistor 300 relative to the method of manufacturing the diode 100 and the transistor 300 one by one.

[0181] Another advantage of the above embodiment is that the deposits 750, 752, 754 and 756 (or in relation to Figure 7 In the case of the disclosed variant, the deposits 752' and 756') are preferably obtained by epitaxy (by epitaxial growth). This therefore allows the first deposit 750 and the second deposit 752 (or in the case of a variant, the region 5200 of the first extrinsic collector region 520 and the deposit 752') to form a pn junction with a very sharp interface, that is, near the first deposit 750 and the second deposit 752, the dopant profile varies greatly. Thus, a varactor 100 with a so-called "hyperabrupt" pn junction is obtained, called a "hyperabrupt varactor". In other words, the varactor 100 is a variable capacitance diode provided with an abrupt dopant profile near the interface of its pn junction.

[0182] Thus, one or several variable capacitance diodes 100 and one or several bipolar transistors 300 as described above may be manufactured in order to produce an electronic circuit.

[0183] Fig.19 The variation curve of the characteristics of the varactor diode obtained using the embodiment of the method is shown.

[0184] Fig.19 It reflects the change of capacitance (expressed as C) of the varactor diode according to the voltage (expressed as V) at its anode ( Fig.18 Terminal 7920) and cathode ( Fig.18 Reverse polarization is applied between terminals 7900 and 7902).

[0185] exist Fig.19 In the example of FIG. 1 : a first curve 90 in solid line illustrates the capacitance change C of the diode 100 as a function of the polarization voltage V, as for Figure 6 As disclosed, the pn junction of the diode 100 is formed by a first deposit 750 and a second deposit 752, both of which are preferably epitaxial; and a second curve 92 in dashed line illustrates the capacitance variation C of another diode (not shown) including a pn junction as a function of the polarization voltage V, (as for Figure 7A pn junction is formed by the fifth deposit 752 ′, which is preferably epitaxial, and by the region 5200 of the first extrinsic collector region 520 , in the disclosed case.

[0186] For zero polarization voltage, the inventors have observed that, as in reference Figure 7 In the case of the disclosed variant, the diode 100 including the pn junction has a capacitance (denoted as C0 100 ) is greater than the capacitance (denoted as C0) of the diode formed by the fifth deposit 752′ and the pn junction formed by the region 5200 of the first extrinsic collector region 520. 100’ ). This phenomenon appears to be explained by the presence of the first deposit 750 in the diode 100, which is inserted between the second deposit 752 and the region 5200 of the first extrinsic collector region 520. Generally, in the case of the diode 100, the presence of the first deposit 750 enables a higher capacitance to be obtained than a diode without the deposit 750.

[0187] Various embodiments and implementations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and that other variations will be readily apparent to those skilled in the art. Figures 1 to 18 The described embodiments use a common implementation (or co-integration) of a bipolar transistor of the NPN type and / or a variable capacitance diode, for example. However, the types of conductivity types (doping) used as examples in this specification may be modified (or inverted), and in particular, based on the description of the functions provided above, the adaptation of the implementation to a common embodiment of a bipolar transistor of the PNP type and a variable capacitance diode is within the capabilities of a person skilled in the art.

[0188] Finally, based on the functional description provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art. Figures 1 to 18 The fabrication of the substrate 500 of the disclosed method is within the capabilities of those skilled in the art. Based on the above description, the deposition, masking and etching operations are also within the capabilities of those skilled in the art.

Claims

1. A method for jointly producing a semiconductor device, comprising jointly producing a bipolar transistor and a variable capacitance diode on a common substrate, wherein the jointly producing comprises: forming a stack including a first layer, a second layer, a third layer, and a fourth layer over an upper surface of the substrate; forming a first opening and a second opening in the second layer, the third layer, and the fourth layer; creating a first spacer inside the first opening and the second opening; as well as A third opening and a fourth opening are formed in the first layer.

2. The method of claim 1 , wherein jointly generating comprises: simultaneously forming a base of the bipolar transistor and a diode node of the variable capacitance diode; depositing a sacrificial layer over the diode node of the variable capacitance diode; as well as Then, the emitter of the bipolar transistor is formed above the base while the diode node of the variable capacitance diode is covered by the sacrificial layer.

3. The method of claim 2, wherein the variable capacitance diode comprises a pn junction, the method comprising: forming the pn junction from a first region having a first conductivity type and a second region having a second conductivity type; Wherein jointly producing further comprises forming the second region and the base of the bipolar transistor during the same step. The method according to claim 3 , wherein the second region is made at an extrinsic collector region constituting the first region. The method of claim 3 , further comprising epitaxially forming the second region. 6 . The method of claim 3 , wherein collectively generating further comprises forming a third region having the first conductivity type between the first region and the second region.

7. The method of claim 6, wherein the third region and the intrinsic collector of the bipolar transistor are made during the same step. The method of claim 6 , further comprising epitaxially forming the third region. 9 . The method of claim 3 , wherein the first conductivity type is n-type and the second conductivity type is p-type. 10 . The method of claim 3 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

11. The method of claim 2, wherein the variable capacitance diode comprises a varactor diode having a hyperabrupt pn junction.

12. The method according to claim 2, comprising the following steps: depositing a fifth layer and a sixth layer over the stack, wherein the sixth layer provides the sacrificial layer; protecting the first area of ​​the sixth layer by the area of ​​the seventh layer; removing the sixth layer except for the first region of the sixth layer and except for the second region of the sixth layer and the third region of the sixth layer; removing the region of the seventh layer; removing the uncovered area of ​​the fifth layer; depositing an eighth layer on a side of the upper surface; removing the eighth layer except for a region of the eighth layer covered by a region of the ninth layer, and removing the first region of the sixth layer; as well as Portions of the uncovered area of ​​the fourth layer are removed, and the area of ​​the ninth layer is removed.

13. The method according to claim 12, further comprising: A first extrinsic collector region is created in the substrate, a first sinker region and a second sinker region are created to the first extrinsic collector region, a second extrinsic collector region is created in the substrate, and a third sinker region is created to the second extrinsic collector region.

14. The method according to claim 13, further comprising: Protecting the variable capacitance diode and the bipolar transistor respectively by using the first region of the tenth layer and the second region of the tenth layer, and removing unprotected portions of the first region, the second region and the third region of the third layer and the second layer; removing a portion of the uncovered area of ​​the first layer, and removing the first area of ​​the tenth layer and the second area of ​​the tenth layer; creating a second spacer that fills in the right angle on the side of the upper surface; as well as A first contact, a second contact and a third contact are respectively produced on the first sedimentation area, the second sedimentation area and the third sedimentation area, a seventh contact is produced on the first deposit, a fourth contact is produced on the first part of the area of ​​the second layer, a fifth contact is produced on the second part of the area of ​​the second layer, and a sixth contact is produced on the area of ​​the eighth layer. 15 . The method of claim 14 , further comprising filling the third opening with a second deposit and with the first deposit, and filling the fourth opening with a third deposit and a fourth deposit. 16 . The method of claim 14 , further comprising filling the third opening with the first deposit and filling the fourth opening with a fifth deposit.

17. The method of claim 1, wherein jointly generating comprises: The variable capacitance diode is covered with a portion of a sacrificial layer, and then an emitter of the bipolar transistor is formed.

18. The method of claim 17, wherein the variable capacitance diode comprises a diode node, and wherein covering comprises depositing the sacrificial layer over the diode node of the variable capacitance diode such that when the emitter of the bipolar transistor is formed, the diode node of the variable capacitance diode is covered by the sacrificial layer.

19. The method according to claim 1, comprising the steps of: The variable capacitance diode is covered with a portion of a sacrificial layer before forming an emitter of at least one bipolar transistor.

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