Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate having a dummy gate layer, the sidewall surface of the dummy gate layer having a first sidewall and a second sidewall located on the sidewall surface of the first sidewall, and the substrate also having a dielectric layer; using a first etching process to remove part of the dummy gate layer, forming a first opening in the dielectric layer, the sidewall of the first opening exposing part of the first sidewall; using a second etching process to remove the first sidewall exposed by the sidewall of the first opening, forming a second opening in the dielectric layer, the sidewall of the second opening exposing part of the second sidewall, the second etching process having a first etching rate for the first sidewall, the second etching process having a second etching rate for the dielectric layer, and the first etching rate being greater than the second etching rate; removing the dummy gate layer exposed at the bottom of the second opening, and forming a third opening located at the bottom of the second opening in the dielectric layer. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved. As the size requirements of components become smaller and smaller, the key size of the corresponding gate structure becomes smaller and smaller.

[0003] The method for forming the gate structure is as follows: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate, wherein the dielectric layer has a dummy gate layer; removing the dummy gate layer, and forming an opening in the dielectric layer; after forming the opening, sequentially forming a barrier layer, a work function layer, and a gate electrode layer on the sidewall and surface of the opening, and the gate electrode layer fills the opening, and forming a gate structure in the opening.

[0004] In order to form a gate structure with a smaller critical dimension, the size of the opening is required to be smaller and smaller. Due to the small size of the opening, the work function layer is easy to accumulate on the top of the opening, resulting in the subsequent gate electrode layer filled in the opening. Voids are easily generated, which in turn affects the performance of the formed semiconductor structure.

[0005] By increasing the size of the top portion of the formed opening, it is possible to avoid the work function layer from being accumulated on the top of the opening, thereby avoiding the formation of voids in the gate electrode layer. However, the performance of the semiconductor structure formed by the prior art is still relatively poor. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0007] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dummy gate layer is provided on the substrate, and the sidewall surface of the dummy gate layer has a first sidewall and a second sidewall located on the sidewall surface of the first sidewall, and the substrate also has a dielectric layer, wherein the dielectric layer is located on the surface of the second sidewall, and the dielectric layer exposes the top surface of the dummy gate layer; using a first etching process to remove a portion of the dummy gate layer, and forming a first opening in the dielectric layer, wherein the sidewall of the first opening exposes a portion of the first sidewall; using a second etching process to remove the first sidewall exposed by the sidewall of the first opening, and forming a second opening in the dielectric layer, wherein the sidewall of the second opening exposes a portion of the second sidewall, the second etching process has a first etching rate for the first sidewall, the second etching process has a second etching rate for the dielectric layer, and the first etching rate is greater than the second etching rate; removing the dummy gate layer exposed at the bottom of the second opening, and forming a third opening located at the bottom of the second opening in the dielectric layer.

[0008] Optionally, the second etching process is a wet etching process.

[0009] Optionally, the etching temperature range of the wet etching process is: 150 degrees Celsius to 175 degrees Celsius.

[0010] Optionally, the material of the first sidewall spacer is different from the material of the dielectric layer; the material of the first sidewall spacer includes: low-dielectric silicon nitride, silicon carbide or silicon boron nitride, and the material of the dielectric layer includes: silicon oxide, silicon oxynitride or titanium dioxide.

[0011] Optionally, the etching solution used in the wet etching process includes: dilute sulfuric acid and silicon.

[0012] Optionally, the volume concentration of silicon in the etching solution is in the range of 30 ppm to 60 ppm.

[0013] Optionally, the first etching process is a dry etching process and a wet etching process, or a combination of the two.

[0014] Optionally, the first etching process is a dry etching process; the process parameters of the dry etching include: the etching gas used includes NF3 and H2, the bias voltage is 4V to 8V, the pressure is 6mTorr to 10mTorr, and the time is 100 seconds to 200 seconds. .

[0015] Optionally, after removing the first side wall exposed by the side wall of the first opening and before removing the pseudo gate layer exposed by the bottom of the second opening, it also includes: using a third etching process to etch a portion of the second side wall exposed by the side wall of the second opening, so that the size of the top of the second opening is larger than the size of the bottom of the second opening, and the angle between the second side wall exposed by the second opening and the surface of the dielectric layer is greater than 90°.

[0016] Optionally, the third etching process is a dry etching process; the process parameters of the dry etching include: the etching gases used include CF4 and N2, and the time is 0 seconds to 20 seconds.

[0017] Optionally, along the width direction of the dummy gate layer, a size of the first opening is 19 nanometers to 22 nanometers, and a size of the second opening is 21 nanometers to 25 nanometers.

[0018] Optionally, the pseudo gate layer also has a pseudo gate dielectric layer at the bottom, and the pseudo gate dielectric layer is located on the surface of the substrate; the method for forming the third opening includes: using a fourth etching process to remove a portion of the pseudo gate layer exposed by the second opening, forming an initial third opening in the dielectric layer, and the bottom of the initial third opening exposes the top surface of the pseudo gate layer; after forming the initial third opening, using a fifth etching process to remove the pseudo gate layer exposed at the bottom of the initial third opening until the surface of the pseudo gate dielectric layer is exposed, and forming the third opening in the dielectric layer.

[0019] Optionally, the fourth etching process is a dry etching process; the parameters of the dry etching process include: the etching gases used include NF3 and H2, the bias voltage is 4V to 8V, the pressure is 6mTorr to 10mTorr, and the time is 50 seconds to 100 seconds.

[0020] Optionally, the fifth etching process is a wet etching process, and the parameters of the wet etching process include: the etching solution used includes dilute ammonia water and tetramethylammonium hydroxide, wherein the volume ratio of ammonia water to water in the dilute ammonia water is 1:2 to 1:10, the processing time is 30 seconds to 60 seconds, and the flow rate is 1 liter / minute to 3 liters / minute; the concentration of the tetramethylammonium hydroxide is 2.38%, the processing time is 4 minutes to 6 minutes, and the flow rate is 1 liter / minute to 3 liters / minute.

[0021] Optionally, it also includes: after forming the third opening, forming a gate structure in the second opening and the third opening; the method for forming the gate structure includes: forming a gate dielectric material film in the second opening, in the third opening, and on the surface of the dielectric layer; after forming the gate dielectric material film, forming a work function material film on the surface of the gate dielectric material film; after forming the work function material film, forming a gate electrode material film on the surface of the work function material film; flattening the gate electrode material film, the gate dielectric material film, and the work function material film until the surface of the dielectric layer is exposed, and forming the gate structure in the second opening and the third opening.

[0022] Optionally, the material of the second sidewall spacer is different from that of the first sidewall spacer; the material of the second sidewall spacer includes: dense silicon nitride, silicon carbide or silicon boron nitride.

[0023] Optionally, the base includes a substrate and a fin located on the surface of the substrate, the pseudo gate layer spans the fin, and the pseudo gate layer covers a portion of the top surface and side wall surface of the fin; the fins on both sides of the pseudo gate layer have source and drain doping regions.

[0024] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by using any of the above methods.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since the second etching process has a first etching rate for the first side wall, the second etching process has a second etching rate for the dielectric layer, and the first etching rate is greater than the second etching rate, the second etching process can remove the first side wall exposed by the side wall of the first opening, so that the size of the formed second opening is larger than the first opening, that is, the size of the second opening is larger, and thus it is not easy to generate voids in the subsequently formed gate structure. At the same time, the second etching process etches a small amount of the dielectric layer, that is, it can avoid reducing the height of the dielectric layer. Since the gate structure subsequently formed in the second opening and the third opening is flush with the surface of the dielectric layer, the subsequently formed gate structure still has a relatively high height. In summary, the semiconductor structure formed by the method has good performance.

[0027] Furthermore, the second etching process can measure the concentration of silicon in the etching solution in real time. By understanding the situation of the etching solution in real time and adjusting the proportion of the etching solution in time, it is beneficial to accurately control the etching process, ensure that while etching and removing the first sidewall exposed by the sidewall of the first opening, the etching damage to the dielectric layer is small, so that the performance of the formed semiconductor structure is better.

[0028] Furthermore, by adjusting the process parameters of the third etching process, the part of the second sidewall exposed by the sidewall of the second opening is etched. On the one hand, the size of the top of the second opening is larger than the size of the bottom of the second opening, which further makes it less likely to produce voids in the gate structure formed subsequently; on the other hand, the angle between the sidewall at the top of the second opening and the surface of the dielectric layer is greater than 90°, which is beneficial to avoid accumulation at the tip of the second opening when filling the material in the second opening, so that the performance of the formed semiconductor structure is better. In addition, in the process of removing the first sidewall exposed by the sidewall of the second opening by the second etching process, certain impurities are attached to the surface of the pseudo gate layer exposed at the bottom of the second opening. The third etching process can remove the impurities, which is beneficial to the subsequent etching process.

[0029] Furthermore, the third opening is formed by using a fourth etching process and a fifth etching process, and the pseudo gate layer exposed at the bottom of the second opening is etched by the fourth etching process, and only a part of the pseudo gate layer is retained. The fourth etching process adopts a dry etching process, and the fifth etching process adopts a wet etching process. Since the etching rate of the fourth etching process is relatively large, most of the pseudo gate layer can be removed in a relatively short time. Furthermore, by using the fifth etching process, and the etching selectivity of the fifth etching process is relatively large, the small part of the pseudo gate layer retained can be completely removed in a relatively short time, while avoiding etching damage to the surface of the first side wall and the second side wall, and avoiding the subsequent gate structure and the source and drain doping area from penetrating to generate leakage current. In summary, the third opening is formed by the fourth etching process and the fifth etching process, which saves process time, and the performance of the formed semiconductor structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 4 The invention is a cross-sectional schematic diagram of each process of a method for forming a semiconductor structure;

[0031] Figures 5 to 11 It is a cross-sectional schematic diagram of each process of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, semiconductor structures have poor performance.

[0033] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 4 The invention is a cross-sectional schematic diagram of each process of a method for forming a semiconductor structure.

[0034] Please refer to Figure 1 A substrate 100 is provided, wherein the substrate 100 has a dielectric layer 110, wherein the dielectric layer 110 has a dummy gate layer 120, and wherein the dielectric layer 110 exposes a top surface of the dummy gate layer 120, wherein a sidewall surface of the dummy gate layer 120 has a first sidewall 131, and a second sidewall 132 located on a sidewall surface of the first sidewall 131.

[0035] Please refer to Figure 2 A first etching process is used to remove a portion of the dummy gate layer 131 , and a first opening 140 is formed in the dielectric layer 110 . The sidewall of the first opening 140 exposes a portion of the first spacer 131 .

[0036] Please refer to Figure 3 , a second etching process is used to remove the first sidewall spacer 131 exposed by the sidewall of the first opening 140 , and a second opening 150 is formed in the dielectric layer 110 .

[0037] Please refer to Figure 4, a third etching process is used to remove the dummy gate layer 120 exposed at the bottom of the second opening 150 , and a third opening 160 located at the bottom of the second opening 150 is formed in the dielectric layer 110 .

[0038] In the above method, dry etching is usually used to perform the second etching process to remove the first side wall 131 exposed by the side wall of the first opening 140, so that the size of the formed second opening 150 is larger than the size of the first opening 140, that is, along the width direction of the pseudo gate layer 120, the size of the second opening 150 is larger, which is beneficial to avoid the formation of voids in the gate structure subsequently formed in the second opening 150 and the third opening 160.

[0039] However, the dry etching process has a low etching selectivity for the first side wall 131 and the dielectric layer 110. While etching the first side wall 131, it is easy to cause etching damage to the dielectric layer 110, resulting in a significant reduction in the height of the dielectric layer 110. As a result, the height of the gate structure subsequently formed to be flush with the surface of the dielectric layer 110 is also greatly reduced, resulting in poor performance of the formed semiconductor structure.

[0040] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: removing a portion of a dummy gate layer by a first etching process, forming a first opening in the dielectric layer, wherein the sidewall of the first opening exposes a portion of the first sidewall; removing the first sidewall exposed by the sidewall of the first opening by a second etching process, forming a second opening in the dielectric layer, wherein the sidewall of the second opening exposes a portion of the second sidewall, wherein the second etching process has a first etching rate for the first sidewall, and the second etching process has a second etching rate for the dielectric layer, and the first etching rate is greater than the second etching rate; removing the dummy gate layer exposed at the bottom of the second opening, and forming a third opening located at the bottom of the second opening in the dielectric layer. The semiconductor structure formed by the method has good performance.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 5 to 11 It is a cross-sectional schematic diagram of each process of a method for forming a semiconductor structure in one embodiment of the present invention.

[0043] Please refer to Figure 5, providing a substrate (not shown in the figure), the substrate having a dummy gate layer 212, the sidewall surface of the dummy gate layer 212 having a first sidewall 221, and a second sidewall 222 located on the sidewall surface of the first sidewall 221, the substrate also having a dielectric layer 230, the dielectric layer 230 is located on the surface of the second sidewall 222, and the dielectric layer 230 exposes the top surface of the dummy gate layer 212.

[0044] In this embodiment, the base includes a substrate 201 and a fin 202 located on the surface of the substrate 201, the pseudo gate layer 212 spans the fin 202, and the pseudo gate layer 212 covers a portion of the top surface and side wall surface of the fin 202; the fin 202 on both sides of the pseudo gate layer 212 has source and drain doping regions.

[0045] In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.

[0046] The material of the substrate 201 and the fin 202 is a semiconductor material. In this embodiment, the material of the substrate 201 and the fin 202 is silicon. In other embodiments, the material of the substrate 201 and the fin 202 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0047] A dummy gate dielectric layer 211 is further provided at the bottom of the dummy gate layer 212 , and the dummy gate dielectric layer 211 is located on the surface of the substrate.

[0048] In this embodiment, the dummy gate dielectric layer 212 is located on a portion of the top surface and sidewall surfaces of the fin 202 .

[0049] The material of the dummy gate dielectric layer 211 includes silicon oxide, and the material of the dummy gate layer 212 includes polysilicon.

[0050] The dummy gate dielectric layer 211 has the following functions: on the one hand, to isolate the fin 202 from the dummy gate layer 211 ; and on the other hand, to improve the interface state between the surface of the fin 202 and the gate structure formed subsequently.

[0051] In this embodiment, the surface of the substrate 201 , the surface of the fin 202 , and the surface of the sidewall of the second spacer 222 further have an etch stop layer (not shown in the figure).

[0052] The material of the first sidewall is different from that of the dielectric layer; the material of the first sidewall 221 includes: low dielectric silicon nitride, silicon carbide or silicon boronitrile, and the material of the dielectric layer 230 includes: silicon oxide, silicon oxynitride or titanium dioxide

[0053] In this embodiment, the material of the dielectric layer 230 is silicon oxide.

[0054] In this embodiment, the material of the first sidewall spacer 221 is low-dielectric silicon oxide, and the process of forming the first sidewall spacer 221 is chemical vapor deposition process, and in the process of forming the first sidewall spacer 221 , carbon and oxygen elements are doped.

[0055] The material of the second sidewall spacer 222 is different from that of the first sidewall spacer 221 ; the material of the second sidewall spacer 222 includes: dense silicon nitride, silicon carbide or silicon boron nitride.

[0056] In this embodiment, the material of the second sidewall spacer 222 is dense silicon nitride, and the process of forming the second sidewall spacer 222 is an atomic layer deposition process.

[0057] Please refer to Figure 6 A first etching process is used to remove a portion of the dummy gate layer 212 to form a first opening 240 in the dielectric layer 230 , wherein a sidewall of the first opening 240 exposes a portion of the first sidewall 221 .

[0058] Forming the first opening 240 through the first etching process is beneficial to subsequently etching the first sidewall spacer 221 exposed by the sidewall of the first opening 240 .

[0059] The first etching process includes: one of a dry etching process and a wet etching process, or a combination of the two.

[0060] The first etching process is a dry etching process; the process parameters of the dry etching include: the etching gases used include NF3 and H2, the bias voltage is 4V to 8V, the pressure is 6mTorr to 10mTorr, and the time is 100 seconds to 200 seconds.

[0061] During the first etching process to remove part of the dummy gate layer 212 , the etching rate of the dielectric layer 230 is relatively low, that is, the etching amount of the dielectric layer 230 is relatively small, which is beneficial to maintaining the height of the dielectric layer 230 and further beneficial to improving the performance of the formed semiconductor structure.

[0062] Please refer to Figure 7A second etching process is used to remove the first sidewall 221 exposed by the sidewall of the first opening 240, and a second opening 250 is formed in the dielectric layer 230. The sidewall of the second opening 250 exposes a portion of the second sidewall 222. The second etching process has a first etching rate for the first sidewall 221, and the second etching process has a second etching rate for the dielectric layer 230, and the first etching rate is greater than the second etching rate.

[0063] Through the second etching process, the size of the second opening 250 is made larger than the size of the first opening 240 .

[0064] Along the width direction of the dummy gate layer 212 , the size of the first opening 240 is 19 nanometers to 22 nanometers, and the size of the second opening 250 is 21 nanometers to 25 nanometers.

[0065] The second etching process is a wet etching process.

[0066] The etching temperature range of the wet etching process is: 150 degrees Celsius to 175 degrees Celsius.

[0067] In this embodiment, the etching solution used in the wet etching process includes: dilute sulfuric acid and silicon.

[0068] The volume concentration of silicon in the etching solution is in the range of 30 ppm to 60 ppm.

[0069] Since the second etching process has a first etching rate for the first sidewall 221, the second etching process has a second etching rate for the dielectric layer 230, and the first etching rate is greater than the second etching rate, the second etching process can remove the first sidewall 221 exposed by the sidewall of the first opening 240, so that the size of the formed second opening 250 is larger than the first opening 240, that is, the size of the second opening 250 is larger, and thus the gate structure formed subsequently is not prone to voids. At the same time, the second etching process etches a small amount of the dielectric layer 230, that is, it can avoid reducing the height of the dielectric layer 230. Since the gate structure subsequently formed in the second opening and the third opening is flush with the surface of the dielectric layer 230, the gate structure subsequently formed still has a relatively high height. In summary, the semiconductor structure formed by the method has better performance.

[0070] Furthermore, the second etching process can measure the concentration of silicon in the etching solution in real time. By understanding the situation of the etching solution in real time and adjusting the proportion of the etching solution in time, it is beneficial to accurately control the etching process, ensure that while etching and removing the first sidewall 221 exposed by the sidewall of the first opening 240, the etching damage to the dielectric layer 230 is small, so that the performance of the formed semiconductor structure is better.

[0071] Furthermore, by using the second etching process, the wafer can be placed in the etching groove in a direction parallel to the wafer surface, thereby etching the entire wafer, ensuring that the etching time of the semiconductor structures located in different areas of the entire wafer remains consistent, which is beneficial to improving the etching accuracy and making the formed semiconductor structure have better performance.

[0072] Please refer to Figure 8 A third etching process is used to etch the portion of the second sidewall 222 exposed by the sidewall of the second opening 250, so that the size of the top of the second opening 250 is larger than the size of the bottom of the second opening 250, and the angle between the sidewall of the top of the second opening 250 and the surface of the dielectric layer 230 is greater than 90°.

[0073] The third etching process is a dry etching process; the process parameters of the dry etching include: the etching gases used include CF4 and N2, and the time is 0 seconds to 20 seconds.

[0074] By adjusting the process parameters of the third etching process, the part of the second sidewall 222 exposed by the sidewall of the second opening 250 is etched. On the one hand, the size of the top of the second opening 250 can be made larger than the size of the bottom of the second opening 250, further making it less likely to produce voids in the gate structure formed subsequently; on the other hand, the angle between the sidewall at the top of the second opening 250 and the surface of the dielectric layer 230 can be made larger than 90°, which is beneficial to avoid accumulation at the tip of the second opening 250 when filling the material in the second opening 250, so that the performance of the formed semiconductor structure is better. In addition, in the process of removing the first sidewall 221 exposed by the sidewall of the second opening 250 by the second etching process, certain impurities are attached to the surface of the dummy gate layer 212 exposed at the bottom of the second opening 250. The third etching process can remove the impurities, which is beneficial to the subsequent etching process.

[0075] Next, the dummy gate layer exposed at the bottom of the second opening is removed, and a third opening located at the bottom of the second opening is formed in the dielectric layer. For the specific process of forming the third opening, please refer to Figures 9 and 10 .

[0076] Please refer to Fig. 9 A fourth etching process is used to remove a portion of the dummy gate layer 212 exposed by the second opening 250 , and an initial third opening 261 is formed in the dielectric layer 230 . The bottom of the initial third opening 261 exposes the top surface of the dummy gate layer 212 .

[0077] The fourth etching process is a dry etching process.

[0078] In this embodiment, the parameters of the dry etching process include: the etching gases used include NF3 and H2, the bias voltage is 4V to 8V, the pressure is 6mTorr to 10mTorr, and the time is 50 seconds to 100 seconds.

[0079] In this embodiment, the dry etching process is anisotropic dry etching. On the one hand, the etching rate of the dry etching process is fast, which can save process time; on the other hand, it is conducive to achieving accurate transfer of the pattern, so that the side wall morphology of the initial third opening is better, which is conducive to improving the performance of the formed semiconductor structure.

[0080] Most of the dummy gate layer 212 exposed at the bottom of the second opening 250 is etched through the fourth etching process, and only a portion of the dummy gate layer 212 is retained, so that the subsequent fifth etching process is controlled to be performed in a shorter time.

[0081] Please refer to Fig.10 After forming the initial third opening 261 , a fifth etching process is used to remove the dummy gate layer 212 exposed at the bottom of the initial third opening 261 until the surface of the dummy gate dielectric layer 211 is exposed, thereby forming the third opening 262 in the dielectric layer 230 .

[0082] The third opening 262 is located at the bottom of the second opening 250 .

[0083] The fifth etching process is a wet etching process, and the parameters of the wet etching process include: the etching solution used includes dilute ammonia water and tetramethylammonium hydroxide, wherein the volume ratio of ammonia water to water in the dilute ammonia water is 1:2 to 1:10, the processing time is 30 seconds to 60 seconds, and the flow rate is 1 liter / minute to 3 liters / minute; the concentration of the tetramethylammonium hydroxide is 2.38%, the processing time is 4 minutes to 6 minutes, and the flow rate is 1 liter / minute to 3 liters / minute.

[0084] The wet etching process has a relatively high etching selectivity and can be used as a buffer etching. While etching the pseudo gate layer 212, the etching damage to the surface of the first side wall 221 and the second side wall 222 is relatively small, which can avoid the subsequent gate structure and the source and drain doping regions from penetrating to generate leakage current, so that the performance of the formed semiconductor structure is better.

[0085] Since the etching rate of the fourth etching process is relatively high, most of the dummy gate layer 212 can be removed in a relatively short time. Furthermore, through the fifth etching process, and the etching selectivity of the fifth etching process is relatively large, it is possible to completely remove the remaining small portion of the dummy gate layer 212 in a relatively short time, while avoiding etching damage to the surface of the first side wall 221 and the second side wall 222, and avoiding the subsequent gate structure and the source and drain doping regions from penetrating to generate leakage current. In summary, the third opening 262 is formed by the fourth etching process and the fifth etching process, which saves process time, and the performance of the formed semiconductor structure is better.

[0086] Please refer to Fig.11 After forming the third opening 262 , a gate structure 270 is formed in the second opening 250 and the third opening 262 .

[0087] The method for forming the gate structure 270 includes: forming a gate dielectric material film (not shown in the figure) in the second opening 250, in the third opening 262, and on the surface of the dielectric layer 230; after forming the gate dielectric material film (not shown in the figure), forming a work function material film (not shown in the figure) on the surface of the gate dielectric material film; after forming the work function material film, forming a gate electrode material film on the surface of the work function material film; planarizing the gate electrode material film, the gate dielectric material film and the work function material film until the surface of the dielectric layer 230 is exposed, and forming the gate structure 270 in the second opening and the third opening.

[0088] The gate dielectric material film is planarized to form a gate dielectric layer (not shown in the figure), and the material of the gate dielectric layer is a high-K dielectric material, such as: HfO2, La2O3, HfSiON, HfAlO2, ZrO2, Al2O3 or HfSiO4.

[0089] The work function material film is subjected to a planarization process to form a work function layer, and the work function layer is used to adjust the threshold voltage of the transistor.

[0090] The gate electrode material film is planarized to form a gate electrode layer, and the material of the gate electrode layer includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.

[0091] Since the size of the second opening 250 is relatively large along the width direction of the gate structure, and the size of the top of the second opening 250 is larger than the size of the bottom of the second opening 250, at the same time, during the process of forming the second opening 250 and the third opening 262, the etching damage to the dielectric layer 230 is relatively small, that is, the dielectric layer 230 still has a relatively high height, thereby ensuring that the gate structure 270 still has a relatively high height, so that the gate control ability of the gate structure 270 is better, and thus the performance of the formed semiconductor structure is better.

[0092] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method.

[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a dummy gate layer is provided on the substrate, wherein the sidewall surface of the dummy gate layer has a first sidewall and a second sidewall located on the sidewall surface of the first sidewall, and wherein a dielectric layer is further provided on the substrate, wherein the dielectric layer is located on the surface of the second sidewall, and the dielectric layer exposes the top surface of the dummy gate layer; Using a first etching process to remove a portion of the dummy gate layer, forming a first opening in the dielectric layer, wherein a sidewall of the first opening exposes a portion of the first sidewall; A second etching process is used to remove the first sidewall spacer exposed by the sidewall of the first opening, the first sidewall spacer remaining after the second etching process is flush with the dummy gate layer exposed by the first opening, a second opening is formed in the dielectric layer, the sidewall of the second opening exposes a portion of the second sidewall spacer, the second etching process has a first etching rate for the first sidewall spacer, the second etching process has a second etching rate for the dielectric layer, and the first etching rate is greater than the second etching rate; Removing the dummy gate layer exposed at the bottom of the second opening, and forming a third opening located at the bottom of the second opening in the dielectric layer; After removing the first sidewall exposed by the sidewall of the first opening and before removing the dummy gate layer exposed by the bottom of the second opening, the method further includes: etching a portion of the second sidewall exposed by the sidewall of the second opening using a third etching process, but keeping the height of the first sidewall and the dummy gate layer unchanged, so that the size of the top of the second opening is larger than the size of the bottom of the second opening, and the angle between the sidewall of the second sidewall exposed by the second opening and the surface of the dielectric layer is larger than 90°; The method for forming the third opening includes: using a fourth etching process to remove a portion of the pseudo gate layer exposed by the second opening to form an initial third opening, wherein the bottom of the initial third opening exposes the top surface of the pseudo gate layer; after forming the initial third opening, using a fifth etching process to remove the pseudo gate layer exposed at the bottom of the initial third opening to form the third opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process is a wet etching process.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etching temperature range of the wet etching process is: 150 degrees Celsius to 175 degrees Celsius.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the first sidewall is different from the material of the dielectric layer; The material of the first sidewall spacer includes: low dielectric silicon nitride, silicon carbide nitride or silicon boron nitride, and the material of the dielectric layer includes: silicon oxide, silicon oxynitride or titanium dioxide.

5. The method for forming a semiconductor structure according to claim 4, wherein: The etching solution used in the wet etching process includes: dilute sulfuric acid and silicon.

6. The method for forming a semiconductor structure according to claim 5, wherein: The volume concentration of silicon in the etching solution is in the range of 30 ppm to 60 ppm.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process is one of a dry etching process and a wet etching process, or a combination of the two.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first etching process is a dry etching process; the process parameters of the dry etching include: the etching gases used include NF3 and H2, the bias voltage is 4V to 8V, the pressure is 6mTorr to 10mTorr, and the time is 100 seconds to 200 seconds.

9. The method for forming a semiconductor structure according to claim 1, wherein: The third etching process is a dry etching process; the process parameters of the dry etching include: the etching gases used include CF4 and N2, and the time is 0 seconds to 20 seconds.

10. The method for forming a semiconductor structure according to claim 1, wherein: Along the width direction of the dummy gate layer, a size of the first opening is 19 nanometers to 22 nanometers, and a size of the second opening is 21 nanometers to 25 nanometers.

11. The method for forming a semiconductor structure according to claim 1, wherein: The pseudo gate layer also has a pseudo gate dielectric layer at the bottom, and the pseudo gate dielectric layer is located on the substrate surface; the pseudo gate layer exposed at the bottom of the initial third opening is removed by a fifth etching process until the surface of the pseudo gate dielectric layer is exposed, thereby forming the third opening in the dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The fourth etching process is a dry etching process; the parameters of the dry etching process include: the etching gases used include NF3 and H2, the bias voltage is 4V to 8V, the pressure is 6mTorr to 10mTorr, and the time is 50 seconds to 100 seconds.

13. The method for forming a semiconductor structure according to claim 12, wherein: The fifth etching process is a wet etching process, and the parameters of the wet etching process include: the etching solution used includes dilute ammonia water and tetramethylammonium hydroxide, wherein the volume ratio of ammonia water to water in the dilute ammonia water is 1:2 to 1:10, the processing time is 30 seconds to 60 seconds, and the flow rate is 1 liter / minute to 3 liters / minute; the concentration of the tetramethylammonium hydroxide is 2.38%, the processing time is 4 minutes to 6 minutes, and the flow rate is 1 liter / minute to 3 liters / minute.

14. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the third opening, forming a gate structure in the second opening and in the third opening; The method for forming the gate structure comprises: forming a gate dielectric material film in the second opening, in the third opening, and on the surface of the dielectric layer; After forming the gate dielectric material film, a work function material film is formed on the surface of the gate dielectric material film; after forming the work function material film, a gate electrode material film is formed on the surface of the work function material film; the gate electrode material film, the gate dielectric material film and the work function material film are planarized until the surface of the dielectric layer is exposed, and the gate structure is formed in the second opening and the third opening.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second sidewall spacer is different from that of the first sidewall spacer; the material of the second sidewall spacer includes: dense silicon nitride, silicon carbide or silicon boron nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: The base includes a substrate and a fin located on the surface of the substrate. The pseudo gate layer spans across the fin and covers a portion of the top surface and sidewall surface of the fin. The fins on both sides of the pseudo gate layer have source and drain doping regions.

17. A semiconductor structure formed by the method according to any one of claims 1 to 16.

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