Wiring structure and method for manufacturing the same

Abstract

A wiring structure includes a first unit, a second unit, a first insulating wall, a first redistribution layer, and a third unit. The first unit is disposed at a first elevation and has a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and has a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulating wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and has a third circuit layer and a third dielectric layer surrounding the third circuit layer.

Description

Technical Field

[0001] This invention relates to wiring structures, and more specifically, to disassembly wiring structures and methods for manufacturing the same. Background Technology

[0002] With technological advancements, semiconductor chips have integrated an increasing number of electronic components to enhance performance. Consequently, semiconductor chips are equipped with a relatively larger number of input / output (I / O) connections.

[0003] The substrate used for packaging or assembling semiconductor chips may need to be scaled up to achieve an increased number of I / O connections for the semiconductor chip. However, as the size of the packaging substrate increases, the bending of the semiconductor chip (device) package can be relatively severe, which may adversely affect the yield of the semiconductor device package. Summary of the Invention

[0004] In some embodiments, the present invention discloses a wiring structure. The wiring structure includes a first unit, a second unit, a first insulating wall, a first redistribution layer, and a third unit. The first unit is disposed at a first elevation and has a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at a first elevation and has a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulating wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit. The first redistribution layer is electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and has a third circuit layer and a third dielectric layer surrounding the third circuit layer.

[0005] In some embodiments, the present invention discloses a method for manufacturing a wiring structure. The method includes: providing a plurality of first units; encapsulating the plurality of first units to form a layer of first units; forming a first redistribution layer on the layer of first units; providing a plurality of second units; encapsulating the plurality of second units to form a layer of second units; and stacking the layers of second units onto the first redistribution layer.

[0006] In some embodiments, the present invention discloses a multilayer substrate. The multilayer includes a first layer, a first redistribution layer, and a second layer. The first layer has a plurality of first units embedded in a first insulating material. The first redistribution layer is disposed on the first layer. The second layer has a plurality of second units embedded in a second insulating material and is disposed on the first redistribution layer.

[0007] In some embodiments, the present invention discloses a wiring structure. The wiring structure includes a first sub-unit, a second sub-unit, a first insulating wall, and a third redistribution layer. The first sub-unit is disposed at a first elevation and has a first circuit layer, a first dielectric layer surrounding the first circuit layer, and a first redistribution layer disposed on the first circuit layer. The second sub-unit is disposed at a first elevation and has a second circuit layer, a second dielectric layer surrounding the second circuit layer, and a second redistribution layer disposed on the second circuit layer. The first insulating wall is disposed between the first sub-unit and the second sub-unit. The third redistribution layer is disposed on the first sub-unit and the second sub-unit and electrically connected between the first sub-unit and the second sub-unit.

[0008] In some embodiments, the present invention discloses a method for manufacturing a wiring structure. The method includes providing a plurality of first sub-units, encapsulating the plurality of first sub-units to form a plurality of first units, and a layer encapsulating the plurality of first units to form a first unit.

[0009] In some embodiments, the present invention discloses a substrate. The substrate comprises a plurality of units embedded in a first insulating material, and at least one of the plurality of units includes a plurality of sub-units embedded in a second insulating material. Attached Figure Description

[0010] Some aspects of embodiments of the invention will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1 A perspective view of a panel illustrating a wiring structure according to some embodiments of the present invention.

[0012] Figure 2 Explanation as follows Figure 1 The layout of layer 10 of panel 1 shown.

[0013] Figure 3 The wiring structure according to some embodiments of the present invention is described.

[0014] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A method for manufacturing a wiring structure according to some embodiments of the present invention is described.

[0015] Figure 4 A cross-sectional view illustrating another wiring structure according to some embodiments of the present invention is provided.

[0016] Figure 5 A comparative embodiment of the panel illustrating the wiring structure of the present invention is provided.

[0017] Figure 6A An assembly view of a panel illustrating a wiring structure according to some embodiments of the present invention.

[0018] Figure 6B Explanation as follows Figure 6A An exploded view of the panel showing the wiring structure.

[0019] Figure 7A Cross-sectional views illustrating wiring structures according to some embodiments of the present invention are provided.

[0020] Figure 7B A cross-sectional view illustrating another wiring structure according to some embodiments of the present invention is provided.

[0021] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E A method for manufacturing a wiring structure according to some embodiments of the present invention is described.

[0022] Figure 9 A comparative embodiment of the wiring structure of the present invention is described. Detailed Implementation

[0023] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of the invention will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0024] Embodiments of the invention are described in detail below. However, it should be understood that the invention provides many applicable concepts that can be implemented in a wide variety of specific situations. The specific embodiments described are merely illustrative and do not limit the scope of the invention.

[0025] To meet the requirement of increased I / O count, the number of dielectric layers in the substrate should be increased. In some comparative embodiments, the fabrication process of the core substrate may include the following stages. First, a core with two copper foils disposed on both sides of the core is provided. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in a corresponding dielectric layer. Therefore, the core substrate may contain multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Since the linewidth / spacing (L / S) of the circuit layers in such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers in such a core substrate is relatively large. Although the manufacturing cost of such a core substrate is relatively low, the manufacturing yield of the circuit layers and dielectric layers of such a core substrate is also relatively low, and therefore, the yield of such a core substrate is relatively low.

[0026] At least some embodiments of the present invention provide wiring structures with an advantageous compromise in terms of yield and manufacturing cost. At least some embodiments of the present invention further provide techniques for manufacturing wiring structures.

[0027] Figure 1 A perspective view of a panel illustrating a wiring structure 1 according to some embodiments of the present invention.

[0028] refer to Figure 1 The panel of wiring structure 1 may include layer 10 and redistribution layer 10'. Panel 1 may include a multi-layer structure. Panel 1 may include a stacked structure of layer 10 and redistribution layer 10'. Panel 1 may include multiple wiring structures 11.

[0029] The wiring structure 11 may comprise a multi-layered structure. The wiring structure 11 can be separated from the panel 1 by using a cutting technique along the cut line (or scribing line) S. Although in Figure 1 The wiring structure 11 is arranged or positioned in a rectangular or rectangular shape; however, it is contemplated that the wiring structure 11 may be arranged in a shape other than those described above.

[0030] Figure 2 Explanation as follows Figure 1 The layout of layer 10 of panel 1 shown.

[0031] refer to Figure 2 Layer 10 may include cells 11a, 11b, 11c, and 11d. The wiring structure 11, which may include a multi-layer structure, may include cells 11a, 11b, 11c, and 11d as shown in the dashed box. Although Figure 2 The diagram illustrates a layer 10 of a wiring structure 11 that may have four units; however, it is anticipated that layer 10 of the wiring structure 11 may contain more or fewer units.

[0032] Figure 3 The wiring structure 11 according to some embodiments of the present invention is described.

[0033] refer to Figure 3 The wiring structure 11 may include unit 111, unit 112, unit 113, unit 114 and other units (not shown in the diagram). Figure 3 (This is from the Chinese text.)

[0034] Unit 111 can be positioned at elevation E1. Unit 111 may have a circuit layer 111a. Unit 111 may have a dielectric layer 111b. The dielectric layer 111b may surround the circuit layer 111a. Unit 111 may have a core 111c. In some other embodiments of the invention, the core 111c may be eliminated.

[0035] Unit 112 may be positioned at an elevation substantially the same as elevation E1. Unit 112 may have a circuit layer 112a. Unit 112 may have a dielectric layer 112b. The dielectric layer 112b may surround the circuit layer 112a. Unit 112 may have a core 112c. In some other embodiments of the invention, the core 112c may be eliminated.

[0036] The wiring structure 11 may have an insulating wall 115 disposed between cells 111 and 112. The wiring structure 11 may have a redistribution layer 116 disposed on cells 111 and 112. The redistribution layer 116 may be electrically connected between cells 111 and 112. The insulating wall 115 may contain a material substantially different from that of the dielectric layer 111b. The insulating wall 115 may contain a material substantially the same as that of the dielectric layer 111b. The insulating wall 115 may contain an encapsulating agent or encapsulating material. The insulating wall 115 may contain microparticles. The insulating wall 115 may contain resin and fillers (or microparticles). The insulating wall 115 may contain molding compounds. The insulating wall 115 may contain thermosetting materials. The insulating wall 115 may contain thermoplastic materials.

[0037] The insulating wall 115 may surround the unit 111. The insulating wall 115 may enclose the unit 111. The insulating wall 115 may be in direct contact with the unit 111.

[0038] The insulating wall 115 may surround the unit 112. The insulating wall 115 may enclose the unit 112. The insulating wall 115 may be in direct contact with the unit 112.

[0039] The redistribution layer 116 can be disposed on the insulating wall 115. The redistribution layer 116 can be in direct contact with the insulating wall 115.

[0040] Unit 113 may be disposed on redistribution layer 116. Unit 113 may have circuit layer 113a. Unit 113 may have dielectric layer 113b. Dielectric layer 113b may surround circuit layer 113a. Unit 113 may have core 113c. Redistribution layer 116 may be electrically connected to unit 113. In some other embodiments of the invention, core 113c may be eliminated.

[0041] Circuit layer 111a may have a spacing substantially the same as that of circuit layer 112a. Circuit layer 111a may have a conductor length / space substantially the same as that of circuit layer 112a. Circuit layer 111a may have a spacing substantially the same as that of circuit layer 113a. Circuit layer 111a may have a conductor length / space substantially the same as that of circuit layer 113a. Circuit layer 111a may have a spacing substantially the same as that of redistribution layer 116. Circuit layer 111a may have a conductor length / space substantially different from that of redistribution layer 116. Circuit layer 111a may have a conductor length / space substantially different from that of redistribution layer 116. Circuit layer 111a may have a spacing approximately 10 μm. Circuit layer 111a may have a conductor length / space approximately 10 μm / 10 μm. Circuit layer 111a may have a conductor length / space less than approximately 10 μm / 10 μm.

[0042] Unit 114 may be disposed on redistribution layer 116. Unit 114 may have circuit layer 114a. Unit 114 may have dielectric layer 114b. Dielectric layer 114b may surround circuit layer 114a. Units 113 and 114 may be disposed at substantially the same elevation E2. Circuit layer 113a may have substantially the same spacing as circuit layer 114a. Circuit layer 113a may have substantially the same conductor length / space as circuit layer 114a.

[0043] The wiring structure 11 may include an insulating wall 117 disposed between cells 113 and 114. The insulating wall 117 may contain a material substantially the same as that of the insulating wall 115. The insulating wall 117 may contain a material substantially different from that of the insulating wall 115. The insulating wall 117 may surround the cell 113. The insulating wall 117 may enclose the cell 113. The insulating wall 117 may be in direct contact with the cell 113.

[0044] The insulating wall 117 may surround the unit 114. The insulating wall 117 may enclose the unit 114. The insulating wall 117 may be in direct contact with the unit 114.

[0045] The wiring structure 11 may include a redistribution layer 118 disposed on units 113 and 114. The redistribution layer 118 may be electrically connected between units 113 and 114. The redistribution layer 118 may be disposed on an insulating wall 117. The redistribution layer 118 may be in direct contact with the insulating wall 117.

[0046] Circuit layer 113a may have substantially the same spacing as redistribution layer 118. Circuit layer 113a may have substantially the same conductor length / space as redistribution layer 118. Circuit layer 113a may have substantially different spacing from redistribution layer 118. Circuit layer 113a may have substantially different conductor length / space from redistribution layer 118.

[0047] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A method for manufacturing a wiring structure according to some embodiments of the present invention is described.

[0048] Figure 3A This describes some wiring structure units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h and 11i, which are tested and can be called good units or functional units.

[0049] Figure 3B Explanation as follows Figure 3A The layout of the cells shown.

[0050] refer to Figure 3B Units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, and 11i may be arranged, positioned, or constructed in a pattern, such as, but not limited to, square, near-square, rectangular, near-rectangular, circular, or other shapes. One of units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, and 11i may be surrounded by an insulating wall 12 or an insulating material 12. One of units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, and 11i may be enclosed by an insulating wall 12 or an insulating material 12. The insulating wall 12 or encapsulating material 12 may encapsulate units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, and 11i. Encapsulating material 12 can be used to encapsulate units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, and 11i by means of, but not limited to, molding techniques. The insulating wall 12 or encapsulating material 12 can be in direct contact with a transverse surface (not shown) of one of units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, and 11i.

[0051] Figure 3C Explain crossing as Figure 3B The cross-sectional view of the structure of line AA' shown.

[0052] refer to Figure 3CUnits 11a and 11b can be placed at substantially the same elevation. Units 11a and 11b can be separated by an insulating wall 12. The insulating wall 12 can surround unit 11a. The insulating wall 12 can surround unit 11b. The insulating wall 12 can enclose unit 11a. The insulating wall 12 can enclose unit 11b. The insulating wall 12 can be in direct contact with unit 11a. The insulating wall 12 can be in direct contact with unit 11b. The insulating wall 12 can be in direct contact with the transverse surface (not shown) of unit 11a. The insulating wall 12 can be in direct contact with the transverse surface (not shown) of unit 11b.

[0053] Each of units 11a and 11b may have a surface 11a1, a surface 11a2 opposite to surface 11a1, and a surface 11a3 extending between surface 11a1 and surface 11a2. Encapsulating units 11a and 11b may include surface 11a3 of each of encapsulating units 11a and 11b, and expose surfaces 11a1 and 11a2 of each of units 11a and 11b.

[0054] refer to Figure 3D The redistribution layer 116' is formed on the reconstructed structure, such as Figure 3B As shown in the diagram. The redistribution layer 116' can be coupled with, for example... Figure 1 The redistribution layer 10' shown is the same as or similar to that shown.

[0055] In such Figure 3C The redistribution layer 116' formed on the structure shown may include electrically connecting the redistribution layer 116' to the reconfigured structure. The redistribution layer 116' may be disposed on the insulating wall 12. The redistribution layer 116' may be formed on cell 11a. The redistribution layer 116' may be formed on cell 11b.

[0056] refer to Figure 3E ,like Figure 3A , Figure 3B and Figure 3C The operations shown can be repeated to form, as Figure 1 The wiring structure 1 shown is a stacked structure or panel. A cutting technique can be applied or performed along the scribe line S to form as shown in the reference. Figure 3 Some wiring structures 11 are described and illustrated.

[0057] Each of units 11c and 11d may have a surface 11c1, a surface 11c2 opposite to surface 11c2, and a surface 11c3 extending between surfaces 11c1 and 11c2. Encapsulating units 11c and 11d may include surface 11c3 of each of encapsulating units 11c and 11d and expose surfaces 11c1 and 11c2 of each of units 11c and 11d.

[0058] The layers of units 11c and 11d can be stacked on the layers of units 11a and 11b. Forming a redistribution layer 118' on the layers of units 11c and 11d may include layers electrically connecting the redistribution layer 118' to units 11c and 11d. The redistribution layer 118' may be disposed on an insulating wall 117'. The redistribution layer 118' may be formed on unit 11c. The redistribution layer 118' may be formed on unit 11d. The layers of units 11c and 11d can be stacked on a redistribution layer 116'. Stacking the layers of units 11c and 11d on the redistribution layer 116' may include layers electrically connecting the redistribution layer 116' to units 11c and 11d.

[0059] Figure 3E Describe a multilayer substrate. For example... Figure 3E As shown, the multilayer substrate may have layers having multiple units (e.g., units 11a and 11b) embedded in an insulating material 12. The multilayer substrate may have a redistribution layer 116' disposed on the layers of units 11a and 11b. The multilayer substrate may include layers having multiple units (e.g., units 11c and 11d) embedded in an insulating material 12. The layers of units 11c and 11d may be disposed on the redistribution layer 116'. One of the multiple units (e.g., units 11a and 11b) may be separable from another via the insulating material 12. One of the multiple units (e.g., units 11c and 11d) may be separable from another via the insulating material 12. A redistribution layer 118' may be disposed on the layers of units 11c and 11d. The redistribution layer 118' may be electrically connected to the layers of units 11c and 11d. The redistribution layer 116' may be electrically connected to the layers of units 11a and 11b. The redistribution layer 116' can be electrically connected to the layers of cells 11c and 11d.

[0060] like Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The operations described herein can improve yield. Assume that the panel of wiring structure 1 can contain a total of X units, and if wiring structure units fail during manufacturing, then the failure rate can be determined as follows:

[0061] Assuming each layer of cells in the panel of wiring structure 1 (e.g., such as...) Figure 1 The defect count for layer 10 shown is 6 cells per layer, and the failure rate of a single layer can be determined as follows:

[0062] Assume that the panel of wiring structure 1 can contain Y layers of wiring structure units, and the yield of the panel of wiring structure 1 can be determined as follows:

[0063] For example, assuming the panel of wiring structure 1 has 80 units and 10 layers, the five-layer structure can be achieved through reference... Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The methods described and explained are formed, and have a general structure. The yield. Another five-layer structure can be achieved through, as referenced... Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The methods described and explained are formed, and have a general structure. The yield. Accordingly, a ten-layer structure can be formed by stacking two five-layer structures, having approximately The yield.

[0064] In addition, Figure 3B Each of the middle units 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h and 11i may have been tested and refactored, which could improve the yield of the panels of wiring structure 1.

[0065] Figure 4 A cross-sectional view illustrating another wiring structure according to some embodiments of the present invention is provided.

[0066] refer to Figure 4 The wiring structure 11a' is similar to that in the reference. Figure 3 The wiring structure 11 described and illustrated differs in that the wiring structure 11a' further includes a redistribution layer 121.

[0067] Redistribution layer 121 may be disposed on redistribution layer 118. Wiring structure 11a may further include intermediate layer 122, which may be disposed between redistribution layers 118 and 121.

[0068] Figure 5 A comparative embodiment of the panel illustrating the wiring structure of the present invention is provided.

[0069] The panel of wiring structure 1' may include stacked circuit layers 10". Circuit layer 10" may have wiring structure units 11a', 11b', 11c', 11d', etc. The panel of wiring structure 1' may not have a distribution layer disposed between circuit layer 10" and another adjacent circuit layer 10". Circuit layer 10" is different from... Figure 1 Layer 10 is shown. Circuit layer 10" does not contain encapsulating material. The panel of wiring structure 1' can be formed by stacking circuit layers 10".

[0070] Assuming the panel of wiring structure 1' can contain a total of X units, and if any wiring structure unit fails during manufacturing, then the failure rate can be determined as follows:

[0071] Assuming each layer of cells in the panel of wiring structure 1' (e.g., as...) Figure 5 The defect count for layer 10" shown is 6 cells per layer, and the failure rate of a single layer can be determined as follows:

[0072] Assuming the panel of wiring structure 1' can contain Y layers of wiring structure units, and the yield of the panel of wiring structure 1' can be determined as follows:

[0073] For example, assuming the panel of wiring structure 1' has 20 units and 10 layers, the ten-layer structure 1' can be formed by the stacking method described above, having approximately The yield.

[0074] Furthermore, a faulty cell in a single circuit layer 10" may cause a fault in wiring structure 11A', which may adversely affect the yield of the panel of wiring structure 1'.

[0075] Figure 6A An assembly view of a panel illustrating a wiring structure according to some embodiments of the present invention.

[0076] refer to Figure 6A The panel of wiring structure 2 may include layer 20 and redistribution layer 20'. Panel 2 may include a multi-layer structure. Panel 2 may include a stacked structure of layer 20 and redistribution layer 20'.

[0077] Although not in Figure 6A The description states that, however, the panel of wiring structure 2 is expected to contain more layers 20' and 20' stacked on top of each other. Although not explicitly stated... Figure 6A The description states that the panel of wiring structure 2 is expected to contain more layers 20' and 20 that are interleaved with each other.

[0078] Figure 6B Explanation as follows Figure 6A An exploded view of the panel showing the wiring structure.

[0079] refer to Figure 6B The wiring structure 2a may contain a multi-layer structure. The wiring structure 2a, which may include unit 201 and redistribution unit 201', can be separated from the panel 2 by using a cutting technique along the cut line (or scribing line) S. Although in Figure 6B The wiring structure of the middle panel 2 is arranged or positioned in a rectangular or quasi-rectangular shape; however, it is anticipated that the wiring structure can be arranged in a shape other than those described above.

[0080] refer to Figure 6B Layer 20 may contain various units (e.g., units 201, 202, 203, 204, etc.). Unit 201 may contain sub-units 201a, 201b, 201c, and 201d. Although Figure 6B The cell 201 of layer 20 may have four sub-cells 201a, 201b, 201c, and 201d; however, in some other embodiments of the invention, the cell 201 of layer 20 is expected to contain more or fewer sub-cells. Sub-cells 201a, 201b, 201c, and 201d may be encapsulated by insulating material 201e. Sub-cells 201a, 201b, 201c, and 201d may be surrounded by insulating material 201e. Sub-cells 201a, 201b, 201c, and 201d may be enclosed by insulating material 201e. Sub-cells 201a, 201b, 201c, and 201d may be in direct contact with insulating material 201e.

[0081] The cells of layer 20 (e.g., cells 201, 202, 203, 204...) can be encapsulated by insulating material 201f. The cells of layer 20 (e.g., cells 201, 202, 203, 204...) can be surrounded by insulating material 201f. The cells of layer 20 (e.g., cells 201, 202, 203, 204...) can be enclosed by insulating material 201f. The cells of layer 20 (e.g., cells 201, 202, 203, 204...) can be in direct contact with insulating material 201f.

[0082] Figure 7A Explanation as follows Figure 6B The diagram shows a cross-sectional view of the wiring structure 2a. The wiring structure 2a may include sub-units 201a, 201b, and 201c (not shown in the diagram). Figure 7A (shown in), subunit 201d (not shown in) Figure 7A (as shown in the figure), and redistribution unit 201'.

[0083] The redistribution unit 201' can be disposed on sub-unit 201a. The redistribution unit 201' can be disposed on sub-unit 201b. The redistribution unit 201' can be disposed on sub-unit 201c. The redistribution unit 201' can be disposed on sub-unit 201d. The redistribution unit 201' can be electrically connected to sub-unit 201a. The redistribution unit 201' can be electrically connected to sub-unit 201b. The redistribution unit 201' can be electrically connected to sub-unit 201c. The redistribution unit 201' can be electrically connected to sub-unit 201d.

[0084] Sub-unit 201a may be positioned at elevation E3. Sub-unit 201a may have a circuit layer 2011. Sub-unit 201a may have a dielectric layer 2012. The dielectric layer 2012 may surround the circuit layer 2011. Sub-unit 201a may have a core 2013. In some other embodiments of the invention, the core 2013 may be eliminated.

[0085] Subunit 201b may be positioned at an elevation substantially the same as elevation E3. Subunit 201b may have a circuit layer 2021. Subunit 201b may have a dielectric layer 2022. The dielectric layer 2022 may surround the circuit layer 2021. Subunit 201b may have a core 2023. In some other embodiments of the invention, the core 2023 may be eliminated. Subunit 201b may have the same or similar structure as subunit 201a.

[0086] Wiring structure 2a may have an insulating wall 201e' disposed between sub-units 201a and 201b. Wiring structure 2a may have an insulating wall 201e' disposed between sub-units 201a and 201c. Wiring structure 2a may have an insulating wall 201e' disposed between sub-units 201a and 201d. Wiring structure 2a may have an insulating wall 201e' disposed between sub-units 201b and 201c. Wiring structure 2a may have an insulating wall 201e' disposed between sub-units 201b and 201d. Wiring structure 2a may have an insulating wall 201e' disposed between sub-units 201c and 201d.

[0087] Insulating wall 201e' may surround sub-unit 201a. Insulating wall 201e' may surround sub-unit 201b. Insulating wall 201e' may surround sub-unit 201c. Insulating wall 201e' may surround sub-unit 201d. Insulating wall 201e' may enclose sub-unit 201a. Insulating wall 201e' may enclose sub-unit 201b. Insulating wall 201e' may enclose sub-unit 201c. Insulating wall 201e' may enclose sub-unit 201d. Insulating wall 201e' may be in direct contact with sub-unit 201a. Insulating wall 201e' may be in direct contact with sub-unit 201b. Insulating wall 201e' may be in direct contact with sub-unit 201c. Insulating wall 201e' may be in direct contact with sub-unit 201d.

[0088] The insulating wall 201e' may contain a material substantially different from that of the dielectric layer 2012. The insulating wall 201e' may contain a material substantially the same as that of the dielectric layer 2012. The insulating wall 201e' may contain an encapsulating agent or encapsulating material. The insulating wall 201e' may contain microparticles. The insulating wall 201e' may contain resin and fillers (or microparticles). The insulating wall 201e' may contain molding compounds. The insulating wall 201e' may contain thermosetting materials. The insulating wall 201e' may contain thermoplastic materials.

[0089] Each of the sub-units (e.g., sub-units 201a, 201b, 201c, and 201d) may contain a redistribution layer. For example, sub-unit 201a may contain a redistribution layer 2014. For example, sub-unit 201b may contain a redistribution layer 2024.

[0090] Each of the sub-units (e.g., sub-units 201a, 201b, 201c, and 201d) may include an intermediate layer disposed between the redistribution layer and the circuit layer. For example, sub-unit 201a may include an intermediate layer 2015 disposed between the redistribution layer 2014 and the circuit layer 2011. For example, sub-unit 201b may include an intermediate layer 2025 disposed between the redistribution layer 2024 and the circuit layer 2021.

[0091] The insulating wall 201e' may comprise a material substantially the same as or similar to the dielectric layer 2022. The insulating wall 201e' may comprise a material substantially different from the dielectric layer 2022. The insulating wall 201e' may surround the redistribution layer 2014. The insulating wall 201e' may enclose the redistribution layer 2014. The insulating wall 201e' may be in direct contact with the redistribution layer 2014.

[0092] The insulating wall 201e' may surround the redistribution layer 2024. The insulating wall 201e' may enclose the redistribution layer 2024. The insulating wall 201e' may be in direct contact with the redistribution layer 2024.

[0093] The redistribution layer 201' can be placed on the insulating wall 201e'. The redistribution layer 201' can be in direct contact with the insulating wall 201e'.

[0094] The insulating wall 201e' may have a transverse surface S1 exposed to air. The redistribution layer 201' may have a transverse surface (not shown). The redistribution layer 201' may have a transverse surface (not shown) that is substantially coplanar with the surface S1 of the insulating wall 201e'. The surface S1 of the insulating wall 201e' may have a relatively large surface roughness.

[0095] Circuit layer 2011 may have substantially the same spacing as circuit layer 2012. Circuit layer 2011 may have substantially the same conductor length / space as circuit layer 2012. Circuit layer 2011 may have substantially the same spacing as redistribution layer 201'. Circuit layer 2011 may have substantially the same conductor length / space as redistribution layer 201'. Circuit layer 2011 may have a spacing substantially different from redistribution layer 201'. Circuit layer 2011 may have a conductor length / space substantially different from redistribution layer 201'. Circuit layer 2011 may have a spacing of approximately 10 μm. Circuit layer 2011 may have a conductor length / space of approximately 10 μm / 10 μm. Circuit layer 2011 may have a conductor length / space less than approximately 10 μm / 10 μm.

[0096] Redistribution layer 2014 may have a spacing substantially different from that of circuit layer 2012. Redistribution layer 2014 may have a spacing substantially smaller than that of circuit layer 2012. Redistribution layer 2014 may have a conductor length / space substantially different from that of circuit layer 2012. Redistribution layer 2014 may have a conductor length / space substantially smaller than that of circuit layer 2012. Redistribution layer 2014 may have a conductor length / space substantially different from that of redistribution layer 201'. Redistribution layer 2014 may have a conductor length / space substantially smaller than that of redistribution layer 201'.

[0097] The redistribution layer 2014 may include a fan-out layer. The redistribution layer 2014 may have a wire length / space of approximately 2 μm / 2 μm. The redistribution layer 2014 may have a wire length / space of less than approximately 2 μm / 2 μm. The redistribution layer 2014 may help reduce the size of the sub-cell 201a. The redistribution layer 2014 may help reduce the thickness of the sub-cell 201a.

[0098] The redistribution layer 2024 can have a similar or identical structure to the redistribution layer 2014.

[0099] Figure 7B A cross-sectional view illustrating another wiring structure according to some embodiments of the present invention is provided.

[0100] refer to Figure 7B The wiring structure 2a' is similar to that in the reference. Figure 7A The wiring structure 2a described and illustrated differs in that the wiring structure 2a' may further include an insulating wall 201f'.

[0101] Insulating wall 201f' may surround sub-unit 201a. Insulating wall 201f' may surround sub-unit 201b. Insulating wall 201f' may surround sub-unit 201c. Insulating wall 201f' may surround sub-unit 201d. Insulating wall 201f' may surround insulating wall 201e'.

[0102] Insulating wall 201f' can surround sub-unit 201a. Insulating wall 201f' can surround sub-unit 201b. Insulating wall 201f' can surround sub-unit 201c. Insulating wall 201f' can surround sub-unit 201d. Insulating wall 201f' can surround insulating wall 201e'.

[0103] Insulating wall 201f' can be separated from or spaced apart from sub-unit 201a via insulating wall 201e'. Insulating wall 201f' can be separated from or spaced apart from sub-unit 201b via insulating wall 201e'. Insulating wall 201f' can be separated from or spaced apart from sub-unit 201c via insulating wall 201e'. Insulating wall 201f' can be separated from or spaced apart from sub-unit 201d via insulating wall 201e'.

[0104] Insulating wall 201e' can be placed between sub-unit 201a and insulating wall 201f'. Insulating wall 201e' can be placed between sub-unit 201b and insulating wall 201f'. Insulating wall 201e' can be placed between sub-unit 201c and insulating wall 201f'. Insulating wall 201e' can be placed between sub-unit 201d and insulating wall 201f'.

[0105] Insulating wall 201f' can be in direct contact with insulating wall 201e'. Insulating wall 201f' can be in direct contact with redistribution layer 201'. Insulating wall 201e' can be in direct contact with redistribution layer 201'. Redistribution layer 201' can be disposed on insulating wall 201e'. Redistribution layer 201' can be disposed on insulating wall 201f'.

[0106] Insulating wall 201f' may contain a material substantially different from that of insulating wall 201e'. Insulating wall 201f' may contain a material substantially the same as that of insulating wall 201e'. Insulating wall 201f' may contain encapsulating material or encapsulating agent. Insulating wall 201f' may contain microparticles. Insulating wall 201f' may contain resin and filler (or microparticles). Insulating wall 201f' may contain molding compound. Insulating wall 201f' may contain thermosetting material. Insulating wall 201f' may contain thermoplastic material.

[0107] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8EA method for manufacturing a wiring structure according to some embodiments of the present invention is described.

[0108] Figure 8A This describes some sub-units 201a, 201b, 201c, and 201d, which pass the test and can be called good sub-units or functional sub-units.

[0109] Figure 8B The description has the following characteristics: Figure 8A Some of the sub-units shown are units 201.

[0110] refer to Figure 8B Unit 201 may include subunits 201a, 201b, 201c, and 201d. Subunits 201a, 201b, 201c, and 201d may be arranged, positioned, or constructed in a pattern, such as, but not limited to, square, near-square, rectangular, near-rectangular, circular, or other shapes. One of subunits 201a, 201b, 201c, and 201d may be surrounded by an insulating wall 201e' or an insulating material 201e'. One of subunits 201a, 201b, 201c, and 201d may be enclosed by an insulating wall 201e' or an insulating material 201e'. The insulating wall 201e' or encapsulating material 201e' may encapsulate subunits 201a, 201b, 201c, and 201d. Encapsulating material 201e' can be used to encapsulate sub-units 201a, 201b, 201c, and 201d by means of, but not limited to, molding techniques. Insulating wall 201e' or encapsulating material 201e' can be in direct contact with a lateral surface (not shown) of one of sub-units 201a, 201b, 201c, and 201d.

[0111] Figure 8C Explain crossing as Figure 8B The cross-sectional view of the structure of line BB' shown.

[0112] refer to Figure 8C Sub-units 201a and 201b can be placed at substantially the same elevation. Sub-units 201a and 201b can be separated by an insulating wall 201e. The insulating wall 201e can surround sub-unit 201a. The insulating wall 201e can surround sub-unit 201b. The insulating wall 201e can enclose sub-unit 201a. The insulating wall 201e can enclose sub-unit 201b. The insulating wall 201e can be in direct contact with sub-unit 201a. The insulating wall 201e can be in direct contact with sub-unit 201b. The insulating wall 201e can be in direct contact with the transverse surface (not shown) of sub-unit 201a. The insulating wall 201e can be in direct contact with the transverse surface (not shown) of sub-unit 201b.

[0113] As shown in 8C, each of subunits 201a and 201b has a surface 201a1, a surface 201a2 opposite to surface 201a1, and a surface 201a3 extending between surface 201a1 and surface 201a2. Encapsulating subunits 201a and 201b in a layer forming the subunits includes surface 201a3 of each of subunits 201a and 201b and exposes surfaces 201a1 and 201a2 of each of subunits 201a and 201b.

[0114] Figure 8D Explanation as follows Figure 6B The layout of layer 20 is shown.

[0115] refer to Figure 8D ,like Figure 8B The units 201, 202, 203, 204... shown can be arranged, placed, or constructed in a pattern, such as, but not limited to, square, near-square, rectangular, near-rectangular, circular, or other shapes. One of the units 201, 202, 203, 204... can be surrounded by an insulating wall 201f or an insulating material 201f. The insulating wall 201f or encapsulating material 201f can encapsulate units 201, 202, 203, 204... The encapsulating material 201f can be used to encapsulate units 201, 202, 203, 204 by, for example, but not limited to, molding techniques.

[0116] refer to Figure 8E This indicates that redistribution layer 20' can be formed on layer 20 and across layers such as Figure 8D The cross-sectional view of the structure of line CC' shown.

[0117] Forming a redistribution layer 20' on layer 20 may include electrically connecting the redistribution layer 20' to layer 20. The redistribution layer 20' may be disposed on an insulating wall 201f'. The redistribution layer 20' may be formed on cell 201. The redistribution layer 20' may be formed on cell 202.

[0118] The cutting technique can be performed along the scribing line S to form such as Figure 7A Some wiring structures 2a are shown. The cutting technique can be performed along the scribing line S to form, as shown... Figure 7B Some wiring structures 2a' are shown. For example, tools (e.g., cutting tools) with relatively large widths can be used to perform... Figure 8E The cutting operation in the middle to form such as Figure 7A Some wiring structures 2a are shown. For example, tools (e.g., cutting tools) with relatively small widths can be used to perform... Figure 8E The cutting operation in the middle to form such as Figure 7B Some wiring structures 2a' are shown in the figure.

[0119] like Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E The operations described herein can improve yield.

[0120] Assuming the panel of wiring structure 2 (e.g.) Figure 6A (As shown) may contain a total of X units, and if one wiring structure unit fails during manufacturing, the failure rate can be determined as follows:

[0121] Assuming each layer of cells in the panel of wiring structure 2 (e.g., such as...) Figure 1 The defect count for layer 20 shown is 6 cells per layer, and the failure rate of a single layer can be determined as follows:

[0122] Assuming that the panel of wiring structure 2 can contain Y layers of wiring structure units, and the yield of the panel of wiring structure 1' can be determined as follows:

[0123] Assume that each cell of the panel in wiring structure 2 can contain Z sub-cells, and the yield of the panel in wiring structure 2 can be determined as follows:

[0124] For example, suppose the panel of wiring structure 2 has 20 units and 10 layers, and each unit has 4 sub-units. The ten-layer structure can be constructed as shown in the reference. Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E The methods described and explained form a general structure. The yield.

[0125] In addition, Figure 8E Each of the middle units 201, 202, 203, 204… has likely been tested and refactored, which could improve the yield of the panels in wiring structure 2. Furthermore, in Figure 8E Each of the neutron cells 201a, 201b, 201c, 201d... may have been tested and reconfigured, which could improve the yield of the panels of wiring structure 2.

[0126] Figure 9 A comparative embodiment of the panel illustrating the wiring structure of the present invention is provided.

[0127] The panel of wiring structure 2' may include a circuit layer 20"'. The circuit layer 20"' may have wiring structure units 211, 212, 213, 214... Unit 211 differs from... Figure 6B and Figure 8B Unit 201 is shown. Unit 211 does not contain sub-units. Although not in Figure 9 The description states that the panel with wiring structure 2' is expected to contain more circuit layers 20”'.

[0128] Assuming the panel of wiring structure 2' can contain a total of X units, and if a wiring structure unit fails during manufacturing, then the failure rate can be determined as follows:

[0129] Assuming each layer of cells in the panel of wiring structure 2' (e.g., as Figure 9 The defect count for layer 20”’) shown is 6 cells per layer, and the failure rate of a single layer can be determined as

[0130] Assuming the panel of wiring structure 2' can contain Y layers of wiring structure units, and the yield of the panel of wiring structure 2' can be determined as follows:

[0131] For example, assuming the panel of wiring structure 2' has 20 units and 10 layers, and each unit does not contain sub-units, then the ten-layer structure 2' can be formed by the stacking method described above, having approximately The yield.

[0132] Furthermore, a faulty cell in each of a single circuit layer 20”’ may cause a fault in the wiring structure, which may adversely affect the yield of the panel of the wiring structure 2’.

[0133] Unless otherwise specified, spatial descriptions such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper part," "above," "below," etc., are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of the invention are not affected by such arrangements.

[0134] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered “substantially” the same as or equal to the second numerical value. For example, “basically” vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0135] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0136] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators.

[0137] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to carry electric current. Conductive materials typically indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0138] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly defined as range limits, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly defined.

[0139] Although the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, artistic representations of the invention may differ from actual devices. Other embodiments of the invention may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

[0140] As used herein, spatial relative terms such as “below,” “below,” “lower than,” “higher than,” “upper,” “lower,” “left,” “right,” and similar terms may be used herein for ease of description to illustrate the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted similarly accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0141] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or very approximately. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” may refer to two surfaces located along the same plane within a few micrometers (μm), for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When referring to the same numerical value or characteristic, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said value.

[0142] The foregoing outlines several embodiments and detailed features of the present invention. The embodiments described herein can readily serve as the basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and variations can be made without departing from the spirit and scope of the invention.

Claims

1. A wiring structure comprising: The first subunit is located at a first elevation and has a first circuit layer, a first dielectric layer surrounding the first circuit layer, and a first redistribution layer disposed on the first circuit layer. The second subunit is located at the first elevation and has a second circuit layer, a second dielectric layer surrounding the second circuit layer, and a second redistribution layer disposed on the second circuit layer. A first insulating wall is disposed between and around the first sub-unit and the second sub-unit; A third redistribution layer is disposed on the first sub-unit and the second sub-unit, and is electrically connected between the first sub-unit and the second sub-unit. The first sub-unit and the second sub-unit are units that have passed the test and have been reconstructed; as well as A second insulating wall surrounds the first sub-unit and the second sub-unit and surrounds the first insulating wall, wherein the second insulating wall is spaced apart from the first sub-unit and the second sub-unit by the first insulating wall, wherein the third redistribution layer is disposed on the first insulating wall and the second insulating wall, and wherein the second insulating wall comprises a material substantially different from the first insulating wall.

2. The wiring structure according to claim 1, wherein the first sub-unit further includes a first core that extends laterally through the first dielectric layer, and the first core is laterally surrounded and directly contacted by the first dielectric layer.

3. The wiring structure according to claim 2, wherein the first intermediate layer is separated from the first core through the first dielectric layer.

4. The wiring structure according to claim 2, wherein there is an interface between the first core and the first dielectric layer, wherein the first insulating wall surrounds and directly contacts the first core.

5. The wiring structure according to claim 2, wherein the second sub-unit further includes a second core that extends laterally through the second dielectric layer, and the second core is laterally surrounded and directly contacted by the second dielectric layer, wherein the first core and the second core are at the same elevation.

6. The wiring structure according to claim 1, wherein the first redistribution layer has a conductor linewidth / spacing of 2 μm / 2 μm or less, and is smaller than the conductor linewidth / spacing of the first circuit layer.

7. The wiring structure according to claim 6, wherein the conductor width / spacing of the first circuit layer is 5 times the conductor width / spacing of the first redistribution layer.

8. The wiring structure according to claim 1, wherein the first insulating wall has a first lateral surface having a larger surface roughness than the second lateral surface of the third redistribution layer.

9. The wiring structure of claim 1, wherein the first sub-unit includes a first intermediate layer disposed between the first redistribution layer and the first circuit layer, wherein the first redistribution layer has a conductor length / space smaller than that of the third redistribution layer, wherein the first redistribution layer has a conductor length / space smaller than approximately 2 μm / 2 μm, wherein the first insulating wall has a lateral surface exposed to air, and wherein the third redistribution layer has a lateral surface substantially coplanar with the lateral surface of the first insulating wall.

10. The wiring structure according to claim 1, wherein the thickness of the first insulating wall, the thickness of the first sub-unit, and the thickness of the second sub-unit are the same, wherein the top surface of the first insulating wall, the top surface of the first sub-unit, and the top surface of the second sub-unit are coplanar and directly contact the third redistribution layer.

11. A method for manufacturing a wiring structure, comprising: (a) Providing multiple first substrate subunits; (b) Encapsulating the plurality of first substrate sub-units with a first insulating material to form a plurality of first substrate sub-units, the first insulating material surrounding the plurality of first substrate sub-units; as well as (c) Encapsulating the plurality of first substrate units with a second insulating material to form a layer of first substrate units, wherein the second insulating material surrounds the plurality of first substrate units and surrounds the first insulating material, wherein the second insulating material is spaced apart from the plurality of substrate sub-units by the first insulating material, and wherein the first insulating material comprises a material substantially different from the second insulating material; The method further includes: testing the plurality of first substrate sub-units before encapsulating them, wherein the plurality of first substrate sub-units are good units or functional units that pass the test; And a redistribution layer is formed on the first insulating material and the second insulating material.

12. The method of claim 11, wherein each of the plurality of first substrate sub-units has a first surface, a second surface opposite to the first surface, and a third surface extending between the first surface and the second surface, wherein (b) includes encapsulating the third surface of each of the plurality of first substrate sub-units and exposing the first surface and the second surface of each of the plurality of first substrate sub-units, wherein each of the plurality of first substrate sub-units has a dielectric layer and a core laterally extending through the dielectric layer, and the core is laterally surrounded and in direct contact with the dielectric layer.

13. A substrate comprising a plurality of substrate units embedded in a first insulating material, and at least one of the plurality of substrate units comprising a plurality of substrate sub-units embedded in a second insulating material, wherein each of the plurality of substrate sub-units has been tested and reconstructed, wherein the first insulating material surrounds the plurality of substrate units and surrounds the second insulating material, the second insulating material surrounds the plurality of substrate sub-units, wherein the first insulating material is spaced apart from the plurality of substrate sub-units by the second insulating material, wherein the first insulating material comprises a material substantially different from the second insulating material, and wherein the substrate further comprises a redistribution layer disposed on the first insulating material and the second insulating material.

14. The substrate of claim 13, wherein each of the plurality of substrate units is separated from the other of the plurality of substrate units by the first insulating material, wherein each of the plurality of substrate units has been tested and reconstructed.

15. The substrate of claim 14, wherein each of the plurality of substrate sub-units is separated from the other of the plurality of substrate sub-units by the second insulating material, wherein each of the plurality of substrate sub-units has a dielectric layer and a core laterally extending through the dielectric layer, and the core is laterally surrounded and in direct contact with the dielectric layer.

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