Layout structure of a memory array

Abstract

Embodiments of the invention relate to layout structures of memory arrays. Embodiments of the invention relate to a layout method comprising: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite the second side of the word line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to layout structures of memory arrays. BACKGROUND

[0002] In integrated circuits (ICs), fuses are often used to store permanent information or to form permanent connections. For example, fuses can be used to determine faulty circuit connections and to replace defective elements in an IC. Fuses can also be used for chip identification or for implementing security features. Fuses can also be used for analog trimming or calibration to improve circuit functionality. Fuses can also be used for inventory control by enabling or disabling features in an IC. Fuses can also be used as one-time programmable (OTP) memory elements, which can be programmed after the chip is in a packaged form. One-time programmable memory elements are used in ICs to provide non-volatile memory ("NVM"). Data in NVM is not lost when the IC is cut off. For example, NVM allows IC manufacturers to store lot numbers and security data on the IC and can be used in many other applications. One type of NVM is commonly referred to as an electrical fuse (E-fuse). However, a person can obtain the manufacturer's proprietary code or information embedded in an electrical fuse by means of reverse engineering, such as physical failure analysis (PFA). Therefore, there is a need to improve the security of a fuse array in an IC. SUMMARY

[0003] According to embodiments of the present invention, a layout method includes forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row includes a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite the second side of the word line.

[0004] According to embodiments of the present invention, a layout structure of a memory array includes a first row and a second row, wherein each of the first row and the second row includes a plurality of storage cells; a word line disposed between the first row and the second row; a plurality of control electrodes disposed across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; a first cut layer located on a first side of the word line and disposed on a first control electrode of the plurality of control electrodes; and a second cut layer located on a second side of the word line and disposed on a second control electrode of the plurality of control electrodes; wherein the first side of the word line is opposite the second side of the word line.

[0005] According to embodiments of the application, a memory array comprises: a first row and a second row, wherein each of the first row and the second row comprises a plurality of memory cells; a word line disposed between the first row and the second row; a first control electrode coupled to a first side of the word line and a first memory cell of the first row; and a second control electrode coupled to a second side of the word line and a second memory cell of the second row; wherein the first side of the word line is opposite the second side of the word line. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the embodiments of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with industry practice, the various constructed elements are not necessarily drawn to scale. Indeed, the various elements can be arbitrarily enlarged or reduced for clarity. It is further noted that certain elements can be shown cross- sectionally for purposes of illustration only. It is to be understood that the drawings are merely schematic and the actual implementation can vary as a result of, for example, tolerancing, wear and tear, manufacturing process variations, and the like.

[0007] Figure 1 is a flowchart illustrating a layout method for forming a layout structure of a memory array according to some embodiments.

[0008] Figure 2 is a diagram illustrating a layout structure of a memory array according to some embodiments.

[0009] Figure 3 is a diagram illustrating a memory array according to some embodiments.

[0010] Figure 4 is a diagram illustrating a layout structure of a memory array according to some embodiments.

[0011] Figure 5 is a diagram illustrating a memory array according to some embodiments.

[0012] Figure 6 is a diagram illustrating a layout structure of a memory array according to some embodiments.

[0013] Figure 7 is a diagram illustrating a layout structure of a memory array according to some embodiments.

[0014] Figure 8 is a diagram illustrating a layout structure of a memory array according to some embodiments.

[0015] Figure 9 is a functional block diagram of an integrated circuit design and modeling system according to embodiments. DETAILED DESCRIPTION

[0016] Embodiments of the present invention provide numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first member being formed over or on a second member can include embodiments in which the first and second members are formed in direct contact, and can also include embodiments in which additional members can be formed between the first and second members such that the first and second members can not be in direct contact. Additionally, reference numerals and / or letters in various examples can be repeated in various instances. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, spatially relative terms (such as "beneath", "below", "lower", "above", "upper", and the like) can be used herein for ease of description to describe one element's or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] Generally, an electrical fuse is integrated into a semiconductor IC by using a narrow strip of conductive material (metal, polysilicon, etc.) between two pads, commonly referred to as an anode and a cathode. A programming current is applied to the electrical fuse to break or blow the link to thus change the electrical resistance of the electrical fuse. This is commonly referred to as "programming" the electrical fuse. The fuse state (i.e., programmed or unprogrammed) can be read by using a sense circuit.

[0019] During programming, a current is applied through the fuse link for a specified period of time. Due to current crowding and heat dissipation differences, the programming current heats the fuse link more than the adjacent regions to create a temperature gradient. The temperature gradient and carrier flux cause electromigration and stress migration to occur and drive materials (such as silicide, dopants, and polysilicon) away from the fuse link.

[0020] Programming generally converts the electrical fuse from an original resistance to a programmed resistance. The programmed resistance is desirably much higher (typically orders of magnitude higher) than the original resistance to allow the electrical fuse to be reliably read using a sense circuit. A first logic state (such as logic "0") is typically assigned to the unprogrammed, low resistance fuse state, and a second logic state (such as logic "1") is assigned to the programmed, high resistance fuse state. The change in resistance is sensed (read) by the sense circuit to produce a data bit.

[0021] Figure 1is a flowchart illustrating a layout method 100 for forming a layout structure of a memory array according to some embodiments. The layout method 100 can be performed by a processor or manually. Some operations in the layout method 100 can be performed manually. The layout method 100 can be compiled in a computer readable program. The computer readable program can be stored in a memory device. The processor can read or load the computer readable program from the memory device to perform the layout method 100 on a layout structure of a memory array. The layout structure of the memory array is composed of a plurality of storage cells. The storage cells can be pre-designed and stored in a cell library. Generally, the layout method 100 is designed to assign the storage cells to a plurality of word lines of the memory array, respectively. Specifically, the layout method 100 is designed to dispose a plurality of cut layers on a polysilicon line(s) of the storage cells to cut the polysilicon line(s) such that each storage cell can be coupled to a corresponding word line. The cut layers are referred to as cut polysilicon layers (CPOs).

[0022] According to some embodiments, the layout method 100 includes operations 102-106. In operation 102, a layout structure of a memory array having a plurality of rows is formed. Each row includes a plurality of storage cells. The memory array can be a fusible memory array. Thus, the storage cells can include a plurality of fuses, respectively.

[0023] In operation 104, a plurality of word lines is disposed horizontally on the memory array. Specifically, each word line is disposed between every two adjacent rows in the memory array.

[0024] In operation 106, a plurality of control electrodes is disposed vertically on the memory array for connecting a plurality of storage cells in the plurality of rows, respectively. Each control electrode includes at least one polysilicon line. In this embodiment, each control electrode includes a plurality of polysilicon lines.

[0025] In operation 108, for each word line, a plurality of cut layers is disposed on a first portion of the control electrodes that is located on an upper side of the word line such that the first portion of the control electrodes is cut and separated from the word line after fabrication. Specifically, each cut layer is located between the upper side of the word line and a corresponding storage cell that is connected to a corresponding control electrode.

[0026] According to some embodiments, for each control electrode in the first portion of the control electrodes, the cut layer can be disposed on a portion or all of the polysilicon lines of the control electrode.

[0027] According to some embodiments, for the cut layer, the cut layer can be disposed on a plurality of consecutive control electrodes in the first portion of the control electrodes. For example, the cut layer can be disposed on two or three consecutive control electrodes of the storage cells.

[0028] In operation 110, for each word line, a plurality of cut layers are disposed on the second portion of the control electrode that is located on the underside of the word line, such that the second portion of the control electrode is cut and separated from the word line after fabrication. Specifically, each cut layer is located between the underside of the word line and a corresponding storage cell that is connected to a corresponding control electrode.

[0029] According to some embodiments, for each control electrode in the second portion of the control electrode, the cut layer can be disposed on some or all of the polysilicon line of the control electrode.

[0030] According to some embodiments, for the cut layer, the cut layer can be disposed on a plurality of consecutive control electrodes in the second portion of the control electrode. For example, the cut layer can be disposed on two or three consecutive control electrodes of a storage cell.

[0031] Additionally, for the word line, the first portion of the control electrode can be different from the second portion of the control electrode.

[0032] According to some embodiments, for the word line, the first portion of the control electrode and the second portion of the control electrode are located on different columns of the memory array, respectively.

[0033] According to some embodiments, for the word line and for the column, the first portion of the control electrode can partially overlap with the second portion of the control electrode.

[0034] According to operations 108 and 110, the processor is arranged to disturb or randomly disturb the cut layer and dispose the disturbed cut layer on the control electrode of the storage cell. The cut layer is configured to cut the control electrode such that the corresponding storage cell is separated from the word line.

[0035] When the layout of the memory array is designed, a fabrication process can be performed to fabricate the physical memory array of the layout.

[0036] When the cut layer disposed on the control electrode is disturbed, the control electrode of the storage cell in the memory array can be distributed irregularly, which can prevent a person from obtaining the manufacturer's proprietary code or information embedded in the memory array 100 by means of reverse engineering.

[0037] According to some embodiments, the storage cell can be formed by a field effect transistor (FET), and a polysilicon line (i.e., a control electrode) is disposed on a diffusion region or an active region of the field effect transistor for inducing a magnetic field on the diffusion region. Thus, the polysilicon line(s) can be regarded as a gate terminal of the field effect transistor.

[0038] Figure 2is a diagram illustrating a layout structure 200 of a memory array according to some embodiments. The layout structure 200 includes a plurality of memory cells 202_1_1 to 202_4_2, a plurality of cut layers 204_1 to 204_4, and a plurality of polysilicon lines (or control electrodes) 206_1 to 206_4. The memory cells 202_1_1 to 202_4_2 are respectively coupled to a plurality of fuses 212_1_1 to 212_4_2. The fuses are respectively coupled to a drain (or source) of a corresponding transistor of the memory cell. The fuses 212_1_1 to 212_4_2 can be metal fuses. According to some embodiments, each of the fuses 212_1_1 to 212_4_2 includes a first pad (e.g., 204), a second pad (e.g., 206), and a link or strip (e.g., 208). When the layout structure 200 is fabricated and before programming, the link 208 is arranged to connect the first and second pads. One of the first and second pads is arranged to be coupled to a drain (or source) of a corresponding transistor of the memory cell, and the other pad (i.e., a bit line) is coupled to a sensing circuit for outputting data. During programming, a current is applied through the link to break or blow the link to thus change a resistance of the fuse.

[0039] In addition, the cut layers 204_1 to 204_4 can be masks for cutting the polysilicon layers on which the cut polysilicon layers are disposed during a fabrication process. In this embodiment, the cut layers 204_1 to 204_4 are cut polysilicon layers. According to some embodiments, the cut layer 204_1 is on an upper side of the conductive path 210 and disposed on the polysilicon line 206_1 of the corresponding memory cell. The cut layer 204_2 is on the upper side of the conductive path 210 and disposed on the polysilicon line 206_3 of the corresponding memory cell. The cut layer 204_3 is on a lower side of the conductive path 210 and disposed on the polysilicon line 206_2 of the corresponding memory cell. The cut layer 204_4 is on the lower side of the conductive path 210 and disposed on the polysilicon line 206_4 of the corresponding memory cell.

[0040] Figure 3 is a diagram illustrating a memory array 300 according to some embodiments. The memory array 300 can be a physical circuit of the layout structure 200. For brevity, Figure 3 some numbers in the memory array 300 in Figure 2 are arranged similarly to the numbers of the layout structure 200 in The memory array 300 includes a plurality of memory cells 302_1_1 to 302_4_2. The memory cells 302_1_1 to 302_4_1 are arranged as a first row, and the memory cells 302_1_2 to 302_4_2 are arranged as a second row. The conductive path 210 is disposed horizontally between the first and second rows.

[0041] The memory array 300 further includes a plurality of first polysilicon lines (or control electrodes) 306_1, a plurality of second polysilicon lines 306_2, a plurality of third polysilicon lines 306_3, a plurality of fourth polysilicon lines 306_4, a plurality of fifth polysilicon lines 306_5, a plurality of sixth polysilicon lines 306_6, a plurality of seventh polysilicon lines 306_7, and a plurality of eighth polysilicon lines 306_8. The polysilicon lines 306_1-306_8 are vertically disposed in the memory cells 302_1_1-302_m_n, respectively. Specifically, the cut layer 204_1 is arranged to cut the polysilicon lines 206_1 during a fabrication process to form the polysilicon lines 306_1 and 306_5. The cut layer 204_2 is arranged to cut the polysilicon lines 206_3 during a fabrication process to form the polysilicon lines 306_3 and 306_7. The cut layer 204_3 is arranged to cut the polysilicon lines 206_2 during a fabrication process to form the polysilicon lines 306_2 and 306_6. The cut layer 204_4 is arranged to cut the polysilicon lines 206_4 during a fabrication process to form the polysilicon lines 306_4 and 306_8.

[0042] According to some embodiments, the conductive path 210 is electrically coupled to the polysilicon lines 306_2, 306_4, 306_6, and 306_8, and the conductive path 210 is not coupled to the polysilicon lines 306_1, 306_3, 306_5, and 306_7. Thus, the conductive path 210 can be a word line for the memory cells 302_2_1, 302_4_1, 302_1_2, and 302_3_2. When a voltage level of the conductive path 210 is enabled (e.g., a high voltage level for N-type transistors or a low voltage level for P-type transistors), data (i.e., logic states) in the memory cells 302_2_1, 302_4_1, 302_1_2, and 302_3_2 can be selected and read out by a sensing circuit. In other words, in the memory array 300, the memory cells selected by a word line (i.e., 210) are not disposed on the same side of the word line. According to embodiments, some memory cells (e.g., 302_2_1 and 302_4_1) are disposed on an upper side of the word line, while other memory cells (e.g., 302_1_2 and 302_3_2) are disposed on a lower side of the word line. Furthermore, on the upper side of the word line (i.e., 210), the memory cells coupled to the word line (e.g., 302_2_1 and 302_4_1) are not contiguous memory cells. The memory cells 302_2_1 and 302_4_1 are separated by the memory cell 302_3_1. On the lower side of the word line (i.e., 210), the memory cells coupled to the word line (e.g., 302_1_2 and 302_3_2) are not contiguous memory cells. The memory cells 302_1_2 and 302_3_2 are separated by the memory cell 302_2_2.

[0043] Thus, in this embodiment, the storage cells 302_2_1, 302_4_1, 302_1_2, and 302_3_2 coupled to the word line (i.e., 210) are arranged in a zigzag pattern. The zigzag arrangement of the storage cells 302_2_1, 302_4_1, 302_1_2, and 302_3_2 can prevent a person from obtaining a manufacturer's proprietary code or information embedded in the memory array 300 by means of reverse engineering, such as physical failure analysis (PFA).

[0044] It should be noted that the storage cells 302_1_1 and 302_3_1 and the storage cells 302_2_2 and 302_4_2 can be controlled by other word lines (not shown) respectively. Figure 3

[0045] Figure 4 is a diagram illustrating a layout structure 400 of a memory array according to some embodiments. The layout structure 400 includes a plurality of storage cells 402_1_1 through 402_4_4, a plurality of cut layers 404_1 through 404_12, and a plurality of polysilicon lines 406_1 through 406_4. The storage cells 402_1_1 through 402_4_4 are respectively coupled to a plurality of fuses (e.g., 412). The fuses are respectively coupled to the drain (or source) of a corresponding transistor of the storage cells. The structure of each fuse is similar to that of the fuses 212_1_1 through 212_4_2, and thus a detailed description is omitted here for brevity.

[0046] In addition, the cut layers 404_1 through 404_4 are arranged to cut the polysilicon lines 406_1 through 406_4 during a manufacturing process such that the storage cells coupled to the conductive paths 408_1 form a first zigzag pattern. The cut layers 404_5 through 404_8 are arranged to cut the polysilicon lines 406_1 through 406_4 during the manufacturing process such that the storage cells coupled to the conductive paths 408_2 form a second zigzag pattern. The cut layers 404_9 through 404_12 are arranged to cut the polysilicon lines 406_1 through 406_4 during the manufacturing process such that the storage cells coupled to the conductive paths 408_3 form a third zigzag pattern. Specifically, the cut layers 404_1, 404_5, and 404_9 are disposed on the polysilicon line 406_1 and are respectively located on the upper sides of the conductive paths 404_1 through 404_3. The cut layers 404_2, 404_6, and 404_10 are disposed on the polysilicon line 406_3 and are respectively located on the upper sides of the conductive paths 404_1 through 404_3. The cut layers 404_3, 404_7, and 404_11 are disposed on the polysilicon line 406_2 and are respectively located on the lower sides of the conductive paths 404_1 through 404_3. The cut layers 404_4, 404_8, and 404_12 are disposed on the polysilicon line 406_4 and are respectively located on the lower sides of the conductive paths 404_1 through 404_3.​

[0047] Figure 5 is a diagram illustrating a memory array 500 according to some embodiments. The memory array 500 can be the physical circuit of the layout structure 400. The memory array 500 includes a plurality of memory cells 502_1_1 through 502_m_n. The parameters “m” and “n” are integers not less than 1. In this embodiment, the parameters “m” and “n” are 4. The memory cells 502_1_1 through 502_4_1 are arranged as a first row, the memory cells 502_1_2 through 502_4_2 are arranged as a second row, the memory cells 502_1_3 through 502_4_3 are arranged as a third row, and the memory cells 502_1_4 through 502_4_4 are arranged as a fourth row. The memory array 500 further includes a plurality of conductive paths 504_1 through 504_3. The conductive path 504_1 is horizontally disposed between the first row and the second row, the conductive path 504_2 is horizontally disposed between the second row and the third row, and the conductive path 504_3 is horizontally disposed between the third row and the fourth row.

[0048] After the manufacturing process of the layout structure 400, due to the cutting of the layers 404_1 through 404_4, the memory cells 502_2_1, 502_4_1, 502_1_2, and 502_3_2 coupled to the first word line (i.e., 504_1) form a first Z-shaped pattern (e.g., the dashed line in Figure 5 Due to the cutting of the layers 404_5 through 404_8, the memory cells 502_2_2, 502_4_2, 502_1_3, and 502_3_3 coupled to the second word line (i.e., 504_2) form a second Z-shaped pattern. Due to the cutting of the layers 404_9 through 404_12, the memory cells 502_2_3, 502_4_3, 502_1_4, and 502_3_4 coupled to the third word line (i.e., 504_3) form a third Z-shaped pattern.

[0049] According to some embodiments, in the top row (i.e., the first row), the memory cells 502_1_1 and 502_3_1 are not coupled to a word line, thus, the memory cells 502_1_1 and 502_3_1 can be dummy cells of the memory array 500. Similarly, in the bottom row (i.e., the fourth row), the memory cells 502_2_4 and 502_4_4 are not coupled to a word line, thus, the memory cells 502_2_4 and 502_4_4 can also be dummy cells of the memory array 500. According to some embodiments, the fuses of the dummy cells (i.e., 502_1_1, 502_3_1, 502_2_4, and 502_4_4) do not blow during programming. Thus, the links of the pads in the fuses connecting the dummy cells remain intact after programming.

[0050] According to some embodiments, the cut layers 404_1 to 404_12 can be arranged to cut the polysilicon lines 406_1, 406_2, 406_3, and 406_4 to form another pattern of storage cells, as shown in Figure 6 Figure 6 is a diagram illustrating a layout structure 600 of a memory array according to some embodiments. The layout structure 600 includes a plurality of storage cells 602_1_1 to 602_4_4. The storage cells 602_1_1 to 602_4_1 are arranged as a first row, the storage cells 602_1_2 to 602_4_2 are arranged as a second row, the storage cells 602_1_3 to 602_4_3 are arranged as a third row, and the storage cells 602_1_4 to 602_4_4 are arranged as a fourth row. The layout structure 600 further includes a plurality of conductive paths 608_1 to 608_3. The conductive path 608_1 is disposed horizontally between the first row and the second row, the conductive path 608_2 is disposed horizontally between the second row and the third row, and the conductive path 608_3 is disposed horizontally between the third row and the fourth row.

[0051] In this embodiment, the cut layers 604_1, 604_5, and 604_9 are disposed on the polysilicon line 606_2 and are located on the upper side of the conductive paths 608_1 to 608_3, respectively. The cut layers 604_2, 604_6, and 604_10 are disposed on the polysilicon line 606_3 and are located on the upper side of the conductive paths 608_1 to 608_3, respectively. The cut layers 604_3, 604_7, and 604_11 are disposed on the polysilicon line 606_1 and are located on the lower side of the conductive paths 608_1 to 608_3, respectively. The cut layers 604_4, 604_8, and 604_12 are disposed on the polysilicon line 606_4 and are located on the lower side of the conductive paths 608_1 to 608_3, respectively.

[0052] According to some embodiments, the storage cells 602_1_1, 602_2_2, 602_3_2, and 602_4_1 coupled to the first word line (i.e., 608_1) are arranged as a first U-shaped pattern (e.g., the dashed line in Figure 6 According to some embodiments, the storage cells 602_1_1, 602_2_2, 602_3_2, and 602_4_1 coupled to the first word line (i.e., 608_1) are arranged as a first U-shaped pattern (e.g., the dashed line in

[0053] In the above embodiments, each cut layer is arranged to cut the polysilicon line of one storage cell. However, this is not a limitation of the embodiments of the present disclosure. The cut layer can be arranged to cut the polysilicon line of more than one storage cell, as shown in Figure 7 ​as shown in FIG. 1. Figure 7 is a diagram illustrating a layout structure 700 of a memory array according to some embodiments. The layout structure 700 includes a plurality of memory cells 702_1_1 through 702_4_4. The memory cells 702_1_1 through 702_4_1 are arranged as a first row, the memory cells 702_1_2 through 702_4_2 are arranged as a second row, the memory cells 702_1_3 through 702_4_3 are arranged as a third row, and the memory cells 702_1_4 through 702_4_4 are arranged as a fourth row. The layout structure 700 of the memory array further includes a plurality of conductive paths 708_1 through 708_3. The conductive path 708_1 is disposed horizontally between the first row and the second row, the conductive path 708_2 is disposed horizontally between the second row and the third row, and the conductive path 708_3 is disposed horizontally between the third row and the fourth row.

[0054] In this embodiment, the cut layer 704_1 is disposed on the polysilicon lines 706_1 and 706_2 and on an upper side of the conductive path 708_1. The cut layer 704_2 is disposed on the polysilicon lines 706_3 and 706_4 and on a lower side of the conductive path 708_1. The cut layer 704_3 is disposed on the polysilicon lines 706_1, 706_2, and 706_3 and on an upper side of the conductive path 708_2. The cut layer 704_4 is disposed on the polysilicon line 706_4 and on a lower side of the conductive path 708_2. The cut layer 704_5 is disposed on the polysilicon lines 706_1, 706_2, 706_3, and 706_4 and on an upper side of the conductive path 708_3.

[0055] According to some embodiments, in a memory array, the cut layers 704_1 through 704_5 can be randomly selected and disposed in place for cutting the polysilicon lines to form a particular pattern of memory cells. Then, the control electrodes of the memory cells in the memory array can be distributed randomly, and a person can be prevented from obtaining a manufacturer's proprietary code or information embedded in the memory array by means of reverse engineering. It should be noted that the particular pattern is a pattern known to the manufacturer.

[0056] In Figure 7 embodiments, the cut layer is arranged to cut the polysilicon lines of more than one memory cell. However, this is not a limitation of embodiments of the present application. The cut layer can be arranged to cut a portion of the polysilicon lines of a memory cell, as shown in Figure 8 In Figure 8is a diagram illustrating a layout structure 800 of a memory array according to some embodiments. The layout structure 800 includes a plurality of memory cells 802_1_1 through 802_2_2. The memory cells 802_1_1 through 802_2_1 are arranged as a first row, and the memory cells 802_1_2 through 802_2_2 are arranged as a second row. The layout structure 800 of the memory array further includes a plurality of conductive paths 808_1 through 808_2. The conductive path 808_1 is disposed horizontally between the first row and the second row, and the conductive path 808_2 is disposed horizontally on the bottom of the second row.

[0057] In this embodiment, the cut layer 804_1 is disposed on the polysilicon lines 806_1 and 806_2 of the memory cell 802_1_1 and on the upper side of the conductive path 808_1. The cut layer 804_2 is disposed on the polysilicon lines 806_5 and 806_6 of the memory cell 802_2_1 and on the upper side of the conductive path 808_1. The cut layer 804_3 is disposed on the polysilicon lines 806_3 and 806_4 of the memory cell 802_1_1 and on the lower side of the conductive path 808_1. The cut layer 804_4 is disposed on the polysilicon lines 806_7 and 806_8 of the memory cell 802_2_1 and on the lower side of the conductive path 808_1.

[0058] The cut layer 804_5 is disposed on the polysilicon lines 806_1 and 806_2 of the memory cell 802_1_2 and on the upper side of the conductive path 808_2. The cut layer 804_6 is disposed on the polysilicon lines 806_5 and 806_6 of the memory cell 802_2_2 and on the upper side of the conductive path 808_2. The cut layer 804_7 is disposed on the polysilicon lines 806_3 and 806_4 of the memory cell 802_1_2 and on the lower side of the conductive path 808_2. The cut layer 804_8 is disposed on the polysilicon lines 806_7 and 806_8 of the memory cell 802_2_1 and on the lower side of the conductive path 808_2.

[0059] For example, after fabrication, the polysilicon lines 806_1 and 806_2 are disconnected from the conductive path 808_1, while the polysilicon lines 806_3 and 806_4 are connected to the conductive path 808_1.

[0060] In this embodiment, the cut layers are arranged to cut two polysilicon lines of a memory cell. However, this is not a limitation of embodiments of the present invention. The cut layers can be arranged to cut one, two, three, or four polysilicon lines of a memory cell. Furthermore, the cut layers 804_1 through 804_8 can be arranged to cut the polysilicon lines 806_1 through 806_8 at random to form a particular pattern of memory cells. It should be noted that the particular pattern is a pattern known to the fabricator.

[0061] According to some embodiments, Figure 6 the type of cut layer shown in FIG. 1, Figure 7 the type of cut layer shown in FIG. 1, and Figure 8 The type of cut layer shown in FIG. 1 can be selected and disposed on polysilicon lines in a memory array to form an irregular pattern of memory cells.

[0062] Briefly, in embodiments of the present invention, the memory cells of a row in a memory array are not coupled to the same side of a word line. For a word line in a memory array, portions of the memory cells can be disposed on an upper side of the word line, while other portions of the memory cells can be disposed on a lower side of the word line. In other words, the control electrodes of the memory cells in a memory array can be distributed irregularly. Thus, a person can be prevented from obtaining a manufacturer's proprietary code or information embedded in a memory array by reverse engineering, and the security of the memory array can be improved.

[0063] Figure 9 is a functional block diagram of an integrated circuit design and modeling system 900 according to embodiments. The integrated circuit design and modeling system 900 includes a first computer system 910, a second computer system 920, a network storage device 930, and a network 940 connecting the first computer system 910, the second computer system 920, and the network storage device 930. In some embodiments, one or more of the second computer system 920, the storage device 930, and the network 940 are omitted. In some embodiments, two or more of the first computer system 910, the second computer system 920, and / or the storage device 930 are combined into a single computer system.

[0064] The first computer system 910 includes a hardware processor 912 communicatively coupled with a non-transitory computer readable storage medium 914 encoded with (i.e., storing) a generated integrated layout 914a, a circuit design 914b, computer program code 914c (i.e., a set of executable instructions), and a standard cell library 914d having the layout pattern described herein. The processor 912 is electrically and communicatively coupled with the computer readable storage medium 914. The processor 912 is configured to execute the set of instructions 914c encoded in the computer readable storage medium 914 to cause the computer 910 to be usable as a placement and routing tool to generate a layout design based on the standard cell library 914d. The processor 912 is also configured to execute the set of instructions 914c encoded in the computer readable storage medium 914 to cause the computer 910 to perform operations 102-106 of the layout method 100.

[0065] In some embodiments, the standard cell library 914d is stored in a non-transitory storage medium other than the storage medium 914. In some embodiments, the standard cell library 914d is stored in a non-transitory storage medium in the network storage 930 or the second computer system 920. In this case, the standard cell library 914d can be accessed by the processor 912 over a network.

[0066] In some embodiments, the processor 912 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0067] In some embodiments, the computer readable storage medium 914 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer readable storage medium 914 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In some embodiments using optical discs, the computer readable storage medium 914 includes a compact disc - read-only memory (CD-ROM), a compact disc - read / write (CD-R / W), and / or a digital video disc (DVD).

[0068] In at least some embodiments, the computer system 910 includes an input / output interface 916 and a display unit 917 (or display). The input / output interface 916 is coupled to the processor 912 (or controller) and allows a circuit designer to manipulate the first computer system 910. In at least some embodiments, the display unit 917 displays the status of the execution of the placement and routing tool 914a in real-time and provides a graphical user interface (GUI). In at least some embodiments, the input / output interface 916 and the display unit 917 allow an operator to operate the computer system 910 in an interactive manner.

[0069] It should be noted that the term "metal" mentioned in the above embodiments is only an example conductive material, and this is not a limitation of the embodiments of the present application.

[0070] In some embodiments, an embodiment of the present invention provides a layout method. The layout method includes forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row includes a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite the second side of the word line.

[0071] In some embodiments, an embodiment of the present invention provides a layout structure of a memory array. The layout structure includes a first row and a second row, a word line, a plurality of control electrodes, a first cut layer, and a second cut layer. Each of the first row and the second row includes a plurality of storage cells. The word line is disposed between the first row and the second row. The plurality of control electrodes is disposed across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively. The first cut layer is located on a first side of the word line and disposed on a first control electrode of the plurality of control electrodes. The second cut layer is located on a second side of the word line and disposed on a second control electrode of the plurality of control electrodes. The first side of the word line is opposite the second side of the word line.

[0072] In some embodiments, an embodiment of the present invention provides a memory array. The memory array includes a first row and a second row, a word line, a first control electrode, and a second control electrode. Each of the first row and the second row includes a plurality of storage cells. The word line is disposed between the first row and the second row. The first control electrode is coupled to a first side of the word line and a first storage cell of the first row. The second control electrode is coupled to a second side of the word line and a second storage cell of the second row. The first side of the word line is opposite the second side of the word line.

[0073] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they can readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will realize that such equivalent constructions do not depart from the spirit and scope of the present invention and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

[0074] Symbol Explanation

[0075] 100 Layout Method

[0076] 102 Operation

[0077] 104 Operation

[0078] 106 Operation

[0079] 108 Operation

[0080] 110 Operation

[0081] 200 Layout Structure

[0082] 202_1_1 to 202_4_2 Storage Units

[0083] 204 First Spacer

[0084] 204_1 to 204_4 Cut Layers

[0085] 206 Second Spacer

[0086] 206_1 to 206_4 Poly Lines

[0087] 208 Links / Strips

[0088] 210 Conductive Paths

[0089] 212_1_1 to 212_4_2 Fuses

[0090] 300 Memory Array

[0091] 302_1_1 to 302_4_2 Storage Units

[0092] 306_1 to 306_8 Poly Lines

[0093] 400 Layout Structure

[0094] 402_1_1 to 402_4_4 Storage Units

[0095] 404_1 to 404_12 Cut Layers

[0096] 406_1 to 406_4 Poly Lines

[0097] 408_1 to 408_3 Conductive Paths

[0098] 500 Memory Array

[0099] 502_1_1 to 502_m_n Storage Units

[0100] 504_1 to 504_3 Conductive Paths

[0101] 600 layout structure

[0102] 602_1_1 to 602_4_4 storage cells

[0103] 604_1 to 604_12 cut layers

[0104] 606_1 to 606_4 polysilicon lines

[0105] 608_1 to 608_3 conductive paths

[0106] 700 layout structure

[0107] 702_1_1 to 702_4_4 storage cells

[0108] 704_1 to 704_5 cut layers

[0109] 706_1 to 706_4 polysilicon lines

[0110] 708_1 to 708_3 conductive paths

[0111] 800 layout structure

[0112] 802_1_1 to 802_2_2 storage cells

[0113] 804_1 to 804_8 cut layers

[0114] 806_1 to 806_8 polysilicon lines

[0115] 808_1 to 808_2 conductive paths

[0116] 900 integrated circuit design and modeling system

[0117] 910 first computer system

[0118] 912 processor

[0119] 914 computer readable storage medium

[0120] 914a generated integrated layout / place and route tool

[0121] 914b circuit design

[0122] 914c computer program code / instruction set

[0123] 914d standard cell library

[0124] 916 input / output interface

[0125] 917 display unit

[0126] 920 second computer system

[0127] 930 network storage device

[0128] 940 network

Claims

1. A layout method comprising: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes located on a first side of the word line such that the first portion of the first control electrode is separated from the word line; and disposing a second cut layer on a second portion of a second control electrode of the plurality of control electrodes located on a second side of the word line such that the second portion of the second control electrode is separated from the word line; wherein the first side of the word line is opposite the second side of the word line.

2. The layout method of claim 1, wherein the first cut layer is located between a first storage cell of the first row and the first side of the word line, the first control electrode is coupled to the first storage cell, the second cut layer is located between a second storage cell of the second row and the second side of the word line, and the second control electrode is coupled to the second storage cell.

3. The layout method of claim 2, wherein the first storage cell and the second storage cell are located on different columns of the memory array.

4. The layout method of claim 1, wherein the first control electrode comprises a plurality of first polysilicon lines, the second control electrode comprises a plurality of second polysilicon lines, the first cut layer is disposed on at least one polysilicon line of the plurality of first polysilicon lines, and the second cut layer is disposed on at least one polysilicon line of the plurality of second polysilicon lines.

5. The layout method of claim 4, wherein the first cut layer is disposed on all of the plurality of first polysilicon lines, and the second cut layer is disposed on all of the plurality of second polysilicon lines.

6. The layout method of claim 1, further comprising: disposing the first cut layer on the first control electrode and a third control electrode of the plurality of control electrodes located on the first side of the word line; wherein the first cut layer is located between first and second storage cells of the first row and the first side of the word line, the first control electrode is coupled to the first storage cell, and the third control electrode is coupled to the second storage cell.

7. The layout method of claim 6, further comprising: disposing the second cut layer on the second control electrode and a fourth control electrode of the plurality of control electrodes located on the second side of the word line; wherein the second cut layer is located between third and fourth storage cells of the second row and the second side of the word line, the second control electrode is coupled to the third storage cell, and the fourth control electrode is coupled to the fourth storage cell. ​ 8. A layout structure of a memory array, comprising: a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; a word line disposed between the first row and the second row; a plurality of control electrodes arranged across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; a first cut layer on a first side of the word line and disposed on a first control electrode of the plurality of control electrodes, the first cut layer configured to separate the first control electrode from the word line; and a second cut layer on a second side of the word line and disposed on a second control electrode of the plurality of control electrodes, the second cut layer configured to separate the second control electrode from the word line; wherein the first side of the word line is opposite the second side of the word line.

9. The layout structure of claim 8, wherein the first cut layer is between a first storage cell of the first row and the first side of the word line, the first control electrode is coupled to the first storage cell, the second cut layer is between a second storage cell of the second row and the second side of the word line, and the second control electrode is coupled to the second storage cell.

10. The layout structure of claim 9, wherein the first storage cell and the second storage cell are on different columns of the memory array.

11. The layout structure of claim 8, wherein the first control electrode comprises: a plurality of first polysilicon lines arranged to couple a first storage cell of the first row and a second storage cell of the second row; and the second control electrode comprises: a plurality of second polysilicon lines arranged to couple a third storage cell of the first row and a fourth storage cell of the second row; and wherein the first cut layer is disposed on at least one polysilicon line of the plurality of first polysilicon lines, and the second cut layer is disposed on at least one polysilicon line of the plurality of second polysilicon lines.

12. The layout structure of claim 11, wherein the first cut layer is disposed on all of the plurality of first polysilicon lines, and the second cut layer is disposed on all of the plurality of second polysilicon lines.

13. The layout structure of claim 8, wherein the first cut layer is disposed on the first control electrode and a third control electrode of the plurality of control electrodes on the first side of the word line, the first cut layer is between a first storage cell and a second storage cell of the first row and the first side of the word line, the first control electrode is coupled to the first storage cell, and the third control electrode is coupled to the second storage cell. ​ ​ ​ 14. The layout structure of claim 13, wherein the second cut layer is disposed on the second control electrode and a fourth control electrode of the plurality of control electrodes located on the second side of the word line, the second cut layer is located between a third storage cell and a fourth storage cell of the second row and the second side of the word line, the second control electrode is coupled to the third storage cell, and the fourth control electrode is coupled to the fourth storage cell.

15. A memory array comprising: a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; a word line disposed between the first row and the second row; a first control electrode coupled to a first side of the word line and a first storage cell of the first row, wherein the first control electrode comprises: a first portion of a polysilicon line that is disconnected from the word line; and a second control electrode coupled to a second side of the word line and a second storage cell of the second row; wherein the first side of the word line is opposite the second side of the word line.

16. The memory array of claim 15, wherein the first storage cell and the second storage cell are located on different columns of the memory array.

17. The memory array of claim 15, wherein the first control electrode comprises: at least one first polysilicon line arranged to couple the first storage cell of the first row; and the second control electrode comprises: at least one second polysilicon line arranged to couple the second storage cell of the second row.

18. The memory array of claim 15, wherein the first control electrode comprises: a second portion of a polysilicon line arranged to couple the first storage cell of the first row.

19. The memory array of claim 15, further comprising: a third control electrode coupled to the first side of the word line and a third storage cell of the first row; a fourth control electrode coupled to the second side of the word line and a fourth storage cell of the second row; wherein the first storage cell, the second storage cell, the third storage cell, and the fourth storage cell are located on different columns of the memory array.

20. The memory array of claim 19, wherein the first storage cell, the second storage cell, the third storage cell, and the fourth storage cell form a zigzag pattern with respect to the word line.

21. A layout method comprising: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes such that the first portion of the first control electrode is separated from the word line.

22. The layout method of claim 21, wherein the plurality of storage cells comprise a plurality of fuses. ​ 23. The layout method of claim 22, wherein each of the plurality of fuses comprises a first pad, a second pad, and a link arranged to connect the first pad and the second pad.

24. The layout method of claim 23, wherein one of the first pad and the second pad is coupled to a source / drain of a transistor of the memory cell, and the other of the first pad and the second pad is coupled to a sense circuit.

25. The layout method of claim 23, wherein the fuse is configured such that a resistance of the fuse can be changed by applying a current through the link.

26. The layout method of claim 21, wherein the first cut layer is configured to function as a mask to cut the first portion of a first control electrode.

27. The layout method of claim 21, wherein a location of the first cut layer is randomly perturbed by a processor.

28. The layout method of claim 21, wherein the first cut layer is located between the word line and a memory cell connected to a corresponding control electrode.

29. The layout method of claim 21, wherein the first cut layer is additionally disposed on a second portion of a second control electrode of the plurality of control electrodes.

30. The layout method of claim 29, wherein the first control electrode and the second control electrode are contiguous.

31. A layout structure of a memory array, comprising: a first row comprising a plurality of memory cells; a word line; a plurality of control electrodes to connect the plurality of memory cells of the first row to the word line; and a first cut layer disposed on a first control electrode of the plurality of control electrodes such that the first control electrode is separated from the word line.

32. The layout structure of claim 31, wherein the plurality of memory cells comprises a plurality of fuses.

33. The layout structure of claim 32, wherein each of the plurality of fuses comprises a first pad, a second pad, and a link arranged to connect the first pad and the second pad, wherein the fuse is configured such that a resistance of the fuse can be changed by applying a current through the link.

34. The layout structure of claim 31, wherein the first cut layer is configured to function as a mask to cut a first portion of a first control electrode.

35. The layout structure of claim 31, wherein a location of the first cut layer is randomly perturbed by a processor.

36. The layout structure of claim 31, wherein the first cut layer is located between the word line and a memory cell connected to a corresponding control electrode.

37. The layout structure of claim 31, wherein the first cut layer is additionally disposed on a second portion of a second control electrode of the plurality of control electrodes.

38. The layout structure of claim 37, wherein the first control electrode and the second control electrode are contiguous.

39. A memory array, comprising: a first row and a second row comprising a plurality of memory cells; a word line; and ​ ​ a first control electrode coupled to the word line and a first storage cell of the first row, wherein the first control electrode comprises a plurality of first polysilicon lines, wherein a first portion of the plurality of first polysilicon lines is disconnected from the word line.

40. The memory array of claim 39, further comprising a second control electrode comprising a plurality of second polysilicon lines and coupled to the word line and a second storage cell of the first row, wherein a second portion of the plurality of second polysilicon lines is disconnected from the word line.

41. A layout method comprising: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells, wherein at least one of the plurality of storage cells comprises a fuse; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row, respectively; disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes located on a first side of the word line such that the first portion of the first control electrode is separated from the word line; and disposing a second cut layer on a second portion of a second control electrode of the plurality of control electrodes located on a second side of the word line such that the second portion of the second control electrode is separated from the word line; wherein the first side of the word line is opposite the second side of the word line.

42. The layout method of claim 41, wherein each of the plurality of fuses comprises a first pad, a second pad, and a link arranged to connect the first pad and the second pad.

43. The layout method of claim 42, wherein one of the first pad and the second pad is coupled to a source / drain of a transistor of the storage cell, and the other of the first pad and the second pad is coupled to a sense circuit.

44. The layout method of claim 42, wherein the fuse is configured such that a resistance of the fuse can be changed by applying a current through the link.

45. The layout method of claim 41, wherein at least one of the storage cells comprises a field effect transistor.

46. The layout method of claim 45, wherein at least one of the control electrodes is disposed on a diffusion region of the field effect transistor.

47. The layout method of claim 45, wherein at least one of the control electrodes is a gate of a transistor of the storage cell.

48. The layout method of claim 41, wherein a location of one of the first cut layer and the second cut layer is scrambled by a processor.

49. The layout method of claim 48, wherein the location of the first cut layer and the second cut layer is randomly scrambled by the processor.

50. The layout method of claim 41, wherein the first cut layer and the second cut layer are arranged to randomly cut the control electrodes to form a particular pattern of the memory cells.

51. The layout method of claim 50, wherein the particular pattern is a pattern known to a manufacturer.

52. A layout structure of a memory array, comprising: a first row and a second row, wherein each of the first row and the second row comprises a plurality of memory cells, wherein at least one of the plurality of memory cells comprises a fuse; a word line disposed between the first row and the second row; a plurality of control electrodes configured to cross the word line for connecting the plurality of memory cells of the first row and the plurality of memory cells of the second row, respectively; a first cut layer on a first side of the word line and disposed on a first control electrode of the plurality of control electrodes, the first cut layer configured to separate the first control electrode from the word line; and a second cut layer on a second side of the word line and disposed on a second control electrode of the plurality of control electrodes, the second cut layer configured to separate the second control electrode from the word line; wherein the first side of the word line is opposite the second side of the word line.

53. The layout structure of claim 52, wherein the first cut layer is between a first memory cell of the first row and the first side of the word line, the first control electrode is coupled to the first memory cell, the second cut layer is between a second memory cell of the second row and the second side of the word line, and the second control electrode is coupled to the second memory cell.

54. The layout structure of claim 53, wherein the first memory cell and the second memory cell are on different columns of the memory array.

55. The layout structure of claim 52, wherein the first control electrode comprises: a plurality of first polysilicon lines arranged to couple a first memory cell of the first row and a second memory cell of the second row; and the second control electrode comprises: a plurality of second polysilicon lines arranged to couple a third memory cell of the first row and a fourth memory cell of the second row; and wherein the first cut layer is disposed on at least one polysilicon line of the plurality of first polysilicon lines and the second cut layer is disposed on at least one polysilicon line of the plurality of second polysilicon lines.

56. The layout structure of claim 55, wherein the first cut layer is disposed on all of the plurality of first polysilicon lines and the second cut layer is disposed on all of the plurality of second polysilicon lines.

57. The layout structure of claim 52, wherein locations of the first cut layer and the second cut layer are randomly disturbed by a processor.

58. A memory array, comprising: a first row and a second row, wherein each of the first row and the second row comprises a plurality of memory cells, wherein at least one of the plurality of memory cells comprises a fuse; a word line disposed between the first row and the second row; a first control electrode coupled to a first side of the word line and a first storage cell of the first row; and a second control electrode coupled to a second side of the word line and a second storage cell of the second row; wherein the first side of the word line is opposite the second side of the word line.

59. The memory array of claim 58, further comprising: a third control electrode coupled to the first side of the word line and a third storage cell of the first row; a fourth control electrode coupled to the second side of the word line and a fourth storage cell of the second row; wherein the first, second, third, and fourth storage cells are on different columns of the memory array.

60. The memory array of claim 59, wherein the first, second, third, and fourth storage cells form a zig-zag pattern with respect to the word line.

Images