Display panel

Abstract

A display panel is provided. The display panel includes: a substrate including a display area and a transmissive area disposed in the display area, the display area being surrounded by a first side extending in a first direction, a second side extending in a second direction intersecting the first direction, a third side facing the first side, and a fourth side facing the second side; pixels disposed in the display area; a first black line extending from the transmissive area to the first side in a third direction different from the second direction and having dummy pixels that do not emit light disposed thereon; and a second black line extending from the transmissive area to the second side in a fourth direction different from the first direction and having dummy pixels that do not emit light disposed thereon, wherein the transmissive area is disposed closer to the first side and the second side than to the third side and the fourth side.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0082828, filed on Jul. 9, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments relate to a display panel and a display device including the display panel. Background Art

[0003] Recently, display devices have been diversely used. In addition, as display devices become thinner and lighter, the range of use of display devices is expanding.

[0004] Since display devices are used in various ways, there are various methods of designing the shape of display devices. In addition, functions that can be associated or linked with display devices are increasing. Summary of the Invention

[0005] One or more embodiments include a method of increasing functions that can be associated or linked with a display device, a display panel having a transmissive area, and a display device including the display panel, in which a camera, a sensor, etc. can be disposed inside the display area in the transmissive area. However, these problems are examples and do not limit the scope of the present disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed proposed embodiments.

[0007] According to one or more embodiments, a display panel includes: a substrate including a display area and a transmissive area disposed in the display area, the display area being surrounded by a first side extending in a first direction, a second side extending in a second direction intersecting the first direction, a third side facing the first side, and a fourth side facing the second side; pixels disposed in the display area; a first black line extending from the transmissive area to the first side in a third direction different from the second direction and having dummy pixels that do not emit light disposed thereon; and a second black line extending from the transmissive area to the second side in a fourth direction different from the first direction and having dummy pixels that do not emit light disposed thereon, wherein the transmissive area is disposed closer to the first side than to the third side and closer to the second side than to the fourth side.

[0008] In an embodiment, the third direction may be opposite to the fourth direction.

[0009] In an embodiment, the width of the first black line and the width of the second black line may be in a range of about 10 μm to about 70 μm.

[0010] In an embodiment, the display panel may further include: a third black line extending from the transmissive region to a corner where the first side and the second side intersect in a certain direction.

[0011] In an embodiment, the display panel may further include a counter electrode corresponding to the pixel, wherein the counter electrode may have a first opening portion corresponding to the transmissive region and a second opening portion corresponding to the dummy pixel.

[0012] In an embodiment, wirings connected to the pixels may be disposed in the display region, and some of the wirings may be connected to some of the dummy pixels.

[0013] In an embodiment, the display panel may further include: a fourth black line extending from the transmissive region to the first side in a second direction and having non-emitting dummy pixels disposed thereon.

[0014] In an embodiment, the display panel may further include: a fifth black line extending from the transmissive region to the second side in a first direction and having non-emitting dummy pixels disposed thereon.

[0015] In an embodiment, the display panel may further include: a first additional black line extending from the transmissive region to the first side in a direction parallel to the first black line, wherein at least one pixel may be disposed between the first black line and the first additional black line.

[0016] In an embodiment, black lines extending from the transmissive region to the third side and the fourth side in certain directions may not be disposed.

[0017] According to one or more embodiments, a display panel includes: a substrate including a transmissive region, a display region at least partially surrounding the transmissive region, and a non-display region outside the display region; pixels disposed in the display region; a plurality of black lines extending from one side of the transmissive region to the non-display region and disposed in the display region; and dummy pixels that do not emit light and correspond to the plurality of black lines, wherein at least one pixel is disposed between adjacent black lines among the plurality of black lines, and wherein the plurality of pixels do not overlap with the plurality of black lines.

[0018] In an embodiment, the display region may include: a first side extending in a first direction; a second side extending in a second direction intersecting the first direction; a third side facing the first side; and a fourth side facing the second side, and the transmissive region may be disposed closer to the first side than to the third side and closer to the second side than to the fourth side.

[0019] In an embodiment, the display panel may further include: a third black line extending from the transmissive region to a corner where the first side and the second side intersect in a certain direction.

[0020] In an embodiment, the display panel may further include: a fourth black line extending from the transmissive region to the first side in the second direction and having dummy pixels disposed thereon that do not emit light; and a fifth black line extending from the transmissive region to the second side in the first direction and having dummy pixels disposed thereon that do not emit light.

[0021] In an embodiment, the width of each of the plurality of black lines may be in the range of about 10 μm to about 70 μm.

[0022] In an embodiment, the display panel may further include a counter electrode corresponding to the pixel, wherein the counter electrode may have a first opening portion corresponding to the transmissive region and a second opening portion corresponding to the dummy pixel.

[0023] In an embodiment, wirings connected to the pixels may be disposed in the display region, and some of the wirings may be connected to some of the dummy pixels.

[0024] In an embodiment, the display panel may further include: a scan line extending from the display region in the first direction and surrounding the edge of the transmissive region; and a data line extending from the display region in a second direction intersecting the first direction and surrounding the edge of the transmissive region.

[0025] In an embodiment, the scan line and the data line may be connected to the dummy pixel.

[0026] In an embodiment, the scan line and the data line may include curved portions around the transmissive region. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0028] Figure 2A 、 Figure 2B and Figure 2C are schematic cross-sectional views of a display device according to one or more embodiments;

[0029] Figure 3A 、 Figure 3B and Figure 3C are cross-sectional views of a display device according to other embodiments;

[0030] Figure 4 is a schematic top plan view of a display panel according to an embodiment;

[0031] Figure 5A and Figure 5B are equivalent circuit diagrams of pixels in a display panel according to some embodiments;

[0032] Figure 6 illustrates the relationship between the black lines disposed around the transmissive region and the pixels according to an embodiment;

[0033] Figure 7 illustrates an example of a mask for forming a display panel according to an embodiment;

[0034] Figure 8 is a schematic diagram of a deposition operation for forming a counter electrode of a display panel according to an embodiment;

[0035] Figure 9 is along Figure 6 schematic cross-sectional views taken along line I-I' and line II-II' in;

[0036] Figure 10 is a top plan view of a part of a display panel according to an embodiment; and

[0037] Figure 11 is a top plan view of a part of a display panel according to an embodiment. Detailed Description

[0038] Embodiments will now be described in detail with reference to the embodiments, examples of which are illustrated in the accompanying drawings, where like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only to explain aspects of the present description by referring to the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." when following a list of elements modify the entire list of elements and not a single element in the list.

[0039] The present disclosure will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. Like reference numerals in the drawings denote like elements and thus their description will be omitted.

[0040] Although terms such as "first", "second", etc. may be used to describe various elements, such elements should not be limited to the above terms.

[0041] Unless otherwise clearly different in context, expressions using the singular form include the plural form.

[0042] In this specification, it will be understood that terms such as "comprising", "having", and "including" are intended to indicate the presence of features or elements disclosed in the specification and are not intended to preclude the possibility that one or more other features or elements may exist or may be added.

[0043] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, the layer, region, or component can be formed directly or indirectly on the other layer, region, or component. That is, for example, there can be intermediate layers, regions, or components.

[0044] For ease of explanation, the dimensions of components in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0045] When a certain embodiment can be implemented differently, the specific process order can be performed in an order different from that described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0046] It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, the layer, region, or component can be directly or indirectly connected to the other layer, region, or component. That is, for example, there can be intermediate layers, regions, or components. For example, it will be understood that when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, the layer, region, or component can be directly or indirectly electrically connected to the other layer, region, or component. That is, for example, there can be intermediate layers, regions, or components.

[0047] Figure 1 is a schematic perspective view of a display device 1 according to an embodiment.

[0048] Referring to Figure 1 , the display device 1 includes a light-emitting display area DA and a non-light-emitting non-display area NDA. The display device 1 can provide an image by using light emitted from a plurality of pixels arranged in the display area DA.

[0049] The display device 1 includes a transmissive area TA. The transmissive area TA can be at least partially surrounded by the display area DA. In an embodiment, Figure 1 shows the transmissive area TA positioned at the edge of the display area DA and surrounded by the display area DA.

[0050] The display area DA can include an area surrounded by a first side SSl extending in a first direction x, a second side SS2 extending in a second direction y intersecting the first direction x, a third side SS3 facing the first side SSl, and a fourth side SS4 facing the second side SS2.

[0051] In this case, as shown in Figure 1 , the transmissive area TA can be arranged closer to the first side SSl than to the third side SS3, and can be arranged closer to the second side SS2 than to the fourth side SS4. However, the arrangement of the transmissive area TA is not limited. Alternatively, compared withFigure 1 Differently, the transmissive region TA may be arranged closer to the third side SS3 than to the first side SS1, and may be arranged closer to the fourth side SS4 than to the second side SS2. The transmissive region TA may be arranged to be biased towards one side in the display region DA.

[0052] The transmissive region TA corresponds to a region through which light and / or sound output from the electronic component to the outside or propagating from the outside towards the electronic component can be transmitted. In an embodiment, when light is transmitted through the transmissive region TA, the light transmittance may be about 50% or greater, more preferably 70% or greater, 75% or greater, 80% or greater, 85% or greater, or 90% or greater.

[0053] The non-display region NDA surrounds the display region DA. A part of the non-display region NDA is located between the display region DA and the transmissive region TA. Hereinafter, for the sake of convenience of description, the region of the non-display region NDA surrounding the transmissive region TA is referred to as the first non-display region NDA1, and the remaining region is referred to as the second non-display region NDA2.

[0054] The first non-display region NDA1 surrounds the transmissive region TA, and a part of the first non-display region NDA1 is located between the display region DA and the transmissive region TA. The display region DA completely surrounds the first non-display region NDA1. In another embodiment, the display region DA partially surrounds the first non-display region NDA1.

[0055] The second non-display region NDA2 may extend along the edge of the display device 1, and the first non-display region NDA1 may not be connected to the second non-display region NDA2. In other words, the first non-display region NDA1 may completely surround the transmissive region TA, the display region DA may completely surround the first non-display region NDA1, and the second non-display region NDA2 may completely surround the display region DA and the first non-display region NDA1.

[0056] Hereinafter, although the organic light-emitting display device is described as an example of the display device 1 according to the embodiment, the display device of the present disclosure is not limited thereto. In another embodiment, various types of display devices such as an inorganic EL display device (inorganic light-emitting display device), a quantum dot light-emitting display device, a liquid crystal display device, etc. may be used.

[0057] Although Figure 1 it is shown that the transmissive region TA is arranged on one side (upper left side) of the rectangular display region DA, the present disclosure is not limited thereto. The display region DA may include a circle, an ellipse, or a polygon (such as a triangle or a pentagon), and the size, shape, number, and position of the transmissive region TA may be variously changed.

[0058] Figure 2A , Figure 2B and Figure 2C are schematic cross-sectional views of a display device 1 according to one or more embodiments taken along line A-A' in Figure 1 .

[0059] Referring to Figure 2A , the display device 1 may include a display panel 10 and a component 20 corresponding to a transmissive region TA, and the display panel 10 includes display elements.

[0060] The display panel 10 may include: a substrate 100; a packaging substrate 300, as a packaging member and facing the substrate 100; and a display element layer 200 disposed between the substrate 100 and the packaging substrate 300, and a sealing material 350 (i.e., a sealant) covering the side surfaces of the display element layer 200 may be disposed between the substrate 100 and the packaging substrate 300. Although Figure 2A the sealing material 350 is shown disposed on both sides of the transmissive region TA, the transmissive region TA may be understood to be completely surrounded by the sealing material 350 when viewed from a direction perpendicular to the main surface of the substrate 100.

[0061] The substrate 100 may include glass or a polymer resin. For example, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0062] The substrate 100 including a polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including an inorganic layer (not shown) and a layer including the above polymer resin. The packaging substrate 300 may include glass or the above polymer resin.

[0063] The display element layer 200 may include: a circuit layer including a thin film transistor TFT; an organic light emitting diode OLED, as a display element and connected to the thin film transistor TFT; and an insulating layer IL located between the thin film transistor TFT and the organic light emitting diode OLED. The thin film transistor TFT and the organic light emitting diode OLED connected to the thin film transistor TFT may be disposed in a display region DA, and some wirings WL of the display element layer 200 may be located in a first non-display region NDA1. The wiring WL may supply a specific signal or voltage to pixels spaced apart from each other by the transmissive region TA between the pixels. Although Figure 2A the wiring WL is shown not overlapping with the sealing material 350 in the first non-display region NDA1, in another embodiment, a part of the sealing material 350 may also be disposed on the wiring WL.

[0064] AsFigure 2A As shown, the display panel 10 may include a through-hole 10H corresponding to the transmissive area TA. For example, the substrate 100 and the encapsulation substrate 300 may respectively include a substrate through-hole 100H and an encapsulation through-hole 300H both corresponding to the transmissive area TA. The display element layer 200 may include a through-hole corresponding to the transmissive area TA.

[0065] Although not shown in Figure 2A , components such as an input sensing member for sensing a touch input, an antireflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may be further disposed above or around the display panel 10.

[0066] The component 20 may be positioned in the transmissive area TA. The component 20 may include electronic components using light or sound. For example, the electronic components may include sensors that receive and use light (such as infrared sensors), cameras that capture images by receiving light, sensors that output and sense light or sound to measure distances or identify fingerprints, etc., small lights that output light, speakers that output sound, etc. The electronic components using light may use various wavelengths of light such as visible light, infrared light, ultraviolet light, etc. As Figure 2A shown, when the display panel 10 includes a through-hole 10H corresponding to the transmissive area TA, the light or sound output or received from the electronic components can be utilized more effectively.

[0067] Different from the display panel 10 including the through-hole 10H corresponding to the transmissive area TA in Figure 2A , some components of the display panel 10 may not include through-holes. For example, as Figure 2B shown, although the encapsulation substrate 300 includes an encapsulation through-hole 300H corresponding to the transmissive area TA, the substrate 100 may not include a through-hole. Optionally, as Figure 2C shown, both the substrate 100 and the encapsulation substrate 300 may not include through-holes corresponding to the transmissive area TA. As Figure 2B and Figure 2C shown, even when the substrate 100 does not include the substrate through-hole 100H, a portion of the display element layer 200 corresponding to the transmissive area TA may be removed to ensure the light transmittance for the electronic components. When the display device 1 includes the display panel 10 as Figure 2B and Figure 2C shown, the electronic components using light may be suitable as the electronic components.

[0068] As Figure 2A , Figure 2B and Figure 2C shown, the component 20 may be located outside the through-hole 10H. However, the position of the component 20 is not limited. For example, Figure 2A , Figure 2B andFigure 2C The component 20 shown in FIG. 1 may be located inside the through hole 10H to overlap with a side surface of the display panel 10 defining the through hole 10H.

[0069] The component 20 may be another component other than the above-mentioned electronic components. In an embodiment, when the display panel 10 is used as a smart watch or an instrument panel for a vehicle, the component 20 may be a component including a watch hand or a pointer indicating specific information (e.g., the speed of the vehicle, etc.). Optionally, the component 20 may include a component such as an accessory that increases the aesthetics of the display panel 10.

[0070] Figure 3A , Figure 3B and Figure 3C It is along Figure 1 A cross-sectional view of a display device 1 according to another embodiment taken along line AA′ in FIG.

[0071] Reference Figure 3A , the display device 1 can be compared with the reference Figure 2A The display device 1 described in the embodiment similarly includes a display panel 10 and a component 20. Figure 3A Although not shown in the figure, the display device 1 may further include an input sensing member, an anti-reflection member, a window, etc., which are arranged above or around the display panel 10 to sense a touch input.

[0072] With reference to above Figure 2A Unlike the display panel 10 described above including the encapsulation substrate 300 and the sealing material 350 as the encapsulation member, the display panel 10 according to the present embodiment may include a thin film encapsulation layer 300' as the encapsulation member. In this case, the flexibility of the display panel 10 can be further improved. Figure 3A The display panel 10 and Figure 2A The difference between the display panels 10 in FIG.

[0073] The thin film encapsulation layer 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3A A first inorganic encapsulating layer 310 , a second inorganic encapsulating layer 330 , and an organic encapsulating layer 320 located between the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 are shown.

[0074] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include silicon oxide (SiO 2 ), silicon nitride (SiN x) at least one inorganic insulating material among silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The organic encapsulation layer 320 may include a polymeric material. The polymeric material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc.

[0075] The display panel 10 may include a through hole 10H corresponding to the transmissive region TA. For example, the substrate 100 and the thin film encapsulation layer 300' may respectively include a substrate through hole 100H and an encapsulation through hole 300'H that both correspond to the transmissive region TA. The first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330, and the organic encapsulation layer 320 may include holes corresponding to the transmissive region TA. The size of the holes in the organic encapsulation layer 320 may be larger than the size of the holes in the first inorganic encapsulation layer 310 and the size of the holes in the second inorganic encapsulation layer 330. Accordingly, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other around the transmissive region TA.

[0076] Unlike Figure 3A the display panel 10 including the through hole 10H corresponding to the transmissive region TA in Figure 3B as shown in Figure 3C the display panel 10 may not include a through hole. As Figure 3B and Figure 3C shown in

[0077] When Figure 3C the thin film encapsulation layer 300' does not include a through hole as shown in Figure 3A each of at least one inorganic encapsulation layer and at least one organic encapsulation layer may cover the substrate 100 in the transmissive region TA. In this case, a portion of the display element layer 200 corresponding to the transmissive region TA between the substrate 100 and the thin film encapsulation layer 300' may be removed. Although

[0078] As Figure 3A shown in Figure 3B and Figure 3CAs shown, the component 20 may be located outside the through hole 10H. However, the position of the component 20 is not limited. The component 20 may be positioned inside the through hole 10H. For example, it may be positioned inside the substrate through hole 100H of the substrate 100 and the through hole 200H of the display element layer 200 as shown in Figure 3A to overlap with the side surface of the through hole 10H defined by the display panel 10, or may be positioned inside the through hole 200H of the display element layer 200 as shown in Figure 3B .

[0079] Although Figure 2A 、 Figure 2B and Figure 2C show that the display panel 10 includes the encapsulation substrate 300 as an encapsulation member, and Figure 3A 、 Figure 3B and Figure 3C show that the display panel 10 includes the thin film encapsulation layer 300' as an encapsulation member, the present disclosure is not limited thereto. For example, the display panel 10 may include any one of the encapsulation substrates 300 as shown in Figure 2A 、 Figure 2B and Figure 2C and any one of the thin film encapsulation layers 300' as shown in Figure 3A 、 Figure 3B and Figure 3C .

[0080] Figure 4 is a schematic top plan view of the display panel 10 according to an embodiment.

[0081] Referring to Figure 4 , the display panel 10 includes a plurality of pixels P arranged in the display area DA. Each of the pixels P may include a display element such as an organic light emitting diode. Each pixel P may emit red, green, blue, or white light through the organic light emitting diode. As described above, the pixel P in the present disclosure may be a pixel that emits any one of red, green, blue, and white light. The display area DA may be covered by the encapsulation members described above with reference to Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3A 、 Figure 3B and Figure 3C to protect against external air, moisture, etc.

[0082] The transmissive area TA may be arranged at the edge of the display area DA and may be surrounded by the display area DA. However, the position of the transmissive area TA is not limited. For example, as compared with Figure 4Differently, the transmissive area TA may be located at the upper left corner, lower right corner, or lower left corner of the display area DA. The transmissive area TA may be arranged in the display area DA adjacent to the first side SS1 and the second side SS2 of the display area DA. Accordingly, a plurality of pixels P are arranged around the transmissive area TA. The plurality of pixels P may be arranged to surround at least a part of the transmissive area TA, and a first non-display area NDA1 where the plurality of pixels P are not arranged is located between the transmissive area TA and the display area DA. Wiring configured to apply a specific signal or power to the pixels P spaced apart from each other around the transmissive area TA may be provided in the first non-display area NDA1. Additionally, some of the wiring may be interrupted by the transmissive area TA.

[0083] Each pixel P may be electrically connected to an external circuit arranged in a non-display area NDA (e.g., the second non-display area NDA2). The first scan driving circuit unit 110, the second scan driving circuit unit 120, the terminal 140, the data driving circuit 150, the first power supply line 160, and the second power supply line 170 are arranged in the second non-display area NDA2.

[0084] The first scan driving circuit unit 110 may provide a scan signal to each pixel P through a scan line SL. The first scan driving circuit unit 110 may provide an emission control signal to each pixel P through an emission control line EL. The second scan driving circuit unit 120 may be arranged in parallel with the first scan driving circuit unit 110 and have the display area DA located between the second scan driving circuit unit 120 and the first scan driving circuit unit 110. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit unit 110, and the remaining pixels P may be connected to the second scan driving circuit unit 120.

[0085] The terminal 140 may be arranged on one side of the substrate 100. The terminal 140 may be exposed by not being covered with an insulating layer and may be electrically connected to a printed circuit board PCB. A printed circuit board terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits signals or power of a controller (not shown) to the display panel 10. Control signals generated by the controller may be respectively transmitted to the first scan driving circuit unit 110 and the second scan driving circuit unit 120 through the printed circuit board PCB. The controller may provide a driving voltage and a common voltage (ELVDD and ELVSS described below in Figure 5A and Figure 5B to the first power supply line 160 and the second power supply line 170 through a first connection line 161 and a second connection line 171, respectively).

[0086] The driving voltage ELVDD can be provided to each pixel P through a driving voltage line PL connected to the first power supply line 160, and a common voltage ELVSS can be provided to a counter electrode of each pixel P connected to the second power supply line 170. The second power supply line 170 can at least partially surround the display area DA in a ring shape with one side open.

[0087] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 can be provided to each pixel P through a connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Although Figure 4 it is shown that the data driving circuit 150 is arranged in the printed circuit board PCB, in another embodiment, the data driving circuit 150 can be arranged above the substrate 100. For example, the data driving circuit 150 can be arranged between the terminal 140 and the first power supply line 160.

[0088] The first power supply line 160 can be connected to a first connection line 161 to receive the driving voltage ELVDD from a controller connected to the terminal 140. The first power supply line 160 can be arranged to correspond to the pixels P of all columns arranged in the first direction, and can transmit the driving voltage ELVDD to the pixels P of each column.

[0089] Figure 5A and Figure 5B are equivalent circuit diagrams of the pixel P in the display panel 10 according to some embodiments.

[0090] Referring to Figure 5A , each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0091] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm to the driving thin film transistor T1 through the data line DL according to the scan signal Sn via the scan line SL.

[0092] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to the difference between the voltage received from the switching thin film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied through the driving voltage line PL.

[0093] The driving thin film transistor T1 is connected to a driving voltage line PL and a storage capacitor Cst, and controls a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a specific brightness according to the driving current.

[0094] Although Figure 5A it is shown that the pixel circuit PC includes two thin film transistors, the present disclosure is not limited thereto. As Figure 5B shown, the pixel circuit PC may include more than two thin film transistors.

[0095] Referring to Figure 5B , the pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor and a plurality of thin film transistors. The storage capacitor and the plurality of thin film transistors may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0096] Although Figure 5B it is shown that each pixel P is connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL, the present disclosure is not limited thereto. In another embodiment, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, the driving voltage line PL, etc. may be shared by adjacent pixels P.

[0097] The plurality of thin film transistors may include a driving thin film transistor (TFT) T1, a switching TFT T2, a compensating TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

[0098] The signal lines include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting a previous scan signal Sn-1 to the first initialization TFT T4 and the second initialization TFT T7, an emission control line EL for transmitting an emission control signal En to the operation control TFT T5 and the emission control TFT T6, and a data line DL intersecting with the scan line SL and transmitting a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initialization voltage line VL transmits an initialization voltage Vint to initialize the pixel electrodes of the driving TFT T1 and the organic light emitting diode OLED.

[0099] The driving gate electrode G1 of the driving TFT Tl is connected to the first storage capacitor plate CE1 of the storage capacitor Cst. The driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line PL via the operation control TFT T5. The driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2, and supplies the driving current I OLED to the organic light emitting diode OLED.

[0100] The switching gate electrode G2 of the switching TFT T2 is connected to the scan line SL. The switching source electrode S2 of the switching TFT T2 is connected to the data line DL. The switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1, and is connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 is turned on according to the scan signal Sn received through the scan line SL, and performs a switching operation of transmitting the data signal Dm transmitted to the data line DL to the driving source electrode S1 of the driving TFT T1.

[0101] The compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1, and is connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. The compensation drain electrode D3 of the compensation TFT T3 is connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on according to the scan signal Sn received through the scan line SL, and electrically connects the driving gate electrode G1 of the driving TFT T1 to the driving drain electrode D1 of the driving TFT T1, so that the driving TFT T1 is connected in the form of a diode.

[0102] The first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL. The first initialization drain electrode D4 of the first initialization TFT T4 is connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the drive gate electrode G1 of the drive TFT T1. The first initialization TFT T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and transmits the initialization voltage Vint to the drive gate electrode G1 of the drive TFT T1 to perform an initialization operation for initializing the voltage of the drive gate electrode G1 of the drive TFT T1.

[0103] The operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control TFT T5 is connected to the drive voltage line PL. The operation control drain electrode D5 of the operation control TFT T5 is connected to the drive source electrode S1 of the drive TFT T1 and the switch drain electrode D2 of the switch TFT T2.

[0104] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control TFT T6 is connected to the drive drain electrode D1 of the drive TFT T1 and the compensation source electrode S3 of the compensation TFT T3. The emission control drain electrode D6 of the emission control TFT T6 is connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0105] The operation control TFT T5 and the emission control TFT T6 are turned on simultaneously according to the emission control signal En received through the emission control line EL. Then, the drive voltage ELVDD is transmitted to the organic light emitting diode OLED to allow the drive current I OLED to flow through the organic light emitting diode OLED.

[0106] The second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED. The second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and initializes the pixel electrode of the organic light emitting diode OLED.

[0107] Although Figure 5B it is shown that the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SL-1, the present disclosure is not limited thereto. In another embodiment, the first initialization TFT T4 may be connected to the previous scan line SL-1 and may be driven according to the previous scan signal Sn-1, but the second initialization TFT T7 may be connected to a separate signal line (e.g., the subsequent scan line) and may be driven according to the signal transmitted to the signal line.

[0108] The second storage capacitor plate CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Accordingly, the organic light emitting diode OLED may emit light by receiving the driving current I OLED from the driving TFT T1 to display an image.

[0109] Although Figure 5B it is shown that the compensation TFT T3 and the first initialization TFT T4 have dual gate electrodes, the compensation TFT T3 and the first initialization TFT T4 may each have one gate electrode.

[0110] Figure 6 shows the relationship between the black line disposed around the transmissive area TA and the pixels according to an embodiment. The black line represents a linear area disposed inside the display area DA and not emitting light and extending from the transmissive area TA to the second non-display area NDA2. The black line may be an area where the counter electrode is not formed.

[0111] Referring Figure 6 thereto, the transmissive area TA may be disposed adjacent to the first side SS1 and the second side SS2 of the display area DA. The transmissive area TA may be disposed in the display area DA, and thus, a plurality of pixels P may be disposed around the transmissive area TA. In addition, wirings for transmitting an electrical signal or voltage to the plurality of pixels P may be disposed to bypass the periphery of the transmissive area TA.

[0112] The scan line SL may extend in the first direction x, and the data line DL may extend in a second direction y intersecting the scan line SL. The scan line SL may extend in the first direction x and be connected to a plurality of pixels P. The data line DL may extend in the second direction y and also be connected to a plurality of pixels P.

[0113] Some scan lines SL can bypass the transmissive region TA. In other words, a scan line SL1 adjacent to the transmissive region TA can be bent along the edge of the transmissive region TA. The bent portion of the scan line SL1 can be disposed in the first non-display region NDA1 around the transmissive region TA. Pixels located at the left and right sides of the transmissive region TA can be electrically connected to each other through the scan line SL1 that bypasses the transmissive region TA.

[0114] Some data lines DL can bypass the transmissive region TA. In other words, a data line DL1 adjacent to the transmissive region TA can be bent along the edge of the transmissive region TA. The bent portion of the data line DL1 can be disposed in the first non-display region NDA1 around the transmissive region TA. Pixels located above and below the transmissive region TA can be electrically connected to each other through the data line DL1 that bypasses the transmissive region TA.

[0115] In the present embodiment, a first black line BL1 and a second black line BL2, which are regions that do not emit light, can be disposed between the transmissive region TA and the first side SSl and between the transmissive region TA and the second side SS2. The first side SSl and the second side SS2 respectively form the periphery of the display region DA. The first black line BL1 can extend in a third direction different from the first direction x and the second direction y. The second black line BL2 can extend in a fourth direction different from the first direction x and the second direction y. In an embodiment, the first black line BL1 and the second black line BL2 can extend in the same third direction. In another embodiment, the first black line BL1 and the second black line BL2 can extend in the same fourth direction. Imaginary lines extending from the first black line BL1 and the second black line BL2 can pass through the center point CP of the transmissive region TA.

[0116] A third black line BL3 extending from the transmissive region TA to the corner where the first side SSl and the second side SS2 of the display region DA intersect can also be disposed. Additionally, additional black lines can be disposed between the first black line BL1 and the third black line BL3 or between the second black line BL2 and the third black line BL3. According to the present invention, no black lines extending from the transmissive region to the third side SS3 and the fourth side SS4 are disposed.

[0117] In the present embodiment, the transmissive region TA and the first black line BL1, the second black line BL2, and the third black line BL3 are regions where counter electrodes are not formed. Figure 7 The mask M shown in is used to perform Figure 8 The deposition operation shown in to form counter electrodes in the display panel according to the present embodiment.

[0118] Refer to Figure 7, the mask M according to the embodiment may include an edge portion ME, a blocking portion MS, and first, second, and third ribs MR1, MR2, and MR3 that connect the edge portion ME to the blocking portion MS to support the blocking portion MS.

[0119] The edge portion ME may include a first side and a second side that intersects the first side. The blocking portion MS may be arranged adjacent to the first and second sides of the edge portion ME and may be supported by the first rib MR1 that connects the first side to the blocking portion MS and the second rib MR2 that connects the second side to the blocking portion MS. The third rib MR3 may also be arranged between the blocking portion MS and the edge portion ME. The third rib MR3 may be connected to the corner where the first and second sides of the edge portion ME intersect.

[0120] As Figure 8 shown, when depositing the counter electrode, the mask M may be arranged between the substrate 100 and the deposition source to prevent the counter electrode from being deposited in the transmissive region TA.

[0121] In other words, the blocking portion MS of the mask M may be arranged to correspond to the transmissive region TA of the display panel, and the first, second, and third ribs MR1, MR2, and MR3 may be arranged to correspond to the first black line BL1, the second black line BL2, and the third black line BL3. In other words, the first rib MR1 may be arranged to correspond to the first black line BL1, and the second rib MR2 may be arranged to correspond to the second black line BL2. Additionally, the third rib MR3 may be arranged to correspond to the third black line BL3.

[0122] Each of the first, second, and third ribs MR1, MR2, and MR3 may preferably have a width between about 10 μm and about 70 μm. When the widths of the first, second, and third ribs MR1, MR2, and MR3 are 10 μm or less, the first, second, and third ribs MR1, MR2, and MR3 may not be able to support the blocking portion MS. When the widths of the first, second, and third ribs MR1, MR2, and MR3 are 70 μm or more, the first, second, and third black lines BL1, BL2, and BL3 formed to correspond to the first, second, and third ribs MR1, MR2, and MR3 may be visible to the user.

[0123] Similarly, the widths Wb of the first, second, and third black lines BL1, BL2, and BL3 may have a range of about 10 μm to about 70 μm. The widths Wb of the first, second, and third black lines BL1, BL2, and BL3 may represent the lengths perpendicular to the longitudinal direction along which the first, second, and third black lines BL1, BL2, and BL3 extend from the transmissive region TA to the second non-display region NDA2.

[0124] When the distance between the human eye and the display panel is about 300 mm, the human eye can see the space between pixels when the distance between the pixels is greater than 70 μm, and the human eye will not see the space between pixels when the distance between the pixels is about 70 μm or less. Therefore, when the widths Wb of the first black line BL1, the second black line BL2, and the third black line BL3 are about 70 μm or less, the user's eyes will not see the first black line BL1, the second black line BL2, and the third black line BL3 in a general environment.

[0125] Return reference Figure 6 , the display panel 10 according to the present embodiment may include dummy pixels Pd arranged corresponding to the first black line BL1, the second black line BL2, and the third black line BL3. The dummy pixels Pd may include the same pixel circuits as the pixels P and may be connected to lines such as scan lines and data lines. In other words, the dummy pixels Pd may receive the same electrical signals as the pixels P.

[0126] Although Figure 6 shows one dummy pixel Pd arranged in the first black line BL1, the second black line BL2, and the third black line BL3, the present disclosure is not limited thereto. For example, two or more dummy pixels Pd may be respectively arranged in the first black line BL1, the second black line BL2, and the third black line BL3.

[0127] Figure 9 is a schematic cross-sectional view taken along Figure 6 the lines I-I' and II-II' in.

[0128] As Figure 9 shown, the pixel P may include a pixel circuit PC including at least one thin film transistor TFT and an organic light emitting diode OLED as a display element. The dummy pixel Pd may include a dummy pixel circuit PC' including at least one dummy thin film transistor TFT'. In some embodiments, the pixel circuit PC and the dummy pixel circuit PC' may have the same structure.

[0129] In the present embodiment, compared with the pixel P, the counter electrode 230 of the organic light emitting diode OLED is not arranged in the dummy pixel Pd, so the dummy pixel Pd does not emit light.

[0130] Although Figure 9 shows that the pixel circuit PC includes only one thin film transistor TFT and the dummy pixel circuit PC' includes one dummy thin film transistor TFT', the present disclosure is not limited thereto. A plurality of thin film transistors TFT and TFT' may be provided. For example, 2 to 7 thin film transistors may be provided, and various changes may be made.

[0131] Hereinafter, the structures of the pixel P and the dummy pixel Pd will now be described in a stacked order.

[0132] The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable characteristics. The substrate 100 may have a single-layer structure or a multi-layer structure of the above materials, and may further include an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 100 may have a structure of organic / inorganic / organic layers.

[0133] Although Figure 9 the substrate 100 is shown to have a substrate through hole 100H corresponding to the transmission region TA, the present disclosure is not limited thereto. As Figure 2B 、 Figure 2C 、 Figure 3B and Figure 3C shown, the substrate through hole 100H may not be formed in the substrate 100.

[0134] The buffer layer 111 may be positioned on the substrate 100 to reduce or block the penetration of foreign substances, moisture, or external air from the lower portion of the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic and inorganic composite material, and may have a single-layer structure or a multi-layer structure including an inorganic layer and an organic layer.

[0135] A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111. The barrier layer may prevent or minimize the penetration of impurities from the substrate 100 to the semiconductor layers A and A'. The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic and inorganic composite material, and may have a single-layer structure or a multi-layer structure including an inorganic layer and an organic layer.

[0136] The semiconductor layers A and A' may be disposed on the buffer layer 111. The semiconductor layers A and A' may include amorphous silicon or polycrystalline silicon. In another embodiment, the semiconductor layers A and A' may include oxides of at least one or more materials selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some embodiments, the semiconductor layers A and A' may include zinc oxide-based materials, and may include Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In another embodiment, the semiconductor layers A and A' may include an In-Ga-Zn-O (IGZO) semiconductor, an In-Sn-Zn-O (ITZO) semiconductor, or an In-Ga-Sn-Zn-O (IGTZO) semiconductor including metals such as In, Ga, and tin (Sn) in ZnO. The semiconductor layers A and A' may include a channel region and source and drain regions disposed on both sides of the channel region. The semiconductor layers A and A' may include a single layer or multiple layers.

[0137] The gate electrodes G and G' are disposed above the semiconductor layers A and A' to at least partially overlap the semiconductor layers A and A', and a first gate insulating layer 112 is located between the gate electrodes G and G' and the semiconductor layers A and A'. The gate electrodes G and G' may include molybdenum (Mo), Al, copper (Cu), Ti, and may include a single layer or multiple layers. In an embodiment, the gate electrodes G and G' may include a single layer of Mo.

[0138] The first gate insulating layer 112 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0139] A second gate insulating layer 113 may be provided to cover the gate electrodes G and G'. The second gate insulating layer 113 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0140] The first storage capacitor plates CE1 and CE1' of the storage capacitors Cst and Cst' may overlap the thin film transistors TFT and TFT'. The gate electrodes G and G' of the thin film transistors TFT and TFT' may function as the first storage capacitor plates CE1 and CE1' of the storage capacitors Cst and Cst'.

[0141] The second storage capacitor plates CE2 and CE2' of the storage capacitors Cst and Cst' are stacked with the first storage capacitor plates CE1 and CE1', and the second gate insulating layer 113 is located between the second storage capacitor plates CE2 and CE2' and the first storage capacitor plates CE1 and CE1'. In this case, the second gate insulating layer 113 can perform the function of the dielectric layer of the storage capacitors Cst and Cst'. The second storage capacitor plates CE2 and CE2' may include a conductive material containing Mo, Al, Cu, Ti, etc., and may include a single layer or multiple layers containing the above materials. In an embodiment, the second storage capacitor plates CE2 and CE2' may include a single layer of Mo or multiple layers of Mo / Al / Mo.

[0142] Although Figure 9 it is shown that the storage capacitors Cst and Cst' are stacked with the thin film transistors TFT and TFT', the present disclosure is not limited thereto. Various changes can be made such that the storage capacitors Cst and Cst' can be arranged not to be stacked with the thin film transistors TFT and TFT'.

[0143] An interlayer insulating layer 115 may be provided to cover the second storage capacitor plates CE2 and CE2' of the storage capacitors Cst and Cst'. The interlayer insulating layer 115 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0144] The source electrodes S and S' and the drain electrodes D and D' may be disposed on the interlayer insulating layer 115. The source electrodes S and S' and the drain electrodes D and D' may include a conductive material containing Mo, Al, Cu, Ti, etc., and may include a single layer or multiple layers containing the above materials. In an embodiment, the source electrodes S and S' and the drain electrodes D and D' may include multiple layers of Ti / Al / Ti.

[0145] The organic light emitting diode OLED may be positioned in the region of the pixel P on a via layer 117 on the source electrodes S and S'. The dummy pixel electrode 210' and the dummy intermediate layer 220' may be disposed in the region of the dummy pixel Pd on the via layer 117.

[0146] The via layer 117 may have a flat surface such that the pixel electrode 210 can be formed flatly. The via layer 117 may include a single layer or multiple layers of films that all include organic materials. The via layer 117 may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HDMSO), common commercial polymers such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, parylene polymers, polyvinyl alcohol polymers, and blends thereof. The via layer 117 may include inorganic materials. In this case, the via layer 117 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. When the via layer 117 includes inorganic materials, chemical planar polishing may be performed. The via layer 117 may include both organic materials and inorganic materials.

[0147] In the display area DA of the substrate 100, an organic light-emitting diode OLED is disposed on the via layer 117. The organic light-emitting diode OLED includes a pixel electrode 210, an intermediate layer 220 including an organic emission layer, and a counter electrode 230.

[0148] A via exposing any one of the source electrode S and the drain electrode D of the thin-film transistor TFT may be provided in the via layer 117, and the pixel electrode 210 contacts the source electrode S or the drain electrode D through the via to be electrically connected to the thin-film transistor TFT. Similarly, a via exposing any one of the source electrode S' and the drain electrode D' of the thin-film transistor TFT' may be provided in the via layer 117, and the pixel electrode 210' contacts the source electrode S' or the drain electrode D' through the via to be electrically connected to the thin-film transistor TFT'.

[0149] The pixel electrode 210 and the dummy pixel electrode 210' may include a (semi)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 and the dummy pixel electrode 210' may include a reflective film containing silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), mixtures thereof, etc., and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may include a stacked structure of ITO / Ag / ITO.

[0150] The pixel defining film 119 may be disposed on the via layer 117, and the pixel defining film 119 may define the emission region of the pixel P by having opening portions (i.e., opening portions 119OP that expose at least the central portions of the pixel electrodes 210) corresponding to each of the pixel electrodes 210 in the display area DA. In addition, the pixel defining film 119 increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210 to prevent arcing from occurring at the edge of the pixel electrode 210. The pixel defining film 119 may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin by a spin coating method or the like.

[0151] The pixel P, that is, the emission region of the pixel P may be defined by the opening portion 119OP of the pixel defining film 119. In other words, the edge of the pixel P may represent the edge of the opening portion 119OP of the pixel defining film 119. In addition, the edge of the opening portion 119OP of the pixel defining film 119 may represent the boundary where the pixel electrode 210 is exposed by the opening portion 119OP.

[0152] The pixel defining film 119 may further include opening portions 119OP' corresponding to the dummy pixels Pd. The opening portions 119OP' may be provided to expose the central portions of the dummy pixel electrodes 210'. The dummy intermediate layer 220' may be disposed inside the opening portions 119OP'.

[0153] The intermediate layer 220 and the dummy intermediate layer 220' of the organic light emitting diode OLED may include a low molecular weight material or a high molecular weight material of a polymer material. When the intermediate layer 220 and the dummy intermediate layer 220' of the organic light emitting diode OLED include a low molecular weight material, the intermediate layer 220 and the dummy intermediate layer 220' may include a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, an electron injection layer, etc. having a stacked structure with a single structure or a complex structure, and may include various organic materials including copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), tris(8-hydroxyquinoline)aluminum (Alq3), etc. These layers may be formed by a vacuum deposition method.

[0154] When the intermediate layer 220 and the dummy intermediate layer 220' of the organic light-emitting diode (OLED) include a high molecular weight polymer material, the intermediate layer 220 and the dummy intermediate layer 220' may have a structure including a hole transport layer and an emission layer. In this case, the hole transport layer may include poly(3,4)-ethylenedioxythiophene (PEDOT), and the emission layer may include polymer materials such as poly(phenylene vinylene) (PPV) and polyfluorene. The intermediate layer 220 and the dummy intermediate layer 220' may be formed by a screen printing method, an inkjet printing method, a laser-induced thermal imaging method, or the like.

[0155] The intermediate layer 220 and the dummy intermediate layer 220' are not limited and may have various structures. The intermediate layer 220 may include an integral layer over the plurality of pixel electrodes 210, or may include a layer patterned to correspond to each of the pixel electrodes 210.

[0156] The counter electrode 230 may be disposed above the display area DA and may be disposed to cover the display area DA. In other words, the counter electrode 230 may be formed integrally with respect to the plurality of organic light-emitting diodes (OLEDs) to correspond to the plurality of pixel electrodes 210.

[0157] The counter electrode 230 may include a first opening portion 230a corresponding to the transmissive area TA and a second opening portion 230b corresponding to the dummy pixel Pd. In other words, the second opening portion 230b of the counter electrode 230 may be disposed to expose at least a portion of the dummy intermediate layer 220' included in the dummy pixel Pd. Therefore, even when an electrical signal is received, the dummy pixel Pd may not emit light. A portion corresponding to an area of the dummy pixel Pd where the counter electrode 230 is not disposed may not emit light.

[0158] Although Figure 9 it is shown that the second opening portion 230b is disposed inside the opening portion 119OP' of the pixel defining film 119, the present disclosure is not limited thereto. The width Wb of the second opening portion 230b may be greater than the width of the opening portion 119OP' of the pixel defining film 119, and the side surface of the second opening portion 230b may be disposed on the upper surface of the pixel defining film 119. In addition, the second opening portion 230b may have a width corresponding to the plurality of dummy pixels Pd.

[0159] Referring Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3A 、 Figure 3B and Figure 3C The encapsulation substrate 300 and / or the thin film encapsulation layer 300' described may be disposed above the counter electrode 230 to protect the display element from external air.

[0160] Figure 10 and Figure 11 is a schematic view of a part of the display panel 10 according to another embodiment. In Figure 10 and Figure 11 , the reference numerals identical to those in Figure 6 denote the same components, and redundant descriptions thereof will be omitted.

[0161] Referring to Figure 10 , in the display panel 10 according to the present embodiment, a transmissive area TA is disposed in a display area DA, and the display panel 10 includes a first black line BL1 and a second black line BL2 that extend from the transmissive area TA to a first side SS1 and a second side SS2 in the display area DA. In addition, a third black line BL3 that extends to a corner where the first side SS1 and the second side SS2 intersect may be provided.

[0162] In the present embodiment, a fourth black line BL4 that extends from the transmissive area TA to the first side SS1 in a second direction y may further be included. In addition, a fifth black line BL5 that extends from the transmissive area TA to the second side SS2 in a first direction x may further be included.

[0163] The fourth black line BL4 and the fifth black line BL5 may be areas where the counter electrode 230 is not formed. The dummy pixels Pd that do not emit light may be disposed corresponding to the fourth black line BL4 and the fifth black line BL5. At least one pixel P may be disposed in the first black line BL1, the second black line BL2, the third black line BL3, the fourth black line BL4, and the fifth black line BL5. An image may be realized by the pixels P disposed in the first black line BL1, the second black line BL2, the third black line BL3, the fourth black line BL4, and the fifth black line BL5.

[0164] The width Wb of each of the first black line BL1, the second black line BL2, the third black line BL3, the fourth black line BL4, and the fifth black line BL5 may be from about 10 μm to about 70 μm. Accordingly, the black lines are not visible to a user when using the display panel 10.

[0165] Referring to Figure 11 , in the display panel 10 according to the present embodiment, a transmissive area TA is disposed in a display area DA, and the display panel 10 includes a first black line BL1 and a second black line BL2 that extend from the transmissive area TA to the first side SS1 and the second side SS2 of the display area DA, respectively, wherein the first black line BL1 extends in a third direction, and the second black line BL2 extends in a fourth direction. The third direction may be opposite to the fourth direction.

[0166] In the present embodiment, it may further include a first additional black line BL1' extending in a direction parallel to the first black line BL1. In this case, the non-light-emitting dummy pixels Pd are arranged in the first black line BL1 and the first additional black line BL1', and at least one pixel P that emits light according to an electrical signal is arranged between the first black line BL1 and the first additional black line BL1'.

[0167] In the present embodiment, it may further include a fourth black line BL4 extending from the transmissive region TA to the first side SS1 in the second direction y. Additionally, it may further include a fifth black line BL5 extending from the transmissive region TA to the second side SS2 in the first direction x.

[0168] Furthermore, it may further include a second additional black line BL2' parallel to the second black line BL2, a third additional black line BL3' parallel to the third black line BL3, a fourth additional black line BL4' parallel to the fourth black line BL4, and a fifth additional black line BL5' parallel to the fifth black line BL5.

[0169] At least one pixel P may be arranged in the first black line BL1, the second black line BL2, the third black line BL3, the fourth black line BL4, and the fifth black line BL5, as well as in the first additional black line BL1', the second additional black line BL2', the third additional black line BL3', the fourth additional black line BL4', and the fifth additional black line BL5'. An image may be realized by the pixels P arranged in the first black line BL1, the second black line BL2, the third black line BL3, the fourth black line BL4, and the fifth black line BL5, as well as in the first additional black line BL1', the second additional black line BL2', the third additional black line BL3', the fourth additional black line BL4', and the fifth additional black line BL5'.

[0170] The widths Wb of the first black line BL1, the second black line BL2, the third black line BL3, the fourth black line BL4, and the fifth black line BL5, as well as the first additional black line BL1', the second additional black line BL2', the third additional black line BL3', the fourth additional black line BL4', and the fifth additional black line BL5' may be from about 10 μm to about 70 μm. Thus, the black lines are not visible to a user when using the display panel 10.

[0171] According to one or more embodiments of the present disclosure, the transmittance may be increased by not forming a counter electrode in a transmissive region corresponding to an electronic component such as a sensor or a camera. However, the effects are illustrative, and the effects according to the embodiments are described in detail.

[0172] Through the disclosed drawings, claims, and detailed description, other aspects, features, and advantages other than those described above will now become apparent.

[0173] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment is generally to be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display panel, the display panel comprising: a substrate including a display area and a transmissive area disposed in the display area, the display area being surrounded by a first side extending in a first direction, a second side extending in a second direction intersecting the first direction, a third side facing the first side, and a fourth side facing the second side; a plurality of pixels disposed in the display area and including counter electrodes; a first black line extending from the transmissive area to the first side in a third direction different from the first direction and the second direction and having dummy pixels disposed thereon that do not emit light; and a second black line extending from the transmissive area to the second side in a fourth direction different from the first direction and the second direction and having the dummy pixels disposed thereon that do not emit light, wherein the transmissive area is disposed closer to the first side than to the third side, and wherein the counter electrodes are not provided in the first black line and the second black line.

2. The display panel according to claim 1, wherein the third direction is opposite to the fourth direction.

3. The display panel according to claim 1, wherein the width of the first black line and the width of the second black line are in the range of 10 μm to 70 μm.

4. The display panel according to claim 1, the display panel further comprising: a third black line extending from the transmissive area to a corner where the first side intersects the second side, wherein the counter electrodes are not provided in the third black line.

5. The display panel according to claim 1, wherein, The counter electrodes correspond to the plurality of pixels, and wherein the counter electrodes have a first opening portion corresponding to the transmissive area and a second opening portion corresponding to the dummy pixels.

6. The display panel according to claim 1, wherein a plurality of wirings connected to the plurality of pixels are disposed in the display area, and some of the plurality of wirings are connected to some of the dummy pixels.

7. The display panel according to claim 1, the display panel further comprising: a fourth black line extending from the transmissive area to the first side in the second direction and having the dummy pixels disposed thereon that do not emit light, wherein the counter electrodes are not provided in the fourth black line.

8. The display panel according to claim 1, the display panel further comprising: a fifth black line extending from the transmissive area to the second side in the first direction and having the dummy pixels disposed thereon that do not emit light, wherein the counter electrodes are not provided in the fifth black line.

9. The display panel according to claim 1, the display panel further comprising: a first additional black line extending from the transmissive area to the first side in a direction parallel to the first black line, wherein the counter electrodes are not provided in the first additional black line, wherein at least one of the plurality of pixels is disposed between the first black line and the first additional black line.

10. The display panel according to claim 1, wherein no black lines extending from the transmissive area to the third side and the fourth side are disposed.

11. A display panel, the display panel comprising: A substrate, including a transmissive region, a display region at least partially surrounding the transmissive region, and a non-display region outside the display region; A plurality of pixels, arranged in the display region and including counter electrodes; A plurality of black lines, extending from one side of the transmissive region to the non-display region and arranged in the display region; And A plurality of dummy pixels, which do not emit light and correspond to the plurality of black lines, Wherein, at least one pixel is arranged between adjacent black lines among the plurality of black lines, Wherein, the plurality of pixels do not overlap with the plurality of black lines, and Wherein, the counter electrodes are not provided in the plurality of black lines.

12. The display panel according to claim 11, wherein, The display region includes: a first side, extending in a first direction; a second side, extending in a second direction intersecting the first direction; a third side, facing the first side; and a fourth side, facing the second side, and The transmissive region is arranged closer to the first side and the second side than to the third side and the fourth side.

13. The display panel according to claim 12, the display panel further includes: A third black line, extending from the transmissive region to a corner where the first side intersects the second side, wherein the counter electrode is not provided in the third black line.

14. The display panel according to claim 12, the display panel further includes: A fourth black line, extending from the transmissive region to the first side in the second direction and arranged with the plurality of non-light-emitting dummy pixels, wherein the counter electrode is not provided in the fourth black line; and A fifth black line, extending from the transmissive region to the second side in the first direction and arranged with the plurality of non-light-emitting dummy pixels, wherein the counter electrode is not provided in the fifth black line.

15. The display panel according to claim 11, wherein, The width of each of the plurality of black lines is in the range of 10 μm to 70 μm.

16. The display panel according to claim 11, wherein, The counter electrode corresponds to the plurality of pixels, and Wherein, the counter electrode has a first opening portion corresponding to the transmissive region and a second opening portion corresponding to the plurality of dummy pixels.

17. The display panel according to claim 11, wherein, A plurality of wirings connected to the plurality of pixels are arranged in the display region, and some of the plurality of wirings are connected to some of the plurality of dummy pixels.

18. The display panel according to claim 11, the display panel further includes: A plurality of scan lines, extending from the display region in a first direction, and at least one of the plurality of scan lines bypasses along the edge of the transmissive region; And A plurality of data lines, extending from the display region in a second direction intersecting the first direction, and at least one of the plurality of data lines bypasses along the edge of the transmissive region.

19. The display panel according to claim 18, wherein, The plurality of scan lines and the plurality of data lines are connected to the plurality of dummy pixels.

20. The display panel according to claim 18, wherein, At least some of the plurality of scan lines and at least some of the plurality of data lines include bent portions around the transmissive region.

Images