Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device is disclosed. The three-dimensional semiconductor device can include a first stack and a second stack separated from each other in a first direction, each of the stacks including electrodes vertically stacked on a base. The three-dimensional semiconductor device can also include a vertical channel structure penetrating the electrodes and connected to the base, an interlayer insulating layer on a top surface of the vertical channel structure, and a support pattern between opposite sidewalls of the first stack and the second stack and in the interlayer insulating layer. A bottom surface of the support pattern can be positioned at a level higher than a level of a top surface of an uppermost one of the electrodes.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2019-0085255, filed on July 15, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to three-dimensional semiconductor devices, and in particular, to three-dimensional semiconductor devices having improved reliability and integration. BACKGROUND

[0003] To address consumer demand for improved performance and lower prices, it is desirable to increase the integration of semiconductor devices. In semiconductor devices, since integration is an important factor in determining product prices, increased integration is particularly desirable. In two-dimensional or planar semiconductor devices, integration is mainly determined by the area occupied by a unit memory cell. As such, the integration of two-dimensional semiconductor devices is affected by the level of fine patterning technology. Increasing the pattern fineness can require expensive processing equipment, which in some cases can be extremely expensive. This cost sets a practical limit on increasing the integration of two-dimensional or planar semiconductor devices. Recently, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have been proposed to overcome the high cost of increasing integration in two-dimensional or planar semiconductor devices. SUMMARY

[0004] Aspects of the present disclosure provide three-dimensional semiconductor devices having improved reliability.

[0005] According to some embodiments of inventive concepts, a three-dimensional semiconductor device can include a first stack and a second stack separated from each other in a first direction, each of the first stack and the second stack including electrodes vertically stacked on a base. The three-dimensional semiconductor device can include a vertical channel structure penetrating the electrodes and connected to the base, an interlayer insulating layer on a top surface of the vertical channel structure, and a support pattern between opposite sidewalls of the first stack and the second stack and in the interlayer insulating layer. A bottom surface of the support pattern can be positioned at a level higher than a level of a top surface of an uppermost one of the electrodes.

[0006] According to some embodiments of the inventive concepts, a three-dimensional semiconductor device can include first and second stacks extending in a first direction and spaced apart from each other in a second direction crossing the first direction. Each of the first and second stacks includes electrodes vertically stacked on a base, and a support pattern is located between opposite sidewalls of the first and second stacks and arranged in the first direction. Each support pattern includes first and second pairs of opposite sidewalls. The three-dimensional semiconductor device can further include an electrode separation structure located between the pair of stacks and in contact with a bottom surface of the support pattern and the first pair of opposite sidewalls of the support pattern. The second pair of opposite sidewalls of the support pattern can be aligned with sidewalls of the electrode separation structure, and a width of the support pattern in the second direction can increase as a distance from the base increases.

[0007] According to some embodiments of the inventive concepts, a three-dimensional semiconductor device can include a base including a cell array region and a connection region arranged in a first direction, first and second stacks each including electrodes and insulating layers alternately stacked on the base, and each having a stepped structure on the connection region. The three-dimensional semiconductor device can further include vertical channel structures located on the cell array region, penetrating the first and second stacks and connected to the base, dummy vertical structures located on the connection region and penetrating the first and second stacks, an interlayer insulating layer in contact with the vertical channel structures and the dummy vertical structures, bit lines located on the interlayer insulating layer and electrically connected to the vertical channel structures, cell contacts located on the connection region, penetrating the interlayer insulating layer and each bonded to a corresponding electrode, support patterns located between opposite sidewalls of the first and second stacks and in the interlayer insulating layer, and an electrode separation structure located in a region between the first and second stacks and covering a bottom surface and a side surface of the support pattern. The support pattern can have a top surface located at a level lower than a level of a bottom surface of the bit line and a bottom surface located at a level higher than a level of a top surface of an uppermost one of the electrodes, and the support pattern can include first support patterns between the vertical channel structures and second support patterns between the cell contacts. BRIEF DESCRIPTION OF DRAWINGS

[0008] To assist in understanding the inventive concepts disclosed herein, examples of embodiments are provided. These example embodiments will be more clearly understood by the following brief description, taken in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments as described herein.

[0009] Figure 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor device according to some embodiments of the inventive concepts.

[0010] Figure 2is a plan view showing a three-dimensional semiconductor device according to some embodiments of the inventive concepts.

[0011] Figure 3A , Figure 3B , Figure 3C and Figure 3D are cross-sectional views taken along lines A-A', B-B', C-C' and D-D' respectively of Figure 2

[0012] Figure 4A and Figure 4B are enlarged views showing portions "AA" of Figure 3A

[0013] Figure 5 is a cross-sectional view taken along line D-D' of Figure 2 to show a three-dimensional semiconductor device according to some embodiments of the inventive concepts.

[0014] Figure 6 is a plan view showing a three-dimensional semiconductor device according to some embodiments of the inventive concepts.

[0015] Figure 7A and Figure 7B are cross-sectional views taken along lines A-A' and B-B' respectively of Figure 6

[0016] Figure 8 is a plan view showing a three-dimensional semiconductor device according to some embodiments of the inventive concepts.

[0017] Figure 9A and Figure 9B are cross-sectional views taken along lines A-A' and B-B' respectively of Figure 8

[0018] Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 are plan views showing a method of manufacturing a three-dimensional semiconductor device according to some embodiments of the inventive concepts.

[0019] Figure 11A , Figure 13A , Figure 15A , Figure 17A , Figure 19A , Figure 21A , Figure 23A , Figure 25A and Figure 27A are cross-sectional views taken along lines A-A', B-B', C-C' and D-D' respectively of Figure 10 ,​​​​ Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 A sectional view taken by line A-A'.

[0020] Figure 11B , Figure 13B , Figure 15B , Figure 17B , Figure 19B , Figure 21B , Figure 23B , Figure 25B and Figure 27B They are respectively along Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 The sectional view taken by line B-B'.

[0021] Figure 21C , Figure 23C , Figure 25C and Figure 27C They are respectively along Figure 20 , Figure 22 , Figure 24 and Figure 26 A sectional view taken by line C-C'.

[0022] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in the exemplary embodiments and are intended to supplement the written description provided below. However, these figures are not to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or properties contained in the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0023] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0024] Figure 1 This is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor device according to some embodiments of the inventive concept.

[0025] Reference Figure 1A cell array of a three-dimensional semiconductor device according to some embodiments of the inventive concepts can include at least one common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL. In Figure 1 In the example shown in FIG. 1, a plurality of common source lines CSL is provided, but the present disclosure is not limited thereto.

[0026] The bit lines BL can extend parallel to each other, and the plurality of cell strings CSTR can be connected in parallel to each bit line BL. The cell strings CSTR can be commonly connected to the at least one common source line CSL. In other words, the plurality of cell strings CSTR can be disposed between the plurality of bit lines BL and the at least one common source line CSL. In some embodiments, as shown in Figure 1 In some embodiments, the common source lines CSL can extend parallel to each other. In some embodiments, the common source lines CSL can be supplied with the same voltage, but in other embodiments, the common source lines CSL can be electrically separated from each other and can be independently controlled.

[0027] Each cell string CSTR can include a ground select transistor GST coupled to the common source line CSL, a string select transistor SST coupled to the bit line BL, and a plurality of memory cell transistors MCT arranged between the ground select transistor GST and the string select transistor SST. In some embodiments, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT can be connected in series.

[0028] The common source line CSL can be commonly connected to a source of the ground select transistor GST. A ground select line GSL can serve as a gate electrode of the ground select transistor GST. A plurality of word lines WL0-WL3 can serve as gate electrodes of the memory cell transistors MCT. A plurality of string select lines SSL0-SSL2 can serve as gate electrodes of the string select transistor SST. The ground select line GSL, the plurality of word lines WL0-WL3, and the plurality of string select lines SSL0-SSL2 can be arranged between the at least one common source line CSL and the bit lines BL. Each memory cell transistor MCT can include a data storage element.

[0029] Figure 2 FIG. 1 is a plan view showing a three-dimensional semiconductor device according to some embodiments of the inventive concepts. Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D are cross-sectional views taken along lines A-A', lines B-B', lines C-C', and lines D-D' of Figure 2 , respectively. Figure 4A and Figure 4B are enlarged views showing a portion "AA" of Figure 3A .

[0030] Referring to Figure 2 , Figure 3A , Figure 3B and Figure 3D , the substrate 100 can include a cell array region CAR and a connection region CNR. The cell array region CAR and the connection region CNR can be adjacent to each other in a first direction D1. The substrate 100 can be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The substrate 100 can be doped to have a first conductivity type. The first conductivity type can be, for example, a p-type.

[0031] The stacks ST can be located on the cell array region CAR and the connection region CNR. The stacks ST can extend in the first direction D1 parallel to each other. The stacks ST can be spaced apart from each other in a second direction D2 perpendicular to the first direction D1. The first direction D1 and the second direction D2 can be horizontal directions each substantially parallel to a top surface of the substrate 100. A buffer insulating layer 101 can be disposed between the stacks ST and the substrate 100. The buffer insulating layer 101 can include a silicon oxide layer.

[0032] Each stack ST can include electrodes EL and insulating layers ILD repeatedly and alternately stacked in a third direction D3 perpendicular to the top surface of the substrate 100. The electrodes EL can have substantially the same thickness, and the insulating layers ILD can have at least two different thicknesses, according to desired characteristics of the semiconductor memory device. In some embodiments, the thickness of each insulating layer ILD can be less than the thickness of each electrode EL. In some embodiments, at least one of the insulating layers ILD can be thicker than the electrodes EL. The electrodes EL can be formed of or include, for example, at least one of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and a transition metal (e.g., titanium, tantalum, etc.). The insulating layers ILD can include, for example, a silicon oxide layer or a low-k dielectric layer.

[0033] As Figure 3CAs best seen, the stack ST can have a stepped structure on the connection region CNR. For example, on the connection region CNR, the length of the electrode EL in the first direction D1 can decrease as the distance from the base 100 increases, and the height of the stack ST can decrease as the distance from the cell array region CAR increases. In addition, on the connection region CNR, the electrode EL can have sidewalls that are spaced apart from each other by a certain distance in the first direction D1. The sidewalls of the electrode EL can be substantially perpendicular to the top surface of the base 100. Each electrode EL can have a pad portion on the connection region CNR, and the pad portions of the electrodes EL can be located at different positions from each other in the horizontal and vertical directions. The stack ST is shown as having a stepped structure in the first direction D1, but in some embodiments, the stack ST can also be provided to have a stepped structure in the second direction D2.

[0034] In some embodiments, the three-dimensional semiconductor device can be a vertical type NAND FLASH memory device, and the electrodes EL can function as gate electrodes for controlling memory cell transistors MCT (see, for example, Figure 1 ). Figure 1 The electrodes EL can function as the string selection lines SSL0-SSL2, the word lines WLO-WL3, and the gate selection lines GSL described with reference to

[0035] The uppermost electrodes EL among the electrodes EL can be spaced apart from each other in the second direction D2 by the insulating separation pattern 40. The uppermost electrodes EL among the electrodes EL can function as the string selection lines SSL0-SSL2 described with reference to Figure 1 The uppermost insulating layer ILD on the top surface of the uppermost electrode EL can be thicker than the insulating layers ILD disposed between the electrodes EL.

[0036] As shown in Figure 4A , the horizontal insulating pattern HP can extend from the region between the electrodes EL and the vertical channel structure VS (described more fully herein) to other regions positioned on the top and bottom surfaces of the electrodes EL. The horizontal insulating pattern HP can include a charge storage layer and a blocking insulating layer that function as part of a data storage layer of a NAND FLASH memory device. In some embodiments, the horizontal insulating pattern HP can include the blocking insulating layer, but can omit the charge storage layer.

[0037] Referring back to Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3DAn insulating planarization layer 150 can be disposed on the base 100 to cover the stack ST. The insulating planarization layer 150 can have a substantially planar top surface and can cover the stepped structure of the stack ST on the connection region CNR. The top surface of the insulating planarization layer 150 can be coplanar with a top surface of an uppermost insulating layer ILD among the insulating layers ILD in the stack ST located on the cell array region CAR. The insulating planarization layer 150 can be or include a single insulating layer or a plurality of stacked insulating layers. For example, the insulating planarization layer 150 can include a silicon oxide layer and / or a low-k dielectric layer.

[0038] The vertical channel structures VS can be disposed on the cell array region CAR to penetrate the stack ST. The vertical channel structures VS can penetrate the electrodes EL and can be electrically connected to the base 100. When viewed in a plan view, the vertical channel structures VS can be arranged to form a zigzag or diagonal shape in the first direction D1. The vertical channel structures VS can be formed of or include a semiconductor material or a conductive material. The vertical channel structures VS can have a bottom surface located between a top surface and a bottom surface of the base 100. In some embodiments, the vertical channel structures VS can extend from the top surface of the base 100 into the base 100.

[0039] In some embodiments, each vertical channel structure VS can include a semiconductor pattern VP penetrating the stack ST and in contact with the base 100, and an insulating fill pattern VI filling an inner space of the semiconductor pattern VP. An upper portion of the semiconductor pattern VP can have a hollow tube shape or a hollow penne shape. The semiconductor pattern VP can also have a bottom portion, which can be closed and can be connected to the base 100. The semiconductor pattern VP can be in an undoped or intrinsic state, or can be doped to have the same conductivity type as that of the base 100. The semiconductor pattern VP can have a polycrystalline or single-crystalline structure. The insulating fill pattern VI can be formed of or include silicon oxide or silicon oxynitride. In some embodiments, the insulating fill pattern VI can be omitted.

[0040] The memory layer DS can be disposed between the semiconductor pattern VP and the electrode EL. In some embodiments, the memory layer DS can be disposed between the semiconductor pattern VP and the horizontal insulating pattern HP. The memory layer DS can include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer stacked sequentially on the semiconductor pattern VP. The blocking insulating layer can be a multi-layer including a plurality of thin films. For example, the blocking insulating layer can include at least one of a hafnium oxide layer, an aluminum oxide layer, and a silicon oxide layer. If there is more than one of the above compounds, the stacking order of the hafnium oxide layer, the aluminum oxide layer, and the silicon oxide layer can be variously changed. The charge storage layer can be a charge trapping layer or an insulating layer containing conductive nanoparticles. The charge trapping layer can be, for example, a silicon nitride layer. The tunnel insulating layer can include a silicon oxide layer. The tunnel insulating layer can further include a high-k dielectric layer (e.g., a hafnium oxide layer or an aluminum oxide layer). In some embodiments, the memory layer DS can be a variable resistance pattern. The variable resistance pattern can include at least one variable resistance material, the resistance of which has a resistance that can be changed.

[0041] The conductive pattern PAD can be disposed on or in an upper portion of the vertical channel structure VS. The conductive pattern PAD can be formed of or include at least one of a doped semiconductor and a metallic material. For example, the conductive pattern PAD can include the same material as the material of the semiconductor pattern VP. In some embodiments, the conductive pattern PAD can be formed of or include doped polysilicon. In some embodiments, the memory layer DS can be disposed on sidewalls of the conductive pattern PAD.

[0042] The first interlayer insulating layer 111 can be disposed to cover the stack ST. In addition, the first interlayer insulating layer 111 can cover the insulating planarization layer 150. The first interlayer insulating layer 111 can include a silicon oxide layer.

[0043] The support pattern SP and the electrode separation structure ESS can be disposed between a pair of adjacent stacks ST. The support pattern SP can be arranged in the first direction D1. The support pattern SP can be disposed between opposite sidewalls of the pair of stacks ST. The support pattern SP can be spaced apart from the top surface of the substrate 100 to support an upper portion of the stack ST. In detail, the support pattern SP can extend from an area disposed between the opposite sidewalls of the pair of stacks ST into the first interlayer insulating layer 111. The support patterns SP can be spaced apart from each other in the first direction D1 to partially expose sidewalls of the stack ST. The electrode separation structure ESS can extend in the first direction D1 to fill a space between the stacks ST.

[0044] In more detail, as Figure 3A , Figure 3D and Figure 4AAs seen in the middle, the support pattern SP can have second side walls sw2 opposite each other in the first direction D1 and first side walls sw1 opposite each other in the second direction D2. The width of each support pattern SP in the second direction D2 can be less than the width of each support pattern SP in the first direction D1. That is, in each support pattern SP, the distance between the second side walls sw2 can be greater than the distance between the first side walls sw1. The first side walls sw1 of the support pattern SP can face the side walls of the stack ST. The second side walls sw2 of the support pattern SP can face the second side walls sw2 of another support pattern SP adjacent thereto. As Figure 4A As shown in the middle, the support pattern SP can have a width W1 that increases with increasing distance from the substrate 100 when measured in the second direction D2. The width of the support pattern SP in the second direction D2 can be greatest at its top level. As Figure 3D As shown in the middle, the width of the support pattern SP in the first direction D1 can be uniform.

[0045] The electrode separation structure ESS can cover the bottom surface bs and the second side walls sw2 of the support pattern SP. The electrode separation structure ESS can not cover the first side walls sw1 of the support pattern SP. The first side walls sw1 of the support pattern SP can be free of the electrode separation structure ESS. The support pattern SP can be inserted in the electrode separation structure ESS such that the top surface of the electrode separation structure ESS can have a recessed region RR. The bottom surface of the recessed region RR can be located at a level lower than the level of the top surface of the stack ST. The width of the electrode separation structure ESS in the second direction D2 can increase with increasing distance from the substrate 100. The width of the electrode separation structure ESS in the second direction D2 can be greatest at its top level. The top surface of the electrode separation structure ESS can be coplanar with the top surface of the support pattern SP. The distance between adjacent stacks ST in the stack ST can be uniform in the second direction D2. Thus, at the same vertical level, the width of the electrode separation structure ESS in the second direction D2 can be equal to the width of the support pattern SP in the second direction D2. That is, the greatest width of the support pattern SP in the second direction D2 can be substantially equal to the greatest width of the electrode separation structure ESS in the second direction D2. Some side walls of the electrode separation structure ESS can be aligned with the first side walls sw1 of the support pattern SP.

[0046] In some embodiments, the electrode separation structure ESS can include a common source plug CSP and an insulating spacer SS. The common source plug CSP can be bonded to a common source region CSR, which can be formed in a region of the substrate 100 between the stacks ST. In some embodiments, the common source region CSR can be an impurity region formed near a top surface of the substrate 100 exposed between adjacent ones of the stacks ST. The common source region CSR can be doped to have a conductivity type different from a conductivity type of the substrate 100. The common source plug CSP can be a plate-like structure extending along the common source region CSR. In some embodiments, the common source plug CSP can have a column shape. In such embodiments, additional lines can be provided to connect the column-shaped common source plugs CSP arranged along the first direction D1 to each other.

[0047] The insulating spacer SS can be disposed between the common source plug CSP and a sidewall of the stack ST. The insulating spacer SS can be formed of or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a low dielectric constant. The insulating spacer SS can electrically disconnect the common source plug CSP from the electrode EL. The insulating spacer SS can also be disposed between the support pattern SP and the common source plug CSP. The insulating spacer SS can be disposed between a bottom surface bs of the support pattern SP and a bottom surface of the recessed region RR of the common source plug CSP. In addition, the insulating spacer SS can be disposed between a second sidewall sw2 of the support pattern SP and an inner sidewall of the recessed region RR of the common source plug CSP.

[0048] A second interlayer insulating layer 112 can be disposed on the first interlayer insulating layer 111. The second interlayer insulating layer 112 can cover a top surface of the support pattern SP and a top surface of the electrode separation structure ESS.

[0049] A bit line BL can be disposed on the second interlayer insulating layer 112 of the cell array region CAR and can be electrically connected to the vertical channel structure VS through a bit line contact plug BPLG. A connection line CL can be disposed on the second interlayer insulating layer 112 of the connection region CNR and can be bonded to the cell contact CPLG.

[0050] Referring to Figure 4B In some embodiments, the support pattern SP can include a recessed portion recessed from a bottom surface thereof toward a top surface thereof. In other words, the support pattern is disposed to define a recessed portion recessed from a bottom surface thereof toward a top surface thereof. The air gap AG can be defined in the recessed portion of the support pattern SP.

[0051] Figure 5 is along the Figure 2is a cross-sectional view of a three-dimensional semiconductor device according to some embodiments of inventive concepts, taken along line D-D' of

[0052] Referring to Figure 5 , a width W2 of the support pattern SP in the first direction D1 can increase as a distance from the base 100 decreases. For example, a distance between sidewalls of two adjacent support patterns SP can increase as a distance from the base 100 increases.

[0053] Figure 6 is a plan view of a three-dimensional semiconductor device according to some embodiments of inventive concepts. Figure 7A and Figure 7B are cross-sectional views taken along lines A-A' and B-B' of Figure 6 , respectively. For brevity of description, elements previously described with reference to Figure 2 and Figures 3A to 3D may be identified by the same reference numerals or numbers without repeating overlapping descriptions thereof.

[0054] Referring to Figure 6 , Figure 7A and Figure 7B , an electrode separation structure ESS according to some embodiments of inventive concepts can include an insulating fill pattern GFI that can fill a space between a pair of stacks ST. The insulating fill pattern GFI can include at least one of a silicone-based material (e.g., a spin-on hard mask (SOH) material) and a carbon-based material (e.g., an amorphous carbon layer (ACL)). The insulating fill pattern GFI can extend in the first direction D1 and can completely fill the space between the stacks ST. That is, a common source plug CSP can not be formed between opposite sidewalls of the stacks ST and can be omitted.

[0055] In some embodiments, a source structure SC can be disposed on a top surface of the base 100. The source structure SC can include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 that are sequentially stacked. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 can be connected to sidewalls of the vertical channel structure VS. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 can be formed of, or include, a doped semiconductor material. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 can be doped to have a conductivity type different from a conductivity type of the base 100.

[0056] Figure 8 is a plan view of a three-dimensional semiconductor device according to some embodiments of inventive concepts. Figure 9A and Figure 9B are cross-sectional views taken along lines A-A' and B-B' of Figure 8cross-sectional view taken along line A-A' and line B-B' of FIG. 1. For simplicity of description, reference is made to the previous description of FIG. 1. Figure 2 and Figures 3A to 3D Elements described previously can be identified by the same reference numerals or characters, without repeating overlapping descriptions thereof.

[0057] Referring to Figure 8 , Figure 9A and Figure 9B , the support pattern SP can include a first portion SPa and a second portion SPb on the first portion SPa. The first portion SPa can be located between the pair of stacks ST and can extend in the third direction D3. In detail, the first portion SPa can extend from an area disposed between opposite sidewalls of the pair of stacks ST into the first interlayer insulating layer 111. A bottom surface of the first portion SPa can be positioned at a level higher than a top surface of the uppermost one of the electrodes EL.

[0058] The second portion SPb can horizontally extend in the second direction D2 in the first interlayer insulating layer 111 and the second interlayer insulating layer 112. The second portion SPb can connect the first portions SPa spaced apart from each other in the second direction D2, with the stacks ST interposed therebetween. The bit line contact plug BPLG can be disposed to penetrate the second portion SPb and can be bonded to the conductive pattern PAD. A top surface of the second portion SPb can be positioned at a level lower than a top surface of the second interlayer insulating layer 112 and higher than a bottom surface of the second interlayer insulating layer 112. In some embodiments, a plurality of second portions SPb can be arranged in the first direction D1.

[0059] Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 are plan views showing a method of manufacturing a three-dimensional semiconductor device according to some embodiments of the inventive concept. Figure 11A , Figure 13A , Figure 15A , Figure 17A , Figure 19A , Figure 21A , Figure 23A , Figure 25A and Figure 27A are cross-sectional views taken along lines A-A' and B-B' of FIG. 1, respectively. Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24and Figure 26 A sectional view taken by line A-A'. Figure 11B , Figure 13B , Figure 15B , Figure 17B , Figure 19B , Figure 21B , Figure 23B , Figure 25B and Figure 27B They are respectively along Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 The sectional view taken by line B-B'. Figure 21C , Figure 23C , Figure 25C and Figure 27C They are respectively along Figure 20 , Figure 22 , Figure 24 and Figure 26 A sectional view taken by line C-C'.

[0060] Reference Figure 10 , Figure 11A and Figure 11B A molded structure MS can be formed on the substrate 100, and then a vertical channel structure VS and a dummy vertical structure DVS can be formed as a through molded structure MS. The molded structure MS can be formed on the cell array region CAR and the connection region CNR of the substrate 100. In some embodiments, a buffer insulating layer 101 as a thermal oxide layer can be formed on the top surface of the substrate 100 before forming the molded structure MS.

[0061] The formation of the molded structure MS may include: forming a stacked structure on a substrate 100 in which the sacrificial layer SL and the insulating layer ILD are stacked vertically and alternately, and performing a trimming process on the stacked structure. As a result of the trimming process, the molded structure MS may be formed to have a stepped structure on the connection region CNR. After forming the molded structure MS, an insulating planarization layer 150 may be formed on the substrate 100. The insulating planarization layer 150 may be formed to have a substantially flat top surface and may be formed of an insulating material that has etch selectivity relative to the sacrificial layer SL.

[0062] The vertical channel structures VS and dummy vertical structures DVS can be formed to penetrate the mold structure MS and be connected to the substrate 100. The vertical channel structures VS can be formed on the cell array region CAR of the substrate 100, and the dummy vertical structures DVS (not specifically shown) can be formed on the connection region CNR of the substrate 100. The formation of the vertical channel structures VS and the dummy vertical structures DVS can include forming vertical holes to penetrate the mold structure MS and the buffer insulating layer 101 and expose the substrate 100, and forming a semiconductor pattern VP, an insulating fill pattern VI, and a conductive pattern PAD in each of the vertical holes. The vertical holes can be formed by forming a mask pattern (not shown) on the mold structure MS and performing an anisotropic etching process using the mask pattern as an etching mask.

[0063] The formation of the semiconductor pattern VP can include depositing a semiconductor layer of a uniform thickness in the vertical hole with the memory layer DS. In some embodiments, the semiconductor layer can be conformally formed to be too thin to completely fill the thickness of the vertical hole. Thus, the semiconductor pattern VP can define an empty space in the vertical hole, and the empty space can be filled with the insulating fill pattern VI or air. In some embodiments, the conductive pattern PAD can be formed in or on an upper portion of the semiconductor pattern VP. The conductive pattern PAD can be an impurity doped region, or can be formed of a conductive material. Although not shown, a selective epitaxial growth (SEG) process can be further performed to form a lower semiconductor pattern between the semiconductor pattern VP and the substrate 100. Thus, the vertical channel structures VS can be formed in the vertical holes on the cell array region CAR of the substrate 100, and the dummy vertical structures DVS can be formed in the vertical holes on the connection region CNR.

[0064] Referring to Figure 12 , Figure 13A and Figure 13B The mold structure MS can be patterned to form a plurality of preliminary stacks PST from the mold structure MS. Trenches T can be formed between the preliminary stacks PST. The formation of the trenches T can include forming a first interlayer insulating layer 111 to cover a top surface of the vertical channel structures VS, and sequentially etching the sacrificial layer SL and the insulating layer ILD using the first interlayer insulating layer 111 as an etching mask.

[0065] The trenches T can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. The trenches T can be formed to be spaced apart from the vertical channel structures VS and to expose the sidewalls of the sacrificial layers SL and the insulating layers ILD. The trenches T can be formed to have a line shape or a rectangular shape. The preliminary stacks PST can be line-shaped structures extending along the trenches T or in the first direction D1. The preliminary stacks PST can be spaced apart from each other in the second direction D2 with the trenches T disposed between the preliminary stacks PST. Accordingly, each of the preliminary stacks PST can include the sacrificial layers SL and the insulating layers ILD alternately stacked on the base 100. In some embodiments, the trenches T can be formed in an over-etching manner, and in this case, the top surface of the base 100 exposed by the trenches T can be recessed to a certain depth.

[0066] In some embodiments, the vertical channel structures VS in one of the preliminary stacks PST can form a certain number of columns (e.g., nine columns) parallel to the first direction D1. In some embodiments, the vertical channel structures VS in a certain column (e.g., the fifth column) can not be connected to the bit lines BL. In some embodiments, the insulating separation patterns 40 extending in the first direction D1 can be formed on each of the molded structures MS. The insulating separation patterns 40 can be formed to cut at least one of the sacrificial layers SL disposed in the upper portion of the preliminary stacks PST.

[0067] Referring to Figure 14 , Figure 15A and Figure 15B , the vertical sacrificial patterns VSP can be formed between the preliminary stacks PST. The formation of the vertical sacrificial patterns VSP can include forming a first gap fill layer (not shown) to fill the trenches T and cover the top surface of the first interlayer insulating layer 111, and then performing a planarization process and / or an etch-back process on the first gap fill layer to remove a portion of the first gap fill layer. The top surface of the vertical sacrificial patterns VSP can be positioned at a level lower than that of the bottom surface of the first interlayer insulating layer 111. The top surface of the vertical sacrificial patterns VSP can be positioned at a level higher than that of the top surface of the uppermost one of the sacrificial layers SL.

[0068] Referring to Figure 16 , Figure 17A and Figure 17B , a second gap fill layer PSPL can be formed on the first interlayer insulating layer 111 to fill the remaining spaces of the trenches T. The second gap fill layer PSPL can be formed of an insulating material having etch selectivity with respect to the sacrificial layers SL and the vertical sacrificial patterns VSP. For example, the second gap fill layer PSPL can be formed of at least one of a silicon resin-based material (e.g., a spin-on hard mask (SOH) material), a carbon-based material (e.g., an amorphous carbon layer (ACL)), polysilicon, and a photoresist material.

[0069] Referring to Figure 18 , Figure 19A and Figure 19B , a preliminary support pattern PSP can be formed by removing a portion of the second gap fill layer PSPL. The removal of the portion of the second gap fill layer PSPL can be performed using a planarization process. Thus, the preliminary support pattern PSP can be formed to have a top surface that is coplanar with the top surface of the first interlayer insulating layer 111. The preliminary support pattern PSP can fill the remaining space of the trench T in which the vertical sacrificial pattern VSP is formed, and can extend in the first direction D1. The preliminary support patterns PSP can be spaced apart from each other in the second direction D2.

[0070] Referring to Figure 20 , Figure 21A , Figure 21B and Figure 21C , a mask pattern MP can be formed on the first interlayer insulating layer 111, and an etching process can be performed to form the support patterns SP from the preliminary support pattern PSP.

[0071] The mask pattern MP can be formed to cover a portion of the preliminary support pattern PSP. The mask pattern MP can have an opening OP extending in the second direction D2. The opening OP can be formed to partially expose the top surface of the preliminary support pattern PSP. Thereafter, a selective etching process using the mask pattern MP as an etching mask can be performed on the preliminary support pattern PSP. Thus, the support patterns SP arranged along the first direction D1 can be formed. The support patterns SP can partially expose the top surface of the vertical sacrificial pattern VSP. In some embodiments, the support patterns SP can be formed such that their width in the first direction D1 increases as the distance from the substrate 100 decreases.

[0072] Referring to Figure 22 , Figure 23A , Figure 23B and Figure 23C , the vertical sacrificial pattern VSP can be removed. The removal of the vertical sacrificial pattern VSP can be performed using, for example, a wet etching process. As a result of the removal of the vertical sacrificial pattern VSP, the opposite sidewalls of the preliminary stack PST can be exposed. The support patterns SP can have a bottom surface positioned at a level higher than a level of the uppermost sacrificial layer SL in the preliminary stack PST, and thus, the support patterns SP can not cover the sidewalls of the sacrificial layers SL.

[0073] Referring to Figure 24 , Figure 25A , Figure 25B and Figure 25CThe stack ST can be formed by replacing the sacrificial layers SL with electrodes EL. Each stack ST can include insulating layers ILD and electrodes EL that are vertically and alternately stacked. In detail, the sacrificial layers SL exposed by the trenches T can be selectively removed, and the electrodes EL can be formed in empty spaces from which the sacrificial layers SL are removed. The horizontal insulating pattern HP can be conformally formed in the empty spaces from which the sacrificial layers SL are removed before the electrodes EL are formed (e.g., see Figure 4A ). The electrodes EL can be formed to completely fill the empty spaces from which the sacrificial layers SL are removed.

[0074] Thereafter, the common source region CSR can be formed by doping the portion of the base 100 exposed between the sidewalls of the stacks ST with impurities. The common source region CSR can be formed to have a conductivity type different from that of the base 100.

[0075] Referring to Figure 26 , Figure 27A , Figure 27B and Figure 27C , the electrode separation structures ESS can be formed between opposite sidewalls of the stacks ST. Each electrode separation structure ESS can include a common source plug CSP and an insulating spacer SS interposed between the common source plug CSP and the sidewall of the stack ST.

[0076] The insulating spacer SS can be formed to cover the opposite sidewalls of the stack ST. A bottom surface of the insulating spacer SS can be etched to expose a top surface of the base 100. The common source plug CSP can be formed to fill a remaining space of the trench T in which the insulating spacer SS is formed. The common source plug CSP can extend in the first direction D1 and can be bonded to the common source region CSR of the base 100. A planarization process can be performed so that the common source plug CSP has a top surface that is coplanar with a top surface of the support pattern SP.

[0077] Referring back to Figure 2 , Figure 3A , Figure 3B and Figure 3D , a second interlayer insulating layer 112 can be formed on the first interlayer insulating layer 111 to cover a top surface of the electrode separation structure ESS and a top surface of the support pattern SP. A bit line contact plug BPLG can be formed on the cell array region CAR to penetrate the first interlayer insulating layer 111 and the second interlayer insulating layer 112 and be bonded to the conductive pattern PAD. A bit line BL can be formed on the second interlayer insulating layer 112.

[0078] The unit contact CPLG can be formed on the connection region CNR to penetrate the first interlayer insulating layer 111, the second interlayer insulating layer 112, and the insulating planarization layer 150 and be joined to the electrode EL of the stack ST. The connection line CL can be formed on the second interlayer insulating layer 112.

[0079] According to some embodiments of the inventive concepts, a support pattern can be disposed between opposite sidewalls of the stack that face each other. Thus, it can be possible to prevent a tilting problem in the stack and to implement a three-dimensional semiconductor device with improved reliability.

[0080] While some example embodiments of the inventive concepts have been particularly shown and described, ordinary skilled persons will appreciate that changes in form and details can be made therein without departing from the scope of the appended claims.

Claims

1. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A first stack and a second stack are separated from each other in a first direction, each of the first stack and the second stack including electrodes vertically stacked on a substrate; Vertical channel structure, penetrating the electrode and connecting to the substrate; Interlayer insulation layer, located on the top surface of the vertical channel structure; The support pattern is located between the opposing sidewalls of the first stack and the second stack and is located in the interlayer insulation layer; as well as The electrode separation structure is located between the first and second stacked components and contacts the bottom and side surfaces of the support pattern. The bottom surface of the support pattern is positioned at a level higher than the top surface of the uppermost electrode in the electrode array. The width of the top surface of the support pattern in the first direction is equal to the width of the top surface of the electrode separation structure in the first direction.

2. The three-dimensional semiconductor device according to claim 1, wherein, The width of the support pattern in the first direction increases with the distance from the substrate.

3. The three-dimensional semiconductor device according to claim 1, wherein, Each of the first and second stacked components also includes an insulating layer. In this configuration, electrodes and insulating layers are stacked alternately, and The support pattern is in direct contact with the topmost insulating layer on the top surface of the topmost electrode in the insulating layer.

4. The three-dimensional semiconductor device of claim 1, further comprising bit lines electrically connecting the vertical channel structures to each other, wherein, The top surface of the supporting pattern is positioned at a level lower than the bottom surface of the position line.

5. The three-dimensional semiconductor device according to claim 1, wherein, The top surface of the support pattern is coplanar with the top surface of the electrode separation structure.

6. The three-dimensional semiconductor device according to claim 1, wherein the three-dimensional semiconductor device further comprises an insulating separation pattern intersecting the uppermost electrode in a second direction perpendicular to the first direction.

7. The three-dimensional semiconductor device according to claim 1, wherein, The support pattern is configured to define a recessed portion extending from its bottom surface toward its top surface.

8. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A first stack and a second stack are separated from each other in a first direction, each of the first stack and the second stack including electrodes vertically stacked on a substrate; Vertical channel structure, penetrating the electrode and connecting to the substrate; Interlayer insulation layer, located on the top surface of the vertical channel structure; as well as The support pattern is located between the opposing sidewalls of the first and second stacked components and within the interlayer insulation layer. The bottom surface of the support pattern is positioned at a level higher than the top surface of the uppermost electrode in the electrode array. Specifically, when measured in a second direction perpendicular to the first direction, the width of the support pattern decreases as the distance from the substrate increases.

9. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A first stack and a second stack are separated from each other in a first direction, each of the first stack and the second stack including electrodes vertically stacked on a substrate; Vertical channel structure, penetrating the electrode and connecting to the substrate; Interlayer insulation layer, located on the top surface of the vertical channel structure; as well as The support pattern is located between the opposing sidewalls of the first and second stacked components and within the interlayer insulation layer. The bottom surface of the support pattern is positioned at a level higher than the top surface of the uppermost electrode in the electrode array. The support pattern includes a first portion extending vertically away from the substrate and a second portion located on the first portion and extending horizontally in a first direction.

10. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A first stack and a second stack extend along a first direction and are spaced apart from each other in a second direction intersecting the first direction, each of the first stack and the second stack including electrodes vertically stacked on a substrate; Multiple support patterns are located between the opposite sidewalls of the first stack and the second stack and arranged in a first direction, each support pattern including a first pair of opposite sidewalls and a second pair of opposite sidewalls; as well as The electrode separation structure is located between the first stack and the second stack and contacts the bottom surface of the support pattern and the first pair of opposing sidewalls of the support pattern. In this configuration, the second pair of opposing sidewalls of the supporting pattern are aligned with the sidewalls of the electrode separation structure, and The width of the support pattern in the second direction increases with the distance from the substrate.

11. The three-dimensional semiconductor device according to claim 10, wherein, Each of the first and second stacked components also includes an insulating layer. In this configuration, insulating layers and electrodes are stacked alternately, and The second pair of opposing sidewalls of the supporting pattern are in direct contact with the uppermost insulating layer on the top surface of the uppermost electrode in the electrode layer.

12. The three-dimensional semiconductor device according to claim 10, wherein, The bottom surface of the support pattern is positioned at a level higher than the top surface of the uppermost electrode in the electrode.

13. The three-dimensional semiconductor device according to claim 10, wherein, The electrode separation structure includes: Common-source plug, extending along a first direction and bonded to a substrate between the first and second stacks; and An insulating spacer is located between the common source plug and the opposite sidewalls of the first and second stacks.

14. The three-dimensional semiconductor device according to claim 13, wherein, The width of the top surface of the common source plug in the second direction is smaller than the width of the top surface of the support pattern in the second direction.

15. The three-dimensional semiconductor device according to claim 10, wherein, The bottom surface of the support pattern has a recessed shape and defines an air gap between the support pattern and the electrode separation structure.

16. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: The substrate includes a cell array region and a connection region arranged in the first direction; The first stack and the second stack each include electrodes and insulating layers alternately stacked on a substrate, and each has a stepped structure on the connection region; A vertical channel structure is located on the cell array area, penetrating the first and second stacks and connecting to the substrate; A virtual vertical structure is located on the connection area and penetrates the first and second stacked components; Interlayer insulation layer, located on vertical channel structure and virtual vertical structure; The bit line is located on the interlayer insulation layer and is electrically connected to the vertical channel structure; Unit contacts are located on the connection area and penetrate the interlayer insulation layer; each unit contact is coupled to the corresponding electrode. The support pattern is located between the opposing sidewalls of the first stack and the second stack and is located in the interlayer insulation layer; as well as The electrode separation structure is located in the region between the first and second stacked components and is in contact with the bottom and side surfaces of the support pattern. The support pattern has a top surface and a bottom surface. The top surface is located at a level lower than the bottom surface of the electrode line, and the bottom surface is located at a level higher than the top surface of the uppermost electrode. The support pattern includes a first support pattern between vertical channel structures and a second support pattern between unit contacts.

17. The three-dimensional semiconductor device according to claim 16, wherein, The first support pattern is in direct contact with the insulating layer.

18. The three-dimensional semiconductor device according to claim 16, wherein, The width of the first support pattern in the first direction decreases as the distance from the substrate increases, and The width of the first support pattern in the second direction, which intersects the first direction, increases with the increase of the distance from the substrate.

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