A power supply control circuit with switchable input and output and device thereof

Abstract

The present invention provides a power supply control circuit and device with switchable input and output, wherein the power supply control circuit comprises a first connector; a first circuit, connected to the first connector and the power supply, respectively; a second connector; a second circuit, connected to the second connector and the power supply, respectively; a controller, connected to the first circuit and the second circuit, respectively; when the first connector is the input end of the power supply, the control circuit controls the second circuit to be an output circuit, so as to control the output voltage of the second connector by controlling the disconnection or conduction of the second circuit; when the second connector is the input end of the power supply, the control circuit controls the first circuit to be an output circuit, so as to control the output voltage of the first connector by controlling the disconnection or conduction of the first circuit. The beneficial effects of the present invention are as follows: the input circuit and the output circuit of the first circuit and the second circuit are interchangeable, and the first connector and the second connector can use the same connector, and the phenomenon of inserting the wrong connector interface is avoided.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a power supply control circuit with switchable input and output and a device thereof. Background Art

[0002] With the rapid development of electronic technology today, power electronics technology has received more and more attention, and the upgrading of power supply technology has further promoted the development of related electronic equipment and components.

[0003] In today's era, as electronic products tend to be miniaturized, people have higher and higher requirements on the power supply technology of electronic products.

[0004] At present, the input interface and the output interface of the power supply are connected by different connectors. Therefore, it is necessary to configure corresponding connectors according to the input interface and the output interface of the power supply. Therefore, the above-mentioned prior art needs to use two different connectors, which easily leads to the phenomenon of wrong connector interface insertion, thereby causing inconvenience to the operator.

[0005] The prior art also provides a power supply circuit that connects the input interface and the output interface. However, the power supply circuit connected in the prior art has no switch control and cannot control the on and off of the load power supply, which brings inconvenience to the operator. Summary of the invention

[0006] In view of the above problems existing in the prior art, a power supply control circuit with switchable input and output and a device thereof are now provided.

[0007] The specific technical solutions are as follows:

[0008] A power supply control circuit with switchable input and output, comprising:

[0009] a first connector;

[0010] A first circuit is connected to the first connector and the power source respectively;

[0011] a second connector;

[0012] A second circuit is connected to the second connector and the power source respectively;

[0013] A control circuit is connected to the first circuit and the second circuit respectively, and when the first connector is the input end of the power supply, the control circuit controls the second circuit to be the output circuit, so as to control the output voltage of the second connector by controlling the disconnection or conduction of the second circuit;

[0014] When the second connector is the input end of the power supply, the first circuit is controlled to be the output circuit, so as to control the output voltage of the first connector by controlling the disconnection or conduction of the first circuit.

[0015] Preferably, a power supply control circuit with switchable input and output, wherein the first circuit includes a first field effect transistor chip, the source of the first field effect transistor chip is connected to the bus voltage, the drain of the first field effect transistor chip is connected to the first connector, the gate of the first field effect transistor chip is respectively connected to the input voltage and the collector of the first transistor, the emitter of the first transistor is connected to the ground terminal, and the base of the first transistor is connected to the controller.

[0016] Preferably, a power supply control circuit with switchable input and output, wherein the second circuit includes a second field effect transistor chip, the source of the second field effect transistor chip is connected to the bus voltage, the drain of the second field effect transistor chip is connected to the second connector, the gate of the second field effect transistor chip is respectively connected to the output voltage and the collector of the second transistor, the emitter of the second transistor is connected to the ground terminal, and the base of the second transistor is connected to the controller.

[0017] Preferably, in the power control circuit with switchable input and output, the first connector is a first connection chip, and the first connection chip includes:

[0018] A first pin, a second pin, a third pin, a fifth pin, and a sixth pin connected to a ground terminal; and

[0019] A fourth pin connected to the drain of the first field effect transistor chip through the first fuse.

[0020] Preferably, in the power control circuit with switchable input and output, the second connector is a second connection chip, and the second connection chip includes:

[0021] A first pin, a second pin, a third pin, a fifth pin, and a sixth pin connected to a ground terminal; and

[0022] A fourth pin connected to the drain of the second field effect transistor chip through the second fuse.

[0023] Preferably, the input and output of the power supply control circuit are switchable, wherein the controller is used to output a control signal;

[0024] When the first connector is the input end of the power supply and the control signal is a low level signal, the control signal controls the second transistor to be in a cut-off state, and the second transistor controls the second field effect transistor chip to be in a disconnected state, so that the output voltage of the second connector is 0V;

[0025] When the first connector is the input end of the power supply and the control signal is a high-level signal, the control signal controls the second transistor to be in a conducting state, and the second transistor controls the second field effect transistor chip to be in a conducting state, so that the output voltage of the second connector is associated with the power supply voltage of the bus voltage input, the voltage drop of the first field effect transistor chip, and the voltage drop of the second field effect transistor chip;

[0026] When the second connector is the input end of the power supply and the control signal is a low level signal, the control signal controls the first transistor to be in a cut-off state, and the first transistor controls the first field effect transistor chip to be in a disconnected state, so that the output voltage of the first connector is 0V;

[0027] When the second connector is the input end of the power supply and the control signal is a high-level signal, the control signal controls the first transistor to be in an on state, and the first transistor controls the first field effect transistor chip to be in an on state, so that the output voltage of the first connector is associated with the power supply voltage of the bus voltage input, the voltage drop of the first field effect transistor chip and the voltage drop of the second field effect transistor chip.

[0028] Preferably, the power supply control circuit with switchable input and output, wherein the first circuit further comprises:

[0029] A first resistor is connected between the gate of the first field effect transistor chip and the bus voltage;

[0030] A first capacitor is arranged in parallel with the first resistor;

[0031] A second capacitor is arranged in parallel with the first resistor;

[0032] A second resistor is connected between the gate of the first field effect transistor chip and the collector of the first transistor;

[0033] a third resistor connected between the base of the first transistor and the controller;

[0034] a fourth resistor, connected between the third resistor and the ground terminal;

[0035] The third capacitor is connected in parallel with the fourth resistor.

[0036] Preferably, in the power supply control circuit with switchable input and output, the second circuit further comprises:

[0037] a fifth resistor connected between the gate of the second field effect transistor chip and the bus voltage;

[0038] a fourth capacitor, arranged in parallel with the fifth resistor;

[0039] a fifth capacitor, arranged in parallel with the fifth resistor;

[0040] A sixth resistor is connected between the gate of the second field effect transistor chip and the collector of the second triode;

[0041] a seventh resistor connected between the base of the second transistor and the controller;

[0042] an eighth resistor, connected between the seventh resistor and the ground terminal;

[0043] The sixth capacitor is connected in parallel with the eighth resistor.

[0044] Preferably, in a power control circuit with switchable input and output, the first field effect transistor chip and the second field effect transistor chip are PMOS transistors.

[0045] Also included is a power supply control device with switchable input and output, which includes any of the power supply control circuits with switchable input and output as described above.

[0046] The above technical solution has the following advantages or beneficial effects:

[0047] First, when the first connector is the input end of the power supply, the output voltage of the second connector is controlled by controlling the disconnection or conduction of the second circuit; or

[0048] When the second connector is the input end of the power supply, the controller controls the disconnection or conduction of the first circuit to control the output voltage of the first connector;

[0049] Second, the input circuit and the output circuit of the first circuit and the second circuit can be interchanged, thereby realizing that the first connector and the second connector can use the same connector, thereby avoiding the phenomenon of wrongly plugging the connector interface;

[0050] Third, the controller controls the disconnection and conduction of the first transistor or the second transistor to control the disconnection and conduction of the first field effect transistor chip or the second field effect transistor chip, that is, by disconnecting and conducting the first circuit or the second circuit, the output voltage of the first circuit or the second circuit is controlled, thereby realizing the on and off control of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0052] Figure 1 A circuit diagram of a first circuit of an embodiment of a power supply control circuit with switchable input and output according to the present invention;

[0053] Figure 2 A circuit diagram of a second circuit of an embodiment of a power control circuit with switchable input and output according to the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0056] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0057] The present invention includes a power supply control circuit with switchable input and output, such as Figure 1-2 As shown, including:

[0058] A first connector P1;

[0059] A first circuit is connected to the first connector P1 and a power source respectively;

[0060] A second connector P2;

[0061] A second circuit is connected to the second connector P2 and a power source respectively;

[0062] A control circuit is connected to the first circuit and the second circuit respectively, and when the first connector is the input end of the power supply, the control circuit controls the second circuit to be the output circuit, so as to control the output voltage of the second connector by controlling the disconnection or conduction of the second circuit;

[0063] When the second connector is the input end of the power supply, the first circuit is controlled to be the output circuit, so as to control the output voltage of the first connector by controlling the disconnection or conduction of the first circuit.

[0064] In the above embodiment, when the first connector is the input end of the power supply, the output voltage of the second connector is controlled by controlling the disconnection or conduction of the second circuit; or

[0065] When the second connector is the input end of the power supply, the controller controls the disconnection or conduction of the first circuit to control the output voltage of the first connector;

[0066] Thus, the input circuit and the output circuit of the first circuit and the second circuit can be interchanged, and the first connector P1 and the second connector P2 can use the same connector, thereby avoiding the phenomenon of wrong connector interface insertion;

[0067] The controller controls the disconnection and conduction of the first transistor or the second transistor to control the disconnection and conduction of the first field effect transistor chip or the second field effect transistor chip, that is, by disconnecting and conducting the first circuit or the second circuit, the output voltage of the first circuit or the second circuit is controlled, thereby realizing the on-off control of the power supply.

[0068] Further, in the above embodiment, the first circuit includes a first field effect transistor chip Q1, the source of the first field effect transistor chip Q1 is connected to the bus voltage IN, the drain of the first field effect transistor chip Q1 is connected to the first connector P1, the gate G of the first field effect transistor chip Q1 is respectively connected to the input voltage and the collector of the first transistor Q3, the emitter of the first transistor Q3 is connected to the ground terminal, and the base of the first transistor Q3 is connected to the controller.

[0069] In the above embodiment, the bus voltage IN is used to input the power supply voltage, wherein the controller is powered by the power supply voltage after voltage transformation, wherein the control signal output by the controller will not affect the power supply of the controller.

[0070] In the above embodiment, the first field effect transistor chip Q1 includes:

[0071] A first source electrode S1 of the first field effect transistor chip Q1 is connected to the bus voltage IN;

[0072] The second source electrode S2 of the first field effect transistor chip Q1 is connected to the bus voltage IN;

[0073] The third source S3 of the first field effect transistor chip Q1 is connected to the bus voltage IN;

[0074] The first drain electrode D1 of the first field effect transistor chip Q1 is connected to the first connector P1;

[0075] The second drain electrode D2 of the first field effect transistor chip Q1 is connected to the first connector P1;

[0076] The third drain electrode D3 of the first field effect transistor chip Q1 is connected to the first connector P1;

[0077] The fourth drain electrode D4 of the first field effect transistor chip Q1 is connected to the first connector P1;

[0078] The gate G of the first field effect transistor chip Q1 is connected to the input voltage and the collector of the first transistor Q3 respectively.

[0079] As a preferred implementation, the model of the first field effect transistor chip Q1 may be PDS4909.

[0080] Further, in the above embodiment, the second circuit includes a second field effect transistor chip Q2, the source of the second field effect transistor chip Q2 is connected to the bus voltage IN, the drain of the second field effect transistor chip Q2 is connected to the second connector P2, the gate G of the second field effect transistor chip Q2 is respectively connected to the output voltage and the collector of the second transistor Q4, the emitter of the second transistor Q4 is connected to the ground terminal, and the base of the second transistor Q4 is connected to the controller.

[0081] In the above embodiment, the second field effect transistor chip Q2 includes:

[0082] A first source electrode S1 of the second field effect transistor chip Q2 is connected to the bus voltage IN;

[0083] The second source electrode S2 of the second field effect transistor chip Q2 is connected to the bus voltage IN;

[0084] The third source S3 of the second field effect transistor chip Q2 is connected to the bus voltage IN;

[0085] The first drain electrode D1 of the second field effect transistor chip Q2 is connected to the first connector P1;

[0086] The second drain electrode D2 of the second field effect transistor chip Q2 is connected to the first connector P1;

[0087] The third drain electrode D3 of the second field effect transistor chip Q2 is connected to the first connector P1;

[0088] The fourth drain electrode D4 of the second field effect transistor chip Q2 is connected to the first connector P1;

[0089] The gate G of the second field effect transistor chip Q2 is connected to the input voltage and the collector of the first transistor Q3 respectively.

[0090] As a preferred implementation, the model of the second field effect transistor chip Q2 may be PDS4909.

[0091] In the above embodiment, the first field effect transistor chip Q1 and the second field effect transistor chip Q2 are the same chip.

[0092] Further, in the above embodiment, the first connector P1 is a first connection chip, and the first connection chip includes:

[0093] A first pin, a second pin, a third pin, a fifth pin, and a sixth pin connected to a ground terminal; and

[0094] A fourth pin connected to the drain of the first field effect transistor chip Q1 through the first fuse F1.

[0095] In the above embodiment, the first fuse F1 is used to prevent the first circuit from being short-circuited, so as to protect the first circuit.

[0096] Further, in the above embodiment, the second connector P2 is a second connection chip, and the second connection chip includes:

[0097] A first pin, a second pin, a third pin, a fifth pin, and a sixth pin connected to a ground terminal; and

[0098] A fourth pin connected to the drain of the second field effect transistor chip Q2 through the second fuse F2.

[0099] In the above embodiment, the second fuse F2 is used to prevent the second circuit from being short-circuited, so as to protect the second circuit.

[0100] Further, in the above embodiment, the controller is used to output a control signal;

[0101] When the first connector is the input end of the power supply (the second connector is the output end of the power supply at this time), and the control signal is a low-level signal, the control signal controls the second transistor Q4 to be in a cut-off state, and the second transistor Q4 controls the second field effect transistor chip Q2 to be in a disconnected state, so that the output voltage of the second connector P2 is 0V;

[0102] In the above embodiment, when the first connector P1 is the input end of the power supply, the current flows as follows:

[0103] From the first connector P1 to the first field effect transistor chip Q1 to the bus voltage IN to the second field effect transistor chip Q2 to the second connector P2 (P1→Q1→IN→Q2→P2);

[0104] It should be noted that the current flow direction of the first field effect transistor chip Q1 and the second field effect transistor chip Q2 in the normal state is from the drain to the source and the gate;

[0105] When the control signal is at a low level, the second transistor Q4 connected to the second field effect transistor chip Q2 is in the cut-off area (that is, the second transistor Q4 is in the cut-off state), that is, the second transistor Q4 is disconnected, and at this time, there is no voltage drop in the second field effect transistor chip Q2 (that is, the voltage value between the gate G and the source S of the second field effect transistor chip Q2 is 0V), so the current flow direction of the second field effect transistor chip Q2 is still from the drain to the source and the gate, that is, the second field effect transistor chip Q2 is not turned on at this time, so the second field effect transistor chip Q2 is disconnected from the second connector P2, so that the output voltage of the second circuit is 0V.

[0106] Further, in the above embodiment, the controller is used to output a control signal;

[0107] When the first connector is the input end of the power supply (the second connector is the output end of the power supply at this time), the control signal controls the second transistor Q4 to be in the on state, and the second transistor Q4 controls the second field effect transistor chip Q2 to be in the on state, so that the output voltage of the second connector P2 is associated with the power supply voltage input by the bus voltage IN, the voltage drop of the first field effect transistor chip P1, and the voltage drop of the second field effect transistor chip P2;

[0108] In the above embodiment, when the first connector P1 is the input end of the power supply, the current flows as follows:

[0109] From the first connector P1 to the first field effect transistor chip Q1 to the bus voltage IN to the second field effect transistor chip Q2 to the second connector P2 (P1→Q1→IN→Q2→P2);

[0110] It should be noted that the current flow direction of the first field effect transistor chip Q1 and the second field effect transistor chip Q2 in the normal state is from the drain to the source and the gate;

[0111] When the control signal is at a high level, the second transistor Q4 connected to the second field effect transistor chip Q2 is in a saturation region (i.e., the second transistor Q4 is in a conducting state), i.e., the second transistor Q4 is turned on, and at this time, there is a voltage drop in the second field effect transistor chip Q2, so the current flow direction of the second field effect transistor chip Q2 can be changed from source to drain, i.e., the second field effect transistor chip Q2 is turned on at this time, so a path is formed between the second field effect transistor chip Q2 and the second connector P2; at this time, the output voltage of the second connector P2 is associated with the power supply voltage input by the bus voltage IN, the voltage drop of the first field effect transistor chip P1, and the voltage drop of the second field effect transistor chip P2, as shown in the following formula:

[0112] V P2 =V IN -V Q1d -V Q2d ; (1)

[0113] In the above formula (1), V P2 Used to indicate the output voltage of the second connector P2;

[0114] V IN Used to indicate the power supply voltage of the bus voltage IN input;

[0115] V Q1d Used to indicate the voltage drop of the first field effect transistor chip P1;

[0116] V Q2d Used to indicate the voltage drop of the second field effect transistor chip P2.

[0117] Further, in the above embodiment, the controller is used to output a control signal;

[0118] When the second connector P2 is the input end of the power supply and the control signal is a low level signal, the control signal controls the first transistor Q3 to be in a cut-off state, and the first transistor Q3 controls the first field effect transistor chip Q1 to be in a disconnected state, so that the output voltage of the first connector P1 is 0V;

[0119] In the above embodiment, when the second connector P2 is the input end of the power supply, the current flows as follows:

[0120] From the second connector P2 to the second field effect transistor chip Q2 to the bus voltage IN to the first field effect transistor chip Q1 to the first connector P1 (P2→Q2→IN→Q1→P1);

[0121] It should be noted that the current flow direction of the first field effect transistor chip Q1 and the second field effect transistor chip Q2 in the normal state is from the drain to the source and the gate;

[0122] When the control signal is at a low level, the first transistor Q3 connected to the first field effect transistor chip Q1 is in the cut-off area (that is, the first transistor Q3 is in the cut-off state), that is, the first transistor Q3 is disconnected, and at this time, there is no voltage drop in the first field effect transistor chip Q1 (that is, the voltage value between the gate G and the source S of the first field effect transistor chip Q1 is 0V), so the current flow direction of the first field effect transistor chip Q1 is still from the drain to the source and the gate, that is, the first field effect transistor chip Q1 is not turned on at this time, so the first field effect transistor chip Q1 is disconnected from the first connector P1, so that the output voltage of the first circuit is 0V.

[0123] Further, in the above embodiment, the controller is used to output a control signal;

[0124] When the second connector P2 is the input end of the power supply and the control signal is a high-level signal, the control signal controls the first transistor Q3 to be in an on state, and the first transistor Q3 controls the first field effect transistor chip Q1 to be in an on state, so that the output voltage of the first connector P1 is associated with the power supply voltage input by the bus voltage IN, the voltage drop of the first field effect transistor chip Q1, and the voltage drop of the second field effect transistor chip Q2.

[0125] In the above embodiment, when the second connector P2 is the input end of the power supply, the current flows as follows:

[0126] From the second connector P2 to the second field effect transistor chip Q2 to the bus voltage IN to the first field effect transistor chip Q1 to the first connector P1 (P2→Q2→IN→Q1→P1);

[0127] It should be noted that the current flow direction of the first field effect transistor chip Q1 and the second field effect transistor chip Q2 in the normal state is from the drain to the source and the gate;

[0128] When the control signal is at a high level, the first transistor Q3 connected to the first field effect transistor chip Q1 is in a saturation region (i.e., the first transistor Q3 is in a conducting state), i.e., the first transistor Q3 is turned on, and at this time, there is a voltage drop in the first field effect transistor chip Q1, so the current flow direction of the first field effect transistor chip Q1 can be changed from source to drain, i.e., the first field effect transistor chip Q1 is turned on at this time, so a path is formed between the first field effect transistor chip Q1 and the first connector P2; at this time, the output voltage of the first connector P2 is associated with the power supply voltage input by the bus voltage IN, the voltage drop of the first field effect transistor chip P1, and the voltage drop of the second field effect transistor chip P2, as shown in the following formula:

[0129] V P1 =V IN -V Q1d -V Q2d ; (2)

[0130] In the above formula (2), V P1 Used to indicate the output voltage of the first connector P1;

[0131] V IN Used to indicate the power supply voltage of the bus voltage IN input;

[0132] V Q1d Used to indicate the voltage drop of the first field effect transistor chip P1;

[0133] V Q2d Used to indicate the voltage drop of the second field effect transistor chip P2.

[0134] Furthermore, in the above embodiment, the first circuit further includes:

[0135] A first resistor R1 is connected between the gate G of the first field effect transistor chip Q1 and the bus voltage IN;

[0136] A first capacitor C1 is arranged in parallel with the first resistor R1;

[0137] A second capacitor C2 is arranged in parallel with the first resistor R1;

[0138] The second resistor R2 is connected between the gate G of the first field effect transistor chip Q1 and the collector of the first transistor Q3;

[0139] A third resistor R3 is connected between the base of the first transistor Q3 and the controller;

[0140] a fourth resistor R4 connected between the third resistor R3 and the ground terminal;

[0141] The third capacitor C3 is connected in parallel with the fourth resistor R4.

[0142] Furthermore, in the above embodiment, the second circuit further includes:

[0143] A fifth resistor R5 is connected between the gate G of the second field effect transistor chip Q2 and the bus voltage IN;

[0144] A fourth capacitor C4 is arranged in parallel with the fifth resistor R5;

[0145] A fifth capacitor C5 is arranged in parallel with the fifth resistor R5;

[0146] A sixth resistor R6 is connected between the gate G of the second field effect transistor chip Q2 and the collector of the second transistor Q4;

[0147] A seventh resistor R7 is connected between the base of the second transistor Q4 and the controller;

[0148] an eighth resistor R8, connected between the seventh resistor R7 and the ground terminal;

[0149] The sixth capacitor C6 is connected in parallel with the eighth resistor R8.

[0150] Furthermore, in the above embodiment, the first field effect transistor chip Q1 and the second field effect transistor chip Q2 are PMOS transistors.

[0151] Furthermore, in the above embodiment, the first transistor Q3 and the second transistor Q4 are NPN transistors.

[0152] In the above embodiment, the first transistor Q3 is used to change the voltage value of the first field effect transistor chip Q1;

[0153] The second transistor Q4 is used to change the voltage value of the second field effect transistor chip Q2.

[0154] Also included is a power supply control device with switchable input and output, which includes any of the power supply control circuits with switchable input and output as described above.

[0155] The specific implementation of the power supply control device with switchable input and output of the present invention is basically the same as the above-mentioned embodiments of the power supply control circuit with switchable input and output, and will not be described in detail here.

[0156] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A power supply control circuit with switchable input and output, characterized in that: include: a first connector; A first circuit is connected to the first connector and a power source respectively; a second connector; a second circuit connected to the second connector and a power source respectively; a control circuit connected to the first circuit and the second circuit respectively, and controlling the output voltage of the second connector by controlling the disconnection or conduction of the second circuit when the first connector is the input end of the power supply; When the second connector is an input end of a power source, the output voltage of the first connector is controlled by controlling the disconnection or conduction of the first circuit; The first circuit comprises a first field effect transistor chip, the source of the first field effect transistor chip is connected to the bus voltage, the drain of the first field effect transistor chip is connected to the first connector, the gate of the first field effect transistor chip is respectively connected to the input voltage and the collector of the first transistor, the emitter of the first transistor is connected to the ground terminal, and the base of the first transistor is connected to the control circuit; The second circuit comprises a second field effect transistor chip, the source of the second field effect transistor chip is connected to the bus voltage, the drain of the second field effect transistor chip is connected to the second connector, the gate of the second field effect transistor chip is respectively connected to the output voltage and the collector of the second triode, the emitter of the second triode is connected to the ground terminal, and the base of the second triode is connected to the control circuit; The control circuit is used to output a control signal; When the first connector is the input end of the power supply and the control signal is a low level signal, the control signal controls the second transistor to be in a cut-off state, and the second transistor controls the second field effect transistor chip to be in a disconnected state, so that the output voltage of the second connector is 0V; When the first connector is an input end of a power supply and the control signal is a high-level signal, the control signal controls the second transistor to be in an on state, and the second transistor controls the second field effect transistor chip to be in an on state, so that the output voltage of the second connector is associated with the power supply voltage of the bus voltage input, the voltage drop of the first field effect transistor chip, and the voltage drop of the second field effect transistor chip; When the second connector is the input end of the power supply and the control signal is a low level signal, the control signal controls the first transistor to be in a cut-off state, and the first transistor controls the first field effect transistor chip to be in a disconnected state, so that the output voltage of the first connector is 0V; When the second connector is the input end of the power supply and the control signal is a high-level signal, the control signal controls the first transistor to be in an on state, and the first transistor controls the first field effect transistor chip to be in an on state, so that the output voltage of the first connector is associated with the power supply voltage of the bus voltage input, the voltage drop of the first field effect transistor chip, and the voltage drop of the second field effect transistor chip.

2. The power supply control circuit with switchable input and output as claimed in claim 1, characterized in that: The first connector is a first connection chip, and the first connection chip includes: A first pin, a second pin, a third pin, a fifth pin, and a sixth pin connected to a ground terminal; and A fourth pin connected to the drain of the first field effect transistor chip through the first fuse.

3. The power supply control circuit with switchable input and output as claimed in claim 2, characterized in that: The second connector is a second connection chip, and the second connection chip includes: A first pin, a second pin, a third pin, a fifth pin, and a sixth pin connected to a ground terminal; and A fourth pin connected to the drain of the second field effect transistor chip through a second fuse.

4. The power supply control circuit with switchable input and output as claimed in claim 1, characterized in that: The first circuit further comprises: A first resistor is connected between the gate of the first field effect transistor chip and the bus voltage; A first capacitor is arranged in parallel with the first resistor; A second capacitor is arranged in parallel with the first resistor; a second resistor connected between the gate of the first field effect transistor chip and the collector of the first transistor; A third resistor is connected between the base of the first transistor and the controller; a fourth resistor, connected between the third resistor and the ground terminal; The third capacitor is connected in parallel with the fourth resistor.

5. The power supply control circuit with switchable input and output as claimed in claim 1, characterized in that: The second circuit further includes: a fifth resistor, connected between the gate of the second field effect transistor chip and the bus voltage; a fourth capacitor, arranged in parallel with the fifth resistor; a fifth capacitor, arranged in parallel with the fifth resistor; a sixth resistor, connected between the gate of the second field effect transistor chip and the collector of the second transistor; a seventh resistor connected between the base of the second transistor and the controller; an eighth resistor, connected between the seventh resistor and the ground terminal; A sixth capacitor is connected in parallel with the eighth resistor.

6. The power supply control circuit with switchable input and output as claimed in claim 1, characterized in that: The first field effect transistor chip and the second field effect transistor chip are PMOS transistors.

7. A power supply control device with switchable input and output, characterized in that: A power supply control circuit with switchable input and output comprising the power supply control circuit as claimed in any one of claims 1 to 6.

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