Semiconductor device

Abstract

A semiconductor device is provided to correct threshold voltage to improve operation accuracy. The semiconductor device includes a first current source circuit and a second current source circuit having the same structure as the first current source circuit. The first current source circuit includes a first transistor, a second transistor, a first capacitor, and first to third nodes. A first terminal of the first transistor is electrically connected to the first node, and a back gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitor. A gate of the first transistor is electrically connected to a second node, and a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor. The first node of the first current source circuit is electrically connected to second nodes of the first and second current source circuits. A threshold voltage of the first transistor is changed by writing a correction voltage to the back gate of the first transistor.

Description

Technical Field

[0001] This specification relates to semiconductor devices, their operating methods, and manufacturing methods. For example, one embodiment of the present invention relates to technical fields such as semiconductor devices, storage devices, processing devices, imaging devices, switching circuits (e.g., power switches, wiring switches, etc.), display devices (e.g., liquid crystal display devices, organic electroluminescent displays, etc.), light-emitting devices, lighting devices, power storage devices, and input devices. Furthermore, their operating methods, manufacturing methods, and methods of use are also included. Background Art

[0002] Metal oxides are attracting attention as semiconductors that can be used in transistors. In-Ga-Zn oxides, also known as "IGZO," are typical examples of multi-component metal oxides. Research on IGZO has revealed CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystal nor amorphous (e.g., Non-Patent Document 1).

[0003] There are reports that transistors containing a metal oxide semiconductor in the channel formation region (hereinafter sometimes referred to as "oxide semiconductor transistors" or "OS transistors") have extremely small off-state currents (e.g., non-patent documents 1 and 2). In addition, various semiconductor devices using OS transistors (e.g., non-patent documents 3 and 4) have been manufactured. The manufacturing process of OS transistors can be included in the existing CMOS process of Si transistors, and OS transistors can be stacked on Si transistors (e.g., non-patent document 4). In addition, Patent Document 1 discloses performing product-sum operations using a memory cell using an OS transistor.

[0004] [Prior technical literature]

[0005] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2017-168099

[0007] [Non-patent literature]

[0008] [Non-patent document 1] S.Yamazaki et al., "Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics," Jpn.J.Appl.Phys., vol.53, 04ED18 (2014).

[0009] [Non-patent document 2] K. Kato et al., "Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide," Jpn.J.Appl.Phys., vol.51, 021201 (2012).

[0010] [Non-patent document 3] S.Amano et al., "Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency," SID Symp.Dig.Papers, vol.41, pp.626-629 (2010).

[0011] [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: AKey Enabler for Low-Power ULSI,” ECS Tran., vol. 79, pp. 149-156 (2017). Summary of the Invention

[0012] Technical problem to be solved by the invention

[0013] Transistors have two polarity types: n-channel and p-channel. Circuits that combine n-channel and p-channel transistors are called complementary circuits, CMOS circuits, etc. On the other hand, circuits that use only n-channel or p-channel transistors of a single conductivity type are called unipolar circuits, single conductivity circuits, etc. Circuits that use only n-channel transistors are sometimes called NMOS circuits, and circuits that use only p-channel transistors are sometimes called PMOS circuits.

[0014] In Si transistors, the polarity can be selected as either n-channel or p-channel depending on the type of impurity doped in the semiconductor layer. On the other hand, for example, when using metal oxides containing indium (e.g., In oxide) or metal oxides containing zinc (e.g., Zn oxide), although n-type semiconductors can be produced, it is difficult to produce p-type semiconductors from the perspective of mobility and reliability. Therefore, circuits composed of OS transistors are mostly n-channel unipolar circuits.

[0015] When constructing unipolar circuits, the number of transistors tends to increase, resulting in circuit scale that is sometimes larger than that of CMOS circuits. Furthermore, the large number of transistors in unipolar circuits can increase heat generation within the circuit itself, causing changes in transistor characteristics. Furthermore, the large number of transistors in unipolar circuits can increase the variation in transistor characteristics (particularly, threshold voltage) during circuit manufacturing.

[0016] One object of one embodiment of the present invention is to provide a semiconductor device that is a unipolar circuit. Another object of one embodiment of the present invention is to provide a semiconductor device that can perform arithmetic processing. Another object of one embodiment of the present invention is to provide a semiconductor device that corrects the threshold voltage of a transistor to improve arithmetic accuracy. Another object of one embodiment of the present invention is to provide a semiconductor device that reduces the effects of ambient temperature.

[0017] Note that the purpose of one embodiment of the present invention is not limited to the purpose listed above. The purposes listed above do not preclude the existence of other purposes. In addition, other purposes are purposes not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purposes and other purposes. In addition, one embodiment of the present invention does not necessarily achieve all of the above-mentioned purposes and other purposes.

[0018] Means of solving technical problems (1)

[0020] One embodiment of the present invention is a semiconductor device including a first current source circuit and a second current source circuit. The second current source circuit has the same structure as the first current source circuit. The first current source circuit includes first to fourth transistors, a first capacitor, a second capacitor, and first to third nodes. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first node. The back gate of the first transistor is electrically connected to the first terminal of the third transistor and the first terminal of the first capacitor. The second terminal of the third transistor is electrically connected to the second node. The gate of the first transistor is electrically connected to the third node. The second terminal of the first capacitor is electrically connected to the second terminal of the first transistor. The gate of the second transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the second capacitor. The second terminal of the second capacitor is electrically connected to the first terminal of the second transistor. The first current source circuit has a function of writing a first correction voltage from the second node to the back gate of the first transistor to change the threshold voltage of the first transistor when the third transistor is in an on state, and a function of maintaining the voltage between the second terminal and the back gate of the first transistor using the first capacitor when the third transistor is in an off state. The first node of the first current source circuit is electrically connected to the third node of the first current source circuit and the third node of the second current source circuit. (2)

[0022] Furthermore, one embodiment of the present invention is a semiconductor device including a first current source circuit and a second current source circuit, the second current source circuit having the same structure as the first current source circuit, the first current source circuit including first to fifth transistors, a first capacitor, a second capacitor, and first to fifth nodes, the first terminal of the first transistor being electrically connected to the first terminal of the fifth transistor and the fifth node, the first terminal of the second transistor being electrically connected to the second terminal of the fifth transistor and the first node, the back gate of the first transistor being electrically connected to the first terminal of the third transistor and the first terminal of the first capacitor, the second terminal of the third transistor being electrically connected to the second node, the gate of the first transistor being electrically connected to the third node, the second terminal of the first capacitor being electrically connected to the second terminal of the first transistor, and the gate of the fifth transistor being electrically connected to the first terminal of the first transistor. The electrode is electrically connected to the fourth node, the gate of the second transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the first terminal of the second transistor, the first current source circuit has a function of writing a first correction voltage from the second node to the back gate of the first transistor to change the threshold voltage of the first transistor when the third transistor is in the on state and a function of using the first capacitor to maintain the voltage between the second terminal and the back gate of the first transistor when the third transistor is in the off state, the first node of the first current source circuit is electrically connected to the fourth node of the first current source circuit and the fourth node of the second current source circuit, and the fifth node of the first current source circuit is electrically connected to the third node of the first current source circuit and the third node of the second current source circuit. (3)

[0024] In addition, in the semiconductor device having the above-mentioned structure (2), the first current source circuit includes a sixth transistor, the first terminal of the sixth transistor is electrically connected to the first terminal of the first transistor, and the first current source circuit has a function of monitoring the current flowing between the second terminal of the first transistor and the second terminal of the sixth transistor when the fifth transistor is in the off state and the sixth transistor is in the on state to set the first correction voltage according to the current. (4)

[0026] Furthermore, in a semiconductor device having any one of the above-mentioned structures (1) to (3), a first circuit, a second circuit, and a readout circuit are included, the first circuit being electrically connected to a first node of the first current source circuit, the second circuit being electrically connected to a first node of the second current source circuit, the readout circuit being electrically connected to a first node of the second current source circuit, the first circuit having a function of absorbing a first current or a second current from the first node of the first current source circuit, the second circuit having a function of absorbing a third current or a fourth current from the first node of the second current source circuit, the second transistor of the first current source circuit having a function of causing a fifth current to flow according to a gate-source voltage of the second transistor of the first current source circuit when absorbing the first current from the first node of the first current source circuit, and the first transistor of the first current source circuit having a function of causing a first difference current between the fifth current and the first current to flow when absorbing the first current from the first node of the first current source circuit The first transistor of the second current source circuit has a function of causing the first difference current to flow when absorbing the first current from the first node of the first current source circuit and a function of causing the second difference current to flow when absorbing the second current from the first node of the first current source circuit. The second transistor of the second current source circuit has a function of causing a sixth current to flow according to the gate-source voltage of the second transistor of the second current source circuit when absorbing the third current and the first difference current from the first node of the second current source circuit, and the readout circuit has a function of absorbing a seventh current obtained by subtracting the sum of the second difference current and the fourth current from the sixth current when the first current absorbed from the first node of the first current source circuit becomes the second current and the third current absorbed from the first node of the second current source circuit becomes the fourth current. (5)

[0028] Furthermore, in the semiconductor device having the above-mentioned structure (4), the second circuit has the same structure as the first circuit, the first circuit includes a seventh transistor, an eighth transistor, and a third capacitor, the gate of the seventh transistor is electrically connected to the first terminal of the eighth transistor and the first terminal of the third capacitor, the first terminal of the seventh transistor of the first circuit is electrically connected to the first node of the first current source circuit, the first terminal of the seventh transistor of the second circuit is electrically connected to the first node of the second current source circuit, the seventh transistor of the first circuit has a function of causing a first current to flow when a first potential is applied to the gate of the seventh transistor of the first circuit and a second potential is applied to the second terminal of the third capacitor, and the first terminal of the seventh transistor of the first circuit is electrically connected to the first node of the second current source circuit. The seventh transistor has a function of causing a second current to flow when a first potential is applied to the gate of the seventh transistor and a third potential is applied to the second terminal of the third capacitor. The seventh transistor of the second circuit has a function of causing a third current to flow when a fourth potential is applied to the gate of the seventh transistor of the second circuit and the second potential is applied to the second terminal of the third capacitor, and has a function of causing a fourth current to flow when a fourth potential is applied to the gate of the seventh transistor of the second circuit and the third potential is applied to the second terminal of the third capacitor. The difference between the first potential and the fourth potential is a potential difference corresponding to the first data, the difference between the second potential and the third potential is a potential difference corresponding to the second data, and the seventh current is a current corresponding to the product of the first and second data. (6)

[0030] In addition, in a semiconductor device having the above-mentioned structure (5), the first circuit includes a ninth transistor and a fourth capacitor, the seventh transistor has a back gate, the back gate of the seventh transistor is electrically connected to the first terminal of the ninth transistor and the first terminal of the fourth capacitor, the second terminal of the fourth capacitor is electrically connected to the second terminal of the seventh transistor, and the first circuit has a function of writing a second correction voltage from the second terminal of the ninth transistor to the back gate of the seventh transistor to change the threshold voltage of the seventh transistor when the ninth transistor is in an on state, and a function of maintaining the voltage between the second terminal and the back gate of the seventh transistor using the fourth capacitor when the ninth transistor is in an off state. (7)

[0032] Furthermore, in the semiconductor device having any one of the above structures (1) to (6), the first current source circuit includes a fifth capacitor, and a first terminal of the fifth capacitor is electrically connected to the gate of the second transistor. (8)

[0034] In addition, in a semiconductor device having any one of the above-mentioned structures (1) to (6), the first circuit includes a tenth transistor, the source and the drain of the tenth transistor are electrically connected to each other, one of the gate and the source of the tenth transistor is electrically connected to the gate of the second transistor, and the channel width of the tenth transistor is less than 0.5 times the channel width of the fourth transistor. (9)

[0036] Furthermore, all transistors included in the semiconductor device having any one of the above-described structures (1) to (8) contain metal oxide in the channel formation region and have the same polarity.

[0037] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit that includes a semiconductor element (transistor, diode, photodiode, etc.), and a device that includes such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, examples of semiconductor devices include integrated circuits, semiconductor wafers with integrated circuits, chips, and electronic components that contain chips in packages. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, or sometimes include semiconductor devices.

[0038] In this specification, the phrase "X and Y are connected" indicates that the following are disclosed: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the drawings or text, and other connection relationships may also be included. X and Y are both objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0039] A transistor includes three terminals: a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Of the two input and output terminals, one terminal is used as the source and the other terminal is used as the drain, depending on the conductivity type of the transistor (n-channel or p-channel) and the potential supplied to the three terminals of the transistor. Therefore, in this specification, etc., "source" and "drain" can be interchanged. In addition, in this specification, etc., the two terminals other than the gate are sometimes referred to as the first terminal and the second terminal.

[0040] A node may also be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit structure or device structure, etc. In addition, a terminal, a wiring, etc. may also be referred to as a node.

[0041] Voltage generally refers to the difference between a certain potential and a standard potential (e.g., ground potential (GND) or source potential). Therefore, voltage can also be called potential. Potential is relative. Therefore, even if it is written as "GND," it does not necessarily mean 0V.

[0042] In this specification, etc., ordinal numbers such as "first," "second," and "third" may be used to indicate order. Furthermore, ordinal numbers may be used to avoid confusion between constituent elements. In these cases, the ordinal numbers do not limit the number or order of constituent elements in one embodiment of the invention. For example, "first" may be replaced with "second" or "third" to describe one embodiment of the invention.

[0043] For convenience, in this specification, terms such as "upper" and "lower" may be used to describe the positional relationships of components with reference to the accompanying drawings. Furthermore, the positional relationships of components may vary depending on the orientation in which the components are described. Therefore, the terms and phrases described in this specification are not limited to those used in this specification and may be substituted as appropriate.

[0044] In this specification, "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be interchanged with "conductive film". For example, "insulating film" may be interchanged with "insulating layer".

[0045] In the drawings, dimensions, layer thicknesses, and regions are sometimes exaggerated for clarity. Therefore, the present invention is not necessarily limited to the dimensions shown above. The drawings schematically illustrate idealized examples and are not limited to the shapes or numerical values ​​shown. For example, variations in signals, voltages, or currents due to noise or timing variations may be present.

[0046] Effects of the Invention

[0047] According to one embodiment of the present invention, a semiconductor device that functions as a unipolar circuit can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of performing arithmetic processing can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device that corrects the threshold voltage of a transistor to improve arithmetic accuracy can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device that mitigates the effects of ambient temperature can be provided.

[0048] Note that the effects of one embodiment of the present invention are not limited to the effects described above. The effects listed above do not preclude the existence of other effects. In addition, other effects are effects not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention has at least one of the effects described above and other effects. Therefore, one embodiment of the present invention may not have the effects mentioned above depending on the circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0050] Figure 2A is a timing chart illustrating an operation example of a circuit included in a semiconductor device, Figure 2B 、 Figure 2C and Figure 2D is a circuit diagram illustrating an operation example of a circuit included in a semiconductor device.

[0051] Figure 3A 、 Figure 3B and Figure 3C is a circuit diagram illustrating an operation example of a circuit included in a semiconductor device.

[0052] Figure 4A is a circuit diagram showing a structural example of a circuit included in a semiconductor device, Figure 4B is a block diagram showing a structural example of a semiconductor device.

[0053] Figure 5A is a circuit diagram showing a structural example of a circuit included in a semiconductor device, Figure 5B is a block diagram showing a structural example of a circuit included in a semiconductor device.

[0054] Figure 6 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0055] Figure 7 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0056] Figure 8 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0057] Figure 9 is a block diagram showing a structural example of a circuit included in a semiconductor device.

[0058] Figure 10 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0059] Figure 11 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0060] Figure 12 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0061] Figure 13 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0062] Figure 14 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0063] Figure 15 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0064] Figure 16 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0065] Figure 17 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0066] Figure 18 is a diagram illustrating an example of a hierarchical neural network.

[0067] Figure 19 is a block diagram showing a structural example of a circuit included in a semiconductor device.

[0068] Figure 20 is a block diagram showing a structural example of a circuit included in a semiconductor device.

[0069] Figure 21 is a block diagram showing a structural example of a circuit included in a semiconductor device.

[0070] Figure 22A and Figure 22B is a block diagram showing a structural example of a circuit included in a semiconductor device.

[0071] Figure 23 is a cross-sectional view showing a structural example of a semiconductor device.

[0072] Figure 24 is a cross-sectional view showing a structural example of a semiconductor device.

[0073] Figure 25A 、 Figure 25B and Figure 25C is a cross-sectional view showing a structural example of a transistor.

[0074] Figure 26A is a top view showing a structural example of a transistor, Figure 26B and Figure 26C is a cross-sectional view showing a structural example of a transistor.

[0075] Figure 27A is a top view showing a structural example of a transistor, Figure 27B and Figure 27C is a cross-sectional view showing a structural example of a transistor.

[0076] Figure 28A is a top view showing a structural example of a transistor, Figure 28B and Figure 28Cis a cross-sectional view showing a structural example of a transistor.

[0077] Figure 29A is a top view showing a structural example of a transistor, Figure 29B and Figure 29C is a cross-sectional view showing a structural example of a transistor.

[0078] Figure 30A is a top view showing a structural example of a transistor, Figure 30B and Figure 30C is a cross-sectional view showing a structural example of a transistor.

[0079] Figure 31A is a top view showing a structural example of a transistor, Figure 31B is a perspective view showing a structural example of a transistor.

[0080] Figure 32A and Figure 32B is a cross-sectional view showing a structural example of a transistor.

[0081] Figure 33A is a top view showing a structural example of a capacitor, Figure 33B and Figure 33C is a cross-sectional perspective view showing a structural example of a capacitor.

[0082] Figure 34A is a top view showing a structural example of a capacitor, Figure 34B is a cross-sectional view showing a structural example of a capacitor, Figure 34C is a cross-sectional perspective view showing a structural example of a capacitor.

[0083] Figure 35A 、 Figure 35B 、 Figure 35C 、 Figure 35D 、 Figure 35E 、 Figure 35F 、 Figure 35G and Figure 35H It is a perspective view showing an example of an electronic device.

[0084] Figure 36A and Figure 36B It is a perspective view showing an example of an electronic device. DETAILED DESCRIPTION

[0085] The following describes an embodiment with reference to the accompanying drawings. Note that one embodiment of the present invention is not limited to the following description. A person skilled in the art will readily understand that the embodiment and details can be modified in various forms without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be construed as being limited to the following embodiment.

[0086] The multiple embodiments shown below can be appropriately combined. In addition, when multiple structural examples (including manufacturing method examples, working method examples, and usage method examples, etc.) are shown in one embodiment, these structural examples can be appropriately combined with each other, and can also be appropriately combined with one or more structural examples in other embodiments.

[0087] In the drawings, the same reference numerals may be used to indicate the same elements, elements having the same function, elements made of the same material, or elements formed simultaneously, and repeated description may be omitted.

[0088] When the same symbol is used for multiple elements and they need to be distinguished, a symbol for identification such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0089] In this specification, the power supply potential VDD may be simply referred to as potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, and wiring, etc.).

[0090] (Implementation 1)

[0091] In this embodiment, a unipolar circuit having a data storage function included in a semiconductor device will be described.

[0092] Figure 1 Circuit 10 shown includes circuit 15, circuit 17, node ss, node bgc, node bw, node ww, node vx, node ot1, node wb, node vb1, node ga, and node st. Node ss is electrically connected to a voltage line for supplying voltage VSS, and node bgc is electrically connected to a voltage line for supplying VBGC1. Voltage VSS is the low power supply voltage of circuit 10 and can be a low-level ("L") voltage applied to nodes ww and wb, etc. Furthermore, voltage VDD is the high power supply voltage of circuit 10 and can be a high-level ("H") voltage applied to nodes ww and wb, etc.

[0093] Circuit 15 includes transistor M1, transistor M2, and capacitor C1. Circuit 17 includes transistors M3 to M5 and capacitor C3. Transistors M1 to M5 are OS transistors with back gates. The back gates of transistors M2, M3, and M5 are input with voltage VBGC1 via node bgc. Voltage VBGC1 can be used to adjust the threshold voltage (Vth) of transistors M2, M3, and M5. The on and off states of transistors M2 to M5 can be switched based on the voltages of nodes ww, wb, ga, and st.

[0094] Circuit 15 has the same circuit structure as a 2T (2-transistor) gain cell. In this specification, the storage node of circuit 15 is referred to as node sn1. That is, the gate of transistor M1 corresponds to node sn1. Transistor M1 is the readout transistor in the 2T gain cell. Node ot1 is the output node. The nodes corresponding to the backgate and source of transistor M1 are referred to as node mb1 and node ms1, respectively.

[0095] Capacitor C1 is a storage capacitor used to maintain the voltage at node sn1. Capacitor C1 capacitively couples node sn1 and node vx. Transistor M2 is an access transistor (also called a write transistor) in the 2T gain cell and has the function of turning node sn1 and node bw on and off.

[0096] Circuit 15 can be used as a storage circuit. To write data, for example, node vx is set to "L" and a voltage corresponding to the data is input to node bw. Next, transistor M2 is turned on, and the voltage at node bw is input to node sn1. To read data, node vx is set to "H" and node ms1 is set to a constant potential, for example, VSS. Consequently, a drain current influenced by the voltage at node sn1 flows through transistor M1, causing the voltage at node ot1 to change according to the drain current of transistor M1. Data can be read by detecting the voltage at node ot1.

[0097] By utilizing the Vds-Id characteristic of the transistor M1, the circuit 15 can be used as a multiplication circuit. Note that Vds is the drain-source voltage, and Id is the drain current.

[0098] The calculation function of circuit 15 will be described using the multiplication of w and d as an example. Data corresponding to the multiplier and multiplicand are input to circuit 15 as voltages. For convenience, the voltages corresponding to w and d are referred to as voltage w and voltage d, respectively. Furthermore, to simplify the description of the calculation function of circuit 15, voltage VSS is assumed to be 0V.

[0099] First, voltage w is input to circuit 15. Specifically, voltage VSS is input to node vx, and voltage w is input to node bw. Next, node ww is set to "H," turning on transistor M2. This causes voltage w to be input to node sn1. Next, while node ww is set to "L," voltage d is input to node vx. Because node vx and node sn1 are capacitively coupled, the voltage at node sn1 becomes w + A. sn d. Here, A sn is the capacitive coupling coefficient between the node sn1 and the node vx, and is affected by the gate capacitance of the transistor M1, the parasitic capacitance of the node sn1, and the like.

[0100] [Formula 1]

[0101]

[0102] When a transistor operates in the saturation region, the drain current Id is expressed as shown in the above equation (1.1) based on the graded channel approximation model. β is a constant that depends on the carrier mobility in the semiconductor, the channel length, the channel width, and the gate capacitance. Vgs is the gate-source voltage, and Vth is the threshold voltage.

[0103] Note that in this specification and other documents, the threshold voltage Vth is Vgs-Id, where the voltage Vgs and the square root of the drain current Id are plotted on the horizontal and vertical axes, respectively. 1 / 2 The tangent line of the characteristic curve with the maximum slope and Id 1 / 2 =0A intersection voltage Vgs. Alternatively, when the ratio of the channel length / channel width of the transistor is L / W, the threshold voltage Vth is sometimes referred to as Id×L / W = 1×10 -12 [A] is the voltage Vgs. In addition, L and W represent the channel length and channel width of the transistor, respectively.

[0104] For convenience, the back gate-source voltage (Vbgs) of transistor M1 is fixed to Vc, and the threshold voltage of transistor M1 is set to V T1 When the transistor M1 operates in the saturation region and the voltage Vgs is w+A sn When d, the drain current Id1(w, d) of the transistor M1 is expressed by the following formula (2.1).

[0105] [Formula 2]

[0106]

[0107] As shown in the following formulas (2.2) to (2.4), the drain current Id1 (w, d) is represented by the sum of the current Ipr (w, d) which is proportional to the product w·d and the current Iost (w, d) which is not proportional.

[0108] [Formula 3]

[0109] Id1(w, d)=Ipr(w, d)+Iost(w, d) ...(2.2)

[0110] Ipr(w, d) = A sn βwd …(2.3)

[0111]

[0112] When the first term on the right side of formula (2.4) corresponds to the drain current Id1 when the voltage d is 0 V, the second term on the right side corresponds to the drain current Id1 when the voltage w is 0 V. Therefore, the current Iost(w, d) is expressed by formula (2.5).

[0113] [Formula 4]

[0114]

[0115] By subtracting the current Iost(w, d) from the drain current Id1(w, d), the current Ipr(w, d) can be obtained. In this specification, etc., the current Iost(w, d) may be referred to as the "offset current." Furthermore, the operation of subtracting the offset current from the current Id1(w, d) is referred to as "offset cancellation."

[0116] For example, currents I1 to I4 are defined as shown in equations (2.6) to (2.9). Then, by executing equation (2.10), current Ipr(w, d) can be obtained.

[0117] [Formula 5]

[0118] I1=Id1(w0+w,d0+d)…(2.6)

[0119] I2=Id1(w0,d0+d) …(2.7)

[0120] I3=Id1(w0+w,d0) …(2.8)

[0121] I4=Id1(w0,d0) …(2.9)

[0122] I1-I3+I4-I2 …(2.10)

[0123] The calculation process of the formula (2.10) is shown below. In Embodiments 2 to 5, the hardware used to execute the formula (2.10) is described.

[0124] [Formula 6]

[0125]

[0126] The circuit 15 may be an analog operation circuit using the Vds-Id characteristic of the transistor M1. In addition, when a plurality of circuits 15 are used for operation, the threshold voltage V T1 Sometimes unevenness occurs, which reduces the accuracy of the operation. In view of this, the threshold voltage V is corrected using circuit 17. T1To correct the threshold voltage of transistor M1 , the drain current Id1 can be used to charge capacitor C3 to adjust Vbgs of transistor M1 . Therefore, circuit 17 can be referred to as a “current-programmed circuit.”

[0127] Figure 2A This is the timing diagram of threshold voltage correction. Figures 2B to 2D 、 Figure 3A 、 Figure 3B 1 and 2 are circuit diagrams illustrating an example of the operation of circuit 10 during periods T1 to T4 of the timing chart. In these diagrams, transistors M3 to M5 are shown as switches. To facilitate understanding of the operation of circuit 10, leakage currents of transistors M1 to M5, capacitor C1, capacitor C3, and the like are not considered in the following description.

[0128] During the threshold voltage correction period, for example, the transistor M2 is in the off state, and the voltages of the node vx and the node ot1 are VSS and V1, respectively.

[0129] During the period T1, the potentials of the nodes ga, wb, and st are "H," "L," and "L," respectively. Figure 2B As shown, transistor M4 is turned on, and voltage VSS is input to node ms1. In addition, voltage V0 is input to node vb1.

[0130] Next, during period T2, the nodes ga, wb, and st become "L," "H," and "H," respectively. Figure 2C As shown, transistor M4 is turned off, and transistors M3 and M5 are turned on. Since node vb1 and node mb1 are in a conductive state, voltage V0 is input to node mb1. In addition, node sn1 and node ms1 are in a conductive state, and thus voltage Vgs of transistor M1 becomes 0V. In addition, the threshold voltage V T1 The voltage V0 is set to be less than 0 V, and the voltage V1 is set to allow the drain current Id1 to flow.

[0131] At this time, the drain current Id1 is input to the node ms1, and the voltage of the node ms1 rises. Since the transistor M3 is turned on, the capacitive coupling of the capacitor C3 does not occur with the voltage rise of the node ms1 and does not change the voltage of the node mb1. Note that the voltage Vbgs of the transistor M1 decreases, so the threshold voltage V T1 Increases. After that, the threshold voltage V T1 reaches a voltage equal to the voltage Vgs of the transistor M1, so that the drain current Id1 is as Figure 2D At this time, if the voltage difference between the node mb1 and the node ms1 is set to Vc, Vc can be said to be used to make the threshold voltage V T1The voltage Vbgs becomes 0 V. Through the above operation, the programming of the voltage Vbgs of the circuit 17 is completed.

[0132] Then, during the period T3, the node wb is set to "L" and the node st is set to "L", so that the transistor M3 is turned off and the transistor M5 is turned off (see Figure 3A ). In addition, Figure 2A In the timing diagram, the nodes wb and st are simultaneously set to "L", but the nodes wb and st can also be set to "L" at different timings. Then, in period T4, the node ga is set to "H", turning on the transistor M4 (refer to Figure 3B ). By correcting the threshold voltage V T1 , the circuit 10 can be set as Figure 3C The threshold voltage V T1 The equivalent circuit of the circuit of transistor M1, transistor M2 and capacitor C1 at 0V.

[0133] The voltage change of the node mb1 caused by the leakage of the charge stored in the capacitor C3 becomes the threshold voltage V T1 Therefore, for example, it is preferable to increase the threshold voltages of the transistors M3 and M5 by the voltage VBGC1 to reduce the off-state currents of the transistors M3 and M5.

[0134] As mentioned above, the threshold voltage V T1 Set to 0 V. The characteristics of the transistor change depending on, for example, the operating temperature, so Figure 1 The structure of the circuit 10 shown can suppress fluctuations in calculation results due to changes in operating temperature and can also suppress variations in calculation results among the plurality of circuits 10 .

[0135] Figure 4A The circuit 11 shown includes a circuit 15 and a circuit 18. The circuit 18 is Figure 1 The circuit 17 shown in FIG. 1 is a circuit that removes the transistors M4 and M5 and is used as a 1T1C type memory cell. In the circuit 11, the circuit 18 stores the voltage Vbgs of the transistor M1. In addition, Figure 4A The node wx of the circuit 11 shown is equivalent to Figure 1 Node ot1 of circuit 10 is shown.

[0136] In the circuit 10, in order to set the threshold voltage V T1 , the voltage Vbgs of the transistor M1 is obtained using the internal circuit 17. On the other hand, in the circuit 11, the voltage Vbgs of the transistor M1 can be adjusted according to the voltage V0t input to the node vb1.

[0137] Turn on the transistor M3 and input the voltage V0t to the node mb1. Then, turn off the transistor M3 so that the capacitor C3 can store the voltage Vbgs of the transistor M1. T1 When it is set to 0 V, a voltage V0t satisfying V0t-VSS=Vc is input to the node vb1.

[0138] <Semiconductor Device 100>

[0139] In order to suppress the threshold voltage V caused by temperature T1 In order to prevent the voltage V0t from changing according to the temperature, it is preferred to change the voltage V0t according to the temperature. Figure 4B shows the threshold voltage V T1 An example of a semiconductor device that performs temperature correction. Figure 4B The semiconductor device 100 shown includes a control circuit 101 , a temperature sensor 102 , a memory device 103 , a DAC (digital-to-analog conversion circuit) 104 , driver circuits 106 to 109 , a readout circuit 112 , and an operation array 113 .

[0140] Operation array 113 includes a plurality of circuits 11 arranged in rows and columns. Operation array 113 includes wiring WW, wiring WB, wiring BW, wiring VX, wiring WX, and wiring WBGM1, corresponding to the arrangement of the plurality of circuits 11. Wiring WW, wiring WB, wiring BW, wiring VX, wiring WX, and wiring WBGM1 are electrically connected to nodes ww, wb, bw, vx, wx, and vb1 of circuits 11, respectively. Operation array 113 also includes circuitry for removing bias current from the output current of circuits 11.

[0141] Driver circuits 106 to 109 supply predetermined signals (or voltages) to each of wirings WW, WB, BW, VX, and WBGM1. Readout circuit 112 reads the calculation results of circuit 11. For example, readout circuit 112 generates a voltage Vac_out corresponding to the current flowing through wiring WX.

[0142] The memory device 103 stores data DBt corresponding to the voltage V0t. The operating temperature range of the semiconductor device 100 is divided into a plurality of ranges, and data DBt is obtained for each temperature range and stored in the memory device 103.

[0143] The control circuit 101 controls the entire semiconductor device 100. For example, the control circuit 101 corrects the threshold voltage V according to the data DTt obtained by the temperature sensor 102. T1Furthermore, data DTt represents temperature. Control circuit 101 generates a control signal for storage device 103 based on data DTt. Storage device 103 outputs data DBt corresponding to data DTt in response to the control signal. DAC 104 converts data DBt into analog data to generate voltage V0t. Voltage V0t corresponds to analog data DTt and is affected by temperature.

[0144] The voltage V0t is output to the driver circuit 109. The control circuit 101 generates timing signals for the driver circuits 106 and 109. The driver circuits 106 and 109 operate according to the timing signals, and the voltage V0t is input to the node mb1 of the circuit 11.

[0145] Data DBt can be obtained based on the circuit 11. For example, a voltage whose calculation result is known with respect to the reference temperature Tref is input to the node sn1 of one circuit 11. Subsequently, a low voltage sufficient to prevent the drain current Id1 from leaking into the wiring WX is input to the node sn1 of another circuit 11. Data DBt corresponding to the reference temperature Tref is obtained based on the voltage Vac_out read by the readout circuit 112. Data DBt for each temperature range is obtained based on the data DBt corresponding to the reference temperature Tref. By storing the data DBt for each temperature range in the storage device 103, the temperature dependence of the calculation results of the circuit 11 caused by changes in the operating temperature can be suppressed, and variations in the calculation results between multiple circuits 11 can be reduced.

[0146] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0147] (Implementation Method 2)

[0148] In this embodiment mode, a current source circuit including a unipolar circuit included in a semiconductor device will be described.

[0149] <Current Source Circuit 30>

[0150] Figure 5A The illustrated current source circuit 30 is a unipolar circuit and includes transistor M11, transistor M12, transistor MA1, transistor MA2, capacitor C11, capacitor C12, node bgc1, node cmg, node ot3, node cm1, node cm2, node cs1, node cs2, node dd, and node ss1. Transistors M11, M12, MA1, and MA2 are OS transistors with back gates. The back gates of transistors MA1 and MA2 are electrically connected to node bgc1.

[0151] The transistor M11 is used as part of a current mirror circuit described later. The gate, source, and drain of the transistor M11 are electrically connected to the node cmg, the node ss1, and the node ot3, respectively. The node ot3 is the output node of the current source circuit 30.

[0152] AND circuit 18 (refer to Figure 4A Similarly, circuit 41, including capacitor C11 and transistor MA1, functions as an 1T1C and stores the voltage Vbgs of transistor M11. Capacitor C11 maintains the voltage Vbgs of transistor M11. Transistor MA1 has the function of connecting or disconnecting node cm1 and the backgate of transistor M11. The on and off states of transistor MA1 can be switched by the voltage of node cm2. Furthermore, to suppress fluctuations in the backgate voltage of transistor M11 caused by leakage of charge held by capacitor C11, it is preferable to adjust the backgate voltage of transistor MA1 to increase the threshold voltage of transistor MA1.

[0153] The transistor M12 functions as a current source. The drain and source of the transistor M12 are electrically connected to the node dd and the node ot3, respectively. The back gate of the transistor M12 is electrically connected to the source.

[0154] AND circuit 18( Figure 4A Similarly, circuit 42, including capacitor C12 and transistor MA2, functions as a 1T1C memory cell and stores the gate-source voltage of transistor M12. Capacitor C12 maintains voltage Vgs of transistor M12. Transistor MA2 has the function of connecting or disconnecting node cs1 from the gate of transistor M12. The voltage at node cs2 can be used to switch transistor MA2 between the on and off states. Furthermore, to suppress fluctuations in the backgate voltage of transistor M12 caused by leakage of charge held by capacitor C12, it is preferable to adjust the backgate voltage of transistor MA2 to increase the threshold voltage of transistor MA2.

[0155] like Figure 5B As shown, by electrically connecting two current source circuits 30, an offset cancellation circuit 50 can be formed. The offset cancellation circuit 50 cancels the offset current in the output current of the multiplication circuit of Embodiment 1. To distinguish between the two current source circuits 30, one of them is referred to as a current source circuit 30r.

[0156] Bias cancellation circuit 50 is electrically connected to wiring WCS, wiring EN_WBG, wiring WBG, wiring WBGr, and voltage lines for supplying voltages VDD, VSS, VBCS, and VBGC. Wiring WX and wiring WXr are electrically connected to circuit 10 and circuit 10r, respectively. Circuit 10r is a replica of circuit 10 and functions as a reference multiplication circuit. Circuits 10 and 10r are electrically connected to wiring VX, wiring WW, and voltage lines for supplying voltages VSS and VBGC. Circuits 10 and 10r are electrically connected to wiring BW and wiring BWr, respectively.

[0157] Specifically, wiring WCS is electrically connected to node cs2 of current source circuit 30 and current source circuit 30r, wiring EN_WBG is electrically connected to node cm2 of current source circuit 30 and current source circuit 30r. Wiring WBG is electrically connected to node cm1 of current source circuit 30, and wiring WBGr is electrically connected to node cm1 of current source circuit 30r. A voltage line for supplying voltage VDD is electrically connected to node dd of current source circuit 30 and current source circuit 30r, a voltage line for supplying voltage VSS is electrically connected to node ss1 of current source circuit 30 and current source circuit 30r, and node ss of circuit 10 and circuit 10r, a voltage line for supplying voltage VBCS is electrically connected to node cs1 of current source circuit 30 and current source circuit 30r, and a voltage line for supplying voltage VBGC is electrically connected to node bgc1 of current source circuit 30 and current source circuit 30r, and node bgc of circuit 10 and circuit 10r. Wiring WX is electrically connected to node ot3 of current source circuit 30 and node wx of circuit 10. Wiring WXr is electrically connected to node ot3 of current source circuit 30r, node wx of circuit 10r, current source circuit 30, and node cmg of current source circuit 30r. Wiring BW is electrically connected to node bw of circuit 10, and wiring BWr is electrically connected to node bw of circuit 10r.

[0158] like Figure 5B As shown, wiring WX is electrically connected to readout circuit 120. Readout circuit 120 includes nodes inro, npr, and switch S20. Node inro is an input node. Switch S20 switches nodes inro and npr between conductive and non-conductive states. Readout circuit 120 may also function as a current-to-voltage conversion circuit that generates a voltage corresponding to the current flowing through node npr.

[0159] To identify the components (transistors, wiring, etc.) associated with current source circuit 30 and current source circuit 30r, the symbols for the components associated with current source circuit 30r are appended with "r." The same applies to the components associated with circuit 10 and circuit 10r. Furthermore, circuit 11 and a replica of circuit 11 may be provided in place of circuit 10 and circuit 10r.

[0160] The following reference Figure 6 and Figure 7 The offset cancellation operation will be explained using the multiplication of data w and data d as an example. By transitioning the states of offset cancellation circuit 50, circuit 10, and circuit 10r from the "initial state" to the "data d writing state," the offset current in the output current of circuit 10 is canceled, resulting in a current Ipr(w, d) proportional to the product w×d. Figure 6 This is a circuit diagram used to illustrate the initial state. Figure 7 3 is a circuit diagram illustrating a state in which data d is written.

[0161] also, Figure 6 、 Figure 7 An example in which the switch S20 is formed of an OS transistor having a back gate is shown. In the following description, the voltage VSS is set to 0V for convenience.

[0162] Threshold Voltage Correction

[0163] Before performing multiplication using the circuit 10 , the threshold voltages of the transistors M1 , M1r , M11 , and M11r are corrected.

[0164] As shown in the first embodiment, the threshold voltages of the transistors M1 and M1r are set to 0 V. Therefore, the circuits 10 and 10r are composed of Figure 3C Furthermore, when the threshold voltages of the transistors M1 and M1r are corrected, the wiring WCS is set to "H" so that the drain current flows through the transistors M12 and M12r.

[0165] Furthermore, in bias cancellation circuit 50, transistors M11 and M11r form a current mirror circuit. Because transistor M11r is a replica of transistor M11, ideally, the drain current of transistor M11r is replicated by transistor M11. However, due to factors such as manufacturing processes, transistor M11r and transistor M11 may have different characteristics. Therefore, before performing multiplication using circuit 10, the voltage Vbgs of transistors M11r and M11 is adjusted to correct the threshold voltages of transistors M11r and M11.

[0166] The voltages Vbgs of transistors M11r and M11 are set to Vb0 and Vb1, respectively, sufficient to bring the threshold voltages of transistors M11r and M11 to 0V. To set the voltages Vbgs of transistors M11r and M11 to Vb0 and Vb1, respectively, Vb0-VSS and Vb1-VSS are input to wirings WBGr and WBG, respectively. Next, wiring EN_WBG is held high for a certain period, turning on transistors MA1 and MA1r. This causes Vb0-VSS and Vb1-VSS to be input to the back gates of transistors M11r and M11, respectively. Then, wiring EN_WBG is set low, turning off transistors MA1 and MA1r. This fixes the voltage Vbgs of transistor M11r to Vb0 via capacitor C11r, and the voltage Vbgs of transistor M11 to Vb1 via capacitor C11.

[0167] Initialization Work

[0168] The initialization operation is used to set the current supplied by the transistor M12r and the transistor M12. During the initialization operation, the switch S20 is in the off state.

[0169] like Figure 6 As shown, voltage w0 and voltage w0+w are input to wiring BWr and wiring BW, respectively. Next, wiring WW is set to "H", turning on transistors M2r and M2, thereby inputting voltage w0 and voltage w0+w to nodes sn1r and sn1, respectively. In addition, voltage w0 and voltage w0+w are maintained by capacitors C1r and C1, respectively. Then, wiring WW is set to "L", turning off transistors M2r and M2, and then d0 is input to wiring VX. As a result, voltage Vgs of transistors M1r and M1 becomes w0+Ags, respectively. sn d0, w0+w+A sn d0, so that current I4 and current I3 flow through transistor M1r and transistor M1 respectively (refer to formula (2.9) and formula (2.8)).

[0170] Wiring WCS is set to "H," turning on transistors MA2r and MA2. Voltage VBCS, the channel lengths and widths of transistors M12 and M12r, and other parameters are set to ensure that a current I4 + I0 exceeding current I4 flows through transistor M12r and a current I3 + I0 exceeding current I3 flows through transistor M12, allowing transistors M12r and M12 to operate in their saturation regions. When the drain current of transistor M12r is I4 + I0, voltage Vgs is Vp4. When the drain current of transistor M12 is I3 + I0, voltage Vgs is Vp3.

[0171] Since current I4 + I0 flows through transistor M12r, current I0 flows through transistor M11r. Since the current mirror circuit is composed of transistor M11r and transistor M11, current I0 also flows through transistor M11.

[0172] Next, wiring WCS is set to "L." The above operation brings bias cancel circuit 50 to its initial state. In this initial state, voltage Vgs of transistor M12r is fixed to voltage Vp4 via capacitor C12r, and voltage Vgs of transistor M12 is fixed to voltage Vp3 via capacitor C12. Consequently, the current supplied by transistor M12r is set to I4 + I0, and the current supplied by transistor M12 is set to I3 + I0.

[0173] Writing data d

[0174] Then, if Figure 7 As shown, the voltage d0+d is input to the wiring VX. Since the transistors M2r and M2 are turned off, the voltages Vgs of the transistors M1r and M1 become w0+A. sn (d0+d), w0+w+A sn (d0+d). Therefore, I2 and I1 flow through transistor M1r and transistor M1, respectively (see formula (2.7) and formula (2.6)).

[0175] Since the voltage Vgs of transistor M12r is fixed to the voltage Vp4, even if the voltage of wiring WXr changes, current I4+I0 flows through transistor M12r. Therefore, the drain current of transistor M11r becomes I0-(I2-I4), so that the drain current of transistor M11r is copied by transistor M11.

[0176] Since the voltage Vgs of the transistor M12 is fixed to the voltage Vp3 , even if the voltage of the wiring WX changes, the current I3 + I0 flows through the transistor M12 .

[0177] When switch S20 is turned on at a predetermined timing, current -I1+I3-I4+I2 flows through node npr. In other words, current -Ipr(w, d) flows through node npr (see formula (2.11)). Readout circuit 120 converts current -Ipr(w, d) into a voltage.

[0178] As described above, by using the bias cancel circuit 50 , the bias current can be canceled from the current I1 generated by the circuit 10 , thereby obtaining a current proportional to the product w×d.

[0179] Furthermore, while the current source circuit 30 and the bias cancel circuit 50 described in this embodiment are unipolar circuits, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the current source circuit 30 or the bias cancel circuit 50 may have a structure that combines a source current source and a sink current source of a PMOS circuit or an NMOS circuit.

[0180] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0181] (Implementation 3)

[0182] In this embodiment, another configuration example of the current source circuit 30 and the offset cancel circuit 50 described in Embodiments 1 and 2 will be described.

[0183] In this embodiment, description of the same parts as those of the current source circuit 30 and the offset cancel circuit 50 in the above-mentioned embodiment is omitted, and different parts are mainly described.

[0184] <Current Source Circuit 60>

[0185] Figure 8 The current source circuit 60 shown is a unipolar circuit, including transistor M11, transistor M12, transistor M13, transistor MA1, transistor MA2, transistor MA3, transistor MS1, transistor MS2, capacitor C11, capacitor C12, capacitor C13, node bgc1, node cmg1, node cmg2, node ot3, node cm1, node cm2, node cs1, node cs2, node cs3, node ot3, node ot4, node pt1, node pt2, node pt3, node po, node dd, node ss1, and node mss. In other words, the current source circuit 60 has a Figure 5A The structure of the current source circuit 30 shown is the structure with transistor M13, transistor MA3, transistor MS1, transistor MS2, capacitor C13, node cmg1, node cmg2, node pt1, node pt2, node pt3, node po, node cs3, node ot3, node ot4, node mss added and node cmg removed.

[0186] The transistor M11 is used as part of a current mirror circuit. The gate, source, and drain of the transistor M11 are electrically connected to the node cmg1, the node mss, and the node ot4, respectively.

[0187] Node po is an input / output node for monitoring the current flowing through transistor M11. Transistor MA3 functions as a switch element for controlling whether this current is input or output to node po. Therefore, one of the source and drain of transistor MA3 is electrically connected to the drain of transistor M11. Furthermore, the gate of transistor MA3 is electrically connected to node pt3.

[0188] For the circuit 41 , reference may be made to the description of the above embodiment.

[0189] The transistor M12 functions as a current source. Similar to the current source circuit 30, the drain and source of the transistor M12 are electrically connected to the node dd and the node ot3, respectively. The back gate of the transistor M12 is electrically connected to the source.

[0190] The transistor M13 is used as part of the current mirror circuit. The gate, source, and drain of the transistor M13 are electrically connected to the node cmg2, the node ot4, and the node ot3, respectively. The node ot3 is the output node of the current source circuit 60.

[0191] That is, the source of the transistor M13 is electrically connected to the drain of the transistor M11 , and the drain of the transistor M13 is electrically connected to the source of the transistor M12 .

[0192] Figure 8 Circuit 42 of the illustrated current source circuit 60 stores the gate-source voltage of transistor M12, similarly to circuit 42 of current source circuit 30. Furthermore, circuit 42 of current source circuit 60 includes a capacitor C13 added to circuit 42 of current source circuit 30 to suppress the charge injection effect. The charge injection effect is a type of switching noise, whereby charge contained in the channel formation region flows through the source and drain sides of a transistor when it switches from an on state to an off state, causing the source and drain potentials of the transistor to fluctuate in response to this charge. Capacitor C13 included in circuit 42 of current source circuit 30 serves to store the charge that flows out of the channel formation region of transistor MA2 when transistor MA2 switches from an on state to an off state, thereby preventing fluctuations in the gate-source voltage of transistor M12.

[0193] As capacitor C13, a transistor is preferably used in which one of the two pairs of electrodes serves as a gate and the other serves as a terminal electrically connected to the source and drain. The channel width of this transistor is preferably 0.4 times or more and 0.6 times or less, more preferably 0.45 times or more and 0.55 times or less, greater than the channel width of transistor MA2. Alternatively, the channel length may be set to 0.4 times or more and 0.6 times or less, more preferably 0.45 times or more and 0.55 times or less, greater than the channel width of transistor MA2. This can further reduce the impact of the charge injection effect in circuit 42.

[0194] Figure 8 For operations other than those described above of the circuit 42 of the current source circuit 60 shown, reference can be made to the description of the circuit 42 of the current source circuit 30 in the above embodiment.

[0195] like Figure 9 As shown, by electrically connecting two current source circuits 60, an offset cancellation circuit 70 can be formed. By using the offset cancellation circuit 70, the offset current in the output current of the multiplication circuit of Embodiment 1 can be canceled more accurately than the offset cancellation circuit 70 shown in Embodiment 2. To distinguish between the two current source circuits 60, one of them will be referred to as a current source circuit 60r.

[0196] Bias cancellation circuit 70 is electrically connected to wiring WCS, wiring WCS2, wiring WBCS, wiring EN_WBG, wiring WBG, wiring WBGr, wiring PO, wiring POr, wiring EN_PO, wiring ENB_PO, wiring MVSSL, wiring MVSSLr, and voltage lines for supplying voltages VDD, VSS, and VBGC. Wiring WX and wiring WXr are electrically connected to circuit 10 and circuit 10r, respectively. For circuits 10 and 10r, reference can be made to the circuits 10 and 10r described in the above embodiment. Wiring MVSSL and wiring MVSSLr are both voltage lines for supplying voltage MVSS.

[0197] Specifically, wiring WCS is electrically connected to node cs2 of current source circuit 60 and current source circuit 60r, wiring WCS2 is electrically connected to node cs3 of current source circuit 60 and current source circuit 60r, wiring WBCS is electrically connected to node cs1 of current source circuit 60 and current source circuit 60r, wiring EN_WBG is electrically connected to node cm2 of current source circuit 60 and current source circuit 60r. Wiring WBG is electrically connected to node cm1 of current source circuit 60, and wiring WBGr is electrically connected to node cm1 of current source circuit 60r. Wiring PO is electrically connected to node po of current source circuit 60, and wiring POr is electrically connected to node po of current source circuit 60r. Wiring EN_PO is electrically connected to nodes pt2 and pt3 of current source circuit 60 and current source circuit 60r, and wiring ENB_PO is electrically connected to node pt1 of current source circuit 60 and current source circuit 60r. Wiring MVSSL is electrically connected to node mss of current source circuit 60, and wiring MVSSLr is electrically connected to node mss of current source circuit 60r. A voltage line for supplying voltage VDD is electrically connected to node dd of current source circuit 60 and current source circuit 60r. A voltage line for supplying voltage VSS is electrically connected to node ss1 of current source circuit 60 and current source circuit 60r, and node ss of circuit 10 and circuit 10r. A voltage line for supplying VBGC is electrically connected to node bgc1 of current source circuit 60 and current source circuit 60r, and node bgc of circuit 10 and circuit 10r. Wiring WX is electrically connected to node ot3 of current source circuit 60 and node wx of circuit 10. Wiring WXr is electrically connected to node ot3 of current source circuit 60r, node wx of circuit 10r, and node cmg2 of current source circuit 60 and current source circuit 60r. Wiring BW is electrically connected to node bw of circuit 10, and wiring BWr is electrically connected to node bw of circuit 10r. Node ot4 of current source circuit 60r is electrically connected to current source circuit 60 and node cmg1 of current source circuit 60r.

[0198] like Figure 9 As shown, the wiring WX is electrically connected to the readout circuit 120. For the readout circuit 120, the contents of the readout circuit 120 described in the above embodiment can be referred to.

[0199] To identify the components (transistors, wiring, etc.) associated with current source circuit 60 and current source circuit 60r, the symbols for the components associated with current source circuit 60r are appended with "r." The same applies to the components associated with circuit 10 and circuit 10r. Furthermore, circuit 11 and a replica of circuit 11 may be provided in place of circuit 10 and circuit 10r.

[0200] Figure 101 and 2 show the electrical connection structure of the transistors M11, M13, MA3, MS1 and MS2 of the current source circuit 60 and the transistors M11r, M13r, MA3r, MS1r and MS2r of the current source circuit 60r. Figure 10 In FIG. 4 , a circuit 41r is shown as a replica of the circuit 41. Focusing on the transistors M11, M11r, M13, and M13r, these transistors form a cascade current mirror circuit. By using the cascade current mirror circuit, the Figure 6 and Figure 7 The current mirror circuit shown, formed by transistors M11 and M11r, more accurately replicates the current. Consequently, a current substantially identical to the current flowing through the source-drain of transistor M13r can flow through the source-drain of transistor M13. At this point, the voltage MVSS input to node mss is preferably low, more preferably negative, to expand the voltage range handled by the cascaded current mirror circuit.

[0201] The following reference Figure 11 and Figure 12 The offset cancellation operation will be explained using the multiplication of data w and data d as an example. By transitioning the states of offset cancellation circuit 70, circuit 10, and circuit 10r from the "initial state" to the "data d writing state," the offset current in the output current of circuit 10 is canceled, resulting in a current Ipr(w, d) proportional to the product w×d. Figure 11 This is a circuit diagram used to illustrate the initial state. Figure 12 3 is a circuit diagram illustrating a state in which data d is written.

[0202] Threshold Voltage Correction

[0203] Furthermore, in the aforementioned cascade current mirror circuit, transistor M11r is a replica transistor of transistor M11. Ideally, the drain current of transistor M11r is replicated by transistor M11. However, due to factors such as manufacturing processes, transistor M11r and transistor M11 may have different characteristics. Therefore, the threshold voltage correction of transistors M11r and M11 in offset cancellation circuit 70 will be described first.

[0204] In the offset cancellation circuit 70, when correcting the threshold voltages of transistors M11 and M11r, wiring EN_PO is set to "H," turning on transistors MS1, MS1r, MA3, and MA3r. At this time, VSS is applied to the gates of transistors M13 and M13r, turning them off. Furthermore, wiring ENB_PO is set to "L," turning off transistors MS2 and MS2r. By applying a potential higher than voltage MVSS to wirings PO and POr, a current flows between the sources and drains of transistors M11 and M11r via a current mirror circuit formed by transistors M11 and M11r. At this time, wiring MVSSL is used to monitor the current flowing between the source and drain of transistor M11, while wiring MVSSLr is used to monitor the current flowing between the source and drain of transistor M11r.

[0205] Here, the voltage Vbgs of transistors M11 and M11r is set based on the current flowing through wiring MVSSL and wiring MVSSLr so that the threshold voltage of transistors M11 and transistor M11r reaches 0V. Assuming that the voltage Vbgs of transistors M11 and transistor M11r at this time is Vbin0 and Vbin1, Vbin1-MVSS and Vbin2-MVSS are input to wiring WBG and wiring WBGr, respectively. Next, wiring EN_WBG is set to "H," turning on transistors MA1 and transistor MA1r. This causes Vbin1-MVSS and Vbin2-MVSS to be input to the back gates of transistors M11 and transistor M11r, respectively. Then, transistors MA1 and transistor MA1r are turned off, fixing the voltage Vbgs of transistor M11r to Vbin0 via capacitor C11r, and fixing the voltage Vbgs of transistor M11 to Vbin1 via capacitor C11.

[0206] Alternatively, after setting the voltages Vbgs of transistors M11 and M11r to Vbin0 and Vbin1, respectively, the currents flowing through wiring MVSSL and wiring MVSSLr may be monitored to reset the voltages Vbgs of transistors M11 and M11r. By repeatedly setting the voltages Vbgs of transistors M11 and M11r, the threshold voltages of transistors M11 and M11r can be brought close to 0V.

[0207] Note that, regarding the correction of the threshold voltages of the transistors M1 and M1r included in the circuits 10 and 10r, reference may be made to the contents described in the above embodiment.

[0208] Initialization Work

[0209] The initialization operation is used to set the current supplied by the transistor M12r and the transistor M12. During the initialization operation, the switch S20 is in the off state.

[0210] like Figure 11 As shown, voltage w0 and voltage w0+w are input to wiring BWr and wiring BW, respectively. Next, wiring WW is set to "H", turning on transistors M2r and M2, thereby inputting voltage w0 and voltage w0+w to nodes sn1 and sn1r, respectively. Then, wiring WW is set to "L", turning off transistors M2r and M2, and then d0 is input to wiring VX. As a result, voltage Vgs of transistors M1r and M1 becomes w0+Ags, respectively. sn d0, w0+w+A sn d0, so that current I4 and current I3 flow through transistor M1r and transistor M1 respectively (refer to formula (2.9) and formula (2.8)).

[0211] Wiring WCS is set to "H," turning on transistors MA2r and MA2. Voltage VBCS, the channel lengths and widths of transistors M12 and M12r, and other parameters are set to ensure that a current I4 + I0 exceeding current I4 flows through transistor M12r and a current I3 + I0 exceeding current I3 flows through transistor M12, allowing transistors M12r and M12 to operate in their saturation regions. When the drain current of transistor M12r is I4 + I0, voltage Vgs is Vp4. When the drain current of transistor M12 is I3 + I0, voltage Vgs is Vp3.

[0212] Because current I4 + I0 flows through transistor M12r, current I0 flows through transistor M13r. At this point, by setting wiring EN_PO to "L," transistors MS1, MS1r, MA3, and MA3r are turned off, and the current mirror circuit formed by transistors M13r and M13 functions. Consequently, current I0 also flows through transistor M13.

[0213] Furthermore, by setting wiring ENB_PO to "L," transistors MS2 and MS2r are turned off, and the current mirror circuit formed by transistors M11r and M11 functions. That is, transistors M11r and M11, along with transistors M13r and M13, function as a cascaded current mirror circuit. Consequently, current I0 flows through transistors M11r and M11.

[0214] Here, by setting wiring WCS to "L," transistors MA2r and MA2 are turned off, and bias cancel circuit 70 enters its initial state. In this initial state, voltage Vgs of transistor MA2r is fixed to voltage Vp4 via capacitor C12r, and voltage Vgs of transistor MA2 is fixed to voltage Vp3 via capacitor C12. Consequently, the current supplied by transistor M12r is set to I4 + I0, and the current supplied by transistor M12 is set to I3 + I0.

[0215] Furthermore, in bias cancellation circuit 70, transistors MC1 and MC1r serve as capacitors C13 and C13r, respectively. Furthermore, wiring WCS2 serves as a wiring for transmitting an inverted signal of a signal input to wiring WCS. Specifically, when transistors MA2 and MA2r are off, an "H" voltage is input to the gates of transistors MC1 and MC1r. This suppresses the charge injection effect caused by transistors MA2 and MA2r. Consequently, compared to bias cancellation circuit 50, fluctuations in the gate voltages of transistors M12 and M12r due to charge injection can be further reduced. Consequently, fluctuations in currents I3+I0 and I4+I0 flowing through transistors M12 and M12r can be reduced.

[0216] Writing data d

[0217] Then, if Figure 12 As shown, the voltage d0+d is input to the wiring VX. Since the transistors M2r and M2 are turned off, the voltages Vgs of the transistors M1r and M1 become w0+A. sn (d0+d), w0+w+A sn (d0+d). Therefore, I2 and I1 flow through transistor M1r and transistor M1, respectively (see formula (2.7) and formula (2.6)).

[0218] Since the voltage Vgs of transistor M12r is fixed to the voltage Vp4, even if the voltage of wiring WXr changes, current I4+I0 flows through transistor M12r. Therefore, the drain current of transistor M11r becomes I0-(I2-I4), so that the drain current of transistor M11r is copied by transistor M11.

[0219] Since the voltage Vgs of the transistor M12 is fixed to the voltage Vp3 , even if the voltage of the wiring WX changes, the current I3 + I0 flows through the transistor M12 .

[0220] When switch S20 is turned on at a predetermined timing, current -I1+I3-I4+I2 flows through node npr. In other words, current -Ipr(w, d) flows through node npr (see formula (2.11)). Readout circuit 120 converts current -Ipr(w, d) into a voltage.

[0221] As described above, by using the bias cancel circuit 70 , the bias current can be canceled from the current I1 generated by the circuit 10 , thereby obtaining a current proportional to the product w×d.

[0222] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0223] (Implementation 4)

[0224] In this embodiment, an offset cancel circuit 80 is provided which is different from the offset cancel circuit 50 described in the second embodiment.

[0225] <Bias Cancelling Circuit 80>

[0226] Figure 13 The bias cancellation circuit 80 shown is a unipolar circuit, including a circuit CS2 , a circuit CS3 , a circuit CS4 , and a switch S21 .

[0227] In the bias cancellation circuit 80, circuit CS2 includes transistor M22, transistor M23, transistor M24, capacitor CD3, capacitor CD4, and terminal ct2; circuit CS3 includes transistor M27, transistor M28, transistor M29, capacitor CD7, capacitor CD8, and terminal ct3; and circuit CS4 includes transistor M32, transistor M33, transistor M34, capacitor CD11, capacitor CD12, and terminal ct4.

[0228] Circuit CS2 is a constant current circuit for generating a current output to terminal ct2, and circuit CS3 is a constant current circuit for generating a current output to terminal ct3. Circuit CS2 generates a current based on the potential held at the first terminal of capacitor CD3 and the first terminal of capacitor CD4, while circuit CS3 generates a current based on the potential held at the first terminal of capacitor CD7 and the first terminal of capacitor CD8.

[0229] Circuit CS4 is a current sink circuit that sinks current from terminal ct4 and has a function of sinking current through the source-drain of transistors M32 and M33 according to the potential held at the first terminal of capacitor CD11 and the first terminal of capacitor CD12.

[0230] In circuit CS2, the first terminal of transistor M22 is electrically connected to a voltage line supplying voltage VDD, the second terminal and back gate of transistor M22 are electrically connected to the first terminal of transistor M23, and the gate of transistor M22 is electrically connected to wiring SW2. Furthermore, the second terminal and back gate of transistor M23 are electrically connected to the second terminal of capacitor CD4 and terminal ct2, and the gate of transistor M23 is electrically connected to the first terminal of transistor M24, the first terminal of capacitor CD3, and the first terminal of capacitor CD4. Furthermore, the second terminal of transistor M24 is electrically connected to wiring VAL supplying an arbitrary voltage, the gate of transistor M24 is electrically connected to wiring SW3, and the second terminal of capacitor CD3 is electrically connected to wiring SW3B.

[0231] In circuit CS3, a first terminal of transistor M27 is electrically connected to a voltage line supplying voltage VDD, a second terminal and back gate of transistor M27 are electrically connected to a first terminal of transistor M28, and a gate of transistor M27 is electrically connected to wiring SW4. Furthermore, a second terminal and back gate of transistor M28 are electrically connected to a second terminal of capacitor CD8 and terminal ct3, and a gate of transistor M28 is electrically connected to a first terminal of transistor M29, a first terminal of capacitor CD7, and a first terminal of capacitor CD8. Furthermore, a second terminal of transistor M29 is electrically connected to wiring VAL supplying an arbitrary voltage, a gate of transistor M29 is electrically connected to wiring SW5, and a second terminal of capacitor CD7 is electrically connected to wiring SW5B.

[0232] Any voltage supplied by the wiring VAL is preferably greater than the voltage VSS.

[0233] In circuit CS4, the first terminal of transistor M32 is electrically connected to the first terminal of transistor M34 and terminal ct4. The second terminal of transistor M32 is electrically connected to the first terminal of transistor M33. The gate of transistor M32 is electrically connected to wiring SW6. Furthermore, the second terminal of transistor M33 is electrically connected to a voltage line supplying voltage VSS. The back gate of transistor M33 is electrically connected to a voltage line supplying voltage VSS. The gate of transistor M33 is electrically connected to the second terminal of transistor M34, the first terminal of capacitor CD11, and the first terminal of capacitor CD12. Furthermore, the gate of transistor M34 is electrically connected to wiring SW7, the second terminal of capacitor CD11 is electrically connected to wiring SW7B, and the second terminal of capacitor CD12 is electrically connected to a voltage line supplying voltage VSS.

[0234] A first terminal of the switch S21 is electrically connected to the terminal ct2 and the wiring WX, and a second terminal of the switch S21 is electrically connected to the terminal ct3 and the terminal ct4.

[0235] Wiring SW1 to wiring SW7 are each supplied with either a low-level potential or a high-level potential. Furthermore, wiring SW3B is a wiring to which an inverted signal of an input signal input to wiring SW3 is input, wiring SW5B is a wiring to which an inverted signal of an input signal input to wiring SW5 is input, and wiring SW7B is a wiring to which an inverted signal of an input signal input to wiring SW7 is input.

[0236] Capacitors CD3, CD7, and CD11 are all circuit elements used to suppress the charge injection effect that occurs when transistors M24, M29, and M34 transition from an on state to an off state. Therefore, bias cancellation circuit 80 operates by inputting an inverse signal of the input signal to each gate of transistors M24, M29, and M34 to each second terminal of each of capacitors CD3, CD7, and CD11. Furthermore, capacitors CD3, CD7, and CD11 preferably utilize transistors in which one of two pairs of electrodes serves as a gate and the other serves as a terminal electrically connecting the source and drain. Furthermore, the channel width of these transistors is preferably 0.4 times to 0.6 times the channel width of transistors M24, M29, and M34, and more preferably 0.45 times to 0.55 times. In addition, this may not involve the channel width but the channel length, that is, the channel length is greater than 0.4 times and less than 0.6 times the channel length of the transistor M24, the transistor M29, and the transistor M34, and more preferably greater than 0.45 times and less than 0.55 times.

[0237] The following reference Figures 14 to 17 The offset cancellation operation will be explained using the example of multiplying data w by data d. By sequentially switching the operation of offset cancellation circuit 80 and circuit 10 from "first operation" to "second operation," "third operation," and "fourth operation," the offset current can be canceled from the output current of circuit 10 to obtain a current Ipr(w, d) proportional to the product w×d. Figure 14 This is a circuit diagram used to illustrate the "first operation". Figure 15 This is a circuit diagram used to illustrate the "second operation". Figure 16 This is a circuit diagram for explaining the "third operation", and Figure 17 This is a circuit diagram used to illustrate the "fourth operation".

[0238] also, Figures 14 to 17 The readout circuit 120 and the circuit 10 are shown. The readout circuit 120 and the circuit 10 are electrically connected to the terminal ct2 of the circuit CS2 of the offset cancel circuit 80. For details about the readout circuit 120 and the circuit 10, reference can be made to the contents of the above embodiment.

[0239] also, Figures 14 to 17An example in which the switch S21 is formed of an OS transistor having a back gate is shown. In the following description, the voltage VSS is set to 0V for convenience.

[0240] First Job

[0241] The first operation is used to set the current supplied by transistor M28 of circuit CS3. During the first operation period, switch S20 is in the OFF state, and switch S21 is in the ON state. Furthermore, during the first operation period, wiring SW2 is set to "L" and wiring SW6 is set to "L", turning off transistor M22 of circuit CS2 and transistor M32 of circuit CS4.

[0242] like Figure 14 As shown, voltage w0 is input to wiring BW. Furthermore, VSS is first input to wiring VX. Next, wiring WW is set to "H," turning on transistor M2, thereby writing voltage w0 to node sn1. Then, wiring WW is set to "L," turning off transistor M2, and then d0 is input to wiring VX. As a result, voltage Vgs of transistor M1 becomes w0 + A sn d0, causing current I4 to flow through transistor M1 (refer to formula (2.9)).

[0243] The wiring SW4 is set to "H", and the wiring SW5 is set to "H", so that the transistors M27 and M29 are turned on. The voltage supplied from the wiring VAL is set so that the current I4 flows through the transistor M28 and the transistor M28 operates in the saturation region. Figure 14 In FIG. 5 , Vp8 represents the voltage Vgs when the drain current of the transistor M28 is I4.

[0244] Next, wiring SW5 is set to "L." This turns off transistor M29, and the voltage Vgs of transistor M28 is fixed to voltage Vp8 via capacitor CD8. Consequently, the current supplied by transistor M28 is set to I4. Furthermore, capacitor CD7 is a circuit element used to suppress the charge injection effect that occurs when transistor M29 switches from on to off. Therefore, when transistor M29 is off, that is, when wiring SW5 is "L," wiring SW5B is "H."

[0245] The Second Job

[0246] The second operation is for setting the current supplied by the transistor M23 of the circuit CS2 and for setting the current sunk by the transistor M33 of the circuit CS4. During the second operation, the switch S20 is in the off state and the switch S21 is in the off state.

[0247] First, the operation for setting the current supplied by the transistor M23 of the circuit CS2 will be described.

[0248] like Figure 15 As shown, voltage w0 is input to wiring BW. Furthermore, VSS is first input to wiring VX. Next, wiring WW is set to "H", turning on transistor M2, thereby writing voltage w0 to node sn1. Then, wiring WW is set to "L", turning off transistor M2. Note that when the second operation is continued after the first operation, voltage w0 has already been written to node sn1, and the above-mentioned writing operation is unnecessary. By inputting d0+d to wiring VX when writing voltage w0 to node sn1, the voltage Vgs of transistor M1 becomes w0+A. sn (d0+d), causing current I2 to flow through transistor M1 (refer to formula (2.7)).

[0249] The wiring SW2 is set to "H", and the wiring SW3 is set to "H", so that the transistors M22 and M24 are turned on. The voltage supplied from the wiring VAL is set so that the current I4 flows through the transistor M23 and the transistor M23 operates in the saturation region. Figure 15 In FIG. 5 , Vp7 represents the voltage Vgs when the drain current of the transistor M23 is I2.

[0250] Next, wiring SW3 is set to "L." This turns off transistor M24, and the voltage Vgs of transistor M23 is fixed to voltage Vp7 via capacitor CD4. Consequently, the current supplied by transistor M24 is set to I2. Furthermore, capacitor CD3 is a circuit element used to suppress the charge injection effect that occurs when transistor M24 switches from on to off. Therefore, when transistor M24 is off, that is, when wiring SW3 is "L," wiring SW3B is "H."

[0251] Next, the operation for setting the current sunk by transistor M33 of circuit CS4 will be described.

[0252] Wiring SW6 is set to "H" and wiring SW7 is set to "H", turning on transistors M32 and M34. As a result, transistor M33 has a diode connection structure where the drain and gate are electrically connected. Therefore, the voltage Vgs of transistor M33 is set so that the current I4 flowing from circuit CS3 flows through transistor M33. Figure 15 In FIG, Vp9 represents the voltage Vgs when the drain current of the transistor M33 is I4. When the size and structure of the transistor M33 are the same as those of the transistor M28, Vp9 may be the same voltage as Vp8.

[0253] Next, wiring SW7 is set to "L." This turns off transistor M34, and voltage Vgs of transistor M33 is fixed to voltage Vp9 via capacitor CD12. Consequently, the current supplied by transistor M28 is set to I4. Furthermore, capacitor CD11 is a circuit element that suppresses the charge injection effect that occurs when transistor M34 switches from on to off. Therefore, when transistor M34 is off, that is, when wiring SW7 is "L," wiring SW7B is "H."

[0254] The Third Job

[0255] The third operation is used to set the current supplied by transistor M28 of circuit CS3. During the third operation period, switch S20 is in the OFF state, and switch S21 is in the ON state. Furthermore, during the third operation period, wiring SW2 is set to "L" and wiring SW6 is set to "L", turning off transistor M22 of circuit CS2 and transistor M32 of circuit CS4.

[0256] like Figure 16 As shown, voltage w0+w is input to wiring BW. Furthermore, VSS is first input to wiring VX. Next, wiring WW is set to "H," turning on transistor M2, thereby writing voltage w0+w to node sn1. Then, wiring WW is set to "L," turning off transistor M2, and then d0 is input to wiring VX. As a result, voltage Vgs of transistor M1 becomes w0+w+A. sn d0, causing current I3 to flow through transistor M1 (refer to formula (2.8)).

[0257] The wiring SW4 is set to "H", and the wiring SW5 is set to "H", so that the transistors M27 and M29 are turned on. The voltage supplied from the wiring VAL is set so that the current I3 flows through the transistor M28 and the transistor M28 operates in the saturation region. Figure 16 In FIG. 5 , Vp10 represents the voltage Vgs when the drain current of the transistor M28 is I3.

[0258] Next, the wiring SW5 is set to "L". As a result, the transistor M29 is turned off, and the voltage Vgs of the transistor M28 is fixed to the voltage Vp10 via the capacitor CD8. As a result, the current supplied by the transistor M28 is set to I3

[0259] The Fourth Job

[0260] The fourth operation is an operation for setting the current I1 flowing through the transistor M1 of the circuit 10 and causing the current -I1+I3-I4+I2 to flow through the node npr of the readout circuit 120 using the currents I2, I3, and I4 set in the first to third operations.

[0261] like Figure 17 As shown, the voltage w0+w is input to the wiring BW. In addition, the wiring VX is first input with VSS. Next, the wiring WW is set to "H", turning on the transistor M2, thereby writing the voltage w0+w to the node sn1. Then, the wiring WW is set to "L", turning off the transistor M2, and then d0+d is input to the wiring VX. As a result, the voltage Vgs of the transistor M1 becomes (w0+w)+A. sn (d0+d), so that current I1 flows through transistor M1 (refer to formula (2.6)).

[0262] By setting wiring SW2 to "H," wiring SW4 to "H," and wiring SW6 to "H," transistors M22, M27, and M32 are turned on. Consequently, circuit CS2 outputs current I2 from terminal ct2, circuit CS3 outputs current I3 from terminal ct3, and circuit CS4 outputs current I2 from terminal ct4.

[0263] Furthermore, by turning on switches S20 and S21 at a predetermined timing, a current of -I1+I3-I4+I2 flows through node npr. In other words, a current of -Ipr(w, d) flows through node npr (see formula (2.11)). The readout circuit 120 converts the current -Ipr(w, d) into a voltage.

[0264] As described above, by using the bias cancel circuit 80 , the bias current can be canceled from the current I1 generated by the circuit 10 , thereby obtaining a current proportional to the product w×d.

[0265] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0266] (Implementation 5)

[0267] In this embodiment, a hierarchical artificial neural network and a calculation circuit using the circuits described in the above embodiment will be described.

[0268] <Hierarchical Neural Network>

[0269] Artificial neural networks (ANN, hereinafter referred to as neural networks) refer to all models that simulate biological neural circuit networks. Generally speaking, in a neural network, units modeled after neurons are connected to each other through units modeled after synapses.

[0270] By providing existing information to a neural network, the binding strength of synapses (also called weight coefficients) can be changed. This process of determining the binding strength by providing existing information to a neural network is sometimes called "learning."

[0271] Furthermore, by providing information to a neural network that has already "learned" (determined its binding strength), new information can be output based on that binding strength. This process of outputting new information based on the provided information and binding strength within a neural network is sometimes called "inference" or "cognition."

[0272] Examples of neural network models include Hopfield networks and hierarchical neural networks. In particular, in this specification, a neural network having a multi-layer structure is referred to as a "deep neural network" (DNN), and a hierarchical neural network having multiple layers will be described in this embodiment.

[0273] Figure 18 An example of a layered neural network is shown. The (k-1)th layer (where k is an integer greater than 2) has a total of m (where m is an integer greater than 1) neurons, namely, neuron N1 (k-1) To neuron N m (k-1) , the kth layer has a total of n (n is an integer greater than 1) neurons, namely neuron N1 (k) To neuron N n (k) .

[0274] exist Figure 18 In the figure, the neuron N1 in the (k-1) layer is shown. (k-1) 、N i (k-1) 、N m (k-1) , neuron N1 in layer k (k) 、N j (k) 、N n (k) , but all other neurons are omitted.

[0275] In a layered neural network, the neurons N i (k-1) (where i is an integer greater than or equal to 1 and less than or equal to m) Output output signal z i (k) , neuron N j (k) (where j is an integer greater than or equal to 1 and less than or equal to n) is input and output signal z i (k-1) and weight coefficient Note that the larger the weight coefficient, the greater the signal sent and received between the neurons.

[0276] exist Figure 18 In the figure, the symbol represents the neuron N1 (k-1) Transmitted to neuron N j (k) signal From the neuron N i (k-1) Transmitted to neuron N j (k) signal From the neuron N m (k-1) Transmitted to neuron N j (k) signal However, the symbols of other signals are omitted.

[0277] Here, we focus on the neuron N j (k) . Input to neuron N j (k) The sum of the signals is expressed by the following formula.

[0278] [Formula 7]

[0279]

[0280] In addition, from neuron N j (k) The output signal z j (k) It is defined by the following formula.

[0281] [Formula 8]

[0282]

[0283] Function f(u j (k) ) is the activation function in a layered neural network. A step function, a linear ramp function, or a sigmoid function can be used. The same activation function can be used for all neurons, or different ones can be used. Furthermore, the output function of neurons can be the same or different in each layer.

[0284] The neural network receives input signals from the first layer (input layer). Each layer from the first layer (input layer) to the last layer (output layer) sequentially generates output signals using equations (3.1) and (3.2) based on the signals input from the previous layer, and then outputs these output signals to the next layer. The signal output from the last layer (output layer) corresponds to the result of the neural network's calculations.

[0285] <Calculation Circuit>

[0286] Here, a calculation circuit for performing the calculation of Formula (3.1) using the circuit shown in the above embodiment will be described.

[0287] Figure 19201A is a block diagram showing a configuration example of an arithmetic circuit. The arithmetic circuit 201A includes an offset cancel circuit 90, a drive circuit 110, a readout circuit 120, and a memory cell array MCA.

[0288] As the offset cancel circuit 90 , the offset cancel circuit 50 described in Embodiment Mode 2 or the offset cancel circuit 70 described in Embodiment Mode 3 can be used as appropriate.

[0289] The memory cell array MCA includes m×2 memory cells. Figure 19 In the example, the storage cells are arranged in a matrix of m rows and 2 columns. In particular, Figure 19 The first and second columns of the memory cell array MCA shown use the circuits 10 and 10r shown in the above embodiment as memory cells, respectively. In this embodiment, the circuits 10 and 10r in the i-th row are denoted as circuits 10[i] and 10r[i], respectively.

[0290] As the readout circuit 120 , the readout circuit 120 described in Embodiment 2 and Embodiment 3 can be used as appropriate.

[0291] Regarding the electrical connection of the bias cancellation circuit 90, the circuits 10[1] to 10[m], the circuits 10r[1] to 10r[m], and the readout circuit 120, reference can be made to the descriptions of Embodiments 2 and 3. That is, when the bias cancellation circuit 90 is the bias cancellation circuit 50, the wiring WX is electrically connected to the node ot3 of the current source circuit 30, and the wiring WXr is electrically connected to the node ot3 of the current source circuit 30r. In addition, when the bias cancellation circuit 90 is the bias cancellation circuit 70, the wiring WX is electrically connected to the node ot3 of the current source circuit 60, and the wiring WXr is electrically connected to the node ot3 of the current source circuit 60r. In addition, the wiring WX is electrically connected to the node wx of each of the circuits 10[1] to 10[m] and the node inro of the readout circuit 120, and the wiring WXr is electrically connected to the node wx of each of the circuits 10r[1] to 10r[m]. Note that, Figure 19 Node ot3, node wx, and node inro are not shown.

[0292] The driving circuit 110 has a function of supplying a predetermined signal (or voltage) to the node vx of the circuit 10 or the circuit 10r through the wiring VX. Figure 19 In the example, the arithmetic circuit 201A has m rows of memory cell array MCA and therefore has m wirings VX. In this embodiment, the wiring VX in the i-th row is referred to as wiring VX[i]. The driver circuit 110 may be the driver circuit 108 described in Embodiment 1.

[0293] By composition Figure 19The calculation circuit 201A shown in FIG. 2 can perform the calculation of formula (3.1). The following describes an example of the operation of the calculation circuit 201A. In the following description, for convenience, the weight coefficient And the output signal z i (k-1) The corresponding voltages are called voltages and voltage z i (k-1) .

[0294] For example, the input to neuron N j (k) u j (k) First, the neuron N i (k-1) With neuron N j (k) The weight coefficient between The voltage is held at the node sn1 of the circuit 10[i] as data w. The voltage w0 is held at the node sn1 of the circuit 10r[i].

[0295] Next, consider the case where the neuron N i (k-1) Input to neuron N j (k) Signal z i (k-1) For data d, voltage d0 and voltage d0+z are applied to wiring VX[i] respectively. i (k-1) When voltage d0 is applied to wiring VX[i], current I3 and current I4 are output from bias cancel circuit 90 through wiring WX and wiring WXr, respectively. i (k-1) In the case of , the current I1 and the current I2 output from the offset cancel circuit 90 through the wiring WX and the wiring WXr respectively can be expressed by the following formulas.

[0296] [Formula 9]

[0297]

[0298]

[0299]

[0300]

[0301] In the above formulas (3.3) to (3.6), by calculating formula (2.10), we can obtain formula (3.7).

[0302] [Formula 10]

[0303]

[0304] Thus, formula (3.7) shows the corresponding i (k-1) Input to neuron N j (k) Signal z i (k-1) With neuron N i (k-1) With neuron N j (k) The weight coefficient between The current value of the sum of the products when i is 1 to m. The current shown in formula (2.10) is supplied to the readout circuit 120 as shown in embodiment 2 and embodiment 3. By supplying the current of formula (3.7) to the readout circuit 120, the input to the neuron N can be obtained. j (k) Formula (3.1).

[0305] Furthermore, by making the readout circuit 120 include an operation circuit for calculating the activation function of formula (3.2), the neuron N can be output from the readout circuit 120. j (k) The output signal z j (k) .

[0306] also, Figure 20 FIG. 201B shows a configuration example of another arithmetic circuit different from the arithmetic circuit 201A. The arithmetic circuit 201B includes n offset cancel circuits 90, a memory cell array MCA, and a readout circuit 120 included in the arithmetic circuit 201A. Figure 20 In the figure, the n bias cancellation circuits 90 are respectively recorded as bias cancellation circuits 90[1] to 90[n], the n memory cell arrays MCA are respectively recorded as memory cell arrays MCA[1] to MCA[n], and the n readout circuits 120 are respectively recorded as readout circuits 120[1] to 120[n].

[0307] Furthermore, the arithmetic circuit 201B includes the same driver circuit 110 as the arithmetic circuit 201A. The driver circuit 110 is electrically connected to the memory cell arrays MCA[1] to MCA[n] via wirings VX[1] to VX[m].

[0308] In addition, Figure 20In the figure, the operation circuit 201B, the bias cancellation circuit 90[1], the bias cancellation circuit 90[n], the memory cell array MCA[1], the memory cell array MCA[n], the read circuit 120[1], the read circuit 120[n], the drive circuit 110, the circuit 10[1], the circuit 10[i], the circuit 10[m], the circuit 10r[1], the circuit 10r[i], the circuit 10r[m], the memory cell array MCA[1], and the memory cell array MCA[1] are shown. The cell array MCA[n] includes circuit 10[1], circuit 10[i], circuit 10[m], circuit 10r[1], circuit 10r[i], circuit 10r[m], wiring WX electrically connected to the bias cancellation circuit 90[1], wiring WXr electrically connected to the bias cancellation circuit 90[n], wiring WX, wiring WXr, wiring WX[1], wiring WX[i], and wiring WX[m], but other block diagrams, wirings, and symbols are omitted.

[0309] By composition Figure 20 The calculation circuit 201B shown can perform multiple calculations of formula (3.1) at the same time. Figure 19 In the description of the arithmetic circuit 201A shown in FIG. Figure 18 The neurons N in the kth layer are shown j (k) Conducted z j (k) calculation, but by using Figure 20 The operation circuit 201B shown can simultaneously calculate Figure 18 The neuron N1 in the kth layer is shown (k) To neuron N n (k) z1 output respectively (k) to z n (k) .

[0310] Specifically, the node sn1 of the circuit 10[i] of the memory cell array MCA[1] holds the neuron N i (k -1) With neuron N1 (k) The weight coefficient between the voltage The node sn1 of the circuit 10r[i] of the memory cell array MCA[1] holds w0. The node sn1 of the circuit 10[i] of the memory cell array MCA[n] holds the neuron N i (k -1) With neuron N n (k) The weight coefficient between the voltage w0 is held in the node sn1 of the circuit 10r[i] of the memory cell array MCA[n]. Figure 20 It is not shown in FIG. 1 , but is held as a neuron N in the node sn1 of the circuit 10[j] of the memory cell array MCA[j]. i (k-1) With neuron N j (k) The weight coefficient between the voltage w0 is held in the node sn1 of the circuit 10r[i] of the memory cell array MCA[1].

[0311] Then, with Figure 19 Similarly, the bias cancellation circuit 90[1], the memory cell array MCA[1], and the drive circuit 110 operate, thereby enabling the readout circuit 120[1] to calculate the input to the neuron N1. (k) u1 (k) In addition, the bias cancellation circuit 90[n], the memory cell array MCA[n], and the driving circuit 110 operate, thereby enabling the readout circuit 120[n] to calculate the input to the neuron N n (k) u n (k) In addition, although Figure 20 Although not shown, the bias cancellation circuit 90[j], the memory cell array MCA[j], and the driving circuit 110 operate so that the readout circuit 120[j] can calculate the input to the neuron N j (k) u j (k) Then, the readout circuits 120[1] to 120[n] can respectively read out the data according to u1. (k) to u n (k) Find z1 (k) to z n (k) .

[0312] exist Figure 20 In the arithmetic circuit 201B, the node sn1 of the circuits 10r[1] to 10r[m] included in the memory cell arrays MCA[1] to MCA[n] maintains the voltage w0. As a result, the amount of current flowing through each wiring WXr electrically connected to the bias canceling circuits 90[1] to 90[n] is equal. That is, when the voltage d0 is applied to the wirings VX[1] to VX[m], the current I2 that is equal to each other flows through each wiring WXr electrically connected to the bias canceling circuits 90[1] to 90[n]. When the voltage d0+z1 is applied to the wirings VX[1] to VX[m], the current I2 that is equal to each other flows through each wiring WXr electrically connected to the bias canceling circuits 90[1] to 90[n]. (k-1) to d0+z m(k-1) In this case, currents I4 that are equal to each other flow through the wirings WXr electrically connected to the offset cancel circuits 90[1] to 90[n].

[0313] therefore, Figure 20 The structure of the arithmetic circuit 201B can be changed to a structure in which the circuits 10r[1] to 10r[m] are shared among the memory cell arrays MCA[1] to MCA[n]. Figure 21 This structure is shown. The arithmetic circuit 201C has a structure in which the memory cell arrays MCA[1] to MCA[n] are grouped into a single memory cell array MCA. The memory cell array MCA includes circuits 10[1,1] to 10[m,n], with each row having a replica circuit corresponding to circuits 10[i,1] to 10[i,n], namely, circuit 10r[i]. In other words, the memory cell array MCA has a structure in which m×n circuits 10 and m×1 circuits 10r are arranged in an m×(n+1) matrix.

[0314] Furthermore, the bias cancel circuit 90 is electrically connected to the memory cell array MCA via a wiring WX[j]. The wiring WX[j] is electrically connected to the circuits 10[1,j] to 10[m,j] and the read circuit 120[j]. Figure 21 The bias cancel circuit 90 shown can cancel the bias current flowing through the wirings WX[1] to WX[n] according to the current flowing through the wiring WXr.

[0315] The calculation circuit 201C can calculate the input to the neuron N1 by performing the same operation as the calculation circuit 201B. (k) To neuron N n (k) u1 (k) to u n (k) .

[0316] Figure 22A This is a block diagram showing a configuration example of an arithmetic circuit using the offset cancel circuit 80 described in Embodiment 4 as an offset cancel circuit. The arithmetic circuit 202A includes the offset cancel circuit 80, a driver circuit 110, a readout circuit 120, and a memory cell array MCA.

[0317] The memory cell array MCA includes m×1 memory cells. Figure 22A In the example, the storage cells are arranged in a matrix of m rows and 1 column. In particular, Figure 22A The memory cell array MCA shown uses the circuit 10 shown in the above embodiment as a memory cell. In this embodiment, the circuit 10 in the i-th row is referred to as circuit 10[i].

[0318] As the readout circuit 120 , the readout circuit 120 described in Embodiment 4 can be used as appropriate.

[0319] The electrical connections between bias cancel circuit 80, circuits 10[1] to 10[m], and readout circuit 120 can be referred to the description of Embodiment 4. Specifically, wiring WX is electrically connected to terminal ct2 of circuit CS2. Furthermore, wiring WX is electrically connected to node wx of each of circuits 10[1] to 10[m] and node inro of readout circuit 120.

[0320] The driving circuit 110 has a function of supplying a predetermined signal (or voltage) to a node vx of the circuit 10 through the wiring VX. Figure 22A In the example, the arithmetic circuit 202A has m rows of memory cell array MCA and therefore has m wirings VX. In this embodiment, the wiring VX in the i-th row is referred to as wiring VX[i]. The driver circuit 110 may be the driver circuit 108 described in Embodiment 1.

[0321] By composition Figure 22A The operation circuit 202A shown in FIG. 1 can perform the calculation of formula (3.1). The following describes an example of the operation of the operation circuit 202A. Figures 19 to 21 Similarly, the weight coefficient And the output signal z i (k-1) The corresponding voltages are called voltages and voltage z i (k-1) .

[0322] For example, the input to neuron N j (k) u j (k) Calculation method.

[0323] First, in the first operation shown in Embodiment 4, voltage w0 is held at node sn1 of circuit 10[i]. Then, by applying voltage d0 to wiring VX[i], current I4 shown in formula (3.6) is output from offset cancel circuit 80.

[0324] Next, in the second operation shown in the fourth embodiment, the voltage w0 is maintained at the node sn1 of the circuit 10[i]. i (k-1) Input to neuron N j (k) The signal is z i (k-1) Apply voltage d0+z to wiring VX[i] i (k-1) , the current I2 shown in formula (3.4) can be output from the bias cancellation circuit 80.

[0325] Next, in the third operation shown in the fourth embodiment, the neuron N i (k-1) With neuron N j (k) The weight coefficient between The voltage is maintained at the node sn1 of the circuit 10[i]. Then, by applying voltage d0 to the wiring VX[i], the current I3 expressed by formula (3.5) can be output from the offset cancel circuit 80 .

[0326] Next, in the fourth operation shown in the fourth embodiment, the voltage is held at the node sn1 of the circuit 10[i]. Then, by applying voltage d0+z to wiring VX[i] i (k-1) , the current I1 shown in formula (3.3) can be output from the bias cancellation circuit 80. At this time, the bias current is canceled by the operation of the bias cancellation circuit 80. Therefore, the current corresponding to the output from the neuron N i (k-1) Input to neuron N j (k) Signal z i (k-1) With neuron N i (k-1) With neuron N j (k) The weight coefficient between The current value of the sum of the products of when i is 1 to m is the formula (3.7). Then, by supplying the current of formula (3.7) to the readout circuit 120, the input to the neuron N can be obtained. j (k) Formula (3.1).

[0327] Furthermore, by making the readout circuit 120 include an operation circuit for calculating the activation function of formula (3.2), the neuron N can be output from the readout circuit 120. j (k) The output signal z j (k) .

[0328] also, Figure 22BThe following shows an example of the structure of another arithmetic circuit different from the arithmetic circuit 202A. The arithmetic circuit 202B includes n bias cancellation circuits 80 included in the arithmetic circuit 202A, a memory cell array MCA, and a readout circuit 120. In addition, the memory cell array MCA of the arithmetic circuit 202B includes m×n circuits 10, which are arranged in a matrix of m rows and n columns. Figure 22B In FIG. 1 , the n bias cancellation circuits 80 are respectively denoted as bias cancellation circuits 80 [ 1 ] to 80 [ n ], and the n readout circuits 120 are respectively denoted as readout circuits 120 [ 1 ] to 120 [ n ].

[0329] Furthermore, the arithmetic circuit 202B includes the same driver circuit 110 as the arithmetic circuit 202A, and the driver circuit 110 is electrically connected to the memory cell array MCA via wirings VX[1] to VX[m].

[0330] In addition, Figure 22B 1 , the diagram shows an operation circuit 202B, a bias cancellation circuit 80[1], a bias cancellation circuit 80[j], a bias cancellation circuit 80[n], a memory cell array MCA, a read circuit 120[1], a read circuit 120[j], a read circuit 120[n], a drive circuit 110, a circuit 10[1,1], a circuit 10[i,1], a circuit 10[m,1], a circuit 10[1,j], a circuit 10[i,j], a circuit 10[m,j], a circuit 10[1,n], a circuit 10[i,n], a circuit 10[m,n], wiring WX[1], wiring WX[j], wiring WX[n], wiring VX[1], wiring VX[i], wiring VX[m], and a memory cell array MCA, but other block diagrams, wirings, and symbols are omitted.

[0331] By composition Figure 22B The calculation circuit 202B shown can perform multiple calculations of formula (3.1) at the same time. Figure 22A In the description of the operation circuit 202A shown in FIG. Figure 18 The neurons N in the kth layer are shown j (k) Conducted z j (k) calculation, but by using Figure 22B The operation circuit 202B shown can simultaneously calculate the input Figure 18 The neuron N1 in the kth layer is shown (k) To neuron N n (k)u1 (k) to u n (k) .

[0332] The arithmetic circuit included in the semiconductor device of one embodiment of the present invention is not limited to the arithmetic circuit described in this embodiment. The arithmetic circuit included in the semiconductor device of one embodiment of the present invention may have a structure obtained by appropriately modifying the arithmetic circuit described in this embodiment.

[0333] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0334] (Implementation 6)

[0335] In this embodiment, a structural example of the OS transistor described in the above embodiment that can be applied to a semiconductor device is described.

[0336] <Structural Examples of Semiconductor Devices>

[0337] Figure 23 The semiconductor device shown includes a transistor 300 , a transistor 500 , and a capacitor 600 . Figure 25A is a cross-sectional view of the transistor 500 in the channel length direction. Figure 25B is a cross-sectional view of the transistor 500 in the channel width direction. Figure 25C is a cross-sectional view of the transistor 300 in the channel width direction.

[0338] Transistor 500 is a transistor containing a metal oxide in its channel formation region (OS transistor). Since transistor 500 has a low off-state current, long-term data retention is possible by using transistor 500 in a semiconductor device, particularly transistors M2 and M3 of circuit 10, transistors MA1 and MA2 of current source circuit 30, and transistors M24, M29, and M34 of bias cancel circuit 80. In other words, the frequency of refresh operations is low or no refresh operation is required, thereby reducing power consumption of the semiconductor device.

[0339] The semiconductor device described in this embodiment mode is as follows Figure 23 As shown, the circuit 10 includes a transistor 300, a transistor 500, and a capacitor 600. The transistor 500 is disposed above the transistor 300, and the capacitor 600 is disposed above the transistor 300 and the transistor 500. In addition, the capacitor 600 may be the capacitor C1 in the circuit 10.

[0340] Transistor 300 is provided on substrate 311 and includes: a conductor 316, an insulator 315, a semiconductor region 313 formed as a portion of substrate 311; and low-resistance regions 314a and 314b serving as source and drain regions. Transistor 300 can be applied to transistor M1 described in the above embodiment, for example.

[0341] like Figure 25C As shown, in transistor 300, conductor 316 covers the top surface and side surfaces of semiconductor region 313 in the channel width direction via insulator 315. By thus providing transistor 300 with a Fin structure, the effective channel width increases, thereby improving the on-state characteristics of transistor 300. Furthermore, since the influence of the electric field on the gate electrode can be reduced, the off-state characteristics of transistor 300 can be improved.

[0342] Furthermore, the transistor 300 may be a p-channel transistor or an n-channel transistor.

[0343] The channel formation region of the semiconductor region 313, the region adjacent thereto, the low-resistance region 314a and the low-resistance region 314b used as the source or drain region, and the like preferably comprise a semiconductor such as a silicon-based semiconductor, more preferably single-crystalline silicon. Alternatively, materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide) may be used. Silicon, in which the effective mass is controlled by applying stress to the crystal lattice and changing the interplanar spacing, may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) using GaAs, GaAlAs, or the like.

[0344] The low-resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus, or an element imparting p-type conductivity such as boron.

[0345] As the conductor 316 used as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0346] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the conductor material. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. To achieve both conductivity and embeddability, a laminate of a metal material such as tungsten or aluminum is preferably used as the conductor, with tungsten being particularly preferred for its heat resistance.

[0347] Notice, Figure 23 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method. For example, when a unipolar circuit having only OS transistors is used in a semiconductor device, as shown in FIG. Figure 24As shown in FIG. 3 , the structure of the transistor 300 may be the same as that of the transistor 500 using an oxide semiconductor. The structure of the transistor 500 will be described later.

[0348] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 300 .

[0349] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0350] Note that in this specification, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon nitride oxide" refers to a material containing more nitrogen than oxygen. Note that in this specification, "aluminum oxynitride" refers to a material containing more oxygen than nitrogen, while "aluminum nitride oxide" refers to a material containing more nitrogen than oxygen.

[0351] The insulator 322 can also be used as a planarization film to reduce steps caused by the transistor 300 provided thereunder. For example, to improve the flatness of the top surface of the insulator 322, the top surface can be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0352] As the insulator 324 , a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 311 , the transistor 300 , or the like into a region where the transistor 500 is provided is preferably used.

[0353] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferable to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 300. Specifically, the film that inhibits the diffusion of hydrogen refers to a film that has a small amount of hydrogen released.

[0354] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the film surface temperature in TDS analysis is within the range of 50°C to 500°C, and the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324, the amount of hydrogen released from the insulator 324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0355] Note that the relative dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0356] Furthermore, conductors 328 and 330, etc., connected to capacitor 600 or transistor 500, are embedded in insulators 320, 322, 324, and 326. Furthermore, conductors 328 and 330 function as plugs or wiring. Note that the same reference numeral may be used to represent multiple conductors that function as plugs or wiring. Furthermore, in this specification and other documents, a wiring and a plug connected to the wiring may be considered a single component. That is, a portion of a conductor may function as wiring, and a portion of a conductor may function as a plug.

[0357] As the material for each plug and wiring (conductor 328 and conductor 330, etc.), a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being particularly preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0358] A wiring layer may be formed on the insulator 326 and the conductor 330. Figure 23 In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed between the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. The conductor 356 can be formed using the same material as the conductors 328 and 330.

[0359] In addition, similar to insulator 324, insulator 350 is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 356 preferably includes a conductor having a hydrogen barrier property. In particular, a conductor having a hydrogen barrier property is formed within the opening of insulator 350 having a hydrogen barrier property. This structure allows transistor 300 and transistor 500 to be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0360] Note that tantalum nitride is preferably used as a conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the electrical conductivity as wiring can be maintained while also suppressing the diffusion of hydrogen from the transistor 300. In this case, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

[0361] Alternatively, a wiring layer may be formed on the insulator 354 and the conductor 356. For example, Figure 23 Insulator 360, insulator 362, and insulator 364 are stacked in this order. Furthermore, conductor 366 is formed between insulators 360, 362, and 364. Conductor 366 functions as a plug or wiring. Conductor 366 can be formed using the same material as conductors 328 and 330.

[0362] In addition, similar to insulator 324, insulator 360 is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 366 preferably includes a conductor having a hydrogen barrier property. It is particularly preferred that the conductor having a hydrogen barrier property be formed within the opening of insulator 360 having a hydrogen barrier property. By adopting this structure, transistor 300 and transistor 500 can be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0363] Alternatively, a wiring layer may be formed on the insulator 364 and the conductor 366. For example, Figure 23 Insulator 370, insulator 372, and insulator 374 are stacked in this order. Furthermore, conductor 376 is formed between insulators 370, 372, and 374. Conductor 376 functions as a plug or wiring. Conductor 376 can be formed using the same material as conductors 328 and 330.

[0364] In addition, similar to insulator 324, insulator 370 is preferably made of an insulator having hydrogen barrier properties, for example. Furthermore, conductor 376 preferably includes a conductor having hydrogen barrier properties. It is particularly preferred that the conductor having hydrogen barrier properties be formed within the opening of insulator 370 having hydrogen barrier properties. By adopting this structure, transistor 300 and transistor 500 can be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0365] Alternatively, a wiring layer may be formed on the insulator 374 and the conductor 376. Figure 23Insulator 380, insulator 382, ​​and insulator 384 are stacked in this order. Furthermore, conductor 386 is formed between insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. Conductor 386 can be formed using the same material as conductors 328 and 330.

[0366] In addition, similar to insulator 324, insulator 380 is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 386 preferably includes a conductor having a hydrogen barrier property. It is particularly preferred that the conductor having a hydrogen barrier property be formed within the opening of insulator 380 having a hydrogen barrier property. By adopting this structure, transistor 300 and transistor 500 can be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0367] While the above description includes a wiring layer including conductor 356, a wiring layer including conductor 366, a wiring layer including conductor 376, and a wiring layer including conductor 386, the semiconductor device of this embodiment is not limited thereto. The number of wiring layers identical to the wiring layer including conductor 356 may be three or fewer, and the number of wiring layers identical to the wiring layer including conductor 356 may be five or more.

[0368] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As one of the insulators 510, 512, 514, and 516, a substance having a barrier property against oxygen or hydrogen is preferably used.

[0369] For example, the insulator 510 and the insulator 514 are preferably made of a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 311 or the region where the transistor 300 is provided into the region where the transistor 500 is provided. Therefore, the insulator 510 and the insulator 514 can be made of the same material as the insulator 324.

[0370] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferable to provide a film that inhibits the diffusion of hydrogen between transistor 300 and transistor 500. Specifically, the film that inhibits the diffusion of hydrogen refers to a film that has a small amount of hydrogen released.

[0371] For example, as a film having a barrier property against hydrogen, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are preferably used for the insulator 510 and the insulator 514 .

[0372] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen and hydrogen and moisture that can cause changes in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0373] For example, the insulators 512 and 516 can use the same material as the insulator 320. Furthermore, by using a material with a low relative dielectric constant as the insulator, parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulators 512 and 516.

[0374] Furthermore, a conductor 518 or a conductor constituting the transistor 500 (for example, the conductor 503) is embedded in the insulators 510, 512, 514, and 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using the same material as the conductors 328 and 330.

[0375] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties to oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer having barrier properties to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 300 into the transistor 500.

[0376] The transistor 500 is provided above the insulator 516 .

[0377] like Figure 25A and Figure 25B As shown, transistor 500 includes: a conductor 503 embedded in an insulator 514 and an insulator 516; an insulator 520 arranged on the insulator 516 and the conductor 503; an insulator 522 arranged on the insulator 520; an insulator 524 arranged on the insulator 522; an oxide 530a arranged on the insulator 524; an oxide 530b arranged on the oxide 530a; a conductor 542a and a conductor 542b arranged on the oxide 530b and separated from each other; an insulator 580 arranged on the conductors 542a and 542b and having an opening overlapping with the conductors 542a and 542b; an oxide 530c arranged on the bottom and side surfaces of the opening; an insulator 550 arranged on the formation surface of the oxide 530c; and a conductor 560 arranged on the formation surface of the insulator 550.

[0378] In addition, if Figure 25A and Figure 25B As shown in FIG. 5 , an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Figure 25A and Figure 25B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 550 and a conductor 560b embedded inside the conductor 560a. Figure 25A and Figure 25B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 550 .

[0379] Note that below, the oxide 530 a , the oxide 530 b , and the oxide 530 c may be collectively referred to as an oxide 530 .

[0380] In the transistor 500, three layers of oxide 530a, oxide 530b, and oxide 530c are stacked in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. In addition, in the transistor 500, the conductor 560 has a two-layer structure, but the present invention is not limited to this. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that, Figure 23 、 Figure 25A and Figure 25B The structure of the transistor 500 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method.

[0381] Here, conductor 560 is used as the gate electrode of the transistor, and conductor 542a and conductor 542b are used as the source electrode or drain electrode. As described above, conductor 560 is buried in the opening of insulator 580 and in the area between conductor 542a and conductor 542b. The arrangement of conductor 560, conductor 542a, and conductor 542b relative to the opening of insulator 580 is selected to be self-aligned. In other words, in transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. As a result, conductor 560 can be formed without providing room for alignment, so the area occupied by transistor 500 can be reduced. As a result, miniaturization and high integration of semiconductor devices can be achieved.

[0382] Furthermore, conductor 560 is formed in a self-aligned manner in the region between conductor 542a and conductor 542b. Therefore, conductor 560 does not include any region overlapping conductors 542a and 542b. This reduces parasitic capacitance between conductor 560 and conductors 542a and 542b. Consequently, the switching speed of transistor 500 can be increased, enabling transistor 500 to have high-frequency characteristics.

[0383] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, by independently changing the potential supplied to conductor 503 without interlocking it with the potential supplied to conductor 560, the threshold voltage of transistor 500 can be controlled. In particular, by supplying a negative potential to conductor 503, the threshold voltage of transistor 500 can be made greater than 0V and the off-state current can be reduced. Therefore, when a negative potential is applied to conductor 503, the drain current when the potential supplied to conductor 560 is 0V can be reduced compared to when no negative potential is applied to conductor 503.

[0384] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated by the conductor 560 and the electric field generated by the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification, etc., the structure of a transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0385] Furthermore, conductor 503 has the same structure as conductor 518. Conductor 503a is formed so as to contact the inner walls of the openings of insulator 514 and insulator 516, and conductor 503b is formed inside the conductor 503a. Although conductor 503a and conductor 503b are stacked in transistor 500, the present invention is not limited to this. For example, conductor 503 may have a single-layer structure or a stacked structure of three or more layers.

[0386] Here, as the conductor 503a, a conductive material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (preventing these impurities from penetrating easily) is preferably used. Furthermore, a conductive material that has the function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (preventing this oxygen from penetrating easily) is preferably used. In this specification, "the function of inhibiting the diffusion of impurities or oxygen" refers to the function of inhibiting the diffusion of any one or both of these impurities and oxygen.

[0387] For example, by providing the conductor 503a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0388] Furthermore, when the conductor 503 also functions as wiring, a highly conductive material primarily composed of tungsten, copper, or aluminum is preferably used as the conductor 503b. In this case, the conductor 505 is not necessarily required. While the conductor 503b has a single-layer structure in the drawings, it may also have a laminated structure. For example, a laminated structure of titanium, titanium nitride, and the aforementioned conductive materials may be used.

[0389] The insulators 520 , 522 , and 524 serve as a second gate insulating film.

[0390] Here, an insulator 524 that is in contact with the oxide 530 preferably contains oxygen exceeding the stoichiometric composition. In other words, an excess oxygen region is preferably formed in the insulator 524. By providing the insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, thereby improving the reliability of the transistor 500.

[0391] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released, calculated as oxygen atoms in TDS (Thermal Desorption Spectroscopy), is 1.0×10 18 atoms / cm 3 above, preferably 1.0×10 19 atoms / cm 3 More than 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0392] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0393] When the insulator 522 has a function of suppressing the diffusion of oxygen or impurities, it is preferable because oxygen contained in the oxide 530 does not diffuse toward the insulator 520. In addition, the conductor 503 can be suppressed from reacting with oxygen contained in the insulator 524 or the oxide 530.

[0394] As the insulator 522, for example, a single layer or stack of insulators made of so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) is preferably used. As transistors are miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material as the insulator used as the gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0395] In particular, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used as an insulating material that has the function of suppressing the diffusion of impurities and oxygen (making oxygen less likely to permeate). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When such a material is used to form the insulator 522, the insulator 522 serves as a layer that suppresses the release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the surrounding area of ​​the transistor 500.

[0396] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0397] The insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferred because of their thermal stability. Furthermore, by combining an insulator made of a high-k material with silicon oxide or silicon oxynitride, a stacked structure of the insulator 520 can be formed that is thermally stable and has a high relative dielectric constant.

[0398] In addition, Figure 25A and Figure 25B In the transistor 500 shown, the second gate insulating film has a three-layer stacked structure including an insulator 520, an insulator 522, and an insulator 524. However, the second gate insulating film may also have a stacked structure of a single layer, two layers, or four or more layers. In this case, the stacked structure is not limited to being made of the same material and may also be made of different materials.

[0399] In the transistor 500, a metal oxide used as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably CAAC-OS or CAC-OS described in Embodiment 4. In addition, as the oxide 530, In-Ga oxide or In-Zn oxide can also be used.

[0400] The metal oxide used as the channel formation region in the oxide 530 preferably has a band gap of 2 eV or greater, preferably 2.5 eV or greater. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0401] In oxide 530, when oxide 530a is provided below oxide 530b, impurities can be prevented from diffusing from structures below oxide 530a to oxide 530b. When oxide 530c is provided above oxide 530b, impurities can be prevented from diffusing from structures above oxide 530c to oxide 530b.

[0402] Furthermore, the oxide 530 preferably has a stacked structure of oxides having different atomic number ratios of metal atoms. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used in the oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used in the oxide 530b. Furthermore, the atomic number ratio of the element M relative to In in the metal oxide used in the oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used in the oxide 530b. Furthermore, the atomic number ratio of In relative to the element M in the metal oxide used in the oxide 530b is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used in the oxide 530a. Furthermore, the metal oxide that can be used for either the oxide 530a or the oxide 530b can be used for the oxide 530c.

[0403] The conduction band bottom energies of oxides 530a and 530c are preferably higher than the conduction band bottom energy of oxide 530b. In other words, the electron affinity of oxides 530a and 530c is preferably lower than that of oxide 530b.

[0404] Here, the energy level of the conduction band bottom changes smoothly at the junction of oxide 530a, oxide 530b, and oxide 530c. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of oxide 530a, oxide 530b, and oxide 530c changing continuously or being continuously connected. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c.

[0405] Specifically, by making oxide 530a and oxide 530b, and oxide 530b and oxide 530c contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. are preferably used as oxide 530a and oxide 530c.

[0406] In this case, the main path for carriers is through oxide 530b. By making oxide 530a and oxide 530c have the above structure, the defect state density at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c, can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0407] Conductors 542a and 542b, serving as source and drain electrodes, are provided on oxide 530b. Conductors 542a and 542b are preferably metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing these metal elements, or alloys combining these metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are also preferred because they have barrier properties against hydrogen and oxygen.

[0408] In addition, although Figure 25AAlthough single-layer conductors 542a and 542b are shown, a stacked structure of two or more layers may be employed. For example, a stacked tantalum nitride film and a tungsten film is preferred. Alternatively, a stacked titanium film and an aluminum film may be employed. Furthermore, a two-layer structure comprising an aluminum film stacked on a tungsten film, a two-layer structure comprising a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure comprising a copper film stacked on a titanium film, or a two-layer structure comprising a copper film stacked on a tungsten film may also be employed.

[0409] Alternatively, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon; a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon; or a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0410] In addition, if Figure 25A As shown, regions 543a and 543b may be formed as low-resistance regions at and near the interface between oxide 530 and conductor 542a (conductor 542b). In this case, region 543a serves as one of the source and drain regions, while region 543b serves as the other. Furthermore, a channel formation region is formed in the region sandwiched between regions 543a and 543b.

[0411] By forming the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer composed of the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in the region 543a (region 543b). In this case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0412] The insulator 544 is provided to cover the conductors 542 a and 542 b to suppress oxidation of the conductors 542 a and 542 b . In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and to be in contact with the insulator 524 .

[0413] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, and magnesium. Alternatively, the insulator 544 can be made of silicon nitride oxide or silicon nitride.

[0414] In particular, as the insulator 544, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium oxides, is preferably used. Hafnium aluminate is particularly heat-resistant compared to hafnium oxide films. Therefore, it is less likely to crystallize during the subsequent heat treatment process, making it preferred. Furthermore, if the conductors 542a and 542b are made of oxidation-resistant materials or their conductivity does not significantly decrease even after oxygen absorption, the insulator 544 is not necessarily required. Appropriate design can be used depending on the desired transistor characteristics.

[0415] The inclusion of the insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b through the oxide 530c and the insulator 550. In addition, oxidation of the conductor 560 by excess oxygen contained in the insulator 580 can be prevented.

[0416] Insulator 550 is used as a first gate insulating film. Insulator 550 is preferably disposed in contact with the inner side (top and side surfaces) of oxide 530c. Similar to insulator 524, insulator 550 is preferably formed using an insulator containing excess oxygen that releases oxygen upon heating.

[0417] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0418] By providing an insulator that releases oxygen when heated as the insulator 550 in contact with the top surface of the oxide 530c, oxygen can be efficiently supplied from the insulator 550 through the oxide 530c to the channel formation region of the oxide 530b. Furthermore, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 550. The thickness of the insulator 550 is preferably not less than 1 nm and not more than 20 nm.

[0419] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 550 to the conductor 560. Providing a metal oxide that suppresses oxygen diffusion suppresses the diffusion of excess oxygen from the insulator 550 to the conductor 560. In other words, the reduction in excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As this metal oxide, a material that can be used for the insulator 544 can be used.

[0420] Furthermore, similar to the second gate insulating film, the insulator 550 can also have a stacked structure. As transistors become increasingly miniaturized and highly integrated, the thinner the gate insulating film becomes, the more problems such as leakage current may arise. Therefore, by making the insulator used as the gate insulating film a stacked structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Furthermore, a stacked structure with thermal stability and a high relative dielectric constant can be achieved.

[0421] exist Figure 25A and Figure 25B In the embodiment, the conductor 560 used as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0422] As the conductor 560a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b due to the oxygen contained in the insulator 550 and the decrease in conductivity. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide is preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be applied to the oxide 530 can be used. At this time, by forming the conductor 560a using a sputtering method, the resistance value of the conductor 560b can be reduced to make it a conductor. The conductor can be referred to as an OC (Oxide Conductor) electrode.

[0423] Conductor 560b is preferably a conductive material primarily composed of tungsten, copper, or aluminum. Since conductor 560b also functions as wiring, it is preferable to use a highly conductive material. For example, a conductive material primarily composed of tungsten, copper, or aluminum can be used. Conductor 560b may also have a laminated structure; for example, a laminated structure of titanium, titanium nitride, and the aforementioned conductive materials can be used.

[0424] Insulator 580 is preferably provided on conductors 542a and 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, insulator 580 preferably comprises silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, silicon oxide with pores, or resin. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide and silicon oxide with pores are particularly preferred because they easily form excess oxygen regions in subsequent steps.

[0425] The insulator 580 preferably has an excess oxygen region. By placing the insulator 580, which releases oxygen upon heating, in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Furthermore, the concentration of impurities such as water and hydrogen in the insulator 580 is preferably reduced.

[0426] The opening of the insulator 580 is formed so as to overlap with the region between the conductors 542a and 542b. Thus, the conductor 560 is embedded in the opening of the insulator 580 and in the region between the conductors 542a and 542b.

[0427] As semiconductor devices are miniaturized, gate lengths need to be shortened, but a decrease in the conductivity of the conductor 560 must be prevented. To this end, increasing the thickness of the conductor 560 may result in the conductor 560 having a high aspect ratio. In this embodiment, the conductor 560 is embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a high aspect ratio, it does not collapse during the process.

[0428] The insulator 574 is preferably provided so as to be aligned with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be formed in the insulator 550 and the insulator 580. Oxygen can thereby be supplied from the excess oxygen region to the oxide 530.

[0429] For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0430] In particular, aluminum oxide has high barrier properties, and even thin films with a thickness of 0.5 nm to 3.0 nm can inhibit the diffusion of hydrogen and nitrogen. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0431] Furthermore, an insulator 581 serving as an interlayer film is preferably provided over the insulator 574. As with the insulator 524 and the like, the concentration of impurities such as water and hydrogen in the insulator 581 is preferably reduced.

[0432] Furthermore, conductors 540a and 540b are disposed in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductors 540a and 540b are disposed so as to face each other with conductor 560 interposed therebetween. Conductors 540a and 540b have the same structure as conductors 546 and 548 described later.

[0433] An insulator 582 is provided on the insulator 581. A material having a barrier property against oxygen or hydrogen is preferably used for the insulator 582. Therefore, the insulator 582 can be made of the same material as the insulator 514. For example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 582.

[0434] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen and hydrogen and moisture that can cause changes in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0435] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. Furthermore, by using a material with a low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used for the insulator 586.

[0436] Furthermore, the conductors 546 and 548 are embedded in the insulators 520 , 522 , 524 , 544 , 580 , 574 , 581 , 582 , and 586 .

[0437] The conductor 546 and the conductor 548 are used as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using the same material as the conductors 328 and 330.

[0438] Next, a capacitor 600 is provided above the transistor 500 . The capacitor 600 includes a conductor 610 , a conductor 620 , and an insulator 630 .

[0439] Furthermore, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 serves as a plug or wiring connected to the transistor 500. The conductor 610 serves as an electrode of the capacitor 600. The conductor 612 and the conductor 610 may be formed at the same time.

[0440] As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be used.

[0441] exist Figure 23 In the embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto and may have a stacked structure of two or more layers. For example, a conductor having high adhesion to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0442] Conductor 620 is provided so as to overlap conductor 610 via insulator 630. Conductor 620 can be made of a conductive material such as a metal, alloy, or metal oxide. High-melting-point materials such as tungsten or molybdenum, which are both heat-resistant and conductive, are preferably used, with tungsten being particularly preferred. When conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal such as Cu (copper) or Al (aluminum) can be used.

[0443] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. In addition, the insulator 650 can be used as a planarization film that covers the concavo-convex shape thereunder.

[0444] This structure can suppress variations in the electrical characteristics of a semiconductor device using a transistor including an oxide semiconductor while improving reliability. Furthermore, it can achieve miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor.

[0445] Example of Transistor Structure

[0446] Note that the structure of the transistor 500 in the semiconductor device described in this embodiment is not limited to the structure described above. Examples of structures that can be used for the transistor 500 are described below. Note that the transistors described below are modified examples of the transistors described above, so the following description focuses on differences and sometimes omits similarities.

[0447] Transistor Structure Example 1

[0448] Reference Figures 26A to 26C An example structure of the transistor 500A will be described. Figure 26A is a top view of transistor 500A. Figure 26B is Figure 26A sectional view of the portion indicated by the dot-dash line L1-L2. Figure 26C is Figure 26A A cross-sectional view of the portion indicated by the dotted line W1-W2. Figure 26A In the top view, some of the components are omitted for clarity.

[0449] exist Figures 26A to 26C The transistor 500A shown in FIG. Figure 25A The transistor 500 shown in the figure further includes an insulator 511 serving as an interlayer film and a conductor 505 serving as wiring.

[0450] In addition, Figures 26A to 26C In the transistor 500A shown, an oxide 530c, an insulator 550, and a conductor 560 are arranged in an opening provided in an insulator 580 via an insulator 544. The oxide 530c, the insulator 550, and the conductor 560 are arranged between the conductor 542a and the conductor 542b.

[0451] As the insulator 511, a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to these insulators. In addition, these insulators can also be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can also be stacked on the above-mentioned insulators.

[0452] For example, the insulator 511 is preferably used as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 500A from the substrate side. Therefore, as the insulator 511, it is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (it is not easy for the above impurities to pass through). In addition, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (it is not easy for the above oxygen to pass through). In addition, for example, aluminum oxide or silicon nitride is preferably used as the insulator 511. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulator 511 to the side of the transistor 500A.

[0453] For example, the dielectric constant of the insulator 512 is preferably lower than that of the insulator 511. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0454] Conductor 505 is formed so as to be embedded in insulator 512. The top surface of conductor 505 can be substantially the same height as the top surface of insulator 512. FIG. 26 illustrates conductor 505 as having a single-layer structure, but the present invention is not limited thereto. For example, conductor 505 may also have a multilayer film structure with two or more layers. A highly conductive material primarily composed of tungsten, copper, or aluminum is preferably used for conductor 505.

[0455] Insulators 514 and 516, like insulators 511 and 512, serve as interlayer films. For example, insulator 514 is preferably used as a barrier film to prevent impurities such as water and hydrogen from entering transistor 500A from the substrate side. This structure prevents impurities such as hydrogen and water from diffusing from the side closer to the substrate than insulator 514 to the transistor 500A side. For example, insulator 516 preferably has a lower dielectric constant than insulator 514. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance generated between wirings.

[0456] The insulator 522 preferably has a barrier property. When the insulator 522 has a barrier property, the insulator 522 serves as a layer that suppresses impurities such as hydrogen from entering the transistor 500A from the periphery of the transistor 500A.

[0457] The oxide 530 c is preferably provided in the opening provided in the insulator 580 via the insulator 544 . When the insulator 544 has a barrier property, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.

[0458] Alternatively, a barrier layer may be provided on the conductors 542a and 542b. The barrier layer is preferably made of a material that has a barrier property against oxygen or hydrogen. This structure can prevent oxidation of the conductors 542a and 542b during the formation of the insulator 544.

[0459] The barrier layer can be made of, for example, a metal oxide. In particular, an insulating film having barrier properties against oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide, is preferably used. Alternatively, silicon nitride formed by CVD may be used.

[0460] The inclusion of a barrier layer broadens the range of materials available for conductors 542a and 542b. For example, conductors 542a and 542b can be made of materials with low oxidation resistance and high conductivity, such as tungsten or aluminum. Furthermore, conductors that are easy to deposit or process can be used.

[0461] The insulator 550 serves as a first gate insulating film and is preferably provided in an opening provided in the insulator 580 via the oxide 530 c and the insulator 544 .

[0462] As with conductor 503, conductors 540a and 540b can be made of a single layer or a stack of conductive materials such as metals, alloys, metal nitrides, or metal oxides. For example, a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and electrical conductivity, is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. Using a low-resistance conductive material can reduce wiring resistance.

[0463] For example, by using a stacked structure of tantalum nitride or the like, which has a barrier property against hydrogen and oxygen, and tungsten, which has high conductivity, as the conductors 540a and 540b, the conductivity of the wiring can be maintained while suppressing the diffusion of impurities from the outside.

[0464] With the above structure, a semiconductor device having a transistor including an oxide semiconductor with a large on-state current can be provided. Furthermore, a semiconductor device having a transistor including an oxide semiconductor with a small off-state current can be provided. Furthermore, a semiconductor device having stable electrical characteristics while suppressing fluctuations in electrical characteristics and having improved reliability can be provided.

[0465] Transistor Structure Example 2

[0466] Reference Figures 27A to 27C An example structure of the transistor 500B will be described. Figure 27A is a top view of transistor 500B. Figure 27B is Figure 27A sectional view of the portion indicated by the dot-dash line L1-L2. Figure 27C is Figure 27A A cross-sectional view of the portion indicated by the dotted line W1-W2. Figure 27A In the top view, some of the components are omitted for clarity.

[0467] The transistor 500B is a modified example of the transistor 500A. Therefore, to avoid duplication of descriptions, the description will focus mainly on the differences from the transistor 500A.

[0468] The transistor 500B includes a region where the conductor 542a (conductor 542b), the oxide 530c, the insulator 550, and the conductor 560 overlap. This structure can provide a transistor with high on-state current and high controllability.

[0469] Conductor 560, serving as the first gate electrode, includes conductor 560a and conductor 560b on conductor 560a. Similar to conductor 503a, conductor 560a is preferably made of a conductive material that inhibits the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Furthermore, a conductive material that inhibits the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) is also preferably used.

[0470] When the conductor 560a has the function of suppressing the diffusion of oxygen, the selectivity of the material of the conductor 560b can be improved. In other words, by including the conductor 560a, oxidation of the conductor 560b can be suppressed, thereby preventing a decrease in conductivity.

[0471] Furthermore, the insulator 544 is provided so as to cover the top surface and side surfaces of the conductor 560 , the side surfaces of the insulator 550 , and the side surfaces of the oxide 530 c .

[0472] The insulator 544 can suppress oxidation of the conductor 560. In addition, the insulator 544 can suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 into the transistor 500B.

[0473] Furthermore, the structure of the contact hole of transistor 500B differs from that of transistor 500A. In transistor 500B, an insulator 576a (insulator 576b) having a barrier property is provided between the conductor 546a (conductor 546b) serving as the contact hole and the insulator 580. The provision of the insulator 576a (insulator 576b) prevents oxygen in the insulator 580 from reacting with the conductor 546 and causing oxidation of the conductor 546.

[0474] Furthermore, by providing an insulator 576a (insulator 576b) having a barrier property, the range of materials available for the conductors used for the plugs or wiring can be expanded. For example, by using a metal material that has oxygen absorption properties and high conductivity as the conductor 546a (conductor 546b), a low-power semiconductor device can be provided. Specifically, materials with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used. Furthermore, for example, conductors that are easy to deposit or process can be used.

[0475] Transistor Structure Example 3

[0476] Reference Figures 28A to 28C An example structure of the transistor 500C will be described. Figure 28A is a top view of transistor 500C. Figure 28B is Figure 28A sectional view of the portion indicated by the dot-dash line L1-L2. Figure 28C is Figure 28AA cross-sectional view of the portion indicated by the dotted line W1-W2. Figure 28A In the top view, some of the components are omitted for clarity.

[0477] The transistor 500C is a modified example of the transistor 500A. Therefore, to avoid duplication of descriptions, the description will focus mainly on the differences from the transistor 500A.

[0478] Figures 28A to 28C The transistor 500C shown has a conductor 547a disposed between the conductor 542a and the oxide 530b, and a conductor 547b disposed between the conductor 542b and the oxide 530b. Here, the conductor 542a (conductor 542b) has a region extending beyond the top surface of the conductor 547a (conductor 547b) and the side surface on one side of the conductor 560 and in contact with the top surface of the oxide 530b. Here, any conductor that can be used for the conductors 542a and 542b can be used. Furthermore, the thickness of the conductors 547a and 547b is preferably at least greater than that of the conductors 542a and 542b.

[0479] because Figures 28A to 28C The transistor 500C shown has the above structure, and compared to the transistor 500A, the conductors 542a and 542b can be closer to the conductor 560. Alternatively, the ends of the conductors 542a and 542b can overlap with the conductor 560. This can reduce the substantial channel length of the transistor 500C, thereby improving the on-state current and frequency characteristics.

[0480] Furthermore, the conductor 547a (conductor 547b) preferably overlaps the conductor 542a (conductor 542b). With this structure, when etching to form the opening that fills the conductor 540a (conductor 540b), the conductor 547a (conductor 547b) serves as an etching stopper, thereby preventing overetching of the oxide 530b.

[0481] In addition, Figures 28A to 28C In the transistor 500C shown, an insulator 545 is provided in contact with an insulator 544. The insulator 544 is preferably used as a blocking insulating film to prevent impurities such as water and hydrogen, or excess oxygen, from entering the transistor 500C from the insulator 580 side. The insulator 545 can be any insulator that can be used for the insulator 544. Alternatively, the insulator 544 can be a nitride insulator such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon nitride, or silicon oxynitride.

[0482] In addition, Figures 28A to 28C The transistor 500C shown, with Figures 26A to 26CUnlike the transistor 500A shown, the conductor 503 has a single-layer structure. In this case, an insulating film serving as the insulator 516 can be formed on the patterned conductor 503, and the top of the insulating film can be removed by a CMP method or the like until the top surface of the conductor 503 is exposed. Here, it is preferable to improve the flatness of the top surface of the conductor 503. For example, the average surface roughness (Ra) of the top surface of the conductor 503 can be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. As a result, the flatness of the insulating layer formed on the conductor 503 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be improved.

[0483] Transistor Structure Example 4

[0484] Reference Figures 29A to 29C An example structure of the transistor 500D will be described. Figure 29A is a top view of transistor 500D. Figure 29B is Figure 29A sectional view of the portion indicated by the dot-dash line L1-L2. Figure 29C is Figure 29A A cross-sectional view of the portion indicated by the dotted line W1-W2. Figure 29A In the top view, some of the components are omitted for clarity.

[0485] The transistor 500D is a modified example of the above-described transistor. Therefore, to avoid duplication of descriptions, the description will focus on the differences from the above-described transistor.

[0486] Unlike transistor 500, transistors 500A to 500C, Figures 29A to 29C The transistor 500D shown includes regions 531a and 531b in a portion of the surface of the exposed oxide 530b, without the conductors 542a and 542b. One of the regions 531a and 531b is used as a source region, and the other is used as a drain region.

[0487] In addition, with Figures 28A to 28C Similar to the transistor 500C shown in FIG, the transistor 500D uses the conductor 503, which functions as a second gate, as a wiring, without providing the conductor 505. Furthermore, an insulator 550 is provided on the oxide 530c, and a metal oxide 552 is provided on the insulator 550. Furthermore, a conductor 560 is provided on the metal oxide 552, and an insulator 570 is provided on the conductor 560. Furthermore, an insulator 571 is provided on the insulator 570.

[0488] The metal oxide 552 preferably has a function of inhibiting oxygen diffusion. By providing the metal oxide 552, which inhibits oxygen diffusion, between the insulator 550 and the conductor 560, oxygen diffusion into the conductor 560 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 by oxygen can be suppressed.

[0489] Alternatively, the metal oxide 552 may be used as part of the first gate electrode. For example, the oxide semiconductor that can be used as the oxide 530 may be used as the metal oxide 552. In this case, by forming the conductor 560 by sputtering, the resistance of the metal oxide 552 can be reduced, thereby converting it into a conductive layer. This may be referred to as an OC (Oxide Conductor) electrode.

[0490] In addition, the metal oxide 552 is sometimes used as part of the gate insulating film. Therefore, when silicon oxide or silicon oxynitride is used as the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide 552. By adopting this stacked structure, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating film can be reduced.

[0491] Although the metal oxide 552 in the transistor 500D is shown as a single-layer structure, a stacked structure of two or more layers may be employed. For example, a metal oxide serving as part of a gate electrode and a metal oxide serving as part of a gate insulating film may be stacked.

[0492] When the metal oxide 552 is used as the gate electrode, the on-state current of the transistor 500D can be increased without weakening the influence of the electric field from the conductor 560. Furthermore, when the metal oxide 552 is used as the gate insulating film, the distance between the conductor 560 and the oxide 530 can be maintained by utilizing the physical thickness of the insulator 550 and the metal oxide 552, thereby suppressing leakage current between the conductor 560 and the oxide 530. Thus, by providing a stacked structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the intensity of the electric field applied from the conductor 560 to the oxide 530 can be easily adjusted.

[0493] Specifically, an oxide semiconductor that can be used for the oxide 530 can be used as the metal oxide 552 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0494] In particular, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as an insulating layer containing an oxide of one or both of aluminum and hafnium. Hafnium aluminate is particularly preferred because it has higher heat resistance than hafnium oxide films. Therefore, it is less likely to crystallize during the subsequent heat treatment process. Note that the metal oxide 552 is not an essential component and can be appropriately designed based on the desired transistor characteristics.

[0495] An insulating material that inhibits the permeation of impurities such as water and hydrogen, as well as oxygen, is preferably used as the insulator 570. For example, aluminum oxide or hafnium oxide is preferably used. This prevents oxidation of the conductor 560 by oxygen from above the insulator 570. Furthermore, impurities such as water and hydrogen from above the insulator 570 are prevented from entering the oxide 530 through the conductor 560 and the insulator 550.

[0496] The insulator 571 is used as a hard mask. Providing the insulator 571 allows the conductor 560 to be processed so that the side surface of the conductor 560 is approximately perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductor 560 and the substrate surface can be made greater than or equal to 75 degrees and less than or equal to 100 degrees, preferably greater than or equal to 80 degrees and less than or equal to 95 degrees.

[0497] Alternatively, the insulator 571 may also function as a barrier layer by using an insulating material having a function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen. In this case, the insulator 570 may not be provided.

[0498] By using the insulator 571 as a hard mask, the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and part of the oxide 530c are selectively removed, whereby their side surfaces can be made substantially aligned and part of the surface of the oxide 530b can be exposed.

[0499] Furthermore, the transistor 500D includes a region 531a and a region 531b in a portion of the surface of the exposed oxide 530b. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region.

[0500] For example, the regions 531 a and 531 b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed oxide 530 b by ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. Note that in this embodiment and other embodiments, "impurity element" refers to an element other than the main component element.

[0501] Alternatively, after partially exposing the surface of the oxide 530 b , a metal film may be formed, and then heat treatment may be performed to diffuse elements contained in the metal film into the oxide 530 b , thereby forming the regions 531 a and 531 b .

[0502] The resistivity of a portion of the oxide 530b into which the impurity element has been introduced decreases. Therefore, the regions 531a and 531b are sometimes referred to as "impurity regions" or "low-resistance regions."

[0503] By using the insulator 571 and / or the conductor 560 as a mask, the regions 531a and 531b can be formed in a self-aligned manner. Therefore, the regions 531a and / or 531b do not overlap with the conductor 560, which can reduce parasitic capacitance. Furthermore, the bias region is not formed between the channel formation region and the source / drain region (region 531a or region 531b). By forming the regions 531a and 531b in a self-aligned manner, it is possible to increase the on-state current, reduce the threshold voltage, and increase the operating frequency.

[0504] Furthermore, to further reduce the off-state current, a bias region may be provided between the channel formation region and the source / drain region. The bias region is a region with high resistivity and is not subjected to the aforementioned impurity element introduction. The bias region can be formed by introducing the aforementioned impurity element after forming the insulator 575. In this case, the insulator 575 also serves as a mask, similar to the insulator 571. Therefore, the region of the oxide 530b that overlaps with the insulator 575 is not subjected to the introduction of the impurity element, thereby maintaining the resistivity of this region high.

[0505] Transistor 500D includes an insulator 575 on the side of insulator 570, conductor 560, metal oxide 552, insulator 550, and oxide 530c. Insulator 575 is preferably an insulator with a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resin is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores is used for insulator 575, it is preferred because excess oxygen regions can be easily formed in insulator 575 in subsequent steps. In addition, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In addition, insulator 575 preferably has the function of diffusing oxygen.

[0506] Furthermore, transistor 500D includes an insulator 544 over insulator 575 and oxide 530. Insulator 544 is preferably formed by sputtering. Using sputtering allows the formation of an insulator with low levels of impurities such as water and hydrogen. For example, aluminum oxide is preferably used as insulator 544.

[0507] Oxide films formed by sputtering sometimes extract hydrogen from the structure being formed. Therefore, the insulator 544 extracts hydrogen and water from the oxide 530 and the insulator 575, thereby reducing the hydrogen concentration in the oxide 530 and the insulator 575.

[0508] Transistor Structure Example 5

[0509] Reference Figures 30A to 30C An example structure of the transistor 500E will be described. Figure 30A is a top view of transistor 500E. Figure 30B is Figure 30A sectional view of the portion indicated by the dot-dash line L1-L2. Figure 30C is Figure 30A A cross-sectional view of the portion indicated by the dotted line W1-W2. Figure 30A In the top view, some of the components are omitted for clarity.

[0510] The transistor 500E is a modified example of the above-described transistor. Therefore, to avoid duplication of descriptions, the description will focus on the differences from the above-described transistor.

[0511] exist Figures 30A to 30C In the transistor 500D, as in the transistor 500D, the exposed portion of the surface of the oxide 530b includes regions 531a and 531b, without the conductors 542a and 542b. One of the regions 531a and 531b is used as a source region, and the other is used as a drain region. Furthermore, an insulator 573 is provided between the oxide 530b and the insulator 544.

[0512] Figure 30B The regions 531a and 531b shown are regions in which the following elements are added to the oxide 530b. The regions 531a and 531b can be formed using, for example, dummy gates.

[0513] Specifically, a dummy gate is provided on oxide 530b, and using this dummy gate as a mask, an element that reduces the resistance of a portion of oxide 530b is added to oxide 530b. Specifically, this element is added to the region of oxide 530 that does not overlap with the dummy gate, thereby forming regions 531a and 531b. Methods for adding this element include ion implantation, which involves mass-separating ionized source gas before addition; ion doping, which involves adding ionized source gas without mass-separating ion gas; and plasma immersion ion implantation.

[0514] Elements that reduce the resistance of a portion of the oxide 530b are typically boron or phosphorus. Alternatively, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, or a rare gas may be used. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. The concentration of these elements can be measured using secondary ion mass spectrometry (SIMS).

[0515] In particular, boron and phosphorus can be added to equipment in a production line for Si transistors whose semiconductor layers include amorphous silicon or low-temperature polysilicon. Therefore, using equipment in this production line can reduce the resistance of a portion of oxide 530b. In other words, a portion of the production line for Si transistors can be used in the manufacturing process of transistor 500E.

[0516] Next, an insulating film serving as the insulator 573 and an insulating film serving as the insulator 544 may be formed over the oxide 530b and the dummy gate. By providing a stack of the insulating film serving as the insulator 573 and the insulating film serving as the insulator 544, a region where the region 531a or the region 531b overlaps with the oxide 530c and the insulator 550 can be provided.

[0517] Specifically, an insulating film serving as the insulator 580 is provided on the insulating film serving as the insulator 544, and then the insulating film serving as the insulator 580 is subjected to a CMP (Chemical Mechanical Polishing) process to remove a portion of the insulating film serving as the insulator 580, thereby exposing the dummy gate. Next, when removing the dummy gate, it is preferred to also remove a portion of the insulator 573 in contact with the dummy gate. As a result, the insulator 544 and the insulator 573 are exposed on the side of the opening provided in the insulator 580, and a portion of the region 531a and the region 531b provided in the oxide 530b are exposed on the bottom surface of the opening. Next, an oxide film serving as the oxide 530c, an insulating film serving as the insulator 550, and a conductive film serving as the conductor 560 are sequentially formed in the opening, and then a portion of the oxide film serving as the oxide 530c, the insulating film serving as the insulator 550, and the conductive film serving as the conductor 560 are removed by CMP or the like until the insulator 580 is exposed, thereby forming a gate. Figures 30A to 30C transistor shown.

[0518] Note that the insulator 573 and the insulator 544 are not necessarily provided and may be appropriately designed according to required transistor characteristics.

[0519] Figures 30A to 30C The transistor shown can utilize an existing device, and the conductor 542a (conductor 542b) is not provided, thereby reducing costs.

[0520] Transistor Structure Example 6

[0521] Although Figure 25A and Figure 25B 5 shows a structural example in which the conductor 560 used as a gate is formed inside the opening of the insulator 580, but, for example, a structure in which the insulator is provided above the conductor may be employed. Figure 31A 、 Figure 31B 、 Figure 32A and Figure 32B An example of the structure of such a transistor is shown.

[0522] Figure 31A is a top view of the transistor, Figure 31B is a three-dimensional diagram of a transistor. In addition, Figure 32A Shown along Figure 31A The cross-sectional view of L1-L2 in Figure 32B Shown along Figure 31A Cross-sectional view of W1-W2 in FIG.

[0523] Figure 31A 、 Figure 31B 、 Figure 32A and Figure 32B The transistor shown includes a conductor BGE that functions as a back gate, an insulator BGI that functions as a gate insulating film, an oxide semiconductor S, an insulator FGI that functions as a gate insulating film, a conductor FGE that functions as a front gate, and a conductor WE that functions as a wiring. Furthermore, the conductor PE functions as a plug that connects the conductor WE to the oxide S, the conductor BGE, or the conductor FGE. Note that the example shown here shows the oxide semiconductor S consisting of three layers of oxides S1, S2, and S3.

[0524] <Capacitor Structure Example>

[0525] exist Figures 33A to 33C As a tool that can be applied to Figure 23 The example of the capacitor 600 of the semiconductor device shown is a capacitor 600A. Figure 33A is a top view of capacitor 600A. Figure 33B is a perspective view of a cross section of the capacitor 600A along the dashed line L3 - L4 , Figure 33C It is a perspective view of a cross section of the capacitor 600A taken along the dashed line W3 - L4 .

[0526] The conductor 610 is used as one of a pair of electrodes of the capacitor 600A, and the conductor 620 is used as the other of the pair of electrodes of the capacitor 600A. In addition, the insulator 630 is used as a dielectric interposed between the pair of electrodes.

[0527] The capacitor 600A is electrically connected to the conductor 546 and the conductor 548 below the conductor 610. The conductor 546 and the conductor 548 are used as plugs or wiring for connecting to other circuit elements. Figure 33B and Figure 33C , the conductor 546 and the conductor 548 are collectively referred to as the conductor 540 .

[0528] In addition, Figures 33A to 33C In order to clearly illustrate the drawings, the insulator 586 in which the conductors 546 and 548 are embedded and the insulator 650 covering the conductors 620 and 630 are omitted.

[0529] Notice, Figure 23 The capacitor 600 and Figures 33A to 33C The capacitor 600A shown is a planar type, but the shape of the capacitor is not limited to this. For example, the capacitor 600 may also be Figures 34A to 34C The cylinder type capacitor 600B is shown.

[0530] Figure 34A is a top view of capacitor 600B. Figure 34B is a cross-sectional view of the capacitor 600B along the dot-dash line L3 - L4, Figure 34C It is a perspective view of a cross section of the capacitor 600B taken along the dashed line W3 - L4 .

[0531] exist Figure 34B In FIG, capacitor 600B includes an insulator 631 on insulator 586 in which conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 as one of a pair of electrodes, and a conductor 620 as the other of the pair of electrodes.

[0532] In addition, Figure 34C In order to clearly illustrate the drawings, the insulator 586, the insulator 650, and the insulator 651 are omitted.

[0533] As the insulator 631 , for example, the same material as that of the insulator 586 can be used.

[0534] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of the same material as the conductor 330 and the conductor 518, for example.

[0535] As the insulator 651 , for example, the same material as that of the insulator 586 can be used.

[0536] Furthermore, as described above, the insulator 651 has an opening, and the opening overlaps with the conductor 611 .

[0537] The conductor 610 is formed on the bottom and side surfaces of the opening. In other words, the conductor 610 overlaps with the conductor 611 and is electrically connected to the conductor 611.

[0538] The conductor 610 is formed by forming an opening in the insulator 651 by etching or the like, and then forming the conductor 610 by sputtering, ALD, or the like. The conductor 610 formed on the insulator 651 is then removed by CMP (Chemical Mechanical Polishing) or the like, so that the conductor 610 formed in the opening remains.

[0539] The insulator 630 is located on the insulator 651 and on the surface where the conductor 610 is formed. In addition, the insulator 630 is used as a dielectric sandwiched between a pair of electrodes in the capacitor.

[0540] The conductor 620 is provided on the insulator 630 so as to fill the opening of the insulator 651 .

[0541] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0542] Figures 34A to 34C The cylinder-type capacitor 600B shown can have a higher capacitance value than the planar-type capacitor 600A. Therefore, by using the capacitor 600B as, for example, the capacitors C1, C3, C11, C12, CD4, CD8, and CD12 described in the above embodiments, the voltage between the capacitor terminals can be maintained for a long period of time.

[0543] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0544] (Implementation 6)

[0545] This embodiment describes the structures of metal oxides CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) and CAAC-OS (c-axis Aligned Crystalline Oxide Semiconductor), which can be used in the OS transistor described in the above embodiment. Note that in this specification, etc., CAC represents an example of a function or material structure, and CAAC represents an example of a crystal structure.

[0546] <Composition of Metal Oxide>

[0547] CAC-OS or CAC-metal oxide has the function of conductivity in a part of the material, has the function of insulation in another part of the material, and has the function of a semiconductor as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the function of conductivity is to allow electrons (or holes) used as carriers to flow through, and the function of insulation is to prevent electrons used as carriers from flowing through. Through the complementary effects of the functions of conductivity and insulation, CAC-OS or CAC-metal oxide can be given a switching function (open / close function). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0548] CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. In addition, the conductive region and the insulating region are sometimes unevenly distributed in the material. In addition, the conductive region is sometimes observed to have fuzzy edges and is connected in a cloud-like shape.

[0549] In CAC-OS or CAC-metal oxide, conductive regions and insulating regions may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0550] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. In addition, the component with a narrow gap complements the component with a wide gap, and the carriers flow through the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field-effect mobility can be obtained in the on-state of the transistor.

[0551] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material or a metal matrix composite material.

[0552] <Structure of Metal Oxide>

[0553] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0554] CAAC-OS has c-axis orientation, with multiple nanocrystals linked in the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the difference in lattice alignment between regions where multiple nanocrystals are linked and other regions where the lattice alignment is consistent.

[0555] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, the distortion sometimes has lattice arrangements such as pentagons and heptagons. In addition, no clear grain boundaries are observed near the distortion of CAAC-OS. That is, it can be seen that the formation of grain boundaries can be suppressed by distorting the lattice arrangement. This may be because CAAC-OS can tolerate distortions caused by the following reasons: low density of oxygen atoms in the ab plane direction or changes in the bonding distance between atoms due to substitution of metal elements.

[0556] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be expressed as an (In, M) layer.

[0557] CAAC-OS is an oxide semiconductor with high crystallinity. In addition, no clear grain boundaries are observed in CAAC-OS, so the decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of oxide semiconductors is sometimes reduced due to the mixing of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (oxygen defects, etc.). Therefore, the physical properties of oxide semiconductors containing CAAC-OS are stable. Therefore, oxide semiconductors containing CAAC-OS have high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called heat accumulation; thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for OS transistors, the degree of freedom of the manufacturing process can be expanded.

[0558] In nc-OS, the atomic arrangement in tiny regions (e.g., regions between 1 nm and 10 nm, and particularly between 1 nm and 3 nm) is periodic. Furthermore, in nc-OS, no regularity in crystal orientation is observed between different nanocrystals. Consequently, no orientation is observed in the entire film. Consequently, nc-OS can sometimes be indistinguishable from a-like OS or amorphous oxide semiconductors using certain analytical methods.

[0559] An a-like OS is an oxide semiconductor with a structure intermediate between that of an nc-OS and an amorphous oxide semiconductor. It contains voids or low-density regions. In other words, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0560] Oxide semiconductors have various structures and properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0561] Transistor having an oxide semiconductor

[0562] Here, a case where the above-mentioned oxide semiconductor is used for a transistor will be described.

[0563] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0564] In addition, it is preferable to use an oxide semiconductor with a low carrier density for a transistor. When the carrier density of an oxide semiconductor film is to be reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state with a low impurity concentration and a low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density of an oxide semiconductor can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 And 1×10 -9 / cm 3 above.

[0565] Furthermore, since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, it is possible to have a low trap state density.

[0566] Furthermore, charges trapped by the high trap state density of an oxide semiconductor take a long time to disappear, sometimes behaving like fixed charges. Consequently, transistors whose channel formation regions are formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

[0567] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0568] <Impurities>

[0569] Here, the influence of each impurity in the oxide semiconductor is described.

[0570] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and near the interface of the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0571] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect energy level is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0572] When an oxide semiconductor contains nitrogen, electrons are generated as carriers, and the carrier density increases, and the oxide semiconductor is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to have normally-on characteristics. Therefore, it is preferable to reduce the nitrogen content of the oxide semiconductor as much as possible. For example, the nitrogen concentration in the oxide semiconductor measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0573] The hydrogen contained in the oxide semiconductor reacts with the oxygen bonded to the metal atom to generate water, thus sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferable to reduce the hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0574] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0575] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0576] (Implementation 8)

[0577] In this embodiment, a product example in which the semiconductor device described in the above embodiment is applied to electronic equipment will be described.

[0578] 〈Notebook Personal Computer〉

[0579] The semiconductor device according to one embodiment of the present invention can be applied to a display included in an information terminal device. Figure 35A 1 shows a notebook personal computer which is one of the information terminal devices and includes a housing 5401 , a display portion 5402 , a keyboard 5403 , a pointing device 5404 , and the like.

[0580] Smartwatch

[0581] The semiconductor device according to one embodiment of the present invention can be applied to a wearable terminal. Figure 35B It is a smart watch which is a type of wearable terminal, and the smart watch includes a frame 5901, a display unit 5902, an operation button 5903, a crown 5904, a strap 5905, and the like. In addition, a display device with the function of a position input device can also be used for the display unit 5902. In addition, the function of the position input device can be added by providing a touch panel on the display device. Alternatively, the function of the position input device can be added by providing a photoelectric conversion element also called a photoelectric sensor on the pixel portion of the display device. In addition, as the operation button 5903, it can have at least one of a power switch for starting the smart watch, a button for operating the software of the smart watch, a button for adjusting the volume, and a switch for turning on or off the display unit 5902. In addition, in Figure 35B The smartwatch shown in the figure shows two operation buttons 5903, but the number of operation buttons included in the smartwatch is not limited to this. In addition, the crown 5904 is used as a crown for adjusting the time of the smartwatch. In addition, the crown 5904 can also be used as an input interface for operating the software of the smartwatch in addition to adjusting the time. Figure 35B The smart watch shown has a structure including a crown 5904 , but is not limited thereto and may also have a structure without a crown 5904 .

[0582] Video Camera

[0583] The semiconductor device according to one embodiment of the present invention can be applied to a video camera. Figure 35CThe video camera shown includes a first housing 5801, a second housing 5802, a display unit 5803, operating keys 5804, a lens 5805, and a connecting portion 5806. The operating keys 5804 and the lens 5805 are disposed in the first housing 5801, while the display unit 5803 is disposed in the second housing 5802. Furthermore, the first housing 5801 and the second housing 5802 are connected by a connecting portion 5806, which allows the angle between the first housing 5801 and the second housing 5802 to be changed. The image on the display unit 5803 can also be switched according to the angle formed between the first housing 5801 and the second housing 5802 by the connecting portion 5806.

[0584] Mobile Phones

[0585] The semiconductor device according to one embodiment of the present invention can be applied to mobile phones. Figure 35D A mobile phone having the function of an information terminal is shown, and includes a housing 5501, a display portion 5502, a microphone 5503, a speaker 5504, and operation buttons 5505. Furthermore, a display device having the function of a position input device can also be used for the display portion 5502. Furthermore, the function of a position input device can be added by providing a touch panel on the display device. Alternatively, the function of a position input device can be added by providing a photoelectric conversion element, also known as a photoelectric sensor, on the pixel portion of the display device. Furthermore, the operation buttons 5505 can include any of a power switch for starting the mobile phone, a button for operating the mobile phone's software, a button for adjusting the volume, and a switch for turning the display portion 5502 on or off.

[0586] In addition, Figure 35D The illustrated mobile phone shows two operation buttons 5505, but the number of operation buttons included in the mobile phone is not limited to this. Figure 35D The mobile phone shown may also include a light emitting device, which may be used as a flash or illumination.

[0587] <Fixed game consoles>

[0588] The semiconductor device according to one embodiment of the present invention can be applied to a stationary game machine, which is an example of a game machine. Figure 35E The game console body 7520 and the controller 7522 are shown as a stationary game console. The game console body 7520 can be connected to the controller 7522 in a wireless or wired manner. Figure 35E Although not shown in the figure, the controller 7522 may include a display unit for displaying game images, a touch panel and a joystick as input interfaces other than buttons, a rotary grip, a sliding grip, etc. In addition, the controller 7522 is not limited to Figure 35EThe shape of controller 7522 can also be changed depending on the type of game. For example, in shooting games such as FPS (First Person Shooter), a trigger button can be used, and a controller shaped like a gun can be used. In music games, for example, controllers shaped like musical instruments can be used. Furthermore, stationary game consoles can be equipped with cameras, depth sensors, microphones, etc., and operated by the player's gestures and / or voice, instead of the controller's shape.

[0589] <Portable Game Console>

[0590] The semiconductor device according to one embodiment of the present invention can be applied to a portable game console, which is an example of a game console. Figure 35F The portable game console shown includes a housing 5201, a display portion 5202, buttons 5203, and the like. Figure 35F The portable game console shown is an example. The arrangement, shape, and number of the display portion, buttons, etc. of the portable game console to which the semiconductor device of one embodiment of the present invention is applied are not limited to those shown in FIG. Figure 35F In addition, the shape of the frame of the portable game console is not limited to Figure 35F The structure shown.

[0591] As examples of game machines, stationary game machines and portable game machines have been mentioned above. However, the semiconductor device according to one embodiment of the present invention can be applied to commercial game machines (arcade machines) and the like other than the above.

[0592] 〈Television equipment〉

[0593] The semiconductor device according to one embodiment of the present invention can be applied to a television device. Figure 35G The television set shown includes a housing 9000, a display portion 9001, speakers 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, etc. A large display portion 9001, for example, 50 inches or more or 100 inches or more, can be incorporated into the television set.

[0594] 〈Mobile Object〉

[0595] The semiconductor device according to one embodiment of the present invention can be applied to the vicinity of a driver's seat of a vehicle as a mobile object.

[0596] For example, Figure 35H It is a diagram showing the periphery of the front windshield in the interior of a vehicle. Figure 35H Display panels 5701, 5702, and 5703 installed on the instrument panel and 5704 installed on the pillar are shown.

[0597] Display panels 5701 through 5703 can provide navigation information, a speedometer, a tachometer, distance traveled, fuel level, gear status, air conditioning settings, and other information. Furthermore, users can adjust the display content and layout of the display panels as appropriate, enhancing design. Display panels 5701 through 5703 can also function as lighting devices.

[0598] By displaying images captured by a camera unit installed on the vehicle body on display panel 5704, it is possible to supplement the field of view (blind spots) blocked by pillars. In other words, by displaying images captured by a camera unit installed on the outside of the vehicle, blind spots can be supplemented, thereby improving safety. Furthermore, by displaying images that supplement the unseen areas, safety confirmation can be made more natural and comfortable. Display panel 5704 can also be used as a lighting device.

[0599] Electronic equipment for electronic advertising

[0600] The semiconductor device according to one embodiment of the present invention can be applied to displays used for electronic advertisements. Figure 36A An example of a digital signage that can be hung on a wall is shown. Figure 36A The digital signage 6200 is shown hung on a wall 6201 .

[0601] Foldable Tablet Information Terminal

[0602] The semiconductor device according to one embodiment of the present invention can be applied to a tablet information terminal. Figure 36B A tablet information terminal having a foldable structure is shown. Figure 36B The illustrated information terminal includes a housing 5321a, a housing 5321b, a display portion 5322, and operation buttons 5323. In particular, the display portion 5322 includes a flexible substrate, which enables a foldable structure.

[0603] The frame 5321a and the frame 5321b are connected by a hinge portion 5321c and can be folded in half by the hinge portion 5321c. The display portion 5322 is provided on the frame 5321a, the frame 5321b, and the hinge portion 5321c.

[0604] In addition, although not shown, Figures 35A to 35C 、 Figure 35E 、 Figure 36A and Figure 36B The electronic device shown may also have a structure including a microphone and a speaker. By adopting such a structure, for example, a sound input function may be added to the electronic device.

[0605] In addition, although not shown in the figure, Figure 35A 、 Figure 35B 、 Figure 35D 、 Figure 36A and Figure 36B The electronic device shown may also have a structure including a camera.

[0606] In addition, although not shown in the figure, Figures 35A to 35G 、 Figure 36A and Figure 36B The electronic device shown may be provided with a sensor inside the housing (the sensor having the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor, or infrared light, etc.). In particular, by providing a measuring device having a sensor for measuring inclination such as a gyroscope sensor or an acceleration sensor, it is possible to determine Figure 35D The screen display of the display portion 5502 is automatically switched according to the orientation of the mobile phone shown (which direction the mobile phone is facing relative to the vertical direction).

[0607] In addition, although not shown in the figure, Figures 35A to 35G 、 Figure 36A and Figure 36B The electronic device shown may also include a device for acquiring biometric information such as fingerprints, veins, irises, or voiceprints. By adopting this structure, an electronic device with a biometric recognition function can be realized.

[0608] Figures 35A to 35G and Figure 36A The display portion of the electronic device shown in FIG. 1 may use a flexible substrate. Specifically, the display portion may also have a structure in which transistors, capacitors, and display elements are provided on the flexible substrate. By using this structure, not only can the frame be realized as Figures 35A to 35G and Figure 36A The electronic device has a flat surface as shown, and can realize Figure 35H An electronic device whose frame has a curved surface, such as the instrument panel and pillar shown.

[0609] As available for Figures 35A to 35G 、 Figure 36A and Figure 36BExamples of materials that can be used as the flexible substrate for the display portion include polyethylene terephthalate resin (PET), polyethylene naphthalate resin (PEN), polyethersulfone resin (PES), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate resin, polyamide resin, polycycloolefin resin, polystyrene resin, polyamide-imide resin, polypropylene resin, polyester resin, polyvinyl halide resin, aromatic polyamide resin, and epoxy resin. Furthermore, a mixture or a laminate of these materials may be used.

[0610] Furthermore, this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0611] [Explanation of symbols]

[0612] M1: transistor, M1r: transistor, M2: transistor, M2r: transistor, M3: transistor, M4: transistor, M5: transistor, M11: transistor, M11r: transistor, M12: transistor, M12r: transistor, M13: transistor, M13r: transistor, M22: transistor, M23: transistor, M24: transistor, M27: transistor, M28: transistor, M29: transistor, M32: transistor, M33: transistor, M34: transistor, MA1: transistor, MA1r: transistor, MA2: transistor, MA2r: transistor, MA3: transistor, MA3r: transistor, MS1: transistor, MS1 r: transistor, MS2: transistor, MS2r: transistor, MC1: transistor, MC1r: transistor, C1: capacitor, C1r: capacitor, C3: capacitor, C11: capacitor, C11r: capacitor, C12: capacitor, C12r: capacitor, C13: capacitor, CD3: capacitor, CD4: capacitor, CD7: capacitor, CD8: capacitor, CD11: capacitor, CD12: capacitor, S20: switch, S21: switch, ss: node, ss1: node, mss: node, dd: node, bgc: node, bgc1: node, bw: node, ww: node, vx: node, ot1: node, ot 3: node, ot4: node, cs1: node, cs2: node, cs3: node, cm1: node, cm2: node, cmg: node, cmg1: node, cmg2: node, pt1: node, pt2: node, pt3: node, po: node, wx: node, wb: node, vb1: node, ga: node, st: node, sn1: node, mb1: node, ms1: node, inro: node, npr: node, WCS: wiring, WCS2: wiring, WBCS: wiring, EN_WBG: wiring, WBG: wiring, WBGr: wiring, VX: wiring, VX[1]: wiring, VX[i]: wiring, VX[m]: Wiring, WW: Wiring, WX: Wiring, WX[1]: Wiring, WX[j]: Wiring, WX[n]: Wiring, WXr: Wiring, BW: Wiring, BWr: Wiring, PO: Wiring, POr: Wiring, EN_PO: Wiring, ENB_PO: Wiring, MVSSL: Wiring, MVSSLr: Wiring, VAL: Wiring, SW2: Wiring, SW3: Wiring, SW3B: Wiring, SW4: Wiring, SW5: Wiring, SW5B: Wiring, SW6: Wiring, SW7: Wiring, SW7B: Wiring, CS2: Circuit, CS3: Circuit, CS4: Circuit, ct2: Terminal, ct3: Terminal, ct4: Terminal, N1 (k－1) :Neurons, N i (k－1) :Neurons, Nm (k－1) :Neurons, N1 (k) :Neurons, N j (k) :Neurons, N n (k): neuron, MCA: memory cell array, MCA[1]: memory cell array, MCA[n]: memory cell array, BGI: insulator, FGI: insulator, BGE: conductor, FGE: conductor, PE: conductor, WE: conductor, 10: circuit, 10[1]: circuit, 10[i]: circuit, 10[m]: circuit, 10[1,1]: circuit, 10[i,1]: circuit, 10[m,1]: circuit, 10[1,j]: circuit, 10[i,j]: circuit, 10[m,j]: circuit, 10[1,n]: circuit, 10[i,n]: circuit, 10[m,n]: circuit, 10r: circuit, 10r[1]: circuit, 10r[i]: circuit, 10r[m]: Circuit, 11: Circuit, 15: Circuit, 17: Circuit, 18: Circuit, 30: Current source circuit, 30r: Current source circuit, 41: Circuit, 41r: Circuit, 42: Circuit, 50: Bias cancellation circuit, 60: Current source circuit, 60r: Current source circuit, 70: Bias cancellation circuit, 80: Bias cancellation circuit, 80[1]: Bias cancellation circuit, 80[j]: Bias cancellation circuit, 80[n]: Bias cancellation circuit, 90: Bias cancellation circuit, 90[1]: Bias cancellation circuit, 90[n]: Bias cancellation circuit, 101: Control circuit, 102: Temperature sensor, 103: Storage device, 104: DAC, 106: Drive circuit, 107: Drive circuit , 108: driving circuit, 109: driving circuit, 110: driving circuit, 112: readout circuit, 113: operation array, 120: readout circuit, 120[1]: readout circuit, 120[j]: readout circuit, 120[n]: readout circuit, 201A: operation circuit, 201B: operation circuit, 201C: operation circuit, 202A: operation circuit, 202B: operation circuit, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor Electrical body, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 500: Transistor, 500A: Transistor, 500B: Transistor, 500C: Transistor, 500D: Transistor, 500E: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 505: Conductor, 510: Insulator, 511: Insulator, 512: Insulator, 514: Insulator,516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530c: Oxide, 531a: Region, 531b: Region, 540: Conductor, 540a: Conductor, 540b: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 546a: Conductor, 546b: Conductor, 547a: Conductor, 547b : Conductor, 548: Conductor, 550: Insulator, 552: Metal Oxide, 560: Conductor, 560a: Conductor, 560b: Conductor, 570: Insulator, 571: Insulator, 573: Insulator, 574: Insulator, 575: Insulator, 576a: Insulator, 576b: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacitor, 600A: Capacitor, 600B: Capacitor, 610: Conductor, 611: Conductor, 612: Conductor, 620: Conductor, 6 21: Conductor, 630: Insulator, 631: Insulator, 650: Insulator, 651: Insulator, 5201: Housing, 5202: Display, 5203: Button, 5321a: Housing, 5321b: Housing, 5321c: Hinge, 5322: Display, 5323: Operation button, 5401: Housing, 5402: Display, 5403: Keyboard, 5404: Pointing device, 5501: Housing, 5502: Display, 5503: Microphone, 5504: Speaker, 5505: Operation button, 5701: Display panel, 5702: Display panel, 5703: Display panel, 5704: Display panel, 5801: First housing, 5802: Second housing, 5803: Display unit, 5804: Operation keys, 5805: Lens, 5806: Connecting unit, 5901: Housing, 5902: Display unit, 5903: Operation buttons, 5904: Crown, 5905: Band, 6200: Digital signage, 6201: Wall, 7520: Game console body, 7522: Controller, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation keys, 9006: Connecting terminal.

Claims

1. A semiconductor device comprising: a first current source circuit and a second current source circuit, The second current source circuit has the same structure as the first current source circuit. The first current source circuit includes first to fourth transistors, a first capacitor, a second capacitor, and first to third nodes. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first node, The back gate of the first transistor is electrically connected to the first terminal of the third transistor and the first terminal of the first capacitor, The second terminal of the third transistor is electrically connected to the second node, The gate of the first transistor is electrically connected to the third node, a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor, The gate of the second transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the second capacitor. a second terminal of the second capacitor is electrically connected to the first terminal of the second transistor, The first current source circuit is configured as follows: When the third transistor is in an on state, a threshold voltage of the first transistor is changed by writing a first correction voltage from the second node to the back gate of the first transistor; and When the third transistor is in the off state, the first capacitor is used to maintain the voltage between the second terminal and the back gate of the first transistor, and the first node of the first current source circuit is electrically connected to the third node of the first current source circuit and the third node of the second current source circuit.

2. A semiconductor device comprising: a first current source circuit and a second current source circuit, The second current source circuit has the same structure as the first current source circuit. The first current source circuit includes first to fifth transistors, a first capacitor, a second capacitor, and first to fifth nodes. The first terminal of the first transistor is electrically connected to the first terminal of the fifth transistor and the fifth node, The first terminal of the second transistor is electrically connected to the second terminal of the fifth transistor and the first node, The back gate of the first transistor is electrically connected to the first terminal of the third transistor and the first terminal of the first capacitor, The second terminal of the third transistor is electrically connected to the second node, The gate of the first transistor is electrically connected to the third node, a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor, The gate of the fifth transistor is electrically connected to the fourth node, The gate of the second transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the second capacitor. a second terminal of the second capacitor is electrically connected to the first terminal of the second transistor, The first current source circuit is configured as follows: When the third transistor is in an on state, a threshold voltage of the first transistor is changed by writing a first correction voltage from the second node to the back gate of the first transistor; and When the third transistor is in an off state, the voltage between the second terminal and the back gate of the first transistor is maintained by the first capacitor, and the first node of the first current source circuit is electrically connected to the fourth node of the first current source circuit and the fourth node of the second current source circuit. Furthermore, the fifth node of the first current source circuit is electrically connected to the third node of the first current source circuit and the third node of the second current source circuit.

3. The semiconductor device according to claim 2, wherein the first current source circuit comprises a sixth transistor, The first terminal of the sixth transistor is electrically connected to the first terminal of the first transistor, And the first current source circuit is configured to: put the fifth transistor in an off state and put the sixth transistor in an on state, monitor the current flowing between the second terminal of the first transistor and the second terminal of the sixth transistor, and determine the first correction voltage based on the current.

4. The semiconductor device according to any one of claims 1 to 3, Also includes a first circuit, a second circuit and a readout circuit, wherein the first circuit is electrically connected to the first node of the first current source circuit, The second circuit is electrically connected to the first node of the second current source circuit, The readout circuit is electrically connected to the first node of the second current source circuit, The first circuit is configured to sink a first current or a second current from the first node of the first current source circuit, The second circuit is configured to sink a third current or a fourth current from the first node of the second current source circuit, The second transistor of the first current source circuit is configured to flow a fifth current corresponding to a gate-source voltage of the second transistor of the first current source circuit when sinking the first current from the first node of the first current source circuit. The first transistor of the first current source circuit is configured as follows: when sinking the first current from the first node of the first current source circuit, causing a first difference current between the fifth current and the first current to flow; and When the second current is absorbed from the first node of the first current source circuit, a second difference current between the fifth current and the second current flows, The first transistor of the second current source circuit is configured as follows: causing the first difference current to flow when the first current is sunk from the first node of the first current source circuit; and causing the second difference current to flow when the second current is absorbed from the first node of the first current source circuit, The second transistor of the second current source circuit is configured to flow a sixth current corresponding to a gate-source voltage of the second transistor of the second current source circuit when sinking the third current and the first difference current from the first node of the second current source circuit. And the readout circuit is configured to absorb a seventh current obtained by subtracting the sum of the second difference current and the fourth current from the sixth current when the first current absorbed from the first node of the first current source circuit changes to the second current and the third current absorbed from the first node of the second current source circuit changes to the fourth current.

5. The semiconductor device according to claim 4, wherein the second circuit has the same structure as the first circuit, The first circuit includes a seventh transistor, an eighth transistor and a third capacitor, The gate of the seventh transistor is electrically connected to the first terminal of the eighth transistor and the first terminal of the third capacitor. a first terminal of the seventh transistor of the first circuit is electrically connected to the first node of the first current source circuit; a first terminal of the seventh transistor of the second circuit is electrically connected to the first node of the second current source circuit; The seventh transistor of the first circuit is configured as follows: When a first potential is applied to the gate of the seventh transistor and a second potential is applied to the second terminal of the third capacitor in the first circuit, the first current flows; as well as When the first potential is applied to the gate of the seventh transistor and the third potential is applied to the second terminal of the third capacitor in the first circuit, the second current flows; The seventh transistor of the second circuit is configured as follows: causing the third current to flow when a fourth potential is applied to the gate of the seventh transistor of the second circuit and the second potential is applied to the second terminal of the third capacitor; as well as When the fourth potential is applied to the gate of the seventh transistor of the second circuit and the third potential is applied to the second terminal of the third capacitor, the fourth current flows. The difference between the first potential and the fourth potential is a potential difference corresponding to the first data, The difference between the second potential and the third potential is a potential difference corresponding to the second data, Furthermore, the seventh current is a current corresponding to the product of the first data and the second data.

6. The semiconductor device according to claim 5, The first circuit includes a ninth transistor and a fourth capacitor. The seventh transistor includes a back gate, The back gate of the seventh transistor is electrically connected to the first terminal of the ninth transistor and the first terminal of the fourth capacitor. The second terminal of the fourth capacitor is electrically connected to the second terminal of the seventh transistor, And the first circuit is configured as follows: When the ninth transistor is in an on-state, writing a second correction voltage from the second terminal of the ninth transistor to the back gate of the seventh transistor to change a threshold voltage of the seventh transistor; and When the ninth transistor is in an off state, the voltage between the second terminal and the back gate of the seventh transistor is maintained by the fourth capacitor.

7. The semiconductor device according to claim 4, wherein the first current source circuit includes a fifth capacitor, And a first terminal of the fifth capacitor is electrically connected to the gate of the second transistor.

8. The semiconductor device according to claim 4, wherein the first circuit includes a tenth transistor, The source and drain of the tenth transistor are electrically connected to each other, One of the gate and the source of the tenth transistor is electrically connected to the gate of the second transistor, Furthermore, a channel width of the tenth transistor is less than 0.5 times a channel width of the fourth transistor.

9. The semiconductor device according to any one of claims 1 to 3, wherein the first current source circuit includes a fifth capacitor, And a first terminal of the fifth capacitor is electrically connected to the gate of the second transistor.

10. The semiconductor device according to claim 5, wherein the first current source circuit includes a fifth capacitor, And a first terminal of the fifth capacitor is electrically connected to the gate of the second transistor.

11. The semiconductor device according to claim 5, wherein the first circuit includes a tenth transistor, The source and drain of the tenth transistor are electrically connected to each other, One of the gate and the source of the tenth transistor is electrically connected to the gate of the second transistor, Furthermore, a channel width of the tenth transistor is less than 0.5 times a channel width of the fourth transistor.

12. A semiconductor device, In the semiconductor device according to any one of claims 1 to 3, all transistors include metal oxide in their channel formation regions and have the same polarity.

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