A low-trigger-voltage ESD and surge co-protection circuit

Abstract

This invention discloses a low-trigger-voltage ESD and surge collaborative protection circuit, which consists of an RC network, an inverter, a voltage detector, a common-source amplifier, and a clamping transistor cascaded together. The RC network is formed by capacitor C1 connected in series with a turned-off PMOS transistor Mp2; the inverter is formed by PMOS transistor Mp3 connected in series with an NMOS transistor Mn3; the voltage detector is formed by resistor R0, NMOS transistor Mn4, and diode string DS1 connected in series; the common-source amplifier is formed by PMOS transistor Mp4 and resistor R1 connected in series; and the clamping transistor is an NMOS transistor Mn5. One end of the RC network, inverter, voltage detector, common-source amplifier, and clamping transistor are all connected to the power supply VDD, and the other end is grounded. This circuit can achieve ESD and surge event detection and discharge functions, with high detection sensitivity and low static leakage current.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit electrostatic discharge and surge protection technology, and relates to a low-trigger-voltage ESD and surge coordinated protection circuit. Background Technology

[0002] Electrostatic discharge (ESD) has been a persistent reliability issue in the development of integrated circuits. As feature sizes continue to shrink, the need for ESD protection in integrated circuits has become increasingly urgent. ESD occurs when an external object carrying static charge comes into contact with the chip, creating a conductive path and resulting in a momentary high voltage and current, causing chip failure. Surges are another reliability problem that can cause integrated circuit failure. Surges refer to the instantaneous high current and high voltage phenomenon in electronic systems caused by external interference. Compared to ESD events, surge currents have a longer rise time, typically in the microsecond range, while ESD events are in the nanosecond range. Furthermore, surge events have more total energy and require a longer discharge time, generally greater than 10 microseconds, while the discharge time of ESD events is generally less than 1 microsecond.

[0003] Power supply clamping circuits are used for ESD protection between power lines and ground, and are an indispensable part of full-chip ESD protection. A current trend in power supply clamping circuit development is to enable discharge not only under ESD events but also under surge events, achieving coordinated ESD and surge protection. Traditional clamping circuits for ESD protection include frequency-sensitive circuits based on RC networks and voltage-sensitive circuits based on diode strings. For example... Figure 1 The diagram shows a frequency-sensitive circuit based on an RC network. When the power-on time is less than the RC time constant, a current is generated in the RC circuit, creating a voltage drop across the resistor. This generates a control signal, turning on the large-size clamped NMOSFET to discharge ESD charge. Figure 2 The diagram shows a voltage-sensitive clamping circuit based on a diode string. When an ESD event occurs, the voltage on the power supply rises. When this voltage exceeds the threshold of the diode string, a control signal is generated to turn on the large clamping NMOSFET behind it and discharge the ESD charge.

[0004] However, both of the above circuits have significant drawbacks when directly used for ESD and surge protection. RC detection circuits require a relatively large time constant to maintain the discharge time; when used for surge protection, the required time constant is over 10 microseconds, which not only occupies a very large layout area but is also susceptible to false triggering by fast power-ups or power supply noise. Therefore, they cannot be directly used for ESD and surge protection. Voltage-sensitive clamping circuits based on diodes can achieve ESD and surge protection, but the diode strings used in these circuits present a problem of balancing static leakage current and trigger voltage. Increasing the number of diodes increases the trigger voltage, which is detrimental to ESD / surge protection; conversely, reducing the number of diodes increases static leakage current. Summary of the Invention

[0005] The purpose of this invention is to provide a low-trigger-voltage ESD and surge protection circuit that solves the problem of balancing layout area, static leakage current and trigger voltage in the prior art.

[0006] The technical solution adopted in this invention is a low-trigger-voltage ESD and surge collaborative protection circuit, which is composed of an RC network, an inverter, a voltage detector, a common-source amplifier, and a clamping transistor cascaded together.

[0007] The RC network consists of capacitor C1 connected in series with the off PMOS transistor Mp2;

[0008] The inverter is composed of a PMOS transistor Mp3 and an NMOS transistor Mn3 connected in series;

[0009] The voltage detector consists of a resistor R0, an NMOS transistor Mn4, and a diode string DS1 connected in series;

[0010] The common-source amplifier is composed of a PMOS transistor Mp4 and a resistor R1 connected in series;

[0011] The clamping transistor used is an NMOS transistor Mn5;

[0012] The RC network, inverter, voltage detector, common-source amplifier, and clamping transistor are connected together at one end to the power supply VDD, and at the other end to ground.

[0013] The low-trigger-voltage ESD and surge coordinated protection circuit of the present invention is further characterized in that,

[0014] The structure of the RC network is as follows: the gate and source of PMOS transistor Mp2 are both connected to VDD, the drain of PMOS transistor Mp2 is connected to the upper plate of capacitor C1, and the lower plate of capacitor C1 is connected to GND.

[0015] The inverter structure is as follows: the gate of the PMOS transistor Mp3 is connected to the output V of the RC network.rc The source of PMOS transistor Mp3 is connected to VDD, the drain of PMOS transistor Mp3 is connected to the drain of NMOS transistor Mn3, and the gate and source of NMOS transistor Mn3 are both connected to GND.

[0016] The voltage detector has the following structure: the upper end of resistor R0 is connected to VDD, the lower end of resistor R0 is connected to the drain of NMOS transistor Mn4, and the gate of NMOS transistor Mn4 is connected to the output VDD of the inverter. a The source of the NMOS transistor Mn4 is connected to the upper end of the diode string DS1, and the lower end of the diode string DS1 is connected to GND.

[0017] The common-source amplifier structure is as follows: the source of the PMOS transistor Mp4 is connected to VDD, and the gate of the PMOS transistor Mp4 is connected to the output V of the voltage detector. rd The drain of PMOS transistor Mp4 is connected to the upper end of resistor R1, and the lower end of resistor R1 is connected to GND.

[0018] The clamping transistor has the following structure: the drain of the clamping NMOS transistor Mn5 is connected to VDD, and the gate of the clamping NMOS transistor Mn5 is connected to the output VDD of the common-source amplifier. g The source of the clamped NMOS transistor Mn5 is connected to GND.

[0019] The beneficial effects of this invention are that it is more sensitive to ESD and surge detection, and has less static leakage current when the circuit is working normally. Attached Figure Description

[0020] Figure 1 It is a frequency-sensitive clamping circuit diagram based on RC networks using traditional technology;

[0021] Figure 2 It is a voltage-sensitive clamping circuit diagram based on diode strings, which is a traditional technology.

[0022] Figure 3 This is a circuit diagram of the voltage-sensitive ESD / surge co-protection clamping circuit of the present invention;

[0023] Figure 4 This is a voltage waveform diagram of the circuit of the present invention under normal chip power-on conditions;

[0024] Figure 5 This is a current waveform diagram of the present invention and a traditional voltage-sensitive clamping circuit under normal chip power-on conditions;

[0025] Figure 6 This is a voltage waveform diagram of the circuit of the present invention under ESD event simulation conditions;

[0026] Figure 7 This is a voltage waveform diagram of the circuit of the present invention under surge event simulation conditions;

[0027] Figure 8 The voltage diagrams are those of the circuit of this invention and conventional voltage-sensitive clamping circuits containing 3 and 4 diodes, respectively, under DC simulation conditions. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0029] Reference Figure 1 , Figure 2 This is the structure of the prior art, and its shortcomings have been described in the background section.

[0030] Reference Figure 3 The circuit structure of this invention consists of a cascaded RC network, an inverter, a voltage detector, a common-source amplifier, and a clamping transistor.

[0031] The RC network consists of capacitor C1 connected in series with the off PMOS transistor Mp2, used to detect changes in VDD and output voltage V. rc Because the conventional resistor is replaced by a PMOS that is turned off, the time constant can be as high as tens of milliseconds.

[0032] The inverter is composed of a PMOS transistor Mp3 and an NMOS transistor Mn3 connected in series, and is used to generate the control signal V. a And output it to the voltage detector; where the aspect ratio of PMOS transistor Mp3 is much larger than that of NMOS transistor Mn3;

[0033] The voltage detector consists of a resistor R0, an NMOS transistor Mn4, and a diode string DS1 connected in series. It is used to detect the voltage VDD and output a voltage signal V. rd For common-source amplifiers;

[0034] The common-source amplifier consists of a PMOS transistor Mp4 and a resistor R1 connected in series, used to amplify the voltage signal V. rd Generates control signal V g The input is given to the clamping transistor.

[0035] The clamping transistor uses a large-size NMOS transistor Mn5 to discharge ESD charge;

[0036] The RC network, inverter, voltage detector, common-source amplifier, and clamping transistor are all cascaded, with one end connected to the power supply VDD and the other end grounded.

[0037] The specific connection relationships between the components of the circuit of this invention are as follows:

[0038] RC network: The gate and source of PMOS transistor Mp2 are both connected to VDD, the drain of PMOS transistor Mp2 is connected to the upper plate of capacitor C1, and the lower plate of capacitor C1 is connected to GND.

[0039] Inverter: The gate of PMOS transistor Mp3 is connected to the output V of the RC network. rc The source of PMOS transistor Mp3 is connected to VDD, the drain of PMOS transistor Mp3 is connected to the drain of NMOS transistor Mn3, and the gate and source of NMOS transistor Mn3 are both connected to GND.

[0040] Voltage detector: The upper end of resistor R0 is connected to VDD, and the lower end of resistor R0 is connected to the drain of NMOS transistor Mn4. The gate of NMOS transistor Mn4 is connected to the output VDD of the inverter. a The source of NMOS transistor Mn4 is connected to the upper end of diode string DS1, and the lower end of diode string DS1 is connected to GND.

[0041] Common-source amplifier: The source of PMOS transistor Mp4 is connected to VDD, and the gate of PMOS transistor Mp4 is connected to the output V of the voltage detector. rd The drain of PMOS transistor Mp4 is connected to the upper end of resistor R1, and the lower end of resistor R1 is connected to GND.

[0042] Clamped Transistor: The drain of clamped NMOS transistor Mn5 is connected to VDD, and the gate of clamped NMOS transistor Mn5 is connected to the output VDD of the common-source amplifier. g The source of the clamped NMOS transistor Mn5 is connected to GND.

[0043] The working principle of the circuit of this invention is as follows:

[0044] 1) During normal power-on, the power supply powers on slowly, typically rising to the normal operating voltage within 1 microsecond to 1 millisecond (this invention uses 1 millisecond as an example). This is because the time constant of the RC network is very large, approximately tens of milliseconds, during which the RC network will respond, resulting in an output voltage V. rc The voltage level is low, therefore the PMOS transistor Mp3 is turned on. Since the NMOS transistor Mn3 is a normally off NMOS, the inverter output V... a This is a high level (i.e., operating voltage). V a This can be viewed as the sum of the gate-source voltage of Mn4 and the voltage drop across the diode string DS1. By appropriately selecting the number of diodes, it can be ensured that the sum of the threshold voltages of Mn4 and the diode string DS1 is greater than the operating voltage. Therefore, Mn4 is in a state of being off or subthreshold conduction, and the current flowing through it is very small. The voltage drop across resistor R0 can be approximately ignored. rdThe state is basically the same as VDD, so the PMOS transistor Mp4 is off at this time. g When the voltage is low, the clamped NMOS is in the off state. After a relatively long period of time, V... rc When the voltage rises to a high level, PMOS transistor Mp3 is turned off. This means both Mn3 and Mp3 are off, and the output Va is determined by their equivalent resistances. By setting the aspect ratio of NMOS transistor Mn3 to be much larger than that of PMOS transistor Mp3, the voltage drop across NMOS transistor Mn3 can be kept very small, thus reducing the inverter's voltage V. a When the output is low, the NMOS transistor Mn4 is strictly turned off, and the static leakage current of the diode string branch drops to the picoampere level.

[0045] 2) When an ESD event occurs, the power-on speed is fast (this invention uses 10ns as an example), the RC network generates a response, V rc When the output is low, PMOS transistor Mp3 is turned on, V a The voltage is equal to VDD. In the initial stage, the clamping transistor Mn5 is not turned on to discharge, so the ESD charge will continue to accumulate on VDD, causing VDD to rise to a high value and exceed the sum of the threshold voltages of the diode string DS1 and the NMOS transistor Mn4. Therefore, both the diode string DS1 and the NMOS transistor Mn4 are turned on, and a voltage divider appears on the resistor R0. Vrd is significantly lower than VDD, thus turning on the PMOS transistor Mp4, pulling Vg up to close to VDD, and turning on the clamping transistor Mn5 to discharge the ESD charge.

[0046] 3) Surge events occur during normal circuit operation. When a surge event occurs, the VDD voltage gradually rises from the operating voltage to a higher value within a few microseconds, similar to an ESD event. The surge also meets the requirements for RC network response and voltage detector conduction, therefore the clamping transistor Mn5 will also be turned on to discharge. Unlike ESD events, after the surge discharge, the VDD voltage gradually decreases to the normal operating voltage, requiring the clamping transistor Mn5 to be turned off. When VDD is less than the voltage detector threshold, there is no longer a voltage drop across resistor R0, Vrd equals VDD, and both PMOS transistor Mp4 and clamping transistor Mn5 are turned off, stopping the discharge.

[0047] In the following simulation verification process, the circuit structure of the present invention is carried out under a 0.18-micron, 1.8V complementary metal-oxide-semiconductor process, wherein the diode string DS1 contains two diodes.

[0048] The technical effects of the circuit of this invention are illustrated by the following specific simulation results:

[0049] Simulation 1) The circuit of this invention was simulated under normal power-on conditions as the power supply voltage VDD rose from 0 to 1.8V in 1ms. The node voltages are as follows: Figure 4 As shown, the static current is as follows Figure 5 As shown. Figure 4 As shown, although the power-on speed is very slow, the time constant of the RC network is very large, therefore the initial V rc It was still significantly lower than VDD, then gradually increased. At this point, the PMOS transistor Mp3 turned on, and V... a It is pulled up to a high level that is in sync with VDD. However, although V a It is already as high as VDD, but since VDD is only 1.8V, the source voltage V of the NMOS transistor Mn4 is... rs The forward voltage of the two diodes is approximately 1.32V, therefore the gate-source voltage of the NMOS transistor Mn4 is 0.48V. The NMOS transistor Mn4 is in a subthreshold conduction state, and the current flowing through the voltage detector branch is very small (960nA). The voltage drop across resistor R0 is very small, therefore V rd Approximately equal to VDD, PMOS transistor Mp4 is turned off, V g When the signal is low, the clamping transistor Mn5 will not be turned on.

[0050] After approximately 18ms, V rc When the voltage rises to a high level, the PMOS transistor Mp3 is turned off. Since the aspect ratio of the NMOS transistor Mn3 is much larger than that of the PMOS transistor Mp3, V... a The voltage is pulled down to near 0V by NMOS transistor Mn3, at which point NMOS transistor Mn4 is strictly turned off, and the static leakage current drops to 600pA. In contrast, Figure 2 The static leakage current of the conventional voltage-sensitive circuit shown (taking a circuit with three diodes as an example) is 21 μA, mainly due to the current in the diode series DS0. Reducing the static leakage current requires increasing the number of diodes, but this reduces detection sensitivity and is detrimental to ESD protection. In fact, even the conventional circuit with only three diodes has lower detection sensitivity than the circuit of this invention, as will be explained below. Therefore, the circuit of this invention is comparable to... Figure 2 Compared to traditional circuits, it can significantly reduce static leakage current.

[0051] Simulation 2) The power supply voltage rises from 0 to 5V within 10ns, with a pulse width of 100ns. The state of the circuit under ESD conditions is simulated. The simulation node voltage diagram is shown below. Figure 6 As shown in the figure, V rc When the voltage is much lower than VDD, the PMOS transistor Mp3 turns on, and V aThe gate voltage is pulled up to a high level, which is held high by VDD. Since VDD is high at this time (5V), the source voltage of NMOS transistor Mn4 reaches 2.3V, while its gate voltage is 5V. Therefore, NMOS transistor Mn4 is turned on, and there is a voltage drop of approximately 2.7V across resistor R0. rd The node voltage is approximately 2.3V, thus turning on the PMOS transistor Mp4 and turning on V. g When the pull-up is high, the clamping transistor Mn5 is turned on to discharge.

[0052] Simulation 3) The power supply voltage rises from the normal operating voltage of 1.8V to 4V within 8μs, and then gradually decreases back to 1.8V within 30μs. The simulation of the invention under surge conditions is shown in the following diagram: Figure 7 As shown in the figure, due to the large time constant of the RC network, during the surge (VDD rises from 1.8V to 1.8V in 30μs), V... rc It remains approximately constant; when the supply voltage rises to approximately 2.2V, V a Rising rapidly, when V a When the voltage rises to around 2.3V, the voltage detector turns on, and a voltage divider appears across resistor R0. At this point, V... rd As the voltage gradually decreases from initially following VDD to around 1.8V, the PMOS transistor Mp4 is turned on, and V... g The voltage also begins to rise rapidly, and clamping transistor Mn5 turns on. As VDD gradually drops below 2.2V, the voltage divider across resistor R0 becomes insufficient to maintain the turn-on of PMOS transistor MP4, therefore V... g When the node is pulled down to a low level, the clamping transistor Mn5 is turned off, and the discharge stops.

[0053] Simulation 4) shows that the power supply voltage rises from 0 to 3V in 8μs, affecting the circuit of this invention and the traditional voltage-sensitive circuit (i.e., Figure 2 The sensitivity of the circuit was compared, and the simulation results showed the node voltages, such as... Figure 8 As shown, as VDD increases, the voltage detection signal Vrd of the circuit of this invention separates from VDD earlier, and its final value is significantly smaller than that of the voltage detection signal V of the traditional circuit. DS0 This demonstrates that the circuit of the present invention has more sensitive detection.

[0054] In summary, the main innovation of this invention is the proposal of a novel voltage detector. In a traditional diode string, the diode directly connected to the resistor is removed and replaced with an NMOS transistor Mn4 whose gate voltage is controlled by an RC network. The advantage of this is that, as VDD increases, the voltage detector's output V... rdThe voltage of the input signal Va will separate from VDD earlier, resulting in higher detection sensitivity. This is because the NMOS transistor Mn4 and resistor R0 form a common-source amplifier similar to a resistor-loaded amplifier. The higher the input signal Va, the higher the output signal V. rd The lower the value, the more inverted the input and output become, thus weakening V as VDD increases. rd The voltage VDS0 shows an increasing trend, and even a decreasing trend in some voltage ranges. In contrast, in a traditional diode string circuit, the output VDS0 always tends to increase as VDD increases.

[0055] Additional explanation: The positions of NMOS transistor Mn4 and diode string DS1 cannot be interchanged; that is, NMOS transistor Mn4 cannot be located below diode string DS1. If the connection is such that NMOS transistor Mn4 is below and diode string DS1 is above, the following situation will occur: When the circuit is powered on normally, in the initial stage, because the RC network will still respond, V... a If VDD = 1.8V, then the gate-source voltage of NMOS transistor Mn4 is 1.8V. Therefore, NMOS transistor Mn4 is in a strongly conducting state, and its source-drain voltage will be very low. rd The gate voltage of Mp4 is approximately equal to 1.8V minus the forward voltage of the two diodes. Therefore, the PMOS transistor Mp4 will be in subthreshold conduction, resulting in V... g When the voltage rises, the NMOS transistor Mn5 turns on and discharges, resulting in a false trigger, which is undesirable. Increasing the number of diodes to three to avoid this false trigger would obviously increase the trigger voltage under ESD and surge conditions, making it less sensitive than the circuit of this invention. Figure 8 As shown.

Claims

1. A low-trigger-voltage ESD and surge co-protection circuit, characterized in that: It consists of a cascaded RC network, an inverter, a voltage detector, a common-source amplifier, and a clamping transistor. The structure of the RC network is as follows: the gate and source of PMOS transistor Mp2 are both connected to VDD, the drain of PMOS transistor Mp2 is connected to the upper plate of capacitor C1, and the lower plate of capacitor C1 is connected to GND. The inverter structure is as follows: the gate of the PMOS transistor Mp3 is connected to the output V of the RC network. rc， The source of PMOS transistor Mp3 is connected to VDD, the drain of PMOS transistor Mp3 is connected to the drain of NMOS transistor Mn3, and the gate and source of NMOS transistor Mn3 are both connected to GND. The voltage detector has the following structure: the upper end of resistor R0 is connected to VDD, the lower end of resistor R0 is connected to the drain of NMOS transistor Mn4, and the gate of NMOS transistor Mn4 is connected to the output VDD of the inverter. a The source of NMOS transistor Mn4 is connected to the upper end of diode string DS1, and the lower end of diode string DS1 is connected to GND; V a It can be considered as the sum of the gate-source voltage of Mn4 and the voltage division of the diode string DS1. By selecting the number of diodes, it is ensured that the sum of the threshold voltages of Mn4 and the diode string DS1 is greater than the normal operating voltage. The common-source amplifier is composed of a PMOS transistor Mp4 and a resistor R1 connected in series. The structure of the common-source amplifier is as follows: the source of the PMOS transistor Mp4 is connected to VDD, and the gate of the PMOS transistor Mp4 is connected to the output V of the voltage detector. rd The drain of PMOS transistor Mp4 is connected to the upper end of resistor R1, and the lower end of resistor R1 is connected to GND. The clamping transistor used is a clamping NMOS transistor Mn5. The structure of the clamping transistor is as follows: the drain of the clamping NMOS transistor Mn5 is connected to VDD, and the gate of the clamping NMOS transistor Mn5 is connected to the output VDD of the common-source amplifier. g The source of the clamped NMOS transistor Mn5 is connected to GND; The RC network, inverter, voltage detector, common-source amplifier, and clamping transistor are connected together at one end to the power supply VDD, and at the other end to ground.

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