Multi-parameter detection circuit for conducting voltage drop and peak value detection

Abstract

The invention discloses a conduction voltage drop and peak value detection multi-parameter detection circuit which comprises a conduction voltage drop test circuit and a peak value voltage detection circuit which are arranged at the two ends of a tested power device in parallel. Respectively collecting the forward conduction voltage drop and the reverse conduction voltage drop; the peak voltage detection circuit is used for capturing transient peak voltage between a collector and an emitter in the turn-off process of the power device; the output ends of the conduction voltage drop test circuit and the peak voltage detection circuit are isolated and then are connected to the analog-to-digital converter, so that simultaneous detection of multiple parameters of the same power device is realized. The circuit provided by the invention can realize high-precision and high-robustness measurement of positive and negative voltage and transient peak voltage in a complex switching environment.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically a multi-parameter detection circuit for on-state voltage drop and peak value detection. Background Technology

[0002] Three-level ANPC (Active Neutral Point Clamped) circuits are widely used in high-voltage, high-power systems such as electric propulsion, rail transportation, wind power generation, and electric vehicle drives due to their ability to reduce voltage stress on switching devices and minimize switching losses. However, in these harsh operating environments, core power devices (such as IGBTs or SiC MOSFETs) are prone to aging, affecting system reliability. Therefore, online status monitoring of power devices is crucial. Forward and reverse voltages and turn-off peak voltages are key electrical parameters of power devices and have significant status characterization value, but their online extraction in practical applications of three-level ANPC circuits still faces significant technical challenges. Compared to the traditional two-level structure, the three-level ANPC topology has a larger number of devices, more complex current commutation paths, and the power loop layout typically exhibits larger parasitic inductance and distributed parameters.

[0003] Under high-frequency switching conditions, when power devices switch on and off, the parasitic inductance of the circuit and the rate of change of current (di / dt) work together to generate a significant voltage overshoot across the device, especially during the commutation of the opposite bridge arm. This can easily lead to a large negative voltage overshoot at the emitter or source side of the device under test. This negative voltage overshoot not only increases the electrical stress on the device itself but also directly couples to the on-state voltage drop detection circuit. Since the on-state voltage drop test circuit typically uses a high-precision operational amplifier to amplify small voltage differences, when a negative voltage exceeding the power supply range appears at its input, it may cause the operational amplifier input to exceed the nominal common-mode range or even enter an abnormal operating range, resulting in measurement errors, response hysteresis, and in severe cases, affecting the reliability and lifespan of the device.

[0004] Furthermore, in the detection of transient peak voltages, existing technologies typically employ active control methods to achieve peak hold or charge / discharge control. This involves using a logic control unit or digital signal processor to actively control the charging and discharging process of the sampling capacitor based on its switching state. While this approach can achieve peak capture, it suffers from the following drawbacks: it requires additional control circuitry and drive units, resulting in a complex system structure and higher costs; the control strategy must be closely matched with the carrier frequency and switching timing, requiring synchronous adjustment of the control logic when the modulation frequency or operating mode changes; and under high-frequency and complex operating conditions, control delays or misjudgments may lead to peak loss or repeated sampling, affecting measurement accuracy and system stability. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-parameter detection circuit for on-state voltage drop and peak voltage detection. This circuit can achieve high-precision and robust measurement of forward and reverse on-state voltages and transient peak voltages under complex switching environments.

[0006] The technical solution of the present invention: a multi-parameter detection circuit for on-state voltage drop and peak voltage detection, applied to a three-level ANPC converter, including an on-state voltage drop test circuit and a peak voltage detection circuit connected in parallel across the power device under test;

[0007] The on-state voltage drop test circuit is used to collect the forward and reverse on-state voltage drops of the power device under on-state and freewheeling conditions, respectively. The on-state voltage drop test circuit includes a negative voltage overshoot suppression and input protection unit, which is used to suppress the interference of negative voltage overshoot caused by parasitic parameters of the power circuit on the measurement.

[0008] The peak voltage detection circuit is used to capture the transient spike voltage between the collector and emitter of the power device during the power device's turn-off process; the peak voltage detection circuit includes an adaptive charge and discharge control unit, which is used to automatically control the capture and discharge of the transient spike voltage according to the change in voltage across the power device.

[0009] The outputs of the conduction voltage drop test circuit and the peak voltage detection circuit are isolated and then connected to the analog-to-digital converter to achieve simultaneous detection of multiple parameters of the same power device.

[0010] The aforementioned on-state voltage drop and peak value detection multi-parameter detection circuit includes, in which the on-state voltage drop test circuit comprises:

[0011] The constant current source unit is used to provide a stable, small excitation current to the power device under test.

[0012] A dual diode clamping unit is connected between the constant current source unit and the power device to block high voltage when the device is turned off and to maintain the measurement path when the device is on and freewheeling.

[0013] The signal processing unit is used to scale and boost the level of the acquired on-state voltage drop signal.

[0014] A negative voltage overshoot suppression and input protection unit is disposed between the dual diode clamping unit and the signal processing unit, and is used to filter out negative voltage overshoot caused by parasitic inductance and current change rate.

[0015] The aforementioned on-state voltage drop and peak value detection multi-parameter detection circuit includes a constant current source unit consisting of transistors Q1, Q2, Q3, and Q4, and a resistor R. 10A bipolar mirror constant current source structure is constructed; the bases of transistors Q1 and Q2 are interconnected and connected to the collector of transistor Q2; the bases of transistors Q3 and Q4 are interconnected and connected to the collector of transistor Q4; the emitters of transistors Q1 and Q2 are connected together to the power supply terminal; the collector of transistor Q1 is connected to the emitter of transistor Q3; the collector of transistor Q2 is connected to the emitter of transistor Q4; the collector of transistor Q4 is connected to resistor R. 10 One end is connected to resistor R 10 The other end is grounded; the collector of the transistor Q3 is connected to the input terminal of the dual diode clamping unit.

[0016] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit includes a dual-diode clamping unit comprising diodes D1, D2, D4, and a Zener diode D3. The anode of diode D2 is connected to the output terminal of the constant current source unit, and the cathode of diode D2 is connected to the anode of diode D1, the cathode of Zener diode D3, and the negative voltage overshoot suppression and input protection unit. The cathode of diode D1 is connected to the collector of the power device under test. The anode of Zener diode D3 is connected to the anode of diode D4, and the cathode of diode D4 is grounded.

[0017] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit includes a negative voltage overshoot suppression and input protection unit, which is a first-order RC low-pass filter network comprising resistors R3 and R4, capacitors C3 and C4. Resistor R3 is connected in series between the output terminal of the constant current source unit and the input terminal of the signal processing unit. Resistor R4 is connected in series between the output terminal of the dual diode clamping unit and the input terminal of the signal processing unit. One end of capacitor C3 is connected between resistor R3 and the signal processing unit, and the other end of capacitor C3 is grounded. One end of capacitor C4 is connected between resistor R4 and the signal processing unit, and the other end of capacitor C4 is grounded.

[0018] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit includes a signal processing unit comprising resistors R5, R6, R7, R8, and R9, and a voltage source V. s1 And operational amplifier U1; the inverting input terminal of operational amplifier U1 is connected to one end of resistors R5 and R7, the other end of resistor R5 is connected to the negative voltage overshoot suppression and input protection unit, and the other end of resistor R7 is connected to the output terminal of operational amplifier U1; the non-inverting input terminal of operational amplifier U1 is connected to one end of resistors R6, R8 and R9, the other end of resistor R6 is connected to the negative voltage overshoot suppression and input protection unit, and the other end of resistor R8 is connected to the voltage source V s1 The positive terminal is connected; the voltage source V s1The negative terminal and the other end of resistor R9 are grounded.

[0019] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit, wherein the peak voltage detection circuit includes:

[0020] A high-bandwidth voltage divider unit is used to divide and compensate the voltage across the power device under test at high frequencies.

[0021] A peak hold unit, connected to the output of the high-bandwidth voltage divider unit, is used to capture and hold the peak voltage of the divided signal.

[0022] An adaptive charge / discharge control unit is connected to the output terminal of the high-bandwidth voltage divider unit and the discharge control terminal of the peak hold unit. It is used to automatically control the peak hold unit to enter the peak capture state when the voltage rises and to discharge the held peak voltage when the voltage drops, based on the voltage change of the voltage of the divided signal.

[0023] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit includes a high-bandwidth voltage divider unit comprising resistors R1 and R2, capacitors C1 and C2; resistor R1 and capacitor C1 are connected in parallel to form a high-voltage arm, the input of which is connected to the collector of the power device under test; resistor R2 and capacitor C2 are connected in parallel to form a low-voltage arm, the output of which is connected to the emitter of the power device under test and the adaptive charge / discharge control unit and grounded; the high-voltage arm and the low-voltage arm are connected in series, and their connection points are also connected to the peak hold unit and the adaptive charge / discharge control unit, respectively.

[0024] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit includes a peak holding unit comprising diode D5, diode D6, and resistor R. 11 The system includes capacitor C5, operational amplifier U2, and operational amplifier U3; the non-inverting input of operational amplifier U2 is connected to a high-bandwidth voltage divider unit, and the inverting input of operational amplifier U2 is connected to the anode of diode D5 and resistor R. 11 One end of the amplifier is connected; the output terminal of the operational amplifier U2 is connected to the cathode of diode D5 and the anode of diode D6; the inverting input terminal of the operational amplifier U3 is connected to its output terminal and resistor R. 11 The other end of the capacitor is connected to the non-inverting input of operational amplifier U3, one end of capacitor C5, the cathode of diode D6, and the adaptive charge / discharge control unit. The other end of capacitor C5 is grounded.

[0025] The aforementioned on-state voltage drop and peak detection multi-parameter detection circuit, wherein the adaptive charge / discharge control unit includes a resistor R. 12 Resistance R 13 MOSFET S1, voltage source V S2The operational amplifier U4 and the driver chip; the inverting input of the operational amplifier U4 is connected to a high-bandwidth voltage divider unit, and the non-inverting input of the operational amplifier U4 is connected to a resistor R. 12 and resistance R 13 One end is connected to resistor R 12 The other end is connected to the voltage source V S2 The positive terminal is connected to the voltage source V. S2 The negative terminal of the amplifier is connected to the high-bandwidth voltage divider unit and the emitter of the power device under test, and grounded; the output terminal of the operational amplifier U4 is connected to the resistor R. 13 The other end is connected to the input terminal of the driver chip; the output terminal of the driver chip is connected to the gate of the MOS transistor S1, the drain of the MOS transistor S1 is connected to the non-inverting input terminal of the operational amplifier U3, and the source of the MOS transistor S1 is connected to the ground terminal of the capacitor C5.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. This invention sets up the conduction voltage drop test circuit and the peak voltage detection circuit in parallel across the two ends of the power device under test, realizing the parallel acquisition of multiple parameters such as forward conduction voltage drop, reverse conduction voltage drop and transient peak voltage of the same device under the same operating conditions, providing more comprehensive status information for system monitoring.

[0028] 2. The present invention sets up a negative voltage overshoot suppression and input protection unit in the conduction voltage drop test circuit. The negative voltage overshoot caused by parasitic inductance and current change rate is effectively filtered out by a first-order RC low-pass filter network, which avoids the operational amplifier input terminal from exceeding the common mode range, thereby improving the reliability and measurement accuracy of the measurement circuit.

[0029] 3. This invention adopts a bipolar mirror constant current source structure to eliminate the influence of the Erlich voltage on the accuracy of the output current, and provides a stable excitation current that is independent of temperature and power supply voltage changes, ensuring the stability and consistency of the on-state voltage drop measurement.

[0030] 4. This invention introduces a MOS discharge structure controlled by a reverse hysteresis comparator in the peak voltage detection circuit, realizing adaptive charge and discharge control. It eliminates the need for additional logic control units and synchronization signals, and can automatically adapt to different operating frequencies and operating states, reducing system complexity and cost, and improving robustness.

[0031] 5. This invention employs a resistor-capacitor voltage divider unit to achieve a wideband flat response from DC to high frequency, ensuring accurate capture of transient peak voltages while meeting high-bandwidth measurement requirements. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the circuit structure of the present invention;

[0033] Figure 2 This is a schematic diagram of the transistor's output characteristic curve and Urrich voltage;

[0034] Figure 3 This is a schematic diagram of the current flow in the forward conduction state;

[0035] Figure 4 This is a schematic diagram of the current flow in the off state;

[0036] Figure 5 This is a schematic diagram of the current flow in the reverse conduction state;

[0037] Figure 6 This is a schematic diagram of the converter operation under ANPC inverter conditions;

[0038] Figure 7 This is a schematic diagram of the waveforms related to the shutdown process;

[0039] Figure 8 This is a schematic diagram of the target cutoff frequency design;

[0040] Figure 9 This is a schematic diagram of the input waveform;

[0041] Figure 10 This is the working principle of an inverse hysteresis comparator;

[0042] Figure 11 It is the forward conduction voltage drop under a load current of 100A;

[0043] Figure 12 It is the reverse conduction voltage drop under a load current of 20-40A;

[0044] Figure 13 This is the voltage waveform at a key node in the lower bridge arm negative pressure measurement process;

[0045] Figure 14 It is a resistor-capacitor voltage divider circuit structure;

[0046] Figure 15 This is the 50A load current turn-off waveform;

[0047] Figure 16 This is the 100A load current turn-off waveform;

[0048] Figure 17 This is the 150A load current turn-off waveform;

[0049] Figure 18 It is the 200A load current turn-off waveform. Detailed Implementation

[0050] The following detailed description of specific embodiments, in conjunction with the technical solution of the present invention, is provided. These embodiments are only used to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0051] Example: A multi-parameter detection circuit for on-state voltage drop and peak voltage detection, applied to a three-level ANPC converter, including an on-state voltage drop test circuit and a peak voltage detection circuit connected in parallel across the power device under test;

[0052] The on-state voltage drop test circuit is used to collect the forward and reverse on-state voltage drops of the power device under on-state and freewheeling conditions, respectively. The on-state voltage drop test circuit includes a negative voltage overshoot suppression and input protection unit, which is used to suppress the interference of negative voltage overshoot caused by parasitic parameters of the power circuit on the measurement.

[0053] The peak voltage detection circuit is used to capture the transient spike voltage between the collector and emitter of the power device during the power device's turn-off process; the peak voltage detection circuit includes an adaptive charge and discharge control unit, which is used to automatically control the capture and discharge of the transient spike voltage according to the change in voltage across the power device.

[0054] The outputs of the conduction voltage drop test circuit and the peak voltage detection circuit are isolated and then connected to the analog-to-digital converter to achieve simultaneous detection of multiple parameters of the same power device.

[0055] The following combination Figure 1 The on-state voltage drop test circuit and peak voltage detection circuit of the present invention are described in detail below:

[0056] 1. On-state voltage drop test circuit: This circuit is used to achieve high-precision measurement of the forward and reverse on-state voltage drops of power devices (IGBT / SiC) under conditions of high stray inductance and significant negative voltage overshoot in a three-level ANPC circuit. It also prevents operational amplifier (op-amp) input over-limit through front-end protection. This circuit acquires the device's forward and reverse on-state voltages, providing sampleable, high-precision electrical parameter inputs for subsequent temperature / health assessments. Includes:

[0057] 1.1 Constant Current Source Circuit: The constant current source unit consists of transistors Q1, Q2, Q3, and Q4, and resistor R. 10 A bipolar mirror constant current source structure is constructed; the bases of transistors Q1 and Q2 are interconnected and connected to the collector of transistor Q2; the bases of transistors Q3 and Q4 are interconnected and connected to the collector of transistor Q4; the emitters of transistors Q1 and Q2 are connected together to the power supply terminal; the collector of transistor Q1 is connected to the emitter of transistor Q3; the collector of transistor Q2 is connected to the emitter of transistor Q4; the collector of transistor Q4 is connected to resistor R. 10 One end is connected to resistor R 10 The other end is grounded; the collector of the transistor Q3 is connected to the input terminal of the dual diode clamping unit.

[0058] The constant current source circuit is used to provide a stable small current excitation. Using a mirrored current source in the bias circuit ensures good stability of the circuit under changes in temperature and power supply voltage. The bias current provided by the mirrored current source in the cutoff region is more accurate than that of a typical resistor. The basic principle is that: since the voltage difference between the base and emitter of the two PNP transistors is the same, the base currents are equal; and the voltage difference between the collector and emitter of the reference potential transistor is fixed, therefore the output current is:

[0059] ;

[0060] Furthermore, based on the output characteristics of the transistor, to ensure stable output current, the emitter voltage must not enter saturation, meaning the collector voltage must not exceed the base potential. For the output terminal, the following formula must be satisfied:

[0061] ;

[0062] ;

[0063] Therefore, ensuring a larger HFE value (Hybrid Forward Current Gain) can increase the accuracy of the output current.

[0064] However, for transistors, i b The output current-voltage characteristic curves of all exhibit a slight slope, and their left extensions intersect at a relatively negative voltage point, namely the Erlich voltage. Figure 2 As shown, therefore the output current i of the transistor C It is related not only to the base current but also to the collector-emitter voltage. Therefore, the collector-emitter voltage oscillation will cause changes in the output current, which will affect the output characteristics of the unipolar current mirror even when the output terminal is at ground level.

[0065] To improve the accuracy of the output current, a bipolar mirror constant current source can be used. The two-stage structure keeps transistors Q2 and Q4 in saturation, thus clamping the base potentials of transistors Q1 and Q3. This clamps the collector potential of output transistor Q3, while transistor Q1 handles voltage variations, eliminating the influence of the Erlich voltage. For the output, the following formula is satisfied:

[0066] ;

[0067] However, compared to a single-stage current mirror, the accuracy of a two-stage current mirror is somewhat lower, so the HFE value of the transistor should be increased when selecting components.

[0068] 1.2 Dual Diode Clamping Circuit: The dual diode clamping unit includes diodes D1, D2, D4, and Zener diode D3; the anode of diode D2 is connected to the output terminal of the constant current source unit, and the cathode of diode D2 is connected to the anode of diode D1, the cathode of Zener diode D3, and the negative voltage overshoot suppression and input protection unit; the cathode of diode D1 is connected to the collector of the power device under test; the anode of Zener diode D3 is connected to the anode of diode D4, and the cathode of diode D4 is grounded.

[0069] In this circuit, diodes D1 and D2 are fast recovery diodes with high blocking voltage, mainly used to block the high voltage when the device is turned off; diode D4 is a Schottky diode, and its forward voltage drop, together with the operating voltage of Zener diode D3, constitutes the clamping voltage for the device in the off-state. The dual-diode clamping circuit has three operating states. Figure 3 A schematic diagram showing the current flow in the forward conduction state is provided. Figure 4 A schematic diagram showing the current flow in the off state is provided. Figure 5 A schematic diagram showing the current flow in the reverse conduction state is provided.

[0070] When the IGBT is in the ON state, the constant current source current flows through diodes D1 and D2, such as... Figure 3 As shown. Assuming the current flowing through diodes D1 and D2 is equal, and that the conduction characteristics, external environment, and junction temperature of diodes D1 and D2 are the same, then V D1 =V D2 V a The voltage includes the forward voltage drop of D1 and D2, while V b The voltage includes the forward voltage drop of D2, therefore the output voltage only needs to meet 2V. b -V a The relationship can eliminate the test error caused by the conduction voltage drop. Taking advantage of the fact that when the reverse voltage of the Zener diode is lower than the reverse breakdown voltage, the clamping diode is in the cut-off state, the reverse resistance is very large, and the leakage current is very small, with a leakage current in the μA level, the current flowing through D2 can be approximately equal to the current flowing through D1.

[0071] When the IGBT is in the off state, such as Figure 4 As shown, the constant current source current cannot flow through diode D2. Instead, the constant current source current flows through the clamping diode, which is in its reverse breakdown operating region. The output voltage is the reverse breakdown voltage of the clamping diode. Note that the clamping diode has dynamic resistance, and the clamping voltage is still related to the constant current source current.

[0072] When the IGBT module is in reverse diode freewheeling mode, such as Figure 5As shown, inductor L continuously discharges into the reverse diode, thus entering a freewheeling process. At this time, the current in the measuring circuit flows from the current source through diode D1, diode D2, and inductor L, then back to the current source, forming a closed loop. At this time, V... O1 If the value is negative, it means that the voltage drop across the anti-parallel diode is measured. The output characteristics are the same as when the IGBT is in the on state. At this time, the clamping circuit D4 is cut off, and no current flows under leakage conditions.

[0073] 1.3 Signal Processing Unit: The signal processing unit includes resistors R5, R6, R7, R8, and R9, and a voltage source V. s1 And operational amplifier U1; the inverting input terminal of operational amplifier U1 is connected to one end of resistors R5 and R7, the other end of resistor R5 is connected to the negative voltage overshoot suppression and input protection unit, and the other end of resistor R7 is connected to the output terminal of operational amplifier U1; the non-inverting input terminal of operational amplifier U1 is connected to one end of resistors R6, R8, and R9, the other end of resistor R6 is connected to the negative voltage overshoot suppression and input protection unit, and the other end of resistor R8 is connected to the voltage source V s1 The positive terminal is connected; the voltage source V s1 The negative terminal and the other end of resistor R9 are grounded.

[0074] Based on the virtual short and virtual open circuit principle and Kirchhoff's laws, the relationship between the common-mode input voltage and the output voltage of the operational amplifier can be derived as follows:

[0075] ;

[0076] Therefore, by adjusting the resistor ratio, the on-state voltage drop output value can be scaled proportionally. To facilitate subsequent isolation output and ADC sampling, this invention scales the ratio by a factor of 1, adjusting R... f / R3 is 1 / 2, ensuring V b Under proportional conditions, the parallel resistance value can be dynamically adjusted according to the reference voltage value, that is:

[0077] ;

[0078] Therefore, we can obtain:

[0079] ;

[0080] ;

[0081] The advantage of this invention is that it can ensure that the output result is positive, so the result can be directly sampled by isolation and ADC. In addition, the common-mode input voltage of the operational amplifier is subject to proportional adjustment and positive bias protection, which enhances reliability.

[0082] 1.4 Negative Voltage Overshoot Suppression and Input Protection Unit: The negative voltage overshoot suppression and input protection unit is a first-order RC low-pass filter network, including resistors R3 and R4, capacitors C3 and C4; resistor R3 is connected in series between the output terminal of the constant current source unit and the input terminal of the signal processing unit; resistor R4 is connected in series between the output terminal of the dual diode clamping unit and the input terminal of the signal processing unit; one end of capacitor C3 is connected between resistor R3 and the signal processing unit, and the other end of capacitor C3 is grounded; one end of capacitor C4 is connected between resistor R4 and the signal processing unit, and the other end of capacitor C4 is grounded.

[0083] The purpose of this circuit is to take the commutation process under ANPC inverter operation as an example, such as... Figure 6 As shown, T2 and T3 are high-frequency transistors. The PWM signal controls the switching of T2 on and off, while T1 and T6 are normally open. Point O is used as the reference zero potential point. At time t0, the voltage of transistor T2 begins to rise (turn off), and the voltage of transistor T3 begins to fall accordingly. At time t1, the voltage of transistor T2 reaches the bus voltage (DC+ to neutral point voltage). At this time, the current i flowing through transistor T2 is... c The commutation begins, transferring to the anti-parallel diode of the lower transistor, forming a diode current i. D Both transistors T2 and T3 experience positive and negative overshoots due to the parasitic inductance on the collector and emitter sides.

[0084] Because negative voltage is directly introduced to the op-amp input side during measurement, the op-amp's allowable common-mode input voltage range is typically smaller than the supply voltage. If the op-amp input voltage exceeds this supply voltage range, it may operate abnormally, reducing its lifespan and weakening the reliability of the entire measurement circuit. Using current fall time (e.g.) Figure 7 As shown, the equivalent switching frequency f corresponding to the time it takes for the current to drop from 90% to 10% is... sw As the target filtering frequency, since t f The current fall time has a linear relationship with both junction temperature and load changes; therefore, the target peak voltage for filtering also depends on t. f Related.

[0085] This embodiment uses a first-order RC filter to implement overshoot voltage protection. The input-output relationship of the first-order RC filter with frequency is as follows:

[0086] ;

[0087] Therefore, the formula can be obtained:

[0088] ;

[0089] in, Let V be the average current drop rate, K be the peak factor, and L be the sum of the parasitic inductances on both sides of the chip. The maximum output value V is designed to be... max Solving the inequality yields the maximum cutoff frequency:

[0090] ;

[0091] Therefore, by setting the current and K coefficient under the proposed operating conditions, an equivalent frequency can be designed to eliminate the peak voltage to V under different turn-off time conditions. max The following step involves calculating the cutoff frequency required for the RC circuit. Taking a current of 400A, a maximum output voltage of 20V, and K=2 as an example... Figure 8 As shown.

[0092] According to the IGBT module datasheet, under a 400A current load with a relatively low gate resistance, t f The time is approximately 80ns, corresponding to a maximum cutoff frequency of 1.547MHz. Since the RC filter introduces a delay when measuring the on-state voltage drop to enter or exit the clamping state, a cutoff frequency value as large as possible is selected to ensure that the delay is minimized. To ensure a certain margin, the cutoff frequency is chosen to be 1MHz.

[0093] 2. Peak voltage detection circuit: This circuit captures transient voltage spikes that occur during the power device's turn-off process and maintains these voltages after turn-off for subsequent sampling and recording. This circuit requires no complex active control, maintains the peak voltage during device turn-off, discharges the peak voltage during turn-on, and automatically adapts to carrier frequency changes to achieve stable peak voltage detection. Specifically, it includes:

[0094] 2.1 High-bandwidth voltage divider unit: The high-bandwidth voltage divider unit includes resistors R1 and R2, capacitors C1 and C2; resistor R1 and capacitor C1 are connected in parallel to form a high-voltage arm, the input of which is connected to the collector of the power device under test; resistor R2 and capacitor C2 are connected in parallel to form a low-voltage arm, the output of which is connected to the emitter of the power device under test and the adaptive charge / discharge control unit and grounded; the high-voltage arm and the low-voltage arm are connected in series, and their connection points are also connected to the peak hold unit and the adaptive charge / discharge control unit, respectively.

[0095] In theory, a pure resistive voltage divider circuit can achieve voltage division at the turn-off peak. However, the actual resistor package has parasitic capacitance, which will result in poor high-frequency characteristics of pure resistive voltage division. Based on this, a resistive-capacitive voltage divider is used to achieve high-bandwidth voltage division.

[0096] R1 and C1 are the high-voltage arm resistor and capacitor, respectively. When connected in parallel, they form the impedance Z1. R2 and C2 are the low-voltage arm resistor and capacitor, respectively. When connected in parallel, they form the impedance Z2.

[0097] The voltage division ratio can be obtained from the following relationship:

[0098] ;

[0099] Therefore, we can conclude that:

[0100] ;

[0101] To ensure stable voltage division, meaning the RC voltage divider is not limited by frequency band, the imaginary part of the voltage division ratio can be designed to be 0, i.e.:

[0102] ;

[0103] Therefore, it is necessary to ensure that R1C1 = R2C2.

[0104] Therefore, when R1 / R2=C2 / C1, the resistor-capacitor voltage divider will not be limited by the frequency band and can realize broadband measurement from DC to high frequency.

[0105] 2.2 Peak Hold Unit: The peak hold unit includes diode D5, diode D6, and resistor R. 11 The system includes capacitor C5, operational amplifier U2, and operational amplifier U3; the non-inverting input of operational amplifier U2 is connected to a high-bandwidth voltage divider unit, and the inverting input of operational amplifier U2 is connected to the anode of diode D5 and resistor R. 11 One end of the amplifier is connected; the output terminal of the operational amplifier U2 is connected to the cathode of diode D5 and the anode of diode D6; the inverting input terminal of the operational amplifier U3 is connected to its output terminal and resistor R. 11 The other end of the capacitor is connected to the non-inverting input of operational amplifier U3, one end of capacitor C5, the cathode of diode D6, and the adaptive charge / discharge control unit. The other end of capacitor C5 is grounded.

[0106] The advantage of the peak hold unit lies in the introduction of two stages of operational amplifiers to achieve negative feedback. Therefore, both operate in the linear region, satisfying virtual short and virtual open circuit requirements, eliminating the delay time required for saturation and linearization, resulting in faster measurement speeds. Furthermore, by connecting the operational amplifier after the load capacitor, only a low static bias current operational amplifier (FET / CMOS) is needed to eliminate the discharge effect. Simultaneously, a switch can be connected in parallel on the load capacitor side to control the MOSFET and achieve charge discharge during the turn-on process, ensuring accurate capture of each transient voltage spike.

[0107] It has three basic operating states: zero voltage state, voltage rise state, and voltage hold state.

[0108] Waveform diagram as follows Figure 9 As shown, in the zero-voltage state, i.e., the initial t0 stage, the capacitor voltage V2 = 0, and the voltage follower V... O2 =0, input voltage is also 0, I R =0.

[0109] During the voltage rise phase, specifically the t0 to t1 stage, the input voltage begins to rise, at which point V in V1 and V3 output positive voltages, which will charge V2. Diode D6 conducts, and D5 is cut off. Due to the virtual open circuit characteristic, no current flows into the inverting input of the preceding op-amp, causing I... R =0, thus ensuring V out =V1, and V1=V in This ensures that the voltage divider signal V output by the high-bandwidth voltage divider unit is guaranteed. divide =V O2 That is, V3 will keep charging until V2 = V divide It is important to note that the power output of the preamplifier should be sufficient to charge the storage capacitor.

[0110] The voltage holding state refers to the period from t1 to t2, where the voltage is lower than the peak voltage, V divide If the voltage is momentarily less than V1, then V3 will output a negative voltage. At this time, D5 will conduct and D6 will be cut off. At this point, V... divide When the voltage changes, V1 changes accordingly, and the resistor will bear the peak output voltage V2 = V. O2 With V1=V divide The voltage difference causes current to flow into the input of the preamplifier, maintaining the capacitor voltage until the peak voltage exceeds V again. O2 .

[0111] It should be noted that because of the junction capacitance of the diode, after the peak voltage drops back to the bus voltage, there will be some energy dissipation due to the du / dt. Therefore, it is necessary to ensure that the junction capacitance of the D6 diode is small enough.

[0112] 2.3 Adaptive Charge / Discharge Control Unit: The adaptive charge / discharge control unit includes a resistor R. 12 Resistance R 13 MOSFET S1, voltage source V S2 The operational amplifier U4 and the driver chip; the inverting input of the operational amplifier U4 is connected to a high-bandwidth voltage divider unit, and the non-inverting input of the operational amplifier U4 is connected to a resistor R. 12 and resistance R 13 One end is connected to resistor R 12 The other end is connected to the voltage source V S2 The positive terminal is connected to the voltage source V. S2 The negative terminal of the amplifier is connected to the high-bandwidth voltage divider unit and the emitter of the power device under test, and grounded; the output terminal of the operational amplifier U4 is connected to the resistor R. 13 The other end is connected to the input terminal of the driver chip; the output terminal of the driver chip is connected to the gate of the MOS transistor S1, the drain of the MOS transistor S1 is connected to the non-inverting input terminal of the operational amplifier U3, and the source of the MOS transistor S1 is connected to the ground terminal of the capacitor C5.

[0113] Wherein, resistance R 12 Resistor R 13 Operational amplifier U4 and voltage source V S2 The reverse hysteresis comparator circuit works by detecting a voltage rise across the IGBT (initiating turn-off), which causes the power drive circuit to output a low level, turning off the MOSFET and enabling normal charge storage and peak detection in the capacitor. Upon detecting a voltage drop (initiating conduction), the reverse hysteresis comparator outputs a high level, turning on the MOSFET to discharge the capacitor charge, facilitating the extraction of the next peak voltage. The hysteresis comparator also aims to eliminate high-frequency signal interference and noise on the comparator's critical voltage nodes, increasing the reliability of charge / discharge control decisions.

[0114] The working principle of the inverse hysteresis comparator is as follows: Figure 10 As shown, the relationship between its positive and negative threshold voltages is as follows:

[0115] ;

[0116] ;

[0117] Set the input signal of the reverse hysteresis comparator to the voltage divider V. ce This refers to the peak voltage detector input signal. During turn-off, the design voltage exceeds V. T+ At the positive threshold voltage node, the hysteresis comparator outputs a potential of 0 V. OL The control MOS is turned off to allow the load capacitor to charge freely. When it is turned on, the design voltage is lower than V. T- At the negative threshold voltage node, the hysteresis comparator outputs a high level V. OH The MOSFET is controlled to conduct, discharging charge and preparing for the next peak voltage detection. The subsequent stage connects to a high-speed, low-delay power driver chip to control the rapid charging and discharging of the load capacitor, enabling accurate identification of peak voltage under high-frequency switching signals.

[0118] Compared to traditional active control schemes, this invention replaces the active control strategy with an adaptive charging and discharging circuit, thus eliminating the need for additional logic control and synchronization signals. This avoids the problem of needing to readjust the control strategy when the frequency changes, reduces system complexity and cost, and improves system robustness.

[0119] Furthermore, to verify the specific effects of the circuit of the present invention, the following experiments were conducted in this embodiment:

[0120] (a) On-state voltage drop circuit test

[0121] Output relationship based on conduction voltage drop test:

[0122] ;

[0123] The design is VS1=15V, therefore the output relationship is:

[0124] ;

[0125] The relationship between the sampling output and isolation output characteristics of the conduction voltage drop test circuit was calibrated using a DC voltage source (RIGOL DP832), and the results are shown in Table 1.

[0126] Table 1

[0127]

[0128] The test results show that the average error of the forward and reverse voltage test circuit in this design is 9.385mV, the average error ratio of forward voltage conduction is 0.442%, and the average error ratio of reverse voltage conduction is 0.828%, which meets the expectation of high precision.

[0129] To verify the operating characteristics of the forward voltage drop test circuit under dynamic conditions, it was tested under a dual-pulse condition. The experiment used a 2MBI800XNE120-50 IGBT module (1200V, 800A, three chips in parallel), with a bus capacitor of 300μF, a load inductance of 210μH, a MAGNA-POWER XR10000-0.2-POS / 240SP power supply, and a 2FHD0115C driver board from Feishide. The forward voltage drop of the lower diode and the reverse diode were measured. The waveform of the dual-pulse experiment is shown below. Figure 11 As shown (the output voltage of the conduction voltage drop test circuit has been normalized), during the conduction phase of the lower transistor, V ce The monitoring circuit can track the actual V in real time. ce Waveform, and V ce The monitored value is almost equal to the actual value. Meanwhile, the reverse conduction voltage drop waveform is as follows: Figure 12 As shown, the forward voltage drop V during the reverse freewheeling phase of the diode is... ce The monitored values ​​were almost equal to the actual values.

[0130] The forward voltage drop of the IGBT and the reverse diode forward voltage drop were measured. Five points were selected in the experiment: 20, 40, 60, 80, and 100 A. The results are shown in Table 2 (forward voltage drop measurement results) and Table 3 (reverse diode voltage drop measurement results), respectively. ce The measurement circuit error is maintained within 1%, and as the conduction current gradually increases, the absolute value of the conduction voltage drop also gradually increases.

[0131] Table 2

[0132]

[0133] Table 3

[0134]

[0135] To verify the actual effect of the negative voltage overshoot circuit, a half-bridge dual-pulse circuit simulation is used as an example. With the upper transistor as the transistor under test, the lower transistor will induce a negative voltage overshoot due to the parasitic inductance. Based on the previously designed cutoff frequency f... c =1MHz, resistance set to 100 ohms, capacitance set to 1.5nF, IGBT selected is Infineon Highspeed chip IKQ75N120CH3, first conduction time set to 20μs, load current of 400A during first turn-off is achieved by changing the load inductance, and the gate resistance value is changed to achieve t f =78.675ns.

[0136] Under these simulation conditions, the voltage waveforms at key nodes during the lower arm negative voltage measurement process are obtained, such as... Figure 13 As shown in the simulation, the peak negative voltage of the lower diode is -55.456V, which is slightly lower than the -60V voltage with a peak factor of 1.5. The peak voltage after filtering is reduced to -16.93V, which can meet the protection requirements. Moreover, the voltage settling time for following the negative voltage change of the anti-parallel diode is only 0.618μs.

[0137] (II) Peak Voltage Detection Circuit Test

[0138] Because the actual parameter values ​​of PCB surface-mount components differ somewhat from their calibrated ideal values, precise measurement of the capacitors and resistors used for voltage division is necessary to design a high-precision RC voltage divider circuit. An impedance analyzer (Tonghui TH2839) is used for parameter calibration. Since the high-voltage side surface-mount resistors have voltage withstand limitations, seven resistors are connected in series. To match the final impedance value, a three-resistor series structure is used on the low-voltage side for easy adjustment. The RC voltage divider circuit structure is as follows: Figure 14 As shown in Table 4, the final measured values ​​(100kHz) are as follows, and the final voltage division ratio is 1:373.5.

[0139] Table 4

[0140]

[0141] After determining the voltage division ratio and impedance matching, the RC voltage divider circuit was tested under dual-pulse test conditions. Simultaneously, the peak voltage detection circuit's peak acquisition under dynamic characteristics was verified. The experiment selected turn-off voltage waveforms under load currents of 50A, 100A, 150A, and 200A, as shown below. Figures 15-18As shown. The experiment used an IGBT module 2MBI800XNE120-50 (1200V, 800A, three chips in parallel). The bus capacitor was 300μF, the load inductance was 210μH, the power supply was a MAGNA-POWER XR10000-0.2-POS / 240SP model, and the driver board was a Feishide 2FHD0115C driver board. To increase the peak voltage, two leads were connected in series to increase the parasitic inductance of the circuit. To test the operating characteristics of the peak detection measurement circuit, the green waveform represents the collector-emitter voltage V of the power device. ce The red waveform represents the low-voltage bridge arm voltage V after being divided by the resistor-capacitor voltage divider. divide The blue waveform represents the peak storage voltage V output by the peak detection circuit. peak V divide With V peak All values ​​were amplified using a voltage division ratio of 373.5. The output results of the peak voltage holding circuit are shown in Table 5. Experiments show that the peak voltage measurement accuracies at load currents of 50A, 100A, 150A, and 200A are 99.46%, 97.57%, 96.20%, and 99.60%, respectively, all exceeding 96%. The circuit can stably capture peak values ​​under different currents without requiring external control signal adjustments.

[0142] Table 5

[0143]

[0144] In summary, the multi-parameter detection circuit provided by this invention can effectively solve the problem of negative voltage overshoot interference in the on-state voltage drop measurement in a three-level ANPC system, and at the same time realize adaptive peak voltage detection without active control, with high precision, high reliability and good adaptability to operating conditions.

[0145] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the corresponding technical solutions to depart from the protection scope defined by the claims of the present invention.

Claims

1. A multi-parameter detection circuit for detecting on-state voltage drop and peak value, applied to a three-level ANPC converter, characterized in that, This includes a forward voltage drop test circuit and a peak voltage detection circuit connected in parallel across the power device under test; The on-state voltage drop test circuit is used to collect the forward and reverse on-state voltage drops of the power device under on-state and freewheeling conditions, respectively. The on-state voltage drop test circuit includes a negative voltage overshoot suppression and input protection unit, which is used to suppress the interference of negative voltage overshoot caused by parasitic parameters of the power circuit on the measurement. The peak voltage detection circuit is used to capture the transient spike voltage between the collector and emitter of the power device during the power device's turn-off process; the peak voltage detection circuit includes an adaptive charge and discharge control unit, which is used to automatically control the capture and discharge of the transient spike voltage according to the change in voltage across the power device. The outputs of the conduction voltage drop test circuit and the peak voltage detection circuit are isolated and then connected to the analog-to-digital converter to achieve simultaneous detection of multiple parameters of the same power device.

2. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 1, characterized in that, The on-state voltage drop test circuit includes: The constant current source unit is used to provide a stable, small excitation current to the power device under test. A dual diode clamping unit is connected between the constant current source unit and the power device to block high voltage when the device is turned off and to maintain the measurement path when the device is on and freewheeling. The signal processing unit is used to scale and boost the level of the acquired on-state voltage drop signal. A negative voltage overshoot suppression and input protection unit is disposed between the dual diode clamping unit and the signal processing unit, and is used to filter out negative voltage overshoot caused by parasitic inductance and current change rate.

3. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 2, characterized in that, The constant current source unit consists of transistors Q1, Q2, Q3, and Q4, and resistor R. 10 A bipolar mirror constant current source structure is constructed; the bases of transistors Q1 and Q2 are interconnected and connected to the collector of transistor Q2; the bases of transistors Q3 and Q4 are interconnected and connected to the collector of transistor Q4; the emitters of transistors Q1 and Q2 are connected together to the power supply terminal; the collector of transistor Q1 is connected to the emitter of transistor Q3; the collector of transistor Q2 is connected to the emitter of transistor Q4; the collector of transistor Q4 is connected to resistor R. 10 One end is connected to resistor R 10 The other end is grounded; the collector of the transistor Q3 is connected to the input terminal of the dual diode clamping unit.

4. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 2, characterized in that, The dual-diode clamping unit includes diodes D1, D2, D4, and Zener diode D3; the anode of diode D2 is connected to the output terminal of the constant current source unit, and the cathode of diode D2 is connected to the anode of diode D1, the cathode of Zener diode D3, and the negative voltage overshoot suppression and input protection unit; the cathode of diode D1 is connected to the collector of the power device under test; the anode of Zener diode D3 is connected to the anode of diode D4, and the cathode of diode D4 is grounded.

5. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 2, characterized in that, The negative voltage overshoot suppression and input protection unit is a first-order RC low-pass filter network, including resistors R3 and R4, capacitors C3 and C4; resistor R3 is connected in series between the output terminal of the constant current source unit and the input terminal of the signal processing unit; resistor R4 is connected in series between the output terminal of the dual diode clamping unit and the input terminal of the signal processing unit; one end of capacitor C3 is connected between resistor R3 and the signal processing unit, and the other end of capacitor C3 is grounded; one end of capacitor C4 is connected between resistor R4 and the signal processing unit, and the other end of capacitor C4 is grounded.

6. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 2, characterized in that, The signal processing unit includes resistors R5, R6, R7, R8, and R9, and a voltage source V. s1 And operational amplifier U1; the inverting input terminal of operational amplifier U1 is connected to one end of resistors R5 and R7, the other end of resistor R5 is connected to the negative voltage overshoot suppression and input protection unit, and the other end of resistor R7 is connected to the output terminal of operational amplifier U1; the non-inverting input terminal of operational amplifier U1 is connected to one end of resistors R6, R8 and R9, the other end of resistor R6 is connected to the negative voltage overshoot suppression and input protection unit, and the other end of resistor R8 is connected to the voltage source V s1 The positive terminal is connected; the voltage source V s1 The negative terminal and the other end of resistor R9 are grounded.

7. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 1, characterized in that, The peak voltage detection circuit includes: A high-bandwidth voltage divider unit is used to divide and compensate the voltage across the power device under test at high frequencies. A peak hold unit, connected to the output of the high-bandwidth voltage divider unit, is used to capture and hold the peak voltage of the divided signal. An adaptive charge / discharge control unit is connected to the output terminal of the high-bandwidth voltage divider unit and the discharge control terminal of the peak hold unit. It is used to automatically control the peak hold unit to enter the peak capture state when the voltage rises and to discharge the held peak voltage when the voltage drops, based on the voltage change of the voltage of the divided signal.

8. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 7, characterized in that, The high-bandwidth voltage divider unit includes resistors R1 and R2, capacitors C1 and C2; resistor R1 and capacitor C1 are connected in parallel to form a high-voltage arm, the input of which is connected to the collector of the power device under test; resistor R2 and capacitor C2 are connected in parallel to form a low-voltage arm, the output of which is connected to the emitter of the power device under test and the adaptive charge / discharge control unit and grounded; the high-voltage arm and the low-voltage arm are connected in series, and their connection points are also connected to the peak hold unit and the adaptive charge / discharge control unit, respectively.

9. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 7, characterized in that, The peak hold unit includes diode D5, diode D6, and resistor R. 11 The system includes capacitor C5, operational amplifier U2, and operational amplifier U3; the non-inverting input of operational amplifier U2 is connected to a high-bandwidth voltage divider unit, and the inverting input of operational amplifier U2 is connected to the anode of diode D5 and resistor R. 11 One end of the amplifier is connected; the output terminal of the operational amplifier U2 is connected to the cathode of diode D5 and the anode of diode D6; the inverting input terminal of the operational amplifier U3 is connected to its output terminal and resistor R. 11 The other end of the capacitor is connected to the non-inverting input of operational amplifier U3, one end of capacitor C5, the cathode of diode D6, and the adaptive charge / discharge control unit. The other end of capacitor C5 is grounded.

10. The multi-parameter detection circuit for on-state voltage drop and peak value detection according to claim 9, characterized in that, The adaptive charge / discharge control unit includes a resistor R. 12 Resistance R 13 MOSFET S1, voltage source V S2 The operational amplifier U4 and the driver chip; the inverting input of the operational amplifier U4 is connected to a high-bandwidth voltage divider unit, and the non-inverting input of the operational amplifier U4 is connected to a resistor R. 12 and resistance R 13 One end is connected to resistor R 12 The other end is connected to the voltage source V S2 The positive terminal is connected to the voltage source V. S2 The negative terminal of the amplifier is connected to the high-bandwidth voltage divider unit and the emitter of the power device under test, and grounded; the output terminal of the operational amplifier U4 is connected to the resistor R. 13 The other end is connected to the input terminal of the driver chip; the output terminal of the driver chip is connected to the gate of the MOS transistor S1, the drain of the MOS transistor S1 is connected to the non-inverting input terminal of the operational amplifier U3, and the source of the MOS transistor S1 is connected to the ground terminal of the capacitor C5.

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