Techniques for efficient execution of data reduction in parallel processing units

Abstract

The present invention discloses a technology for effectively executing data reduction in a parallel processing unit, and specifically discloses a technology for reducing the delay associated with executing data reduction in a multi-threaded processor. In response to a single instruction associated with a group of threads executed in the multi-threaded processor, a thread bundle reduction unit obtains register values ​​stored in a source register, wherein each register value is associated with a different thread included in the group of threads. The thread bundle reduction unit performs one or more operations on the register values ​​to calculate a total value. The thread bundle reduction unit stores the total value in a destination register, which can be accessed by at least one thread in the group of threads. Because the data reduction is executed via a single instruction using hardware dedicated to the data reduction, the number of cycles required to execute the data reduction is reduced compared to the prior art that uses hardware not dedicated to the data reduction to execute via multiple instructions.

Description

Background Art

[0001] Fields of various embodiments

[0002] Embodiments of the present disclosure relate generally to parallel processing systems and, more particularly, to techniques for efficiently performing data reduction in parallel processing units.

[0003] Related technical notes

[0004] A parallel processing unit ("PPU") is capable of achieving very high performance using a large number of small parallel execution threads on a dedicated programmable hardware processing unit. In a PPU, a "warp" is a group of threads in which each active thread executes the same instruction simultaneously on different input data. In many parallel processing algorithms, the threads in one or more warps are configured to generate per-thread results simultaneously, and then "data reduction" is performed across the per-thread results to generate a single aggregate result. For example, each of the 162,944 threads can calculate a different per-thread result based on a different part of an image. The threads can then apply an addition operation to the per-thread results to generate an aggregate value.

[0005] In one method of performing data reduction, each thread performs atomic operations (i.e., performs operations without interference from other threads) to aggregate per-thread results to a common memory location that is accessible to all threads. It should be noted that each thread initially stores the associated per-thread results in a register that has a relatively fast access time but is not directly accessible to other threads. In contrast, the common memory location is typically located in a memory with a relatively slow access time, such as shared memory, global memory. One disadvantage of this approach is that the time required to perform atomic operations on the common memory location can significantly reduce the overall performance of the associated parallel processing algorithm. For example, for each of the 162,944 threads, it takes 162,944 cycles to perform an atomic addition of "1" to a single location in global memory.

[0006] To reduce the time required to perform an atomic addition operation, some PPUs have the ability to perform a portion of the atomic addition operation "inline" between the hardware processing unit and global memory. However, the inlining feature does not reduce the time required to perform data reductions using other reduction operations (such as arithmetic minimum) and / or storing the aggregate result in another memory (such as shared memory or shared registers).

[0007] The other PPUs use shuffle instructions to perform initial data reductions on the per-thread results of each warp. The shuffle instructions enable each thread included in the warp to access the surface private registers of different threads in the warp based on a configurable pattern. To perform initial data reductions on a warp of N threads, the first shuffle instruction enables each thread in the N / 2 threads to apply a reduction operation to different pairs of per-thread results to generate a two-way result. The second shuffle instruction enables each thread in the N / 4 threads to apply a reduction operation to different pairs of two-way results to generate a four-way result. After the last shuffle instruction, the first thread is associated with the per-warp result, while the other threads are associated with meaningless results. The first thread of each warp then executes an atomic version of the reduction operation to aggregate the associated per-warp results to a common memory location.

[0008] Using a shuffle operation to perform the initial data reduction reduces the total number of atomic operations on common memory by a factor of N. For example, if each warp includes 32 threads, the total number of memory operations for a data reduction of 162,944 per-thread results is reduced from 162,944 to 5,092. Therefore, the time required to perform the overall data reduction is reduced compared to some other methods of performing data reduction operations. However, computing each per-warp result typically involves executing at least 15 instructions, storing intermediate results in temporary registers, computing wasted results, and hundreds of cycles. Despite the reduction in the number of memory operations, these inefficiencies can significantly reduce the overall performance of the associated parallel processing algorithm.

[0009] As described above, there is a need in the art for more efficient techniques for applying reduction operations to values ​​associated with different threads included in a warp. Summary of the invention

[0010] One embodiment of the present disclosure describes a computer-implemented method for applying a reduction operation to values ​​associated with different threads included in a thread warp, the method comprising: in response to a single instruction associated with multiple threads executing in a multi-threaded processor, accessing multiple register values ​​stored in multiple source registers, wherein each source register of the multiple source registers is associated with a different thread included in the multiple threads; performing one or more operations on the multiple register values ​​to generate an aggregate value; and storing the aggregate value in a first destination register, which is accessible to at least one thread included in the multiple threads.

[0011] Compared to the prior art, the disclosed technology has at least one of the following technical advantages: Using the disclosed technology can shorten the time required to perform data reduction. Compared to the existing shuffle-based technology, each thread warp-level data reduction is performed in response to a single instruction without using temporary registers and without calculating redundant output values, which can reduce latency by an order of magnitude. In addition, the thread warp reduction unit can perform data reductions that include a variety of different reduction operations, data types, and data sizes. Compared to the prior art, these technical advantages represent one or more technical advances. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to understand the relevant features of the various embodiments described above in more detail, the above briefly summarized inventive concept may be described in more detail by reference to various embodiments (some of which have been illustrated in the accompanying drawings). However, it should be noted that the attached drawings only illustrate typical embodiments of the inventive concept and are therefore not intended to limit the scope in any way, and there are other equally effective embodiments.

[0013] Figure 1 To illustrate a block diagram of a system configured to implement one or more aspects of the present disclosure;

[0014] Figure 2 According to various embodiments Figure 1 A block diagram of a parallel processing unit included in a parallel processing subsystem of FIG.

[0015] Figure 3 According to various embodiments Figure 2 A block diagram of a general processing cluster included in a parallel processing unit of

[0016] Figure 4 According to various embodiments Figure 3 A block diagram of a streaming multiprocessor included in a general processing cluster;

[0017] Figure 5 According to various embodiments Figure 3 A block diagram of a streaming multiprocessor included in a general processing cluster;

[0018] Figure 6 is a conceptual description of a REDUX instruction according to various embodiments, which Figure 4 or Figure 5 The warp reduction unit is configured to apply a reduction operation to values ​​associated with different threads included in the warp.

[0019] Figure 7 According to various embodiments Figure 4 and Figure 5 A more detailed description of the warp reduction unit in .

[0020] Figure 8 is a flow chart of method steps for applying a reduction operation to values ​​associated with different threads included in a warp, according to various embodiments. DETAILED DESCRIPTION

[0021] In the following description, numerous specific details are set forth to provide a more thorough understanding of various embodiments. However, it will be apparent to one skilled in the art that these inventive concepts may be practiced without one or more of these specific details.

[0022] Figure 1 1 is a block diagram of a system 100 configured to implement one or more aspects of the present disclosure. As shown, the system 100 includes, but is not limited to, a central processing unit (CPU) 102, a system memory 104, which is coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. The memory bridge 105 is further coupled to an I / O (input / output) bridge 107 via a communication path 106, and the I / O bridge 107 is coupled to a switch 116.

[0023] In operation, I / O bridge 107 is configured to receive user input information from input device 108 (such as a keyboard or mouse) and forward the input information to CPU 102 for processing via communication path 106 and memory bridge 105. Switch 116 is configured to provide connections between I / O bridge 107 and other components of system 100 (such as network adapter 118 and various add-in cards 120 and 121).

[0024] As also shown, the I / O bridge 107 is coupled to a system disk 114, which can be configured to store content, applications, and data for use by the CPU 102 and the parallel processing subsystem 112. In general, the system disk 114 provides non-volatile storage for applications and data, and can include a fixed or removable hard drive, a flash memory device, and a CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Versatile Disk-ROM), Blu-ray, HD-DVD (High Definition DVD), or other magnetic, optical, or solid-state storage device. Finally, although not explicitly shown, other components (such as a universal serial bus or other port connection, an optical disk drive, a digital versatile disk drive, a film recording device, etc.) can also be connected to the I / O bridge 107.

[0025] In various embodiments, memory bridge 105 may be a north bridge chip, and I / O bridge 107 may be a south bridge chip. In addition, communication paths 106 and 113 and other communication paths within system 100 may be implemented using any technically suitable protocol, including but not limited to AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0026] In some embodiments, parallel processing subsystem 112 includes a graphics subsystem that delivers pixels to display device 110, which may be any conventional cathode ray tube, liquid crystal display, light emitting diode display, etc. In such embodiments, parallel processing subsystem 112 incorporates circuits optimized for graphics and video processing, including, for example, video output circuitry. Figure 2 As described in more detail in , such circuits may be incorporated across one or more parallel processing units (PPUs) included in parallel processing subsystem 112. In other embodiments, parallel processing subsystem 112 incorporates circuits optimized for general purpose and / or computational processing. Likewise, such circuits may be incorporated across one or more PPUs included in parallel processing subsystem 112, which are configured to perform such general purpose and / or computational operations. In other embodiments, one or more PPPs included in parallel processing subsystem 112 may be configured to perform graphics processing, general purpose processing, and computational processing operations. System memory 104 includes at least one device driver 103 that is configured to manage processing operations of one or more PPUs in parallel processing subsystem 112.

[0027] In various embodiments, the parallel processing subsystem 112 may be coupled to Figure 1 The parallel processing subsystem 112 may be integrated with one or more other elements of the CPU 102 to form a single system. For example, the parallel processing subsystem 112 may be integrated with the CPU 102 and other connected circuits on a single chip to form a system on a chip ("SoC").

[0028] It should be understood that the system shown herein is illustrative, and variations and modifications are possible. The connection topology (including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112) can be modified as needed. For example, in some embodiments, system memory 104 can be directly connected to CPU 102, rather than being connected to CPU 102 through memory bridge 105, and other devices will communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 can be connected to I / O bridge 107 or directly to CPU 102, rather than being connected to memory bridge 105. In other embodiments, I / O bridge 107 and memory bridge 105 can be integrated into a single chip, rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 1 One or more of the components shown may not be present. For example, the switch 116 may be eliminated, and the network adapter 118 and add-in cards 120 , 121 may be connected directly to the I / O bridge 107 .

[0029] Figure 2 According to various embodiments Figure 1 1 is a block diagram of a parallel processing unit (PPU) 202 included in the parallel processing subsystem 112 of FIG. Figure 2 One PPU 202 is depicted, as described above, but the parallel processing subsystem 112 may include any number of PPUs 202. As shown, the PPU 202 is coupled to a local parallel processing ("PP") memory 204. The PPU 202 and the PP memory 204 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit ("ASIC") or a memory device, or in any other technically feasible manner.

[0030] In some embodiments, PPU 202 includes a graphics processing unit ("GPU") that can be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data provided by CPU 102 and / or system memory 104. When processing graphics data, PP memory 204 can be used as graphics memory to store one or more conventional frame buffers (and one or more other rendering targets, if desired). Among other things, PP memory 204 can be used to store and update pixel data and transmit the final pixel data or display frame to display device 110 for display. In some embodiments, PPU 202 can also be configured for general processing and computing operations.

[0031] In operation, CPU 102 is the main processor of system 100, controlling and coordinating the operation of other system components. In particular, CPU 102 issues commands that control the operation of PPU 202. In some embodiments, CPU 102 writes a command stream for PPU 202 into a data structure ( Figure 1 or Figure 2 The push buffer is a data structure that is stored in memory (not explicitly shown) and can be located in system memory 104, PP memory 204, or another storage location accessible to both CPU 102 and PPU 202. A pointer to the data structure is written to the push buffer to start processing the command stream in the data structure. PPU 202 reads the command stream from the push buffer and then executes the commands asynchronously with respect to the operation of CPU 102. In embodiments where multiple push buffers are generated, the application can specify an execution priority for each push buffer via device driver 103 to control the scheduling of different push buffers.

[0032] As also shown, the PPU 202 includes an I / O (input / output) unit 205 that communicates with the rest of the system 100 via the communication path 113 and the memory bridge 105. The I / O unit 205 generates packets (or other signals) for transmission on the communication path 113, and also receives all incoming packets (or other signals) from the communication path 113, directing the incoming packets to the corresponding components of the PPU 202. For example, commands related to processing tasks may be directed to the host interface 206, while commands related to memory operations (e.g., reading from or writing to the PP memory 204) may be directed to the crossbar unit 210. The host interface 206 reads each push buffer and sends the command stream stored in the push buffer to the front end 212.

[0033] As above combined Figure 1 As described, the connection of PPU 202 to the rest of system 100 may vary. In some embodiments, parallel processing subsystem 112 (which includes at least one PPU 202) is implemented as an add-in card that can be inserted into an expansion slot of system 100. In other embodiments, PPU 202 may be integrated on a single chip using a bus bridge, such as memory bridge 105 or I / O bridge 107. Likewise, in other embodiments, some or all elements of PPU 202 may be included with CPU 102 in a single integrated circuit or system on chip (SoC).

[0034] In operation, the front end 212 sends processing tasks received from the host interface 206 to a work distribution unit (not shown) within the task / work unit 207. The work distribution unit receives pointers to processing tasks, which are encoded as task metadata ("TMD") and stored in memory. The pointer to the TMD is included in a command stream, which is stored as a push buffer and received by the front end unit 212 from the host interface 206. The processing task that can be encoded as a TMD includes an index associated with the data to be processed, and state parameters and commands that define how to process the data. For example, the state parameters and commands can define the program to be executed on the data. The task / work unit 207 receives tasks from the front end 212 and ensures that the general processing cluster ("GPC") 208 is configured to a valid state before starting the processing task specified by each TMD. A priority can be specified for each TMD, which is used to schedule the execution of the processing task. The processing task can also be received from the processing cluster array 230. Optionally, the TMD may include a parameter that controls whether the TMD is added to the head or tail of a list of processing tasks (or a list of pointers to processing tasks), thereby providing another level of control over execution priority.

[0035] PPU 202 advantageously implements a highly parallel processing architecture based on a processing cluster array 230, which includes a set of C GPCs 208, where C ≥ 1. Each GPC 208 is capable of executing a large number (e.g., hundreds or thousands) of threads simultaneously, where each thread is an instance of a program. In various applications, different GPCs 208 may be assigned to process different types of programs or perform different types of computations. The assignment of GPCs 208 may differ depending on the workload generated by each type of program or computation.

[0036] The memory interface 214 includes a set of D partition units 215, where D ≥ 1. Each partition unit 215 is coupled to one or more dynamic random access memories (DRAMs) 220 residing within the PP memory 204. In one embodiment, the number of partition units 215 is equal to the number of DRAMs 220, and each partition unit 215 is coupled to a different DRAM 220. In other embodiments, the number of partition units 215 may be different from the number of DRAMs 220. It will be appreciated by those skilled in the art that the DRAMs 220 may be replaced with any other technically suitable storage device. In operation, various rendering targets (such as texture maps and frame buffers) may be stored across the DRAMs 220, allowing the partition units 215 to write portions of each rendering target in parallel, thereby efficiently using the available bandwidth of the PP memory 204.

[0037] A given GPC 208 may process data to be written to any DRAM 220 in PP memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or any other GPC 208 for further processing. GPCs 208 communicate with memory interface 214 via crossbar unit 210 to read from or write to individual DRAMs 220. In one embodiment, crossbar unit 210 is connected to I / O unit 205 in addition to connecting to PP memory 204 via memory interface 214, thereby enabling processing cores in different GPCs 208 to communicate with system memory 104 or other memory that is not local to PPU 202. In Figure 2 In an embodiment, the crossbar unit 210 is directly connected to the I / O unit 205. In various embodiments, the crossbar unit 210 can separate the traffic flow between the GPCs 208 and the partition units 215 using virtual channels.

[0038] Likewise, the GPCs 208 may be programmed to perform processing tasks associated with various applications, including, but not limited to, linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying laws of physics to determine the position, velocity, and other properties of an object), image rendering operations (e.g., tessellation shaders, vertex shaders, geometry shaders, and / or pixel / fragment shaders), general-purpose computing operations, etc. In operation, the PPU 202 is configured to transfer data from the system memory 104 and / or the PP memory 204 to one or more on-chip memory units, process the data, and write the resulting data back to the system memory 104 and / or the PP memory 204. The resulting data may then be accessed by other system components (including the CPU 102, another PPU 202 in the parallel processing subsystem 112, or another parallel processing subsystem 112 in the system 100).

[0039] As described above, any number of PPUs 202 may be included in the parallel processing subsystem 112. For example, multiple PPUs 202 may be provided on a single add-in card, or multiple add-in cards may be connected to the communication path 113, or one or more PPUs 202 may be integrated into a bridge chip. The PPUs 202 in a multi-PPU system may be the same or different from each other. For example, different PPUs 202 may have different numbers of processing cores and / or different numbers of PP memories 204. In implementations where there are multiple PPUs 202, these PPUs 202 may operate in parallel to process data at a higher throughput than is possible with a single PPU 202. Systems including one or more PPUs 202 may be implemented in a variety of configurations and form factors, including but not limited to desktops, laptops, handheld personal computers or other handheld devices, servers, workstations, game consoles, embedded systems, and the like.

[0040] Figure 3 According to various embodiments Figure 2 208. In operation, GPC 208 may be configured to execute a large number of threads in parallel to perform graphics, general processing and / or computing operations. As used herein, "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, single instruction, multiple data ("SIMD") instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction, multiple thread ("SIMT") technology is used to support the parallel execution of a large number of generally synchronized threads using a general instruction unit configured to issue instructions to a group of processing engines in GPC 208. Unlike a SIMD execution architecture (where all processing engines generally execute the same instructions), SIMT execution allows different threads to more easily follow different execution paths through a given program. It should be recognized by those of ordinary skill in the art that a SIMD processing architecture represents a functional subset of a SIMT processing architecture.

[0041] The operation of GPC 208 is controlled via pipeline manager 305, which distributes processing tasks received from a work distribution unit (not shown) within task / work unit 207 to one or more streaming multiprocessors (“SMs”) 310. Pipeline manager 305 may also be configured to control work distribution crossbar 330 by specifying the destination of processed data output by SM 310.

[0042] In one embodiment, the GPC 208 includes a set of M SMs 310, where M ≥ 1. In addition, each SM 310 includes a set of functional units (not shown), such as execution units and load-store units. The processing operations specific to any functional unit can be pipelined, so that new instructions can be issued for execution before the previous instructions have completed execution. Any combination of functional units in a given SM 310 can be provided. In various embodiments, the functional units can be configured to support a variety of different operations, including integer and floating-point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit shifts, and calculations of various algebraic functions (e.g., planar interpolation and trigonometric functions, exponential functions and logarithmic functions, etc.). Advantageously, the same functional unit can be configured to perform different operations.

[0043] In operation, each SM 310 is configured to process one or more thread groups. As used herein, a "thread group" or "warp" refers to a group of threads that execute the same program simultaneously on different input data, where a thread in the group is assigned to a different execution unit in the SM 310. A thread group may include fewer threads than the number of execution units in the SM 310, in which case some execution units may be idle during a cycle when the thread group is being processed. A thread group may also include more threads than the number of execution units in the SM 310, in which case processing may occur in consecutive clock cycles. Since each SM 310 can support up to G thread groups simultaneously, up to G*M thread groups may be executed in the GPC 208 at any given time.

[0044] In addition, multiple related thread groups may be active (in different stages of execution) simultaneously in SM 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array." The size of a particular CTA is equal to m*k, where k is the number of threads executing simultaneously in the thread group, which is typically an integer multiple of the number of execution units in SM 310, and m is the number of thread groups active simultaneously within SM 310.

[0045] although Figure 3Not shown, but each SM 310 includes a level one ("L1") cache, or uses space in a corresponding L1 cache external to the SM 310 to support load and store operations, etc., performed by the execution units. Each SM 310 may also access a level two ("L2") cache (not shown) that is shared among all GPCs 208 in the PPU 202. The L2 cache may be used to transfer data between threads. Finally, the SM 310 may also access off-chip "global" memory, which may include PP memory 204 and / or system memory 104. It should be understood that any memory external to the PPU 202 may be used as global memory. In addition, as shown in FIG. Figure 3 As shown, a level 1.5 (“L1.5”) cache 335 may be included in GPC 208 and is configured to receive and store data requested from memory by SM 310 via memory interface 214. Such data may include, but is not limited to, instructions, uniform data, and constant data. In embodiments having multiple SMs 310 within GPC 208, SMs 310 may beneficially share common instructions and data cached in L1.5 cache 335.

[0046] Each GPC 208 may have an associated memory management unit ("MMU") 320 that is configured to map virtual addresses to physical addresses. In various embodiments, the MMU 320 may reside within the GPC 208 or the memory interface 214. The MMU 320 includes a set of page table entries ("PTEs") for mapping virtual addresses to physical addresses of tiles or pages of memory, and optionally to cache line indices. The MMU 320 may include an address translation lookaside buffer (TLB) or cache resident within the SM 310, one or more L1 caches, or the GPC 208.

[0047] In graphics and compute applications, GPC 208 may be configured such that each SM 310 is coupled to a texture unit 315 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data.

[0048] In operation, each SM 310 sends processed tasks to the work distribution crossbar 330 to provide the processed tasks to another GPC 208 for further processing, or to store the processed tasks in an L2 cache (not shown), parallel processing memory 204, or in system memory 104 via the crossbar unit 210. In addition, a pre-raster operation ("preROP") unit 325 is configured to receive data from the SM 310, direct the data to one or more raster operation ("ROP") units in the partition unit 215, perform optimization of color blending, organize pixel color data, and perform address translation.

[0049] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. Among other things, any number of processing units, such as SM 310, texture unit 315, or preROP unit 325, may be included in GPC 208. Figure 2 As described above, the PPU 202 may include any number of GPCs 208 that are configured to be functionally similar to one another so that execution behavior does not depend on which GPC 208 receives a particular processing task. In addition, each GPC 208 operates independently of the other GPCs 208 in the PPU 202 to execute tasks of one or more application programs. In view of the above, it should be understood by those skilled in the art that Figure 1-Figure 3 The architecture described in no way limits the scope of the present disclosure.

[0050] Figure 4 According to various embodiments Figure 3 2 is a block diagram of a streaming multiprocessor (SM) 310 included in a general processing cluster (GPC) 208 of FIG. 1. As shown, SM 310 includes, but is not limited to, sub-partition units 410(1)-410(4), a memory input / output ("MIO") control unit 470, an MIO unit 480, a level 1 (L1) cache 490, and a convergence barrier unit ("CBU") 420. In alternative embodiments, SM 310 may include any number of sub-partition units 410. For purposes of explanation, reference numbers identifying objects and parenthetical numbers identifying instances as needed are used to indicate multiple instances of similar objects.

[0051] The warps assigned to the SM 310 are distributed among the sub-partition units 410. Each sub-partition unit 410 may be assigned any number of warps, however, a given warp is assigned to only one sub-partition unit 410. As shown, each sub-partition unit 410 includes, but is not limited to, an instruction cache 442, a micro-scheduling dispatch unit 440, a core datapath unit 450, and a unified register file 432. The parenthesized number "x" of each of the unified register file 432(x), instruction cache 442(x), micro-scheduling dispatch unit 440(x), and core datapath unit 450(x) indicates the associated sub-partition unit 410(x).

[0052] As combined Figure 3As described, SM 310 receives processing tasks from pipeline manager 305. For each thread warp, assigned sub-partition unit 410 (x) receives the assigned processing tasks and stores the associated instructions in instruction cache 442 (x). Micro-scheduling dispatch unit 440 (x) reads instructions from instruction cache 442 (x). If the given instruction is for a functional unit 454 included in core datapath unit 450 (x), micro-scheduling dispatch unit 440 (x) issues the instruction to functional unit 454 (x). Otherwise, micro-scheduling dispatch unit 440 (x) forwards the instruction to MIO control unit 470.

[0053] The core datapath unit 450(x) includes, but is not limited to, any number of functional units 454 and register files 452(x). Each functional unit 454 included in the core datapath unit 450(x) may perform any number and type of operations to execute threads in the thread warps assigned to the sub-partition unit 410(x). Each functional unit 454 included in the core datapath unit 450(x) has a fixed latency, such as an arithmetic logic unit ("ALU"). Each functional unit 454 included in the core datapath unit 450(x) is connected to the register files 452(x) and the unified register file 432(x) via any number of buses.

[0054] Register file 452(x) is a cache memory that includes, but is not limited to, any number of registers and any number of read and / or write ports. Each register in register file 452(x) is assigned to one of the threads in one of the warps assigned to sub-partition unit 410(x), and is not directly accessible to any other thread. In this manner, each thread in each warp assigned to sub-partition unit 410(x) has exclusive use of a set of registers in register file 452(x). As shown in conjunction with Figure 6 Described in more detail, any number of registers may be organized as vector registers storing N M-bit values. For example, in some embodiments, a vector register may store a different 32-bit value for each thread in a warp of 32 threads. Register file 452(x) may be implemented in any technically feasible manner. In alternative embodiments, registers included in register file 452(x) may be arranged and assigned to threads and / or warps in any technically feasible manner.

[0055] Unified register file 432(x) is a cache memory that includes, but is not limited to, any number of unified registers and any number of read and / or write ports. Each unified register in unified register file 432(x) is accessible by all threads included in a warp. Unified register file 432(x) may be implemented in any technically feasible manner. In alternative embodiments, unified registers included in register file 452(x) may be arranged and assigned to threads and / or warps in any technically feasible manner.

[0056] CBU 420 manages scattered threads, performs synchronization operations, and ensures forward progress for all non-exited threads included in the warp. When only a portion of the threads in the warp participate in an instruction, the threads in the warp are referred to as "scattered" during instruction execution. CBU 420 can be configured to perform any number and type of synchronization operations based on any number and type of synchronization instructions.

[0057] For example, the CBU 420 may be configured to converge a group of threads included in a warp via a "WARPSYNC" instruction. The CBU 420 blocks different threads included in the group of threads under the "WARPSYNC" instruction until all threads included in the group of threads execute the WARPSYNC instruction together. At the exit of the WARPSYNC instruction, the group of threads is converged, and the CBU 420 configures a group of threads to execute the WARPSYNC instruction immediately after the WARPSYNC instruction.

[0058] The MIO unit 480 includes, but is not limited to, any number of functional units 454. The functional units 454 included in the MIO unit 480 perform any number and type of operations to execute threads assigned to the SM 310, regardless of the assigned sub-partition unit 410. Each functional unit 454 included in the MIO unit 480 has variable latency, such as a load / store unit, and / or each functional unit 454 has a lower throughput relative to the functional units 454 in the core datapath units 450(1)-450(4). It should be noted that if a given functional unit 454 is included in the core datapath units 450(1)-450(4), four different instances of the functional unit 454 may be executing on four warps assigned to four sub-partition units 410(1)-410(4) at any given time. Conversely, if a given functional unit 454 is included in the MIO unit 480, one instance of the functional unit 454 may be executing on one warp assigned to the SM 310 at any given time. Each functional unit 454 included in the MIO unit 480 is connected to register files 452 ( 1 )- 452 ( 4 ) and unified register files 432 ( 1 )- 432 ( 4 ) via any number of buses.

[0059] As shown, MIO unit 480 interfaces with register files 452(1)-452(4), unified register files 432(1)-432(4), and L1 cache 490. L1 cache 490 may include any type and amount of on-chip memory arranged in any technically feasible manner. MIO unit 480 and any number of buses enable each functional unit 454 included in SM 310 to access memory locations included in L1 cache 490.

[0060] One limitation of conventional PPUs is that the overall performance of parallel processing algorithms that involve performing data reductions across per-thread results to generate aggregate values ​​can be significantly reduced by inefficiencies associated with sharing data between threads. As previously described, performing atomic operations that aggregate per-thread results to a common memory location accessible to all threads typically requires at least one cycle per thread. The inline atomic addition operations available in some conventional PPUs can reduce the time required to perform data reductions involving addition operations and global memory, but do not reduce the time required to perform other types of data reductions. Some conventional PPUs support shuffle instructions that allow threads in the same warp to exchange data. Using shuffle instructions to generate per-warp results and then aggregating the per-warp results to a common memory location can reduce the total number of atomic operations on the common memory location by a factor of N, where N is the number of threads in the warp. However, computing each per-warp result typically involves executing at least 15 instructions, storing intermediate results in multiple temporary registers, computing meaningless output values, and hundreds of cycles.

[0061] Warp Profile Unit

[0062] To enable more efficient data reduction, one of the functional units 454 included in the MIO unit 480 is a warp reduction unit 460. The REDUX instruction configures the warp reduction unit 460 to apply a reduction operation to the "source" values ​​(in the source vector registers) associated with a group of threads in the warp and store the resulting aggregate value in the destination unified register. Figure 6 Described in more detail, the REDUX instruction specifies the reduction operation, data type / size, destination unified register, and source vector register. In addition, the REDUX instruction is associated with a "guard predicate" that is associated with the MACTIVE register ( Figure 4 REDUX instruction (not shown) together defines a group of threads in the thread warp that participate in the REDUX instruction (ie, participate in the data specification). The group of threads in the thread warp that participate in the REDUX instruction is also referred to as a "participating thread set" in this article.

[0063] SM 310 and / or the compiler may ensure that the set of participating threads is convergent when executing a REDUX instruction in any technically feasible manner. For example, in some embodiments, the compiler replaces a portion of software application code that performs a data reduction on a group of threads in a warp with a WARPSYNC instruction followed by a REDUX instruction. The WARPSYNC instruction may ensure that the set of participating threads is convergent when executing a REDUX instruction.

[0064] For purposes of explanation only, units included in SM 310 that contain an example REDUX instruction for a warp assigned to subpartition 410(1) are depicted in bold. Subpartition unit 410(1) stores the REDUX instruction in instruction cache 442(1). Subsequently, micro-scheduling dispatch unit 440(1) reads the REDUX instruction from instruction cache 442(1) and appends the associated protection predicate to generate a predicated REDUX instruction ( Figure 4 (not shown). Since the warp reduction unit 460 is not included in the core datapath unit 450 ( 1 ), the micro-scheduling dispatch unit 440 ( 1 ) forwards the predicated REDUX instruction to the MIO control unit 470 . The MIO control unit 470 schedules and issues the predicated REDUX instruction to the warp reduction unit 460 .

[0065] When the warp reduction unit 460 receives the predicated REDUX instruction, the warp reduction unit 460 obtains a list of source values. The list of source values ​​includes values ​​associated with the participating thread set stored in the source vector registers. The warp reduction unit 460 may obtain the list of source values ​​in any technically feasible manner. For example, in some embodiments, the warp reduction unit 460 may include any number and type of logic to retrieve source values ​​for the participating thread set from the source vector registers included in the register file 452(1).

[0066] As combined Figure 7 As described in more detail, the warp reduction unit 460 includes, but is not limited to, a floating point subunit and an integer subunit. If the data type / size specifies a floating point data type, the floating point subunit applies a reduction operation to the source values ​​in the source value list to generate a single aggregate value. Otherwise, the integer subunit applies a reduction operation to the source values ​​in the source value list to generate a single aggregate value. The warp reduction unit 460 stores the aggregate value in an output unified register included in the unified register file 432(1).

[0067] It should be noted that the techniques described herein are illustrative, not restrictive, and may be modified without departing from the broader spirit and scope of the present disclosure. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments and techniques. In various embodiments, any number of the techniques disclosed herein may be implemented, while other techniques may be omitted in any technically feasible manner. In general, the techniques outlined herein may be applicable to performing data reductions in hardware across at least two threads in a warp based on a single instruction.

[0068] For example, in an alternative embodiment, the REDUX instruction may specify one or more source memory locations and one or more destination memory locations located in any number and type of memory. The warp reduction unit 460 may obtain source values ​​from the one or more source memory locations and store the aggregate value in the one or more destination memory locations in any technically feasible manner. In some embodiments, the warp reduction unit 460 may broadcast the aggregate value to the participating thread set. To "broadcast" the aggregate value, the warp reduction unit 460 or any other unit in the SM 310 may store the aggregate value in multiple destination registers, where each destination register is associated with a different thread in the participating thread set. In the same embodiment or other embodiments, the warp reduction unit 460 may determine the participating thread set in any technically feasible manner.

[0069] Advantageously, the warp reduction unit 460 performs each warp-level data reduction using a single instruction, without temporary registers, and without computing any wasted results. In various embodiments, the warp-level data reduction can be executed in approximately 25 cycles. The latency is reduced by an order of magnitude relative to data reductions based on existing shuffle techniques. For example, in some embodiments, the estimated latency is 25 cycles. In addition, the estimated throughput is increased relative to data reductions based on existing shuffle techniques and existing inline atomic reductions. In some embodiments, the throughput is one REDUX instruction every two cycles for each SM 310. Another advantage of the disclosed technology is that, unlike existing inline atomic reductions, the warp reduction unit 460 can support a wide variety of data types, data sizes, and reduction operations. For these reasons, using REDUX instructions to perform data reductions can improve the efficiency of many parallel processing algorithms.

[0070] It should be understood that the SM 310 shown herein is illustrative and that variations and modifications are possible. For example, the interconnections between the various components of the SM 310, the number of sub-partition units 410, the number and type of registers, etc., may be modified as needed. In another embodiment, since the warp reduction unit 460 has a fixed latency, the warp reduction unit 460 may be moved from the MIO unit 480 to the core datapath unit 450. In general, moving the functional unit from the MIO unit 480 to the core datapath unit 450 may improve latency and throughput, but requires more area (because the functional unit is replicated in each core datapath unit 450).

[0071] Figure 5 According to various embodiments Figure 3 1 is a block diagram of a streaming multiprocessor 310 included in a general processing cluster of FIG. The functional combination of SM 310, sub-partition units 410(1)-410(4), MIO control unit 470, MIO unit 480, L1 cache 490, CBU 420 and thread warp reduction unit 460 Figure 4 However, the warp reduction unit 460 is included in the core data path unit 450 instead of the MIO unit 480 .

[0072] As shown, warp reduction units 460(1)-460(4) are included in core datapath units 450(1)-450(4), respectively. Thus, SM 310 includes four instances of warp reduction unit 460. Warp reduction unit 460(x) executes REDUX instructions on warps assigned to subpartition 410(x). In an alternative embodiment, SM 310 may include S subpartition units 310, C core datapath units 450, and W warp reduction units 460, where S, C, and W are any positive integers.

[0073] For purposes of explanation only, units included in SM 310 that are included in an example REDUX instruction for a warp assigned to subpartition 410(1) are indicated in bold. Subpartition unit 410(1) stores the REDUX instruction in instruction cache 442(1). Subsequently, micro-scheduling dispatch unit 440(1) reads the REDUX instruction from instruction cache 442(1) and appends the associated protection predicate to generate a predicated REDUX instruction ( Figure 5 (not shown). Since the warp reduction unit 460(1) is included in the core datapath unit 450(1), the micro-scheduling dispatch unit 440(1) schedules and issues the predicated REDUX instruction to the warp reduction unit 460(1). The warp reduction unit 460(1) performs the above combined Figure 4Describes the REDUX directive with predicates.

[0074] The estimated latency is at least reduced by half and the estimated throughput is increased by a factor of 4 relative to an embodiment in which the warp reduction unit 460 is included in the MIO unit 480. In various embodiments, the warp-level data reduction can be performed in approximately 12 cycles, and the estimated throughput is 4 REDUX instructions per two cycles for each SM 310. In an alternative embodiment, each of the N sub-partition units 410 includes an instance of the warp reduction unit 460, and the estimated throughput is increased by a factor of N relative to an embodiment in which the warp reduction unit 460 is included in the MIO unit 480.

[0075] REDUX directive

[0076] Figure 6 is a conceptual illustration of a REDUX instruction 620, which Figure 4 and Figure 5 The thread warp reduction unit 460 is configured to apply a reduction operation to values ​​associated with different threads included in the thread warp. As shown, the REDUX instruction format 610 is "{@{!}Pg}REDUX{.op}{.sz}URd, Ra", where the guard predicate "(@{!}Pg)" 622 is optionally preceded by the REDUX instruction 620. The REDUX instruction 620 includes, but is not limited to, an instruction name of "REDUX" 624, a reduction operation ("op") 626, a data type / size ("sz") 628, a destination unified register ("URd") 632, and a source vector register ("Ra") 634. The predicated REDUX instruction 630 includes, but is not limited to, the guard predicate 622 and the REDUX instruction 620. The REDUX instruction 620 and the optional portions of the predicated REDUX instruction 630 are depicted in dashed boxes.

[0077] Note that for purposes of explanation only, the warp reduction unit 460 is described herein as if the REDUX instruction 620 is also an internal dispatch command. However, those skilled in the art will recognize that, in various embodiments, the internal dispatch command may be derived from the REDUX instruction 620 or the predicated REDUX instruction 630 in any technically feasible manner. Furthermore, the internal dispatch command may configure the warp reduction unit 460 to implement the reduction operations described herein on the set of participating threads in any technically feasible manner.

[0078] The guard predicate 622 is written as "@Pg" or is optionally negated and written as "@!Pg", where Pg specifies a one-bit predicate register (also referred to herein as a "thread register"). If the guard predicate 622 is written as "@Pg", then the guard predicate 622 is the value stored in the predicate register Pg. However, if the guard predicate 622 is written as "@!Pg", then the guard predicate 622 is the negation of the value stored in the predicate register Pg. For a given thread, if the guard predicate 622 is not explicitly specified, then the thread operates as if the guard predicate 622 is 1.

[0079] For each thread in the warp for which a REDUX instruction 620 is issued, if the associated guard predicate 622 is 1 (or omitted) and the thread is active, the thread participates in the execution of the REDUX instruction 620. Otherwise, the thread does not participate in the execution of the REDUX instruction 620. If a register is referred to herein as a "MACTIVE register" ( Figure 7 420) is true, then the thread is active. Otherwise, the thread is inactive. Therefore, the MACTIVE register names the active thread set. The MACTIVE register is one of several hidden machine registers included in CBU 420. In alternative embodiments, protection predicate 622 and the active thread set can be specified in any technically feasible manner. In the same embodiment or other embodiments, the participating thread set (i.e., the thread set participating in the execution of specification instruction 620) can be determined in any technically feasible manner.

[0080] If a given thread participates in a reduce instruction 620, the source value associated with the thread stored in source vector register 634 is included in the source value list ( Figure 6 Alternatively, the source value associated with the thread stored in the source vector register 632 is excluded from the source value list and does not participate in the data reduction.

[0081] The reduce operation 626 specifies the operation that the warp reduce unit 460 applies to the source values ​​in the source value list to calculate the aggregate value ( Figure 6 For example, if the input list includes six source values ​​a, b, c, d, e, and f, the aggregate value produced by the warp reduction unit 460 is "a op b op c op d ope op f". Note that the reduction operation 626 is associative and commutative, and reduces a set of values ​​to a single value.

[0082] As shown, supported values ​​for the reduce operation 626 are bitwise AND (“AND”), bitwise OR (“OR”), bitwise XOR (“XOR”), arithmetic minimum (“MIN”), arithmetic maximum (“MAX”), and arithmetic sum (“SUM”). It should be noted that the warp reduce unit 460 truncates arithmetic sums based on the data type / size 628 (e.g., truncated to 32 bits for a data type / size 628 of a 32-bit unsigned integer). If a given REDUX instruction 620 does not specify a reduce operation 626, the reduce operation 626 defaults to bitwise AND. In alternative embodiments, the warp reduce unit 460 and the REDUX instruction 620 may support any number of reduce operations 626, which may default to any of the supported reduce operations 626.

[0083] The data type / size 628 specifies the data type and data size of each source value in the source value list of the REDUX instruction 620. As shown, the supported values ​​of the data type / size 628 are 32-bit unsigned integers ("U32"), 32-bit signed integers ("S32"), and 32-bit floating points ("F32"). If a given REDUX instruction 620 does not specify a data type / size 628, the data type / size 628 defaults to a 32-bit unsigned integer. In alternative embodiments, the warp reduction unit 460 and the REDUX instruction 620 may support any number of data types / sizes 628, and the data type / size 628 may default to any one of the supported data types / sizes 628.

[0084] The destination unified register 632 specifies the unified register into which the warp reduction unit 460 stores the aggregate value resulting from the data reduction. In alternative embodiments, the destination unified register 632 may be replaced with any type of memory location (e.g., a register). In some embodiments, the destination unified register 632 may be replaced with any number and type of destination memory locations to which the warp reduction unit 460 broadcasts the aggregate value resulting from the data reduction.

[0085] Source vector registers 634 specify vector registers storing source values ​​on which data reductions are performed. In alternative embodiments, source vector registers 634 may be replaced with any number and type of source memory locations specifying source values ​​for data reductions in any technically feasible manner.

[0086] Advantageously, REDUX instructions 620 can be used to speed up many commonly performed operations for a variety of workloads. For example, a REDUX instruction 620 specifying an XOR reduction operation 626 can improve the efficiency of parity calculations used for error checking in areas such as 5G. REDUX instructions 620 for floating point numbers can be used to reduce the time required to perform batch normalization steps in many deep learning algorithms.

[0087] Figure 7 According to various embodiments Figure 4 and Figure 5 A more detailed illustration of the warp reduction unit 460 of FIG. For explanation purposes only, Figure 7 The data specification specified via predicated REDUX instruction 630 for a 32-thread warp assigned to subpartition 410(1) is described. Figure 7 The predicated REDUX instruction 630 is described as "0xFFFF0000 REDUX.OR.U32 UR(2)R(2)", where "0xFFFF0000" is the value that would be produced by extracting the guard predicate 622 into a 32-bit register. In addition, Figure 7 An example value of the MACTIVE register 720 is depicted, which specifies the active thread set as 0xFFFFFFFF, thereby specifying that all threads in the warp associated with the predicated REDUX instruction 630 are active.

[0088] The warp reduction unit 460 includes, but is not limited to, a floating point subunit 760 and an integer subunit 770. The floating point subunit 760 includes, but is not limited to, logic capable of performing any number and type of data reductions including floating point data types / sizes 628 and floating point reduction operations 626 supported by the REDUX instruction 620. For example, in some embodiments, the floating point subunit 760 includes multiple ALU trees and iteration logic to iterate over the trees. In various embodiments, the floating point subunit 760 implements additional bits of precision during accumulation to reduce floating point errors.

[0089] The integer subunit 770 includes, but is not limited to, any number and type of logic capable of performing data reductions including integer data types / sizes 628 and integer reduction operations 626 supported by the REDUX instruction 620. For example, in some embodiments, the integer subunit 770 includes multiple ALU trees and iteration logic to traverse the trees. In alternative embodiments, the warp reduction unit 460 may include one of the floating point subunit 760 and the integer subunit 770, but not both.

[0090] After receiving the predicated REDUX instruction 630, the warp reduction unit 460 obtains the source value list 730 based on the protection predicate 622, the MACTIVE register 720, and the source vector register 634 of R(2). The warp reduction unit 460 may obtain the source value list 730 in any technically feasible manner. For example, in some embodiments, the warp reduction unit 460 includes input logic for obtaining the source value list 730.

[0091] As shown, R(2) is a vector register 710(2), which is one of the V vector registers 710 included in the register file 452(1). Each vector register 710 includes, but is not limited to, 32 32-bit registers, each of which is associated with a different thread in a warp. In vector registers 710(x), each register is designated as R(x, y), where y specifies the associated thread. Vector registers 710(2) include 32 registers R(2,1)-R(2,32).

[0092] Since the “extracted” protection predicate 622 is “0xFFFF0000” and the MACTIVE register 720 specifies that all threads 1-32 in the warp are included in the set of active threads, threads 16-32 participate in the execution of the reduce instruction 620. Therefore, the warp reduce unit 460 obtains the source value list 730, which includes 512 bits stored in 16 registers R(2,16)-R(2,32).

[0093] The data type / size 628 is an unsigned 32-bit integer, and therefore, the integer sub-unit 770 applies the bitwise OR reduction operation 626 across the source value list 730 to generate the aggregate value 790. The size and type of the aggregate value 790 is specified by the data type / size 628. Since the data type / size 628 is an unsigned 32-bit integer, the aggregate value 790 includes 32 bits. The warp reduction unit 460 stores the aggregate value 790 in the destination unified register 632. The warp reduction unit 460 may store the aggregate value 790 in the destination unified register 632 in any technically feasible manner. For example, in some embodiments, the warp reduction unit 460 includes output logic that stores the aggregate value 790 in the destination unified register 632. As shown, the destination unified register 632 is one of any number of unified registers ("UR") included in the unified register file 432(1).

[0094] In alternative embodiments, the REDUX instruction 620 may specify any number and type of source memory locations instead of the source vector register 634, and / or any number and type of destination memory locations instead of the destination unified register 632. If more than one destination memory location is specified, the warp reduction unit 460 broadcasts the aggregate value 790 to each destination memory location.

[0095] Figure 8 is a flowchart of method steps for applying a reduction operation to values ​​associated with different threads included in a warp according to various embodiments. Figure 1-Figure 8 Although the present disclosure describes a system as described above, those skilled in the art will understand that any system configured to implement the method steps in any order falls within the scope of the present disclosure.

[0096] As shown, the method 800 starts at step 802, where the micro-scheduling dispatch unit 440(x) reads the REDUX instruction from the instruction cache 442(x) and appends the protection predicate 622 to the REDUX instruction 620 to generate the predicated REDUX instruction 630. In step 804, the micro-scheduling dispatch unit 440(x) or the MIO control unit 470 issues the predicated REDUX instruction 630 to the warp reduction unit 460.

[0097] In step 806, the warp reduction unit 460 retrieves the source value list 730 from one or more source memory locations based on the predicated REDUX instruction 630 and the MACTIVE register 720. In step 808, the warp reduction unit 460 determines whether the data type / size 628 specifies a floating point data type. In step 808, if the warp reduction unit 460 determines that the data type / size 628 specifies a floating point data type, the method 800 proceeds to step 810. In step 810, the floating point subunit 760 calculates the aggregate value 790 based on the source value list 730 and the reduction operation 626. The method 800 then proceeds directly to step 814. In step 814, the warp reduction unit 460 stores the aggregate value 790 in one or more destination memory locations, and the method 800 terminates.

[0098] However, if, in step 808, the warp reduction unit 460 determines that the data type / size 628 does not specify a floating point data type, the method 800 proceeds directly to step 812. In step 812, the integer subunit 770 calculates the aggregate value 790 based on the source value list 730 and the reduction operation 626. In step 814, the warp reduction unit 460 stores the aggregate value 790 in one or more destination memory locations, and the method 800 terminates.

[0099] In summary, the REDUX instruction configures the warp reduction unit to apply a reduction operation to the values ​​in the source vector registers associated with the participating thread set and store the resulting aggregate value in the destination unified register. The reduction operation, data type / size, source vector register, and destination unified register are specified in the REDUX instruction. The participating thread set is defined based on the protection predicate associated with the REDUX instruction and the MACTIVE register that defines the active thread set in the warp. In some embodiments, the compiler ensures that the participating thread set is active and converged before executing the REDUX instruction. For example, the compiler can insert a WARPSYNC instruction immediately before the REDUX instruction, which specifies the participating thread set. The WARPSYNC instruction will cause each thread in the participating thread set to block until all threads in the participating thread set are under the WARPSYNC instruction.

[0100] In one embodiment, the thread warps assigned to the SM are distributed among a plurality of sub-partition units, each of which includes, but is not limited to, an instruction cache, a thread warp reduction unit, a register file, a unified register file, and a micro-scheduling dispatch unit. Each thread warp reduction unit can access registers and unified registers for the associated thread warp, but cannot access registers and unified registers for other thread warps. When one of the micro-scheduling dispatch units reads a REDUX instruction from an associated instruction cache, the micro-scheduling dispatch unit appends a protection predicate to the REDUX instruction, and then issues the resulting predicated REDUX instruction to the associated thread warp reduction unit.

[0101] In another embodiment, the multiple warp reduction units included in the sub-partition unit are replaced with a single warp reduction unit included in a memory input / output (MIO) unit. The warp reduction unit can access registers and unified registers for all warps assigned to the SM. When one of the micro-scheduling dispatch units reads a REDUX instruction from an associated instruction cache, the micro-scheduling dispatch unit appends an associated protection predicate to the REDUX instruction and then forwards the resulting predicated REDUX instruction to the MIO control unit. The MIO control unit receives the predicated REDUX instruction and issues the predicated REDUX instruction to the warp reduction unit.

[0102] When the warp reduction unit receives a predicated REDUX instruction, the warp reduction unit obtains a list of source values. The list of source values ​​includes source values ​​associated with the participating thread set stored in source vector registers. The warp reduction unit applies a reduction operation to the source values ​​in the list of source values ​​to generate an aggregate value. The warp reduction unit may include logic (e.g., one or more ALU trees, iteration logic, etc.) capable of performing data reduction to obtain any number and type of supported data sizes, data types, and reduction operations. The warp reduction unit then stores the aggregate value in a destination unified register specified by the predicated REDUX instruction.

[0103] At least one technical advantage of the disclosed technology over the prior art is that the warp reduction unit can reduce the latency of warp-level data reductions by an order of magnitude compared to existing shuffle-based techniques. In particular, the warp reduction unit performs each warp-level data reduction in response to a single REDUX instruction, without using temporary registers, and without generating redundant output values. In addition, the warp reduction unit can perform data reductions involving a variety of different reduction operations, data types, and data sizes. For these reasons, performing data reductions using REDUX instructions can improve the efficiency of many parallel processing algorithms. These technical advantages represent one or more technical advances over prior art approaches.

[0104] 1. In some embodiments, a computer-implemented method, the method comprising: in response to a single instruction associated with multiple threads executing in a multi-threaded processor, accessing a plurality of register values ​​stored in a plurality of source registers, wherein each source register of the plurality of source registers is associated with a different thread included in the plurality of threads; performing one or more operations on the plurality of register values ​​to generate an aggregate value; and storing the aggregate value in a first destination register, the first destination register being accessible to at least one thread included in the plurality of threads.

[0105] 2. The method of clause 1, wherein the first destination register comprises a unified register accessible by each thread included in the plurality of threads.

[0106] 3. The method of clause 1 or 2, wherein the first destination register is associated with a first thread included in the plurality of threads, and the method further comprises: storing the aggregate value in a second destination register associated with a second thread included in the plurality of threads.

[0107] 4. The method of any one of clauses 1-3, wherein the plurality of threads are included in a thread group that concurrently executes the same program, and the method further comprises: determining to apply the single instruction to the plurality of threads based on a protection predicate associated with the single instruction.

[0108] 5. The method of any of clauses 1-4, wherein performing one or more operations on the plurality of register values ​​comprises applying a reduction operation specified in the single instruction to the plurality of register values.

[0109] 6. A method as described in any of clauses 1-5, wherein the reduction operation includes one of a bitwise AND operation, a bitwise OR operation, a bitwise XOR operation, an arithmetic minimum operation, an arithmetic maximum operation, and an arithmetic sum operation.

[0110] 7. The method of any of clauses 1-6, wherein each register value included in the plurality of register values ​​comprises a floating point number, an unsigned integer, or a signed integer.

[0111] 8. The method of any of clauses 1-7, wherein the plurality of source registers comprises vector registers.

[0112] 9. The method of any of clauses 1-8, wherein a first data size of the aggregate value matches a second data size of each register value included in the plurality of register values.

[0113] 10. In some embodiments, a thread bundle reduction unit includes: input logic, which, in response to receiving a first instruction associated with multiple threads, accesses multiple register values ​​stored in multiple source registers, wherein each source register of the multiple source registers is associated with a different thread included in the multiple threads; a first reduction subunit, which is coupled to the input logic and performs one or more operations on the multiple register values ​​to generate an aggregate value; and output logic, which is coupled to the first reduction subunit and stores the aggregate value in a first destination register for access by at least one thread included in the multiple threads.

[0114] 11. A thread bundle reduction unit as described in clause 10, wherein the aggregate value includes an integer, and the thread bundle reduction unit further includes: a second reduction subunit, which is coupled to the input logic and the output logic, the second reduction subunit performs one or more operations on multiple floating-point numbers accessed by the input logic in response to a second instruction to generate an aggregate floating-point number, and the output logic stores the aggregate floating-point number in a second destination register.

[0115] 12. The warp specification unit of clause 10 or 11, wherein the first destination register comprises a unified register accessible by each thread included in the plurality of threads.

[0116] 13. The warp reduction unit of any of clauses 10-12, the plurality of threads being included in a thread group that concurrently executes a same program, and wherein the input logic determines to apply the first instruction to the plurality of threads based on a protection predicate associated with the first instruction.

[0117] 14. The warp reduction unit of any of clauses 10-13, wherein performing one or more operations on the plurality of register values ​​comprises applying a reduction operation specified in the first instruction to the plurality of register values.

[0118] 15. The warp specification unit of any of clauses 10-14, wherein the plurality of source registers comprises vector registers.

[0119] 16. In some embodiments, a device comprises: an instruction scheduler that issues a first instruction associated with multiple threads for execution; multiple source registers, wherein each of the multiple source registers stores a register value associated with a different thread included in the multiple threads; a destination register, the destination register being accessible by at least one thread included in the multiple threads; and a thread bundle reduction unit that is coupled to the instruction scheduler, the thread bundle reduction unit: receives the first instruction from the instruction scheduler, in response to receiving the first instruction, accesses multiple register values ​​stored in the multiple source registers, performs one or more operations on the multiple register values ​​to generate a total value, and stores the total value in the destination register for access by at least one thread included in the multiple threads.

[0120] 17. The apparatus of clause 16, wherein the destination register comprises a unified register accessible by each thread included in the plurality of threads.

[0121] 18. The apparatus of clause 16 or 17, wherein the plurality of threads are included in a thread group that concurrently executes a same program, and wherein the warp reduction unit determines to apply the first instruction to the plurality of threads based on a protection predicate associated with the first instruction.

[0122] 19. The apparatus of any of clauses 16-18, wherein performing one or more operations on the plurality of register values ​​comprises applying a reduction operation specified in the first instruction to the plurality of register values.

[0123] 20. The apparatus of any of clauses 16-19, wherein a first source register included in the plurality of source registers is accessible to a first thread included in the plurality of threads and is inaccessible to a second thread included in the plurality of threads.

[0124] Any and all combinations of any claim elements recited in any claim and / or any elements described in this application in any way are within the scope of the present disclosure and protection.

[0125] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0126] Aspects of the present embodiment may be embodied as a system, method or computer program product. Therefore, aspects of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.) or an embodiment of a combination of software and hardware aspects, all of which are collectively referred to as "modules", "systems" or "computers" herein. In addition, any hardware and / or software technology, process, function, component, engine, module or system described in the present disclosure may be implemented as a circuit or a group of circuits. In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media, which contains computer-readable program code.

[0127] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium includes, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples (non-exhaustive) of computer-readable storage media may include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the context of this document, a computer-readable storage medium may be any tangible medium that may include or store a program for use by or in conjunction with an instruction execution system, device, or apparatus.

[0128] Aspects of the present disclosure are described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine. When the instruction is executed by the processor of a computer or other programmable data processing device, it is possible to implement the function / action specified in one or more boxes of the flowchart and / or block diagram. Such processors can be, but are not limited to, general-purpose processors, special-purpose processors, application-specific processors or field programmable gate arrays.

[0129] The flowchart and block diagram in the figure show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, segment or part of the code, and the code includes one or more executable instructions for implementing one or more specified logical functions. It should also be noted that in some alternative embodiments, the functions indicated in the box may not occur in the order indicated in the figure. For example, two boxes displayed in succession can actually be executed roughly at the same time, or these boxes can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented by a system based on special-purpose hardware, which performs a specified function or action or a combination of special-purpose hardware and computer instructions.

[0130] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the appended claims.

Claims

1. A computer-implemented method, the method comprising: receiving a single reduction operation instruction associated with a plurality of threads executing in a multithreaded processor; In response to receiving the single reduce operation instruction, access a plurality of register values ​​stored in a plurality of source registers in a memory, wherein each source register in the plurality of source registers is associated with a different thread included in the plurality of threads; performing a reduction operation specified in the single reduction operation instruction on the plurality of register values ​​to generate an aggregate value associated with the plurality of register values; as well as The aggregate value is stored in a first destination register in the memory, the first destination register being accessible to at least one thread included in the plurality of threads. 2 . The method of claim 1 , wherein the first destination register comprises a unified register that is accessible by each thread included in the plurality of threads.

3. The method of claim 1 , wherein the first destination register is associated with a first thread included in the plurality of threads, the method further comprising: The aggregate value is stored in a second destination register in the memory associated with a second thread included in the plurality of threads.

4. The method of claim 1, wherein the plurality of threads are included in a thread group that simultaneously executes the same program, the method further comprising: Based on a guard predicate associated with the single reduce operation instruction, a determination is made to apply the single reduce operation instruction to the plurality of threads.

5. The method of claim 1, wherein the single reduction operation instruction comprises one of a bitwise AND operation, a bitwise OR operation, a bitwise XOR operation, an arithmetic minimum operation, an arithmetic maximum operation, and an arithmetic OR operation. 6 . The method of claim 1 , wherein each register value included in the plurality of register values ​​comprises a floating point number, an unsigned integer, or a signed integer.

7. The method of claim 1, wherein the plurality of source registers comprises vector registers. 8 . The method of claim 1 , wherein a first data size of the aggregate value matches a second data size of each register value included in the plurality of register values.

9. A thread warp reduction unit included in a multi-threaded processor, comprising: input logic that, in response to receiving a first reduce operation instruction associated with a plurality of threads executing in a multithreaded processor, accesses a plurality of register values ​​stored in a plurality of source registers in a memory, wherein each source register in the plurality of source registers is associated with a different thread included in the plurality of threads; a first reduction subunit, coupled to the input logic, for performing a reduction operation specified in the first reduction operation instruction on the plurality of register values ​​to generate a total value associated with the plurality of register values; and Output logic, coupled to the first reduction subunit, stores the aggregate value in a first destination register in the memory for access by at least one thread included in the plurality of threads.

10. The warp reduction unit of claim 9, wherein the aggregate value comprises an integer, and the warp reduction unit further comprises: A second reduction subunit is coupled to the input logic and the output logic, the second reduction subunit performs one or more operations on a plurality of floating point numbers accessed by the input logic to generate an aggregate floating point number in response to a second instruction, and the output logic stores the aggregate floating point number in a second destination register in the memory.

11. The warp specification unit of claim 9, wherein the first destination register comprises a unified register, the unified register being accessible by each thread included in the plurality of threads.

12. The warp specification unit of claim 9, wherein: The plurality of threads are included in a thread group that executes the same program simultaneously, and The input logic determines to apply the first reduce operation instruction to the plurality of threads based on a guard predicate associated with the first reduce operation instruction.

13. The warp specification unit of claim 9, wherein the plurality of source registers comprise vector registers.

14. An apparatus comprising: an instruction scheduler, the instruction scheduler issuing first reduction operation instructions associated with a plurality of threads for execution; A memory that stores: a plurality of source registers, wherein each source register of the plurality of source registers stores a register value associated with a different thread included in the plurality of threads, and a destination register, the destination register being accessible by at least one thread included in the plurality of threads; as well as A thread warp reduction unit, coupled to the instruction scheduler, wherein: receiving the first reduction operation instruction from the instruction scheduler, In response to receiving the first reduction operation instruction, accessing a plurality of register values ​​stored in the plurality of source registers, performing a reduction operation specified in the first reduction operation instruction on the plurality of register values ​​to generate an aggregate value associated with the plurality of register values, and The aggregate value is stored in the destination register for access by the at least one thread included in the plurality of threads. 15 . The apparatus of claim 14 , wherein the destination register comprises a unified register accessible by each thread included in the plurality of threads.

16. The apparatus of claim 14, wherein: The plurality of threads are included in a thread group that executes the same program simultaneously, and The warp reduction unit determines to apply the first reduce operation instruction to the plurality of threads based on a protection predicate associated with the first reduce operation instruction. 17 . The apparatus of claim 14 , wherein a first source register included in the plurality of source registers is accessible to a first thread included in the plurality of threads and is inaccessible to a second thread included in the plurality of threads.

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