Encapsulated integrated circuit memory device and method of operation thereof

Abstract

A memory device and a memory package are provided. The memory device includes: a pad area having a flag pad separate from an external host and a signal pad connected to the external host. A memory bank area is configured to have a plurality of memory cells therein. An on-chip termination (ODT) setting circuit is provided, configured to receive a control command and an ODT enable signal, the control command including first data corresponding to a termination resistor requested by the host. The setting circuit is configured to generate second data corresponding to the ODT resistor. An ODT enable circuit is provided, configured to output an ODT flag signal to the flag pad in response to the control command and the ODT enable signal. A resistor circuit is provided, configured to connect the ODT resistor to the signal pad using the second data.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0086350, filed on July 17, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to packaged integrated circuit devices, and more specifically, to packaged multi-channel memory devices and methods of operation thereof. Background Technology

[0004] Memory devices can store and output data and can be applied in various fields. To improve integration, memory packages comprising multiple memory devices can be mounted on electronic devices, and various operating methods can be employed to simultaneously drive two or more memory devices within the memory package, thereby improving operating speed and / or power consumption. To prevent performance degradation of memory devices under high-speed operation, it is necessary to minimize signal distortion and ensure signal integrity. Summary of the Invention

[0005] One aspect of the present invention provides a memory device and a memory package for setting an on-chip termination (ODT) resistor to minimize distortion of signals transmitted / received between the memory device, host, memory controller, etc.

[0006] According to one aspect of the present invention, a memory device includes a pad area having a flag pad separate from an external host and a signal pad connected to the external host. A memory bank area is configured to have a plurality of memory cells therein. An on-chip termination (ODT) setting circuit is provided, configured to receive a control command and an ODT enable signal, the control command including first data corresponding to a termination resistor requested by the external host, and the ODT setting circuit is further configured to generate second data corresponding to the ODT resistor. An ODT enable circuit is provided, configured to output an ODT flag signal to the flag pad in response to the control command and the ODT enable signal. A resistor circuit is provided, configured to connect the ODT resistor to the signal pad using the second data.

[0007] According to one aspect of the present invention, a memory package includes a package substrate having a plurality of pads. A first memory device is mounted on the package substrate. The first memory device includes a first on-chip termination (ODT) resistor and a first ODT circuitry for determining the value of the first ODT resistor. In response to an ODT request from a host, the first ODT circuitry sets the first ODT resistor to a first resistance value and outputs an ODT flag signal. A second memory device is mounted on the package substrate and includes a second ODT resistor and a second ODT circuitry for determining the value of the second ODT resistor. Specifically, when receiving the ODT flag signal from the first memory device, the second ODT circuitry is configured to set the second ODT resistor to a second resistance value.

[0008] According to one aspect of the present invention, a memory device includes a resistor circuit providing an on-chip termination (ODT) resistor connected to a pad for receiving signals from an external host. An ODT setting circuit is provided, configured to control the resistor circuit such that the ODT resistor has a value greater than the termination resistor when the termination resistor included in an ODT request received from the host is lower than a predetermined reference resistor. An ODT enabling circuit is provided, configured to output an ODT flag signal when the termination resistor is lower than the reference resistor. When an ODT request is received along with at least one of a command / address signal and a clock signal, the ODT enabling circuit is configured to output the ODT flag signal to a first number of other memory devices, and when an ODT request is received along with at least one of a data signal and a data strobe signal, the ODT enabling circuit is configured to output the ODT flag signal to a second number of other memory devices. The second number may be less than the first number.

[0009] According to another embodiment of the invention, a packaged integrated circuit device is provided, comprising a plurality of integrated circuits having respective on-chip termination (ODT) circuits therein. The ODT circuits have respective inputs, which (i) are commonly connected to terminals of the packaged integrated circuit device, and (ii) commonly provide a parallel array of resistors with adjustable pure resistance between the terminals and a reference potential. Furthermore, in response to a first ODT request issued by a host outside the packaged integrated circuit device, the first of the plurality of integrated circuits sends a flag signal to the other integrated circuits. Adjustment of the pure resistance is responsive to (e.g., synchronized with) the transmission of the flag signal. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a schematic diagram illustrating a memory package according to an embodiment of the concept of the present invention.

[0012] Figure 2 This is a diagram schematically illustrating a memory device according to an embodiment of the concept of the present invention.

[0013] Figure 3 and Figure 4 This is a diagram schematically illustrating a memory device according to an embodiment of the concept of the present invention.

[0014] Figure 5 This is a diagram schematically illustrating a memory device according to an embodiment of the concept of the present invention.

[0015] Figures 6 to 8 This is a diagram illustrating the operation of a memory package according to an embodiment of the present invention.

[0016] Figure 9 This is a diagram illustrating the operation of a memory device according to an embodiment of the present invention.

[0017] Figure 10 This is a timing diagram illustrating the operation of setting the terminating resistor in a memory device according to an embodiment of the present invention.

[0018] Figures 11 to 13 This is a diagram illustrating an ODT circuit included in a memory device according to an embodiment of the present invention.

[0019] Figure 14 This is a diagram illustrating the operation of a memory package according to an embodiment of the present invention.

[0020] Figures 15 to 17 This is a diagram illustrating an ODT circuit included in a memory device according to an embodiment of the present invention.

[0021] Figure 18 and Figure 19 This is a diagram illustrating the operation of a memory package according to an embodiment of the present invention.

[0022] Figure 20 This is a block diagram schematically illustrating an electronic device including a memory device according to an embodiment of the present invention. Detailed Implementation

[0023] In the following description, preferred embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram illustrating a memory package according to an embodiment of the present invention. (Refer to...) Figure 1According to an embodiment of the present invention, the memory package 10 may include a plurality of memory devices 20 (i.e., 21 to 24) and a package substrate 30 on which the plurality of memory devices 20 may be mounted. For example, the plurality of memory devices 20 may be mounted on the upper surface of the package substrate 30, and a plurality of bumps (e.g., solder balls) 31 for transmitting and receiving signals and power may be formed on the lower surface of the package substrate 30.

[0025] In this embodiment, each of the plurality of memory devices 20 may be a dynamic random access memory (DRAM) device. At least a portion of the plurality of memory devices 20 may be stacked on top of each other on a package substrate 30. Figure 1 In the illustrated embodiment, the first memory device 21 and the second memory device 22 can be stacked on top of each other as a first pair of DRAM chips, and the third memory device 23 and the fourth memory device 24 can be stacked on top of each other as a second pair of DRAM chips. The number of the plurality of memory devices 20 included in the memory package 10, their arrangement on the package substrate 30, their mounting form, etc., can be modified in various ways according to the embodiments.

[0026] At least a portion of the multiple memory devices 20 may share pads for transmitting and / or receiving signals and / or power. (Refer to...) Figure 1 The pads 41 and 42 formed in the first memory device 21 and the second memory device 22, respectively, can be electrically connected to the substrate pad 32. The third memory device 23 and the fourth memory device 24 can be connected to the package substrate 30 in a similar manner to the first memory device 21 and the second memory device 22.

[0027] exist Figure 1 In the illustrated embodiment, when a data signal and a data strobe signal are input to at least one of the first memory device 21 and the second memory device 22, or when a data signal and a data strobe signal are output from at least one of the first memory device 21 and the second memory device 22, the host can simultaneously drive the first memory device 21 and the second memory device 22. When a data signal and a data strobe signal are input to at least one of the third memory device 23 and the fourth memory device 24, and when a data signal and a data strobe signal are output from at least one of the third memory device 23 and the fourth memory device 24, the host can simultaneously drive the third memory device 23 and the fourth memory device 24. When inputting / outputting command / address signals, clock signals, etc., the host can simultaneously drive the first memory device to the fourth memory device 20. Depending on the capacity, channel configuration, etc., of the memory package 10, the memory package 10 can be operated in a manner different from the above.

[0028] For example, when the host sends an on-die-termination (ODT) request to the first memory device 21 to input a command / address signal to the memory device 20, only the ODT resistor of the first memory device 21 can be connected to the pads to which the command / address signal is input. Since the host simultaneously drives the memory device 20, this signal can be reflected in the second to fourth memory devices 24, which do not connect their ODT resistors to the pads to which the command / address signal is input. As described above, the reflection of the signal occurring in memory devices not connected to the pads to which the input signal is input via ODT resistors reduces the signal's eye margin and degrades signal integrity.

[0029] In embodiments of the present invention, when two or more memory devices are driven simultaneously by a host, the remaining memory devices, other than the one receiving an ODT request from the host, can also connect ODT resistors to the pads to which they input signals. Therefore, signal eye diagram tolerance and signal integrity can be improved by minimizing signal reflections occurring in memory devices that have not yet directly received an ODT request from the host. For example, considering the type of signal input from the host, the operating frequency, and the value of the terminating resistor included in the ODT request, the memory device that has received an ODT request from the host can determine whether to request connecting an ODT resistor to the remaining memory devices being driven simultaneously.

[0030] Figure 2 This is a schematic diagram illustrating a memory device according to an embodiment of the concept of the present invention. (Refer to...) Figure 2 The memory device 50 according to an embodiment of the present invention may include a plurality of memory banks 60 and logic circuitry 70. Each of the plurality of memory banks 60 may include a memory bank array 61 having a plurality of memory cells, a row decoder 62, a column decoder 63, a sense amplifier (SA) 64, etc. In embodiments, a portion of the plurality of memory banks 60 may be grouped into a single group.

[0031] Multiple memory banks 60 included in memory device 50 may share logic circuitry 70. Logic circuitry 70 may specify addresses for reading data from memory bank array 61 or storing data in memory bank array 61, or it may determine the operating mode of memory device 50. Logic circuitry 70 may include input / output pads for sending data to be stored in the multiple memory banks 60 and outputting data from the multiple memory banks 60. In this example, logic circuitry 70 may control the multiple memory banks 60 in response to control commands received from an external host or the like.

[0032] In embodiments of the present invention, logic circuit 70 may include an ODT circuit capable of setting the ODT resistor connected to the pad. The operation of the ODT circuit may vary depending on whether memory device 50 receives an ODT request from the host. In an example, when memory device 50 receives an ODT request from the host, the ODT circuit may use a control command included in the ODT request to set the ODT resistor of memory device 50 to a predetermined resistance value. Alternatively, when memory device 50 receives an ODT request from the host, the ODT circuit may output an ODT flag signal in response to a control command received from the host and an ODT enable signal, which is used to activate the ODT resistors of other memory devices being driven simultaneously.

[0033] When memory device 50 does not receive an ODT request from the host, the ODT circuitry can activate the ODT resistor based on whether an ODT flag signal is sent from another memory device. When an ODT flag signal is sent from another memory device that drives with the host, the ODT circuitry of memory device 50 can connect the ODT resistor to the pad for communication with the host, regardless of whether memory device 50 has received an ODT request from the host. Therefore, since memory device 50 does not connect the ODT resistor to the pad for communication with the host, signal reflections can be minimized, and signal integrity, including eye diagram tolerance, can be improved.

[0034] Figure 3 and Figure 4 This is a diagram schematically illustrating a memory device according to an embodiment of the concept of the present invention. Figure 3 This is a simplified block diagram illustrating the internal structure of a memory device 100 according to an embodiment of the present invention. For example, in Figure 3 In the embodiment shown, the memory device 100 can be connected to... Figure 2 The embodiment shown corresponds to one of the plurality of memory banks 60 included in the memory device 50.

[0035] Reference Figure 3 The memory device 100 according to an embodiment of the present invention may include a memory bank array 110, a controller 120, etc. In an embodiment, the controller 120 may be a concept including control logic 121, row driver 122, and column driver 123, and the memory bank array 110 may include a plurality of memory cells MC.

[0036] In this embodiment, row driver 122 can be connected to memory cell MC via word lines WL, and column driver 123 can be connected to memory cell MC via bit lines BL. Row driver 122 can selectively write data to or read data from memory cell MC, and column driver 123 may include read / write circuitry for writing data to or reading data from memory cell MC. The operation of row driver 122 and column driver 123 can be controlled by control logic 121.

[0037] Next, refer to Figure 4 The memory array 110 according to an embodiment of the present invention may include a plurality of memory cells MC. The memory cells MC may be disposed in adjacent regions intersecting with a plurality of word lines WL and a plurality of bit lines BL. For example, each of the memory cells MC may be connected to one of the plurality of word lines WL and one of the plurality of bit lines BL.

[0038] Each of the memory cells MC may include a switching element SW and a storage capacitor CC. In an embodiment, the switching element SW may include a transistor, the gate terminal of which may be connected to the word line WL, and the source / drain terminals of which may be connected to the bit line BL and the storage capacitor CC, respectively.

[0039] The memory device can write or erase data via multiple word lines WL and multiple bit lines BL by charging the storage capacitor CC in each of the plurality of memory cells MC or by discharging the charge in the storage capacitor CC. Additionally, the memory device can read data from each of the plurality of memory cells MC by reading the voltage of the storage capacitor CC, etc. In an embodiment, the memory device can periodically perform refresh operations to rewrite data into the plurality of memory cells MC, ensuring that the charge in the storage capacitor CC is not over-discharged and that no data is lost.

[0040] Figure 5 This is a schematic diagram illustrating a memory device according to an embodiment of the concept of the present invention. (Refer to...) Figure 5 According to an embodiment of the present invention, the memory device 200 may include a pad area 210, a logic area 220, and a memory bank area 230. The memory bank area 230 may include a plurality of memory banks, each of which may include memory cells connected to word lines and bit lines.

[0041] Logic area 220 may include circuitry for controlling memory cells and ODT circuitry 221. In an embodiment, ODT circuitry 221 may be connected to signal pads 211 and flag pads 212 included in pad area 210. Signal pads 211 may be one of pads for sending signals to and receiving signals from an external host. In an embodiment, memory device 200 may send at least one of command / address signals, clock signals, data signals, and data strobe signals to a host via signal pads 211, and receive at least one of command / address signals, clock signals, data signals, and data strobe signals from the host.

[0042] The flag pad 212 may be a pad used by the ODT circuit 221 to communicate with ODT circuitry included in other memory devices. For example, the flag pad 212 may be connected to the flag pads of other memory devices included in a memory package besides memory device 200, and may not be connected to the host. For example, the ODT circuit 221 may output an ODT flag signal to the ODT circuitry included in other memory devices via the flag pad 212, or may receive an ODT flag signal from the ODT circuitry included in other memory devices.

[0043] The operation of the ODT circuit 221 can be determined based on whether the memory device 200 receives an ODT request from the host. In an embodiment, the ODT request received by the memory device 200 from the host may include control commands and ODT enable signals, etc., wherein the control commands include first data corresponding to the terminating resistor requested by the host. When the memory device 200 receives an ODT request, the ODT circuit 221 may connect the ODT resistor to the signal pad 211.

[0044] The ODT resistor may be the same as or different from the terminating resistor requested by the host. In the example, when the ODT circuit 221 outputs the ODT flag signal to the flag pad 212, the ODT resistor may be different from the terminating resistor requested by the host. In an embodiment, the ODT circuit 221 may output the ODT flag signal when the terminating resistor requested by the host is lower than a predetermined reference resistor. When the ODT circuit 221 does not output the ODT flag signal to the flag pad 212, the ODT resistor may be equal to the terminating resistor requested by the host. In an embodiment, the ODT circuit 221 may not output the ODT flag signal when the terminating resistor requested by the host is equal to or higher than the predetermined reference resistor.

[0045] When memory device 200 does not receive an ODT request, ODT circuit 221 can determine whether to send an ODT flag signal from another memory device via flag pad 212. When no ODT flag signal is sent, ODT circuit 221 may not connect an ODT resistor to signal pad 211. When an ODT flag signal is sent, ODT circuit 221 may connect an ODT resistor set to a previously stored resistance value to signal pad 211. For example, the ODT resistor set to a previously stored resistance value may be higher than the terminating resistance included in an ODT request received by another memory device from the host.

[0046] Figures 6 to 8 This is a diagram illustrating the operation of a memory package according to an embodiment of the present invention. (Refer to...) Figure 6 The memory package 300 according to an embodiment of the present invention may include a plurality of memory devices 310 to 340. The memory package 300 can be operated by control commands sent by the host 400, which may include command / address signals, data signals, data strobe signals, etc. The number of memory devices 310 to 340 included in the memory package 300 may be varied according to embodiments.

[0047] Memory devices 310 to 340 may have the same architecture. For example, the first memory device 310 may include a first ODT circuit 311 and a second ODT circuit 312. The first ODT circuit 311 may be connected to a first pad 301 of the memory package 300, and the second ODT circuit 312 may be connected to a second pad 302 of the memory package 300. For example, the first pad 301 and the second pad 302 may be pads for inputting and outputting signals that are different from each other.

[0048] Additionally, the first pad 301 can be shared by the first memory device 310 through the fourth memory device 340. (See reference...) Figure 6 The first ODT circuits 311, 321, 331, and 341 of the first memory device 310 to the fourth memory device 340 can be collectively connected to the first pad 301. In an embodiment, the first pad 301 can be a pad for inputting / outputting command / address signals, clock signals, etc.

[0049] The second pad 302 can be shared by the first memory device 310 and the second memory device 320. (See reference...) Figure 6The second ODT circuits 312 and 322 of the first memory device 310 and the second memory device 320 can be connected to the second pad 302. Additionally, the second ODT circuits 332 and 342 of the third memory device 330 and the fourth memory device 340 can be jointly connected to the third pad 303. In this embodiment, the second pad 302 and the third pad 303 can be pads for inputting / outputting signals different from the signal of the first pad 301. For example, data signals, data strobe signals, etc., can be input / output through the second pad 302 and the third pad 303. The first pads 301 to the third pads 303 of the memory package 300 can be connected to the first pads 401 to the third pads 403 of the host 400.

[0050] The host 400 can select one of the memory devices 310 to 340 and output a command / address signal to the first pad 401. The command / address signal can be input to the first pad 301 of the memory package 300, and the memory devices 310 to 340 connected to the first pad 301 can be connected as the load of the command / address signal.

[0051] Reference Figure 7 In normal operation of the memory package 300, only the memory devices 310 to 340 that receive an ODT request from the host 400 can activate the ODT resistor and connect it to the first pad 301. For example, when the host 400 sends an ODT request to the first memory device 310, only the first ODT circuit 311 of the first memory device 310 can connect the ODT resistor to the first pad 301. The first ODT circuits 321, 331, and 341 of the second to fourth memory devices 320 may not be activated and may not connect the ODT resistor to the first pad 301. Therefore, signal integrity is degraded because signal reflection occurs in the second to fourth memory devices 320 to 340, and the command / address signals sent from the host 400 are distorted.

[0052] Therefore, to address these potential signal distortion problems, embodiments of the present invention operate such that when the host 400 sends an ODT request to the first memory device 310, the first ODT circuit 311 of the first memory device 310 can also activate the first ODT circuits 321, 331, and 341 of the second memory device 320 to the fourth memory device 340. For example, the first ODT circuit 311 can operate as a master device for the remaining first "slave" ODT circuits 321, 331, and 341.

[0053] Reference Figure 8The first ODT circuit 311 of the first memory device 310, which receives an ODT request from the host 400, can determine whether to activate the slave ODT circuits 321, 331, and 341 in the second to fourth memory devices 340 that are driven together with the first memory device 310, by referring to the operating frequency of the memory package 300, etc. For example, when the operating frequency of the memory package 300 is higher than a predetermined reference frequency, the first ODT circuit 311 of the first memory device 310 can activate the slave ODT circuits 321, 331, and 341 of the second to fourth memory devices 340.

[0054] exist Figure 8 In the illustrated embodiment, the first ODT circuit 311 of the first memory device 310, which receives an ODT request from the host 400, can generate an ODT flag signal and send the ODT flag signal to the slave ODT circuits 321, 331, and 341 of the second memory device 320 to the fourth memory device 340. The slave ODT circuits 321, 331, and 341 of the second memory device 320 to the fourth memory device 340 can connect an ODT resistor to the first pad 301 in response to the ODT flag signal, and can set the ODT resistor to a predetermined resistance value.

[0055] For example, the ODT circuits 321, 331, and 341 of the second memory devices 320 to the fourth memory devices 340 can set the ODT resistor connected to the first pad 301 to a previously stored value. The ODT resistor connected to the first pad 301 via the first ODT circuit 311 can be set to a value such that the entire combined resistance of the ODT resistors connected to the first pad 301 via the first ODT circuits 311 to 341 can be consistent with the desired terminating resistance included in the ODT request from the host 400.

[0056] For example, when the termination resistor requested by host 400 is set to 40 ohms, and the slave ODT circuits 321, 331 and 341 of the second memory device 320 to the fourth memory device 340 are set to have an ODT resistor of 240 ohms, the first ODT circuit 311 of the first memory device 310 can set its ODT resistor to 80 ohms (because 80║240║240║240=80║240║120=80║80=40 ohms). Alternatively, when the terminating resistor requested by the host 400 is 60 ohms, and the slave ODT circuits 321, 331, and 341 of the second memory device 320 to the fourth memory device 340 are set to have an ODT resistor of 240 ohms, the first ODT circuit 311 of the first memory device 310 can set the ODT resistor to have 240 ohms (because 240║240║240║240=120║120=60 ohms).

[0057] Figure 9 This is a diagram illustrating the operation of a memory device according to an embodiment of the present invention. Figure 9 This is a diagram illustrating an ODT circuit 500 included in a memory device according to an embodiment of the present invention. For example, the ODT circuit 500 may be included in a logic area of ​​the memory device. (Refer to...) Figure 9 The ODT circuit 500 may include an ODT setting circuit 510, an ODT enabling circuit 520, a resistor circuit 530, etc. The ODT circuit 500 may also include a transmitter Tx and a receiver Rx sharing a flag pad 540, and the transmitter Tx and receiver Rx may not be activated simultaneously.

[0058] The transmitter Tx can be activated to enable the memory device including the ODT circuit 500 to receive an ODT request from the host. In this example, the transmitter Tx can be turned on via the ODT enable signal (EN) included in the ODT request. When the memory device including the ODT circuit 500 does not receive an ODT request from the host, the receiver Rx can be activated. The receiver Rx can be turned on via the inverted ODT enable signal (ENB). The operation of the memory device including the ODT circuit 500 when receiving an ODT request from the host will be described below.

[0059] When a memory device including ODT circuit 500 receives an ODT request, the ODT enable signal (EN) can turn on the transmitter Tx and turn off the receiver Rx. ODT circuit 500 can receive first data 551 transmitted along with the ODT request. First data 551 can be included in the mode register MR command and can be transmitted. For example, first data 551 can be generated by a memory controller (such as an application processor, central processing unit, system-on-a-chip, etc.) included in the host and can be input to ODT circuit 500. First data 551 can correspond to the terminating resistor "data" requested by the host.

[0060] The terminating resistor "data" included in the first data 551 can be determined by the host and can vary according to the operating frequency of the memory device. For example, when the operating frequency of the memory device is higher than a predetermined reference frequency, the terminating resistor can be lower than a predetermined reference resistor. When the operating frequency is equal to or lower than the reference frequency, the terminating resistor can be equal to or higher than the reference resistor. For example, when the operating frequency is relatively high, the host can request a relatively low terminating resistor in the memory device. When the operating frequency is relatively low, the host can request a relatively high terminating resistor in the memory device.

[0061] In the example, the ODT setting circuit 510 can generate second data 552 by comparing the terminating resistor included in the first data 551 with a predetermined reference resistor. The second data 552 may include data corresponding to the ODT resistor provided by the resistor circuit 530. In an embodiment, when the terminating resistor included in the first data 551 is lower than the reference resistor, the ODT setting circuit 510 can generate second data 552 corresponding to an ODT resistor different from that terminating resistor, and can send the second data 552 to the resistor circuit 530. When the terminating resistor included in the first data 551 is equal to or higher than the reference resistor, the ODT setting circuit 510 can generate second data 552 corresponding to an ODT resistor (such as a terminating resistor), and can send the second data 552 to the resistor circuit 530. For example, when the terminating resistor included in the first data 551 is equal to or higher than the reference resistor, the first data 551 and the second data 552 may be the same. The resistor circuit 530 can refer to the second data 552 to determine the ODT resistor, which may be connected to pads for sending signals to and receiving signals from the host.

[0062] When the terminating resistor included in the first data 551 is lower than the reference resistor, the ODT enable circuit 520 can output an ODT flag signal (FLAG) 553 via transmitter Tx. The ODT flag signal 553 can be a one-bit flag signal and can be sent to the ODT circuitry of other memory devices that have not yet received an ODT request from the host via flag pad 540. These other memory devices can be memory devices that can be driven by the host along with the memory device including the ODT circuitry 500.

[0063] Next, the operation of the memory device including the ODT circuit 500 when it does not receive an ODT request from the host will be described. When the memory device including the ODT circuit 500 does not receive an ODT request from the host, the first data 551 may not be input to the ODT circuit 500, and the ODT enable circuit 520 may not operate.

[0064] Additionally, the inverted ODT enable signal (ENB) can turn on the receiver Rx and turn off the transmitter Tx. When the receiver Rx receives the ODT flag signal 553 from another memory device via the flag pad 540, the ODT setting circuit 510 can generate second data 552 and send the second data 552 to the resistor circuit 530. The second data 552 may include data corresponding to previously stored ODT resistors.

[0065] Figure 10 This is a timing diagram illustrating the operation of setting the terminating resistor in a memory device according to an embodiment of the present invention. Figure 10 This is a circuit illustrating an embodiment of a resistor circuit 600 included in an ODT circuit. (Refer to...) Figure 10 The resistor circuit 600 according to an embodiment of the present invention may include a plurality of pull-up transistors PU1 to PUN, a plurality of pull-up resistors R11 to RN1, a plurality of pull-down transistors PD1 to PDN, and a plurality of pull-down resistors R12 to RN2. The output terminals of the resistor circuit 600 may be connected to a signal pad 610. For example, the signal pad 610 may be a pad for sending signals to and receiving signals from a host computer.

[0066] Multiple pull-up transistors PU1 to PUN can be turned on or off individually via pull-up control signals CU1 to CUN. Similarly, multiple pull-down transistors PD1 to PDN can be turned on or off individually via pull-down control signals CD1 to CDN. The resistance of resistor circuit 600 can be determined by controlling the on / off state of the multiple pull-up transistors PU1 to PUN and the multiple pull-down transistors PD1 to PDN.

[0067] The pull-up control signals CU1 to CUN and pull-down control signals CD1 to CDN used to determine the on / off switching of multiple pull-up transistors PU1 to PUN and multiple pull-down transistors PD1 to PDN can be determined by the ODT setting circuit included in the ODT circuit together with the resistor circuit 600. For example, the ODT setting circuit can determine the pull-up control signals CU1 to CUN and pull-down control signals CD1 to CDN based on first data received from the host, ODT flag signals received from other memory devices, etc., and can control the magnitude of the ODT resistance provided by the resistor circuit 600.

[0068] Figures 11 to 13 This is a diagram illustrating an ODT circuit included in a memory device according to an embodiment of the present invention. (Refer to...) Figures 11 to 13 The ODT circuit 700 of the memory device according to an embodiment of the present invention may include an ODT setting circuit 710, an ODT enabling circuit 720, a resistor circuit 730, etc. The ODT setting circuit 710 may include a default circuit 711, a master circuit 712, a slave circuit 713, and a common circuit 714 connected to the output terminals of circuits 711 to 713. The common circuit 714 may include a buffer, multiple logic gates, etc.

[0069] When the memory device including the ODT circuit 700 receives an ODT request from the host, and when the terminating resistor corresponding to the first data 751 received along with the ODT request is equal to or higher than a predetermined reference resistor, the default circuit 711 can be activated. When the default circuit 711 is activated, the ODT setting circuit 710 can output the first data 751 as the second data 752 as is. Therefore, the ODT resistance provided by the resistor circuit 730 can be equal to the terminating resistor requested by the host.

[0070] When the memory device including the ODT circuit 700 receives an ODT request from the host and when the terminating resistor corresponding to the first data 751 received along with the ODT request is equal to or lower than a predetermined reference resistor, the main circuit 712 can be activated. When the main circuit 712 is activated, the ODT setting circuit 710 can generate second data 752 corresponding to an ODT resistor different from the terminating resistor, and output the second data 752. In the example, the ODT resistor output by the main circuit 712 corresponding to the second data 752 can be higher than the terminating resistor requested by the host.

[0071] When the memory device including the ODT circuit 700 receives an ODT request from the host and when the termination resistor corresponding to the first data 751 is lower than the reference resistor, the ODT enable circuit 720 can be activated. The ODT enable circuit 720 can output an ODT flag signal 753 via a transmitter Tx that is turned on by the ODT enable signal (EN). The ODT flag signal 753 can be output to the flag pad 740.

[0072] When the memory device including the ODT circuit 700 does not receive an ODT request from the host, the slave circuit 713 can be activated. For example, when the memory device including the ODT circuit 700 does not receive an ODT request from the host, the inverted ODT enable signal (ENB) can turn on the receiver Rx. When the receiver Rx receives the ODT flag signal 753 from another memory device via the flag pad 740, the ODT flag signal 753 can be input to the slave circuit 713.

[0073] The slave circuit 713, which receives the ODT flag signal 753, can output second data 752, enabling the resistor circuit 730 to provide an ODT resistance of a predetermined size. In this example, regardless of the terminating resistor requested by the master, the ODT resistance corresponding to the second data 752 generated by the slave circuit 713 can include a constant resistance value.

[0074] Figure 12 This corresponds to an embodiment in which a memory device including ODT circuitry 700 receives an ODT request from a host. See also... Figure 12 The ODT circuit 700 can receive first data 751 corresponding to a termination resistor requested by the host. When the first data 751 is received, the ODT enable circuit 720 can compare the termination resistor with a predetermined reference resistor. For example, when the termination resistor is lower than the reference resistor, the ODT enable circuit 720 can set the ODT flag signal 753 to a high logic value and output the ODT flag signal 753. The transmitter Tx can output the ODT flag signal 753 via the flag pad 740. The ODT flag signal 753 can be a signal representing one bit of data.

[0075] The flag pad 740 can be connected to the flag pads of other memory devices included in the memory package (such as memory devices including ODT circuitry 700). Therefore, the ODT flag signal 753 can be sent to the ODT circuitry of other memory devices that have not yet received an ODT request from the host. Additionally, the main circuitry 712 can be activated when the terminating resistor included in the first data 751 is lower than a reference resistor. The main circuitry 712 can generate second data 752 corresponding to an ODT resistor that can be lower than the terminating resistor. The ODT setting circuitry 710 can output the second data 752 to a resistor circuitry 730, which can use the second data to connect the ODT resistor to a signal pad of the memory device. The signal pad can be a pad used to send a signal to and receive a signal from a host that has sent an ODT request.

[0076] When the terminating resistance is equal to or higher than the reference resistance, the ODT enable circuit 720 can set the ODT flag signal 753 to a low logic value. Figure 12 Conversely, those shown can activate the default circuit 711 instead of the main circuit 712, and the ODT resistor corresponding to the second data 752 can be equal to the terminating resistor corresponding to the first data 751. For example, when the default circuit 711 is activated, the second data 752 can be equal to the first data 751.

[0077] Figure 13 This can correspond to the case where the memory device including the ODT circuit 700 is a memory device that has not yet received an ODT request from the host. (See reference...) Figure 13 and Figure 12 In comparison, the ODT circuit 700 may not receive the first data 751 from the host, and the receiver Rx may receive the ODT flag signal 753 via the flag pad 740. See reference... Figure 12 The ODT flag signal 753 can be a signal output from a memory device that receives an ODT request from a host. In an embodiment, the ODT flag signal 753 can have a high logic value when the terminating resistor requested by the host is lower than a reference resistor.

[0078] The ODT flag signal 753 can be input to the slave circuit 713 of the ODT setting circuit 710. For example, when the ODT flag signal 753 with a high logic value is input to the slave circuit 713, the slave circuit 713 can output a second data 752 corresponding to a predetermined ODT resistor. Figure 13 In the illustrated embodiment, the ODT resistor corresponding to the second data 752 can have a constant value, regardless of the terminating resistor requested by the host. Resistor circuit 730 can connect the ODT resistor determined by the second data 752 to the signal pad.

[0079] Figure 14 This is a diagram illustrating the operation of a memory package according to an embodiment of the present invention. (Refer to...) Figure 14 According to an embodiment of the present invention, the memory package 800 may include a plurality of memory devices 810 to 840, each of which may include ODT circuits 811, 821, 831 and 841. The ODT circuits 811, 821, 831 and 841 may share a signal pad 801, which may be connected to a pad 901 of the host 900.

[0080] When host 900 selects one of memory devices 810 to 840 to send an ODT request and transmits a signal via signal pad 801, signal reflection occurs within the memory device, thereby degrading signal integrity. For example, when the first ODT circuit 811 of the first memory device 810, which only receives ODT requests, connects the first ODT resistor R1 to the signal pad 801, and when the second ODT circuit 821, the third ODT circuit 831, and the fourth ODT circuit 841 do not connect the second ODT resistors R2 to the fourth ODT resistors R4 to the signal pad 801, the signal will be reflected in the second memory device 820 to the fourth memory device 840.

[0081] In embodiments of the present invention, the first ODT circuit 811 of the first memory device 810 can send an ODT flag signal to the second ODT circuit 821, the third ODT circuit 831, and the fourth ODT circuit 841 of unselected second to fourth memory devices 820 to 840. In response to the ODT flag signal, the second ODT circuit 821, the third ODT circuit 831, and the fourth ODT circuit 841 can connect the second ODT resistor R2 to the fourth ODT resistor R4 to the pad 801, and can minimize signal reflection. For example, the ODT flag signal can be sent via a flag pad different from the signal pad 801, and can be a 1-bit flag signal. The flag pad can be a pad separate from the host 900.

[0082] The first ODT circuit 811 can be referenced. Figure 12 The ODT circuit 700 described herein operates in the same manner. The second ODT circuit 821, the third ODT circuit 831, and the fourth ODT circuit 841 can operate in the same manner as described above. Figure 13 The ODT circuit 700 described herein operates in the same manner. As shown in Table 1 below, the first ODT resistor R1 to the fourth ODT resistor R4 provided by each of the ODT circuits 811, 821, 831 and 841 can be determined based on the terminating resistor requested by the host 900.

[0083] [Table 1]

[0084] Terminating resistor (ohms) R1 (Ohm) R2 (Ohms) R3 (Ohm) R4 (Ohm) 40 80 240 240 240 48 120 240 240 240 60 240 240 240 240 80 OFF 240 240 240 120 120 OFF OFF OFF 240 240 OFF OFF OFF

[0085] In Table 1 above, OFF corresponds to the case where the ODT resistor is not connected to the signal pad 801. Referring to Table 1 above, when the terminating resistor is lower than a predetermined reference resistor, the second ODT circuit 821, the third ODT circuit 831, and the fourth ODT circuit 841 included in the unselected second memory devices 820 to the fourth memory devices 840 can be activated to connect the second ODT resistor R2 to the fourth ODT resistor R4 to the signal pad 801. In the embodiment shown in Table 1, the reference resistor can be set to a value higher than 80 ohms and equal to or lower than 120 ohms, but is not limited to such a resistance value. In addition, the second ODT resistor R2 to the fourth ODT resistor R4 can have constant values ​​regardless of the terminating resistor. For example, when the terminating resistor is lower than the reference resistor, the second ODT circuit 821, the third ODT circuit 831, and the fourth ODT circuit 841 included in the second memory devices 820 to the fourth memory devices 840 can have the same size.

[0086] When the terminating resistor is lower than the reference resistor, the first ODT resistor R1 provided by the first ODT circuit 811 of the first memory device 810, which receives the ODT request from the host 900, can be higher than the terminating resistor. The value of the first ODT resistor R1 can be set such that the combined resistance of the first ODT resistor R1 to the fourth ODT resistor R4 has the terminating resistor 900 requested by the host. As described above, since the second ODT resistor R2 to the fourth ODT resistor R4 have constant values ​​regardless of the terminating resistor, the first ODT circuit 811 can use the terminating resistor to determine the value of the first ODT resistor R1.

[0087] Figures 15 to 17 This is a diagram illustrating an ODT circuit included in a memory device according to an embodiment of the present invention. Figures 15 to 17 In the embodiment of the present invention shown, the ODT circuit 1000 may include an ODT setting circuit 1010, an ODT enabling circuit 1020, a resistor circuit 1030, a transmitter Tx, a receiver Rx, etc. Alternatively, when the memory device including the ODT circuit 1000 receives an ODT request from the host, the ODT enabling signal (EN) can turn on the transmitter Tx, and the inverted ODT enabling signal (ENB) can turn on the receiver Rx. When the memory device including the ODT circuit 1000 does not receive an ODT request from the host, the receiver Rx can be turned on, and the transmitter Tx can be turned off.

[0088] In this embodiment, when data signals, data strobe signals, etc. are sent to and received from the host, reference is made. Figures 15 to 17 The described ODT circuit 1000 can be a circuit used to provide a terminating resistor requested by the host. For example, the ODT circuit 1000 can be activated when a data routing command (WR_CMD) 1071 and an ODT enable signal (ODT_ON) 1072 are received from the host, and the ODT circuit 1000 may not operate during data read operations.

[0089] When the memory device including the ODT circuit 1000 receives an ODT request from the host, the ODT setting circuit 1010 can receive first data 1061. The ODT setting circuit 1010 may include a default circuit 1011, a master circuit 1012, a slave circuit 1013, a common circuit 1014, etc. The common circuit 1014 can be connected to the output terminals of the default circuit 1011, the master circuit 1012, and the slave circuit 1013, and can output second data 1062.

[0090] In the example, the first data 1061 may be data received from the host along with the ODT request by a memory device including the ODT circuit 1000, and may be data corresponding to the terminating resistor requested by the host. The second data 1062 may be sent to the resistor circuit 1030, which may use the second data 1062 to connect the ODT resistor to the signal pad, or to send or receive data signals, data strobe signals, etc. from the signal pad.

[0091] ODT enabling circuit 1020 may include a first ODT enabling circuit 1021 and a second ODT enabling circuit 1022. The first ODT enabling circuit 1021 may operate when receiving first data 1061 and when the terminating resistance included in the first data 1061 is lower than a predetermined reference resistance.

[0092] The output terminals of the first ODT enable circuit 1021 and the second ODT enable circuit 1022 can be connected to the transmitter control circuit 1041 and the receiver control circuit 1042. The transmitter control circuit 1041 can receive the entire ODT enable signal (ODT_EN) 1073 and the outputs of the first ODT enable circuit 1021 and the second ODT enable circuit 1022. The entire ODT enable signal 1073 can be a signal used to activate the ODT circuits of all memory devices sharing a signal pad, from which data signals, data strobe signals, etc., are sent or received.

[0093] When receiver Rx is turned on, receiver control circuit 1042 can use the output of receiver Rx and the output of second ODT enable circuit 1022 to generate ODT flag signal 1063. ODT flag signal 1063 can be a one-bit flag signal. ODT flag signal 1063 can be input to slave circuit 1013, which can generate second data 1062. When slave circuit 1013 generates second data 1062, resistor circuit 1030 can connect a constant ODT resistor to the signal pad regardless of the terminating resistor requested by the host.

[0094] Figure 16 This corresponds to a situation where a memory device including ODT circuitry 1000 receives an ODT request from a host. In this embodiment, the memory device including ODT circuitry 1000 can receive a data write command 1071, an ODT enable signal 1072, and a full ODT enable signal 1073 from the host. (See also...) Figure 16 The ODT circuit 1000 can receive first data 1061 from the host, which may include data corresponding to the terminating resistor requested by the host.

[0095] The first ODT enable circuit 1021 can compare the terminating resistor included in the first data 1061 with a predetermined reference resistor. When the terminating resistor is lower than the reference resistor, the output of the first ODT enable circuit 1021 can be determined to be a logic value that allows the ODT circuitry of other memory devices to be activated by a signal output by the transmitter Tx.

[0096] Additionally, when the terminating resistor included in the first data 1061 is lower than the reference resistor, the main circuit 1012 can be activated. The main circuit 1012 can generate second data 1062 corresponding to an ODT resistor higher than the terminating resistor. The ODT resistor corresponding to the second data 1062 can provide the terminating resistor corresponding to the first data 1061, as well as the ODT resistor provided by an ODT circuit activated in another memory device. The ODT setting circuit 1010 can output the second data 1062 to the resistor circuit 1030, which can use the second data 1062 to connect the ODT resistor to the signal pad.

[0097] When the terminating resistor is equal to or higher than the reference resistor, the output of the first ODT enable circuit 1021 can be determined to a logic value that can activate the ODT circuits of other memory devices. The signal output by the transmitter Tx through the flag pad 1050 can be directly sent to the flag pads of other memory devices that have not yet received an ODT request from the host.

[0098] When the terminating resistance is equal to or higher than the reference resistance, and Figure 16 The embodiment shown differs in that default circuit 1011 can be activated instead of main circuit 1012. When default circuit 1011 is activated, second data 1062 can be the same as first data 1061. Therefore, the ODT resistance of resistor circuit 1030 can be equal to the terminating resistance corresponding to first data 1061.

[0099] Figure 17 This can correspond to the case where the memory device including the ODT circuit 1000 is a memory device that has not yet received an ODT request from the host. (See reference...) Figure 17 and Figure 16 In comparison, the ODT circuit 1000 may not receive the first data 1061 from the host. The transmitter Tx can be turned off by the ODT enable signal (EN), and the receiver Rx can be turned on by the inverted ODT enable signal (ENB).

[0100] In ODT circuit 1000, the first ODT enabling circuit 1021 may not operate, while the second ODT enabling circuit 1022 may operate. Due to the output of the second ODT enabling circuit 1022 and the signal received by receiver Rx through the flag pad 1050, the ODT flag signal 1063 may have a high logic value, allowing operation of the slave circuit 1013. The slave circuit 1013 can set the ODT resistor to a previously stored value and can generate second data 1062 corresponding to the ODT resistor. For example, the previously stored value in the slave circuit 1013 may be higher than or equal to the terminating resistor requested by the host.

[0101] Figure 18 and Figure 19 This is a diagram illustrating the operation of a memory package according to an embodiment of the present invention. (Refer to...) Figure 18 and Figure 19 According to an embodiment of the present invention, the memory package 1100 may include a plurality of memory devices 1110 to 1140, each of which may include ODT circuits 1111, 1121, 1131, and 1141. The first ODT circuit 1111 and the second ODT circuit 1121 may share a first signal pad 1101, and the third ODT circuit 1131 and the fourth ODT circuit 1141 may share a second signal pad 1102. The first signal pad 1101 and the second signal pad 1102 may be connected to the first pad 1201 and the second pad 1202 of the host 1200, respectively.

[0102] In an embodiment, the first signal pad 1101 and the second signal pad 1102 of the memory package 1100 may be pads for transmitting and receiving data signals, data strobe signals, etc. In an embodiment, the first memory device 1110 and the second memory device 1120 sharing the first signal pad 1101 may be classified into a different class than the third memory device 1130 and the fourth memory device 1140 sharing the second signal pad 1102.

[0103] Figure 18 This corresponds to an embodiment where the host 1200 selects at least one of the first memory device 1110 and the second memory device 1120 to execute data routing commands. See also... Figure 18 The first ODT circuit 1111 of the first memory device 1110 and the second ODT circuit 1121 of the second memory device 1120 can both be activated to minimize signal reflection and improve signal integrity. The first ODT resistor R1 and the second ODT resistor R2 can be set such that the combined resistance of the first ODT resistor R1 and the second ODT resistor R2 corresponds to the terminating resistor 1200 requested by the host.

[0104] The host 1200 can transmit an ODT request along with data routing commands to one of the first memory device 1110 and the second memory device 1120. For example, when the host 1200 transmits an ODT request to the first memory device 1110, the operation of the first ODT circuit 1111 can be as described above. Figure 16 The operation of the ODT circuit 1000 described above is the same. The operation of the second ODT circuit 1121 of the second memory device 1120, which has not yet received an ODT request from the host 1200, can be the same as described above. Figure 17 The operation of the described ODT circuit 1000 is the same. In the embodiment, as shown in Table 2 below, the first ODT resistor R1 and the second ODT resistor R2 provided by each of the first ODT circuit 1111 and the second ODT circuit 1121 can be determined based on the terminating resistor 1200 requested by the host.

[0105] [Table 2]

[0106] Terminating resistor (ohms) R1 (Ohm) R2 (Ohms) 40 80 80 48 120 80 60 240 80 80 OFF 80 120 120 OFF 240 240 OFF

[0107] As shown in Table 2 above, when the terminating resistor is lower than a predetermined reference resistor, the second ODT circuit 1121 included in the second memory device 1120 can be activated by the first memory device 1110. In the embodiment shown in Table 2, the value of the reference resistor can be higher than 80 ohms and equal to or lower than 120 ohms. Furthermore, regardless of the terminating resistor requested by the host 1200, the second ODT resistor R2 provided by the second ODT circuit 1121 can have a constant value.

[0108] When the terminating resistor is lower than the reference resistor, the first ODT resistor R1 of the first ODT circuit 1111 in the first memory device 1110, which includes the host 1200 transmitting an ODT request to it, can be lower than the terminating resistor. The value of the first ODT resistor R1 can be set such that the combined resistance of the first ODT resistor R1 and the second ODT resistor R2 is equal to the terminating resistor 1200 requested by the host. As described above, since the second ODT resistor R2 has a constant value regardless of the terminating resistor, the first ODT circuit 1111 can use the terminating resistor to determine the value of the first ODT resistor R1.

[0109] Figure 19 This corresponds to an embodiment where the host 1200 selects at least one of a third memory device 1130 and a fourth memory device 1140 to execute data routing commands. Figure 19 In, with Figure 18 In a similar manner to the embodiment shown, the third ODT circuit 1131 of the third memory device 1130 and the fourth ODT circuit 1141 of the fourth memory device 1140 can both be activated to reduce signal reflections and improve signal integrity. The combined resistance of the third ODT resistor R3 and the fourth ODT resistor R4 can be equal to the terminating resistor requested by the host 1200.

[0110] Figure 20 This is a block diagram schematically illustrating an electronic device including a memory device according to an embodiment of the present invention. Figure 20 The electronic device 2000 of the illustrated embodiment may include a display 2010, a sensor unit 2020, a memory 2030, a communication unit 2040, a processor 2050, and a port 2060. Additionally, the electronic device 2000 may also include a power supply unit, an input / output unit, etc. Figure 20 Among the components shown, port 2060 can be a device that provides communication with electronic device 2000, such as a video card, sound card, memory card, or Universal Serial Bus (USB) device. Electronic device 2000 can be a concept including general-purpose desktop or laptop computers, smartphones, tablet PCs, smart wearable devices, etc.

[0111] The processor 2050 can perform specific operations, commands, tasks, etc. The processor 2050 can be a central processing unit (CPU), microprocessor unit (MCU), system on chip (SoC), etc., and can be connected to the display 2010, sensor unit 2020, memory 2030, communication unit 2040 and other units of connection port 2060 via bus 2070.

[0112] The memory 2030 can be a storage medium for storing data, multimedia data for operating the electronic device 2000, etc. The memory 2030 can include volatile memory (such as random access memory (RAM)), non-volatile memory (such as flash memory), etc. The memory 2030 can also include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage unit. Figure 20 In the embodiments shown, the memory 2030 may include components according to the above references. Figures 1 to 19 The memory devices or memory packages described in various embodiments.

[0113] According to embodiments of the present invention, a memory device that receives an ODT enable signal from a host among two or more simultaneously driven memory devices can transmit an ODT flag signal to the remaining memory devices. The remaining memory devices receiving the ODT flag signal can connect a predetermined ODT resistor to the host. The ODT resistor of the memory device that has received the ODT enable signal from the host can be configured such that the combined resistance of the ODT resistors connected to the host matches a terminating resistor requested by the host. Therefore, signal reflections in host-driven memory devices can be minimized to reduce signal distortion, and signal integrity and / or eye diagram tolerance can be improved to enhance the performance of the memory devices and memory packages.

[0114] The various advantages and effects of the present invention are not limited to those described above, and can be more readily understood in the process of describing specific embodiments of the present invention.

[0115] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and alterations may be made thereto without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: The pad area has marking pads and signal pads; A storage area having multiple memory cells; An on-chip terminal setting circuit is configured to receive a control command and an on-chip terminal enable signal, the control command including first data corresponding to a terminal resistor requested by an external host, and the on-chip terminal setting circuit is further configured to generate second data corresponding to the on-chip terminal resistor. An on-chip termination enable circuit is configured to output an on-chip termination flag signal to the flag pad in response to the control command and the on-chip termination enable signal; and A resistor circuit is configured to connect the on-chip terminating resistor to the signal pad in response to the second data.

2. The memory device according to claim 1, further comprising: A transmitter having an output terminal electrically coupled to the mark pad; as well as The receiver has an input terminal electrically coupled to the marked pad.

3. The memory device according to claim 2, wherein, In response to receiving the on-chip terminal enable signal via the on-chip terminal enable circuit, the receiver is disconnected and the transmitter is turned on, thereby outputting the on-chip terminal flag signal.

4. The memory device according to claim 3, wherein, When the on-chip terminal enable signal is not present, the transmitter is disconnected and the receiver is turned on.

5. The memory device according to claim 2, wherein, When the transmitter is disconnected and the on-chip terminal flag signal is received by the receiver, the on-chip terminal setting circuit is configured to set the on-chip terminal resistor with a pre-stored value.

6. The memory device according to claim 1, wherein, The on-chip termination setting circuit is configured to: set the on-chip termination resistor to a value corresponding to the termination resistor when the operating frequency of the memory device is less than the reference frequency, but set the on-chip termination resistor to a value different from the termination resistor when the operating frequency is greater than the reference frequency.

7. The memory device according to claim 1, wherein, The on-chip termination setting circuit is configured to: set the on-chip termination resistor to a value corresponding to the termination resistor when the termination resistor is greater than the reference resistor, but set the on-chip termination resistor to a value different from the termination resistor when the termination resistor is less than the reference resistor.

8. The memory device according to claim 7, wherein, The on-chip terminal enable circuit is configured to set the on-chip terminal flag signal with a low logic value when the terminal resistor is higher than the reference resistor, but to set the on-chip terminal flag signal with a high logic value when the terminal resistor is lower than the reference resistor.

9. The memory device according to claim 1, wherein, The on-chip terminating resistor is electrically coupled to the signal pad, and the signal pad receives at least one of the following signals from the external host: command / address signal, clock signal, data signal, and data strobe signal.

10. The memory device according to claim 1, wherein, The storage area includes an array of dynamic random access memory cells located therein.

11. The memory device according to claim 2, wherein, The on-chip terminal enable circuit has an output terminal electrically coupled to the input terminal of the transmitter; and wherein the on-chip terminal setting circuit has an input terminal electrically coupled to the output terminal of the receiver.

12. A memory package, comprising: A packaging substrate having multiple pads on it; A first memory device, mounted on the package substrate, includes a first on-chip termination resistor and a first on-chip termination circuit. The first on-chip termination circuit determines the value of the first on-chip termination resistor, wherein, in response to an on-chip termination request from a host, the first on-chip termination circuit sets the first on-chip termination resistor to a first resistance value and outputs an on-chip termination flag signal; and A second memory device, mounted on the package substrate, includes a second on-chip termination resistor and a second on-chip termination circuit. The second on-chip termination circuit determines the value of the second on-chip termination resistor, wherein, when receiving the on-chip termination flag signal from the first memory device, the second on-chip termination circuit sets the second on-chip termination resistor to a second resistance value. Wherein, when the first on-chip terminating resistor and the second on-chip terminating resistor are connected together to the pads for receiving command / address signals and / or clock signals from the host, the value of the first resistor is equal to or lower than the value of the second resistor.

13. The memory package according to claim 12, wherein, The first on-chip terminal circuit and the second on-chip terminal circuit have equivalent structures.

14. The memory package according to claim 12, wherein, The first memory device and the second memory device share the plurality of pads, and the first on-chip terminating resistor and the second on-chip terminating resistor have their respective terminals that are commonly connected to one of the plurality of pads.

15. The memory package according to claim 12, wherein, The first on-chip terminating resistor and the second on-chip terminating resistor are connected in parallel with each other, and the combined resistance of the first on-chip terminating resistor and the second on-chip terminating resistor is equal to the terminating resistor included in the on-chip terminating request.

16. The memory package according to claim 15, wherein, The terminating resistor is lower than the predetermined reference resistor.

17. The memory package according to claim 12, wherein, The first on-chip terminal circuit is operated as a master device, and the second on-chip terminal circuit is operated as a slave device relative to the master device.

18. The memory package according to claim 12, wherein, When the first on-chip terminating resistor and the second on-chip terminating resistor are connected to the pads for receiving data signals and / or data strobe signals, the value of the first resistor is equal to or higher than the value of the second resistor.

19. A memory device, comprising: A resistor circuit that provides on-chip terminating resistors connected to pads that receive signals from an external host. An on-chip terminal setting circuit is configured to control the resistor circuit such that the value of the on-chip terminal resistor is greater than the terminal resistor when the terminal resistor included in the on-chip terminal request received from the host is lower than a predetermined reference resistor. as well as An on-chip terminal enable circuit is configured to output an on-chip terminal flag signal when the terminal resistor is lower than the reference resistor. Specifically, when the on-chip terminal request is received along with at least one of a command / address signal and a clock signal, the on-chip terminal enable circuit is configured to output the on-chip terminal flag signal to a first number of other memory devices. Furthermore, when the on-chip terminal request is received along with at least one of a data signal and a data strobe signal, the on-chip terminal enable circuit is further configured to output the on-chip terminal flag signal to a second number of the other memory devices, where the second number is less than the first number.

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