Semiconductor device and semiconductor package

Abstract

A semiconductor device and a semiconductor package are provided. The semiconductor device includes a semiconductor substrate having an active surface on which a semiconductor element is disposed. An interlayer insulating film is disposed on the semiconductor substrate. A first via structure passes through the semiconductor substrate. The first via structure has a first diameter. A second via structure passes through the semiconductor substrate. The second via structure has a second diameter that is greater than the first diameter. The first via structure has a stepped portion that is in contact with the interlayer insulating film.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2019-0087761, filed on July 19, 2019 with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices and semiconductor packages, and more specifically, to semiconductor devices and semiconductor packages that process data at high speeds and have low power consumption. Background Technology

[0004] With the rise of three-dimensional (3D) packages that horizontally stack multiple semiconductor chips and mount them together in a single semiconductor package, silicon via (TSV) technology, which forms vertical electrical connections through a substrate or die, is gaining popularity. Summary of the Invention

[0005] According to one aspect of the present invention, a semiconductor device includes a semiconductor substrate having an active surface, and a semiconductor element disposed on the active surface. An interlayer insulating film is disposed on the semiconductor substrate. A first via structure is configured to pass through the semiconductor substrate. The first via structure has a first diameter. A second via structure is configured to pass through the semiconductor substrate. The second via structure has a second diameter greater than the first diameter. The first via structure includes: a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate; and a body portion having a second width in the same direction parallel to the upper surface of the semiconductor substrate. The second width is less than the first width. A stepped portion contacts the interlayer insulating film between the head portion and the body portion. The lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate.

[0006] According to one aspect of the present invention, a semiconductor device includes a semiconductor substrate. An interlayer insulating film is disposed on the semiconductor substrate. A signal path structure is configured to pass through the semiconductor substrate and the interlayer insulating film. A power path structure is configured to pass through the semiconductor substrate and the interlayer insulating film. The power path structure extends and passes through a device isolation film in the semiconductor substrate. The signal path structure includes: a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate; and a body portion having a second width in the same direction parallel to the upper surface of the semiconductor substrate. The second width is smaller than the first width. A lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate.

[0007] According to an aspect of the present inventive concept, a semiconductor package includes a first semiconductor device including a cell region and a peripheral region, and a second semiconductor device stacked on the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device. The first semiconductor device includes a semiconductor substrate and an interlayer insulating film disposed on the semiconductor substrate. The first semiconductor device includes a first via structure and a second via structure located in the peripheral region. The first via structure passes through the semiconductor substrate and has a first diameter. The second via structure passes through the semiconductor substrate and has a second diameter greater than the first diameter. A sidewall of a via hole of the first via structure includes at least one undercut portion. The first via structure includes a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate, and a body portion having a second width in the direction parallel to the upper surface of the semiconductor substrate. The second width is less than the first width. A lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate. BRIEF DESCRIPTION OF DRAWINGS

[0008] A more complete appreciation of the present disclosure and its many attendant aspects will be readily understood by the following detailed description taken in connection with the accompanying drawings, wherein:

[0009] FIG. 1 is a plan layout view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0010] FIG. 2 is a plan layout view showing FIG. 1 a silicon via (TSV) unit region;

[0011] FIG. 3 is a side sectional view taken along line III-III' of FIG. 2 the semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] FIG. 4 is a side sectional view taken along line III-III' of FIG. 2 the semiconductor device according to an exemplary embodiment of the present disclosure;

[0013] FIG. 5 is a side sectional view taken along line III-III' of FIG. 2 the semiconductor device according to an exemplary embodiment of the present disclosure;

[0014] FIG. 6A and FIG. 6B are detailed partial enlarged views of region VI of FIG. 5 the semiconductor device according to an exemplary embodiment of the present disclosure;

[0015] FIG. 7 is a side sectional view taken along line III-III' of the semiconductor device according to an exemplary embodiment of the present disclosure; FIG. 2

[0016] FIG. 8 is a side sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] FIG. 9 is a side sectional view taken along line III-III' of the semiconductor device according to an exemplary embodiment of the present disclosure; FIG. 2

[0018] FIG. 10 is a flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0019] FIG. 11A to FIG. 11K is a side sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0020] FIG. 12 is a detailed flowchart showing an operation of forming a preliminary recess shown in FIG. 10

[0021] FIG. 13 is a detailed flowchart showing an operation of exposing a semiconductor substrate at a first position of FIG. 12

[0022] is a side sectional view taken along line III-III' of the semiconductor device according to an exemplary embodiment of the present disclosure; FIG. 14 FIG. 2 is a side view showing a process sequence of a method of manufacturing a semiconductor device of

[0023] FIG. 15A to FIG. 15F FIG. 14 is a side view showing a process sequence of a method of manufacturing a semiconductor device of

[0024] FIG. 16 is a cross-sectional view showing key components of a semiconductor package according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals can be used to designate the same or similar elements, and, in terms of omitting repetitive descriptions of these elements, it can be assumed that the omitted elements are at least similar to the corresponding elements for which detailed descriptions have been provided herein.

[0026] FIG. 1 ​​​​​is a plan layout diagram illustrating a semiconductor device 100 according to an example embodiment of the present disclosure.

[0027] Referring to FIG. 1 , the semiconductor device 100 can include a memory chip 12 having a plurality of cell regions 14. A plurality of memory cells can be arranged in each of the plurality of cell regions 14. A plurality of word lines, a plurality of bit lines, and sense amplifiers can be arranged in various ways within the plurality of cell regions 14. A peripheral region can be provided to at least partially surround each of the plurality of cell regions 14. The peripheral region can include a plurality of column decoders 16, a plurality of row decoders 18, and a through silicon via (TSV) region 20. The plurality of column decoders 16 can receive an address, decode the address, and select a column line of the cell regions 14. The plurality of row decoders 18 can receive an address, decode the address, and output a row address for selecting a row line of the cell regions 14. The memory chip 12 can further include write drivers, input / output (I / O) sense amplifiers, and I / O buffers.

[0028] The TSV region 20 can be located at about a central portion of the memory chip 12. A plurality of TSV structures 30 can be arranged in the TSV region 20. FIG. 1 The number and shape of the plurality of TSV structures 30 shown in FIG. 1 are exemplary only, and the inventive concept is not limited to For example, about several hundreds to several thousands of TSV structures 30 can be provided in the TSV region 20.

[0029] The I / O buffers included in the memory chip 12 can receive external signals through the TSV structures 30, or transmit signals to the outside through the TSV structures 30.

[0030] The TSV region 20 can include a plurality of TSV unit regions. For example, the TSV region 20 can include a first TSV unit region 22, a second TSV unit region 24, a third TSV unit region 26, and a fourth TSV unit region 28. Although FIG. 1 an example in which the TSV region 20 includes four TSV unit regions (e.g., the first to fourth TSV unit regions 22, 24, 26, and 28) is shown, the inventive concept is not limited to FIG. 1 the example shown in The TSV region 20 can include various different numbers of TSV unit regions.

[0031] FIG. 2 is an enlarged view illustrating the first TSV unit region 22 of FIG. 1 Although FIG. 2The first TSV unit region 22 is shown, but one of ordinary skill in the art will understand that each of the second TSV unit region 24, the third TSV unit region 26, and the fourth TSV unit region 28 can also have the same structure as that of the first TSV unit region 22.

[0032] Referring to FIG. 2 , the first TSV unit region 22 can include a plurality of via structures. For example, the first TSV unit region 22 can include first via structures 110 having a relatively small diameter and second via structures 120 having a relatively large diameter.

[0033] Since the second via structures 120 have a relatively large diameter, the second via structures 120 can have a lower resistance and can supply power more efficiently than the first via structures 110. Since the first via structures 110 have a relatively small diameter, the first via structures 110 can have a lower capacitance and provide a higher data transmission rate than the second via structures 120. Accordingly, in some exemplary embodiments of the present disclosure, the first via structures 110 can include signal via structures, and the second via structures 120 can include power via structures.

[0034] In some exemplary embodiments of the present disclosure, a plurality of first via structures 110 serving as signal transmission paths can be arranged in a lattice form, and a plurality of second via structures 120 serving as power transmission paths can be arranged in a straight line form. However, the inventive concept is not limited to this particular arrangement.

[0035] FIG. 3 is a side sectional view taken along line III-III' of the semiconductor device 100 according to an exemplary embodiment of the present disclosure. FIG. 2

[0036] Referring to FIG. 3 , the semiconductor device 100 can include a semiconductor substrate 101, an interlayer insulating film 134 formed on the semiconductor substrate 101, first via structures 110 configured to pass through the semiconductor substrate 101, and second via structures 120 configured to pass through the semiconductor substrate 101.

[0037] ​The semiconductor substrate 101 can include a semiconductor such as silicon (Si) and / or germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). In at least one embodiment, the semiconductor substrate 101 can have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate 101 can include a buried oxide (BOX) layer. In some example embodiments of the present disclosure, the semiconductor substrate 101 can include a conductive region, e.g., a doped well or a doped structure. Also, the semiconductor substrate 101 can have various device isolation films such as a shallow trench isolation (STI) structure.

[0038] The interlayer insulating film 134 can include a single material layer or a multilayer material structure of at least two material layers stacked on each other. In some example embodiments of the present disclosure, the interlayer insulating film 134 can include a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, or an ultra-low-K (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK film can include, for example, a silicon oxycarbide (SiOC) film or a silicon oxycarbide-hydride (SiCOH) film. In some example embodiments of the present disclosure, the interlayer insulating film 134 can include a silicon nitride (SiN) film or a silicon oxynitride (SiON) film.

[0039] A variety of semiconductor elements 132 can be disposed in the interlayer insulating film 134 and the semiconductor substrate 101. The semiconductor elements 132 can include various microelectronic devices such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a system large-scale integrated circuit (LSI), an image sensor (e.g., a CMOS image sensor (CIS)), a microelectromechanical system (MEMS), an active element, and a passive element. The semiconductor elements 132 can be electrically connected to the conductive region of the semiconductor substrate 101. In addition, each semiconductor element 132 can be electrically isolated from other adjacent semiconductor elements by the device isolation film 105.

[0040] The device isolation film 105 can include a single material layer or a multilayer material structure of at least two material layers stacked on each other. In some example embodiments of the present disclosure, the device isolation film 105 can have an STI structure. In some example embodiments of the present disclosure, an upper surface of the device isolation film 105 can be substantially coplanar with the upper surface 101A of the semiconductor substrate 101. In some example embodiments of the present disclosure, the device isolation film 105 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Although in the above description, the device isolation film 105 is described as being formed on the semiconductor substrate 101, the device isolation film 105 can be formed on the semiconductor element 132 in some example embodiments of the present disclosure. FIG. 3Only one device isolation film 105 is shown in the figure, but those skilled in the art will understand that multiple device isolation films 105 can be provided.

[0041] The first passage structure 110 may include a first passage insulating film 116, a first barrier film 114, and a first passage plug 112. The first passage insulating film 116 covers the sidewall of the first passage hole 110H, the first barrier film 114 covers the sidewall of the first passage insulating film 116, and the first passage plug 112 is configured to fill the internal space defined by the first barrier film 114.

[0042] In some exemplary embodiments of this disclosure, the first via insulating film 116 may extend along the sidewall of the first via aperture 110H to a substantially uniform thickness. The first via insulating film 116 may include an oxide film, a nitride film, a carbide film, a polymer film, or a combination thereof. In some exemplary embodiments of this disclosure, the first via insulating film 116 may be formed using a chemical vapor deposition (CVD) process. In some exemplary embodiments of this disclosure, the first via insulating film 116 may have a thickness of approximately 500 angstroms. to approximately The thickness.

[0043] In some exemplary embodiments of this disclosure, the first barrier film 114 may extend along the sidewall of the first via insulating film 116 to a substantially uniform thickness. The first barrier film 114 may include a conductive layer having a relatively low interconnect resistance. For example, the first barrier film 114 may include a single-layer film or multilayer structure comprising tungsten (W), tungsten nitride (WN), tungsten carbide (WC), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and / or nickel boron (NiB). For example, the first barrier film 114 may have a multilayer structure comprising TaN / W, TiN / W, or WN / W. The first barrier film 114 may have approximately To date The thickness. In some exemplary embodiments of this disclosure, a physical vapor deposition (PVD) process, a CVD process, or an atomic layer deposition (ALD) process may be used to form the first barrier film 114, but the inventive concept is not limited thereto.

[0044] The second passage structure 120 may include a second passage insulating film 126, a second barrier film 124, and a second passage plug 122. The second passage insulating film 126 covers the sidewall of the second passage hole 120H, the second barrier film 124 covers the sidewall of the second passage insulating film 126, and the second passage plug 122 is configured to fill the internal space defined by the second barrier film 124.

[0045] The second via insulating film 126, the second barrier film 124, and the second via plug 122 can be substantially the same as the first via insulating film 116, the first barrier film 114, and the first via plug 112, respectively. Since the first via insulating film 116, the first barrier film 114, and the first via plug 112 have been described in detail above, detailed description of the second via insulating film 126, the second barrier film 124, and the second via plug 122 will be omitted here, and it can be assumed that the omitted description is at least similar to the corresponding elements for which detailed description has been provided herein.

[0046] In some example embodiments of the present disclosure, the first via structure 110 can include a head portion H and a body portion B. The head portion H and the body portion B can be connected to each other. In some example embodiments of the present disclosure, the head portion H can be integrally formed with the body portion B. When viewed in a plan view, for example, when viewed in the plan layout shown in FIG. 1A, the head portion H can have a planar form such as a circular, polygonal, and / or elliptical form. However, the present inventive concept is not limited thereto. FIG. 1 When viewed in a plan view, for example, when viewed in the plan layout shown in FIG. 1A, the head portion H can have a planar form such as a circular, polygonal, and / or elliptical form. However, the present inventive concept is not limited thereto.

[0047] In a direction parallel to the upper surface 101A of the semiconductor substrate 101 (e.g., the X direction), the head portion H can have a first width F1, and the body portion B can have a second width F2 smaller than the first width F1. Both the first width F1 and the second width F2 can change depending on the position of the first via structure 110 in a vertical direction (or longitudinal direction of the semiconductor substrate 101, e.g., the Z direction). Even if the first width F1 and the second width F2 change depending on the position of the first via structure 110, a minimum value of the first width F1 can be greater than a maximum value of the second width F2. The first width F1 can increase in a direction away from the body portion B. FIG. 3

[0048] Similarly, in a direction parallel to the upper surface 101A of the semiconductor substrate 101, a barrier width (not shown) of the first barrier film 114 at the head portion H can be greater than a barrier width (e.g., the first barrier width E1 hereinafter) of the first barrier film 114 at the body portion B.

[0049] The first via structure 110 can have a stepped portion ST in contact with the interlayer insulating film 134. The stepped portion ST can be defined by the head portion H and the body portion B having different widths in a width direction (or lateral direction, e.g., the X direction). Meanwhile, the second via structure 120 can not include the stepped portion. The second via structure 120 can have a shape such that the width of the second via structure 120 in the lateral direction continuously changes within the interlayer insulating film 134. FIG. 3

[0050] ​​The sidewall of the head portion H can be in contact with the interlayer insulating film 134. The lower surface LS of the head portion H can also be in contact with the interlayer insulating film 134. The lower surface LS of the head portion H can be substantially parallel to the upper surface 101A of the semiconductor substrate 101.

[0051] The upper portion of the body portion B can be in contact with the interlayer insulating film 134, and the other portion of the body portion B can be in contact with the semiconductor substrate 101.

[0052] In some example embodiments of the present disclosure, the lower surface LS of the head portion H can be located at a level higher than the upper surface of the semiconductor element 132.

[0053] The first via structure 110 can have a first diameter D1, and the second via structure 120 can have a second diameter D2 that is greater than the first diameter D1. In some example embodiments of the present disclosure, the second diameter D2 can be about 1 pm to about 5 pm greater than the first diameter D1. The first diameter D1 and the second diameter D2 can be the outer diameter of the first via insulating film 116 and the outer diameter of the second via insulating film 126, respectively.

[0054] The first barrier film 114 of the first via structure 110 can have a first barrier width E1, and the second barrier film 124 of the second via structure 120 can have a second barrier width E2. In some example embodiments of the present disclosure, the second barrier width E2 can be greater than the first barrier width E1. In some example embodiments of the present disclosure, the second barrier width E2 can be about 1 pm to about 4 pm greater than the first barrier width E1.

[0055] One end of each of the first via structure 110 and the second via structure 120 can be electrically connected to a multilayer interconnect structure 146 including a plurality of metal interconnect layers 142 and a plurality of contact plugs 144. Although FIG. 3 While a case where the multilayer interconnect structure 146 is in direct contact with the first via structure 110 and the second via structure 120 is shown, the multilayer interconnect structure 146 can be electrically connected to the first via structure 110 and the second via structure 120 through another conductor. In addition, a plurality of multilayer interconnect structures 146 can be insulated from each other by an intermetal dielectric (IMD) film 148.

[0056] In some example embodiments of the present disclosure, an upper insulating film 150 can be formed on the IMD film 148. The upper insulating film 150 can include a silicon oxide film, a silicon nitride film, a polymer film, or a combination thereof. A hole 150H can be formed in the upper insulating film 150 and can expose a bonding pad 152 connected to the multilayer interconnect structure 146. The bonding pad 152 can be connected to an upper connection terminal 154 through the hole 150H.

[0057] The other end of each of the first path structure 110 and the second path structure 120 may be covered with a conductive layer 172. The coupling terminal 174 can be electrically connected to the first path structure 110 and the second path structure 120 through the conductive layer 172.

[0058] The upper connection terminal 154 and the coupling terminal 174 are not limited to FIG. 3 The shapes shown are illustrated. Both the upper connection terminal 154 and the coupling terminal 174 can be configured as conductive pads, solder balls, solder blocks, or redistributed conductive layers. In some exemplary embodiments of this disclosure, the upper connection terminal 154 may be omitted from the semiconductor device 100 according to this embodiment.

[0059] FIG. 4 It is along the semiconductor device according to exemplary embodiments of the present disclosure. FIG. 2 The side cross-sectional view taken from line III-III'. Except for the second pathway structure 120 being surrounded by the device isolation film 105, FIG. 4 The embodiments shown can be compared with FIG. 3 The embodiments shown are essentially the same. Therefore, a detailed description will be provided. FIG. 3 and FIG. 4 The differences between the embodiments shown are noted, and it can be assumed that those elements not disclosed herein are at least similar to the corresponding elements described in detail elsewhere in this application.

[0060] Reference FIG. 4 The second pathway structure 120 can pass through the device isolation membrane 105. (See reference...) FIG. 3 As described, multiple device isolation films 105 may be disposed in a semiconductor substrate 101. A second passage structure 120 may extend vertically to pass through one of the multiple device isolation films 105.

[0061] The device isolation film 105 is configured to pass through the second passage structure 120 and may surround the side surface of the second passage structure 120 at a partial height. For example, the device isolation film 105 may contact the side surface of the second passage structure 120 and may surround the second passage structure 120 in a lateral direction at a partial height. In some exemplary embodiments of this disclosure, the second passage insulating film 126 of the second passage structure 120 may contact the device isolation film 105 configured to pass through the second passage structure 120.

[0062] FIG. 5 It is along the semiconductor device according to exemplary embodiments of the present disclosure. FIG. 2a side sectional view taken along the line III-III' of FIG. 3. Except that the side wall of the first via hole 110H is configured to include the first via structure 110 and the side wall of the first via hole 110H has an undercut portion, FIG. 5 The embodiments shown in FIG. 3 may be substantially the same as the embodiments shown in FIG. 3 and FIG. 5 Thus, the differences between the embodiments shown in

[0063] Referring to FIG. 5 , in some exemplary embodiments of the present disclosure, the side wall of the first via hole 110H can include at least one undercut portion. The undercut portion can mean a portion protruding toward the center of the first via hole 110H. As described below, the first via hole 110H can be formed using a method such as a deep reactive ion etching (DRIE) process. In this case, a fine rough portion can be formed on the side wall of the first via hole 110H, and the undercut portion can be significantly protruding compared to the fine rough portion.

[0064] FIG. 5 The case in which the first via hole 110H includes one undercut portion is shown, but the inventive concept is not limited thereto. The first via hole 110H can include at least two undercut portions, for example, two or more undercut portions.

[0065] FIG. 6A and FIG. 6B is a detailed partial enlarged view of the region VI of FIG. 5

[0066] Referring to FIG. 6A , the undercut portion UC having a protruding shape can be provided at the first via hole 110H. Due to the protruding shape of the undercut portion UC, the first via insulating film 116 and the first barrier film 114 sequentially stacked on the undercut portion UC can also have a protruding shape. Since the first via insulating film 116 and the first barrier film 114 are each conformally formed to a substantially constant thickness, the protruding shape of the undercut portion UC of the first via hole 110H can be inherited identically or similarly to the first via insulating film 116 and the first barrier film 114.

[0067] Referring to FIG. 6B ​having a protruding shape can be provided at the first via hole 110H. The first via hole 110H can be formed using a Bosch process. For example, to form the first via hole 110H in the semiconductor substrate 101, an inductively coupled plasma (ICP) DRIE process using SF6or O2plasma and a CF4etching process are used. The first via hole 110H can be formed by repeating the sidewall passivation process several times. As a result, as shown in FIG. 10B, the first via hole 110H having a plurality of scallop-shaped SCs can be formed. x The sidewall passivation process of any one of the Bosch® series (such as C4F8) can be repeated several times. As a result, as shown in FIG. 10B, the first via hole 110H having a plurality of scallop-shaped SCs can be formed. FIG. 6B

[0068] Due to the protruding shape of the scallop-shaped SCs and the undercut portion UC, the first via insulating film 116 and the first barrier film 114 sequentially stacked on the scallop-shaped SCs and the undercut portion UC can also have a shape corresponding to the protruding shape of the scallop-shaped SCs and the undercut portion UC.

[0069] Compared to the sidewall of the first via hole 110H, the rough portion of the scallop-shaped SCs at the interface between the first via insulating film 116 and the first barrier film 114 can be reduced. In some example embodiments of the present disclosure, the interface between the first via plug 112 and the first barrier film 114 can have a portion that does not inherit the rough portion of the scallop-shaped SCs.

[0070] FIG. 7 is a side cross-sectional view taken along line III-III’ of FIG. 10A in a semiconductor device according to example embodiments of the present disclosure. Except that the sidewall of the first via hole 110H is configured to include the first via structure 110 having the undercut portion and the first via structure 110 has different diameters at the upper and lower portions of the undercut portion, FIG. 2 the embodiments shown in FIG. 10B can be substantially the same as the embodiments shown in FIG. 10A. Therefore, the differences between the embodiments shown in FIG. 10B and FIG. 10A will be mainly described in detail, and it can be assumed that those elements not disclosed herein are at least similar to the corresponding elements described in detail elsewhere in this application. FIG. 7 FIG. 3 Referring to FIG. 10A and FIG. 10B, FIG. 3 FIG. 7 the sidewall of the first via hole 110H can have the undercut portion, and the first via structure 110 can have a first width W1 at the upper portion of the undercut portion and a second width W2 at the lower portion of the undercut portion. The first width W1 can be different from the second width W2. In some example embodiments of the present disclosure, the first width W1 can be greater than the second width W2. In other embodiments, the first width W1 can be less than the second width W2.

[0071] FIG. 7 the sidewall of the first via hole 110H can have the undercut portion, and the first via structure 110 can have a first width W1 at the upper portion of the undercut portion and a second width W2 at the lower portion of the undercut portion. The first width W1 can be different from the second width W2. In some example embodiments of the present disclosure, the first width W1 can be greater than the second width W2. In other embodiments, the first width W1 can be less than the second width W2.

[0072] ​​​​The first width W1 and the second width W2 can each be less than a second diameter (refer to D2) of the second via structure 120. FIG. 3

[0073] FIG. 8 is a side cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure. Except that the semiconductor device further includes a third via structure 180 having a third diameter D3 greater than the second diameter D2, FIG. 8 the embodiments shown in FIG. 3 may be substantially the same as the embodiments shown in FIG. 3 and FIG. 8 . Therefore, the differences between the embodiments shown in

[0074] Referring to FIG. 8 , the third via structure 180 can have a third diameter D3 and include a third via plug 182, a third barrier film 184 formed on a surface of the third via plug 182 in a substantially uniform thickness, and a third via insulating film 186 formed on a surface of the third barrier film 184 in a substantially uniform thickness.

[0075] Since the third via plug 182, the third barrier film 184, and the third via insulating film 186 are substantially the same as the first via plug 112, the first barrier film 114, and the first via insulating film 116, respectively, except for their sizes, detailed descriptions thereof will be omitted here.

[0076] The third via structure 180 can have a third diameter D3 that can be greater than the second diameter D2 of the second via structure 120. In some exemplary embodiments of the present disclosure, the third diameter D3 can be about 1 μm to about 5 μm greater than the second diameter D2. The third diameter D3 can be an outer diameter of the third via insulating film 186.

[0077] The third barrier film 184 of the third via structure 180 can have a third barrier width E3 that can be greater than the second barrier width E2 of the second via structure 120. The third barrier width E3 can be about 1 μm to about 4 μm greater than the second barrier width E2.

[0078] In this case, the second via structure 120 can include at least one cutout portion (e.g., UC3). Also, the first via structure 110 can include at least two cutout portions (e.g., UC1 and UC2). The first via structure 110 can include more cutout portions than the second via structure 120. In some exemplary embodiments of the present disclosure, the first via structure 110 can include two cutout portions UC1 and UC2, and the second via structure 120 can include one cutout portion UC3. ​

[0079] In some example embodiments of the present disclosure, the horizontal height of the cutout portion UC3 of the second via structure 120 can be located between the two cutout portions UC1 and UC2 of the first via structure 110. For example, based on the lower surface 101B of the semiconductor substrate 101, the horizontal height of the cutout portion UC2 of the first via structure 110 can be the lowest, the horizontal height of the cutout portion UC1 of the first via structure 110 can be the highest, and the horizontal height of the cutout portion UC3 of the second via structure 120 can be located between the horizontal height of the cutout portion UC1 and the horizontal height of the cutout portion UC2 of the first via structure 110.

[0080] In addition, the device isolation film 105 can be provided around the third via structure 180. The device isolation film 105 can be in contact with the side surface of the third via structure 180 and can at least partially surround the third via structure 180 in the lateral direction on the local height of the third via structure 180.

[0081] FIG. 9 is a side sectional view taken along the line III-III’ of the semiconductor device according to example embodiments of the present disclosure. Except that the semiconductor device further includes an etching stop film 136 provided in the interlayer insulating film 134, FIG. 2 the embodiment shown in FIG. 9 may be substantially the same as the embodiment shown in FIG. 3 . Therefore, the differences between the embodiments shown in FIG. 3 and FIG. 9 will be mainly described in detail, and it can be assumed that those elements not disclosed herein are at least similar to the corresponding elements described in detail elsewhere in this application.

[0082] Referring to FIG. 9 , the etching stop film 136 can be provided in the interlayer insulating film 134. The etching stop film 136 can extend between the top surface and the bottom surface of the interlayer insulating film 134 in a direction parallel to the upper surface of the semiconductor substrate 101. In some example embodiments of the present disclosure, the upper surface of the etching stop film 136 can be in contact with the lower surface LS of the head portion H of the first via structure 110.

[0083] In some example embodiments of the present disclosure, the semiconductor element 132 can be provided between the upper surface of the semiconductor substrate 101 and the etching stop film 136.

[0084] The etching stop film 136 can include any material having etching selectivity with respect to the interlayer insulating film 134. The etching stop film 136 can include a TEOS film, an HDP film, a BPSG film, an FCVD oxide film, a SiN film, a SiON film, or an ultra low K (ULK) film having an ultra low dielectric constant K of about 2.2 to about 2.4.

[0085] Although the thickness of the etching stop film 136 is not particularly limited, the thickness of the etching stop film 136 can be in a range of, for example, about 0.1 μm to about 50 μm. The etching stop film 136 can be formed using a CVD process, an ALD process, or a PVD process, but is not limited thereto.

[0086] FIG. 10 is a flowchart of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. FIG. 11A to FIG. 11K is a side cross-sectional view of a method of manufacturing a semiconductor device according to the example embodiment shown in FIG. 10

[0087] Referring to FIG. 10 and FIG. 11A , an interlayer insulating film 134 can be formed on the semiconductor substrate 101 (S110). In some example embodiments of the present disclosure, before the interlayer insulating film 134 is formed, a semiconductor element 132 can be formed on the semiconductor substrate 101. The semiconductor element 132 and the interlayer insulating film 134 formed before the multi-layer interconnection structure is formed can be collectively referred to as a front-end-of-line (FEOL) structure 130.

[0088] Thereafter, a first mask pattern 201 can be formed on the interlayer insulating film 134. The first mask pattern 201 can be a photoresist pattern. The formation of the first mask pattern 201 can include coating a photoresist material film and performing an exposure process and a development process.

[0089] The first mask pattern 201 can be configured to expose the interlayer insulating film 134 at a position for forming a first via structure (hereinafter, referred to as a "first position").

[0090] Referring to FIG. 10 , a preliminary recess having a first depth can be formed at the first position (S120).

[0091] FIG. 12 is a detailed flowchart of an operation of forming FIG. 10 the preliminary recess. Referring to FIG. 12 , to form the preliminary recess, first, the semiconductor substrate 101 at the first position can be exposed without exposing the semiconductor substrate 101 at a position for forming a second via structure (hereinafter, referred to as a "second position") (S121). Thereafter, the semiconductor substrate 101 exposed at the first position can be etched to form the preliminary recess (S125).

[0092] FIG. 13 is a detailed flowchart of an operation of exposing the semiconductor substrate at the first position of FIG. 12 FIG. 13 ​​First, the interlayer insulating film 134 can be partially removed at the first position (S1211). Thereafter, the interlayer insulating film 134 can be exposed at the second position (S1213). Subsequently, the remaining interlayer insulating film 134 can be removed at the first position, thereby exposing the semiconductor substrate 101 at the first position (S1215).

[0093] FIG. 11B to FIG. 11F is a side sectional view showing process operations up to formation of a preliminary recess.

[0094] Referring to FIG. 11B , FIG. 12 and FIG. 13 , the first mask pattern 201 can be used as an etching mask to remove a portion of the interlayer insulating film 134 at the first position. The portion of the interlayer insulating film 134 can be removed using an anisotropic etching process. In some example embodiments of the present disclosure, a timed etching process can be performed to remove the portion of the interlayer insulating film 134 at the first position. In some example embodiments of the present disclosure, in order to remove the portion of the interlayer insulating film 134 at the first position, an etching stop film 136 can be previously provided in the interlayer insulating film 134, as shown in FIG. 9 .

[0095] The portion of the interlayer insulating film 134 removed using the first mask pattern 201 as an etching mask can have a planar form, for example, in the form of a circle, a polygon, and an ellipse. However, the inventive concept is not limited thereto.

[0096] Referring to FIG. 11C , FIG. 12 and FIG. 13 , the first mask pattern 201 can be removed, and then a second mask pattern 202 can be formed. The first mask pattern 201 can be removed by a dissolving process using a solvent or an ashing process performed in an oxidizing atmosphere. Subsequently, a new photoresist film can be formed and patterned using an exposure process and a development process, thereby forming the second mask pattern 202.

[0097] The second mask pattern 202 can expose the interlayer insulating film 134 at the second position. Also, the second mask pattern 202 can expose the interlayer insulating film 134 at the first position. In this case, the second mask pattern 202 can have an opening with a width smaller than that of the opening of the first mask pattern 201. As shown in FIG. 11C , the second mask pattern 202 can be in contact with a side wall of a recess of the interlayer insulating film 134 formed by partially removing the interlayer insulating film 134 at the first position. In addition, the second mask pattern 202 can be in contact with a portion of a bottom surface of the recess of the interlayer insulating film 134 formed by partially removing the interlayer insulating film 134 at the first position.

[0098] Referring to FIG. 11D , FIG. 12 and FIG. 13 , the remaining interlayer insulating film 134 at the first position can be removed, thereby exposing the upper surface of the semiconductor substrate 101 at the first position. In this case, the interlayer insulating film 134 can be partially removed at the second position.

[0099] The removing of the remaining interlayer insulating film 134 at the first position can be performed using an anisotropic etching process.

[0100] In FIG. 11A to FIG. 11D , the side surface of each pattern is shown as an inclined surface rather than a vertical surface, but the inventive concept is not limited thereto. According to actual manufacturing conditions, the side surface of each pattern can be a vertical surface rather than an inclined surface.

[0101] Referring to FIG. 11E , FIG. 12 and FIG. 13 , the exposed semiconductor substrate 101 can be etched to form a preliminary recess having a depth H1. In this case, since the semiconductor substrate 101 at the first position has etching selectivity with respect to the interlayer insulating film 134 at the second position, the interlayer insulating film 134 at the second position can not be etched or can be only slightly etched compared to other etching of the semiconductor substrate 101 while the preliminary recess is formed by etching the semiconductor substrate 101 at the first position.

[0102] In some exemplary embodiments of the disclosure, the forming of the preliminary recess at the first position can be performed using a DRIE process.

[0103] Referring to FIG. 10 and FIG. 11F , the upper surface of the semiconductor substrate 101 can be exposed at the second position (S130). An anisotropic etching process can be performed to expose the upper surface of the semiconductor substrate 101 at the second position.

[0104] As described with reference to FIG. 11E , since the semiconductor substrate 101 at the first position has etching selectivity with respect to the interlayer insulating film 134 at the second position, the preliminary recess at the first position can not be etched or can be only slightly etched during etching and removing of the interlayer insulating film 134 at the second position.

[0105] Referring to FIG. 10 and FIG. 11GThe preliminary recess and the semiconductor substrate 101 at the second position can be etched at the same time, thereby forming a via hole (referred to as "first via hole") 110H for the first via structure and a via hole (referred to as "second via hole") 120H for the second via structure (S140). The first via hole 110H and the second via hole 120H can each have a second depth that is greater than the first depth (S140).

[0106] The above-described DRIE process can be performed to form the first via hole 110H and the second via hole 120H. The first via hole 110H can have a first diameter D1, and the second via hole 120H can have a second diameter D2. The second diameter D2 can be greater than the first diameter D1. Since the second diameter D2 is greater than the first diameter D1, the etching rate of the second via hole 120H can be higher than the etching rate of the first via hole 110H. Although the etching rate of the semiconductor substrate 101 at the first via hole 110H is lower than the etching rate of the semiconductor substrate 101 at the second via hole 120H, since the preliminary recess is formed in advance, the first via hole 110H can have the same depth as the second via hole 120H at the time point at which the etching stops.

[0107] In addition, after the preliminary recess is formed at the first via hole 110H using the DRIE process (refer to FIG. 11E ), when the semiconductor substrate 101 is etched using the DRIE process to form a remaining portion of the first via hole 110H, a notch portion can be formed at an interface between portions etched by the two DRIE processes, respectively. For example, the horizontal height of the notch portion of the first via hole 110H can correspond to the horizontal height of the bottom surface of the preliminary recess.

[0108] Referring to FIG. 10 and FIG. 11H The via insulating material film 116m and the barrier material film 114m can be sequentially formed on the side walls and the bottom surfaces of the first via hole 110H and the second via hole 120H and the exposed surface of the interlayer insulating film 134.

[0109] The via insulating material film 116m and the barrier material film 114m can each be formed by using a PVD process, a CVD process, or an ALD process. The materials for the via insulating material film 116m and the barrier material film 114m are described above with reference to FIG. 3

[0110] ​A plug material film 112m configured to fill the remaining space can be formed on the barrier material film 114m. The plug material film 112m can be formed using, for example, an electroplating process. For example, a metal seed layer can be formed on a surface of the barrier material film 114m, a metal film can be grown from the metal seed layer due to the electroplating process, and the plug material film 112m configured to fill the remaining space can be formed on the barrier material film 114m. The metal seed layer can include copper (Cu), a Cu alloy, cobalt (Co), nickel (Ni), ruthenium (Ru), cobalt / copper (Co / Cu), or ruthenium / copper (Ru / Cu). The metal seed layer can be formed using a PVD process. A main material of the plug material film 112m can include Cu or W. In some example embodiments of the present disclosure, the plug material film 112m can include copper (Cu), copper tin (CuSn), copper magnesium (CuMg), copper nickel (CuNi), copper zinc (CuZn), copper palladium (CuPd), copper gold (CuAu), copper tungsten (CuW), tungsten (W), or a W alloy, but is not limited thereto. The electroplating process can be performed at a temperature of about 10°C to about 65°C. For example, the electroplating process can be performed at room temperature. After the plug material film 112m is formed, when necessary, the resulting structure including the plug material film 112m can be annealed at a temperature of about 150°C to about 450°C.

[0111] Referring to FIG. 10 and FIG. 11I The plug material film 112m, the barrier material film 114m, and the via insulating material film 116m can be partially removed, respectively, to form the first via structure 110 and the second via structure 120 (S150).

[0112] The partial removal of the plug material film 112m, the barrier material film 114m, and the via insulating material film 116m can be performed using, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0113] Referring to FIG. 10 and FIG. 11J The plurality of metal interconnection layers 142, the plurality of contact plugs 144, and the bonding pad 152 electrically connected to the first via plug 112 can be formed at the first location. Also, the plurality of metal interconnection layers 142, the plurality of contact plugs 144, and the bonding pad 152 electrically connected to the second via plug 122 can be formed at the second location.

[0114] Thereafter, the upper insulating film 150 can be formed to expose at least a portion of the bonding pad 152, and the upper connection terminal 154 can be formed on the bonding pad 152.

[0115] Referring to FIG. 10 and FIG. 11KThe semiconductor substrate 101 can be partially removed so that the end portions of the first via structure 110 and the second via structure 120 can pass through the lower surface 101B of the semiconductor substrate 101 and be exposed.

[0116] In some example embodiments of the present disclosure, the partial removal of the semiconductor substrate 101 can be performed using, for example, a CMP process.

[0117] Further, a lower insulating film 160 can be formed to cover the lower surface 101B of the semiconductor substrate 101. The lower insulating film 160 can be formed to cover the first via insulating film 116 and the second via insulating film 126 protruding from the lower surface 101B of the semiconductor substrate 101. In some example embodiments of the present disclosure, the lower insulating film 160 can be formed using a CVD process. In some example embodiments of the present disclosure, the lower insulating film 160 can include a silicon oxide film, a silicon nitride film, or a polymer film.

[0118] Thereafter, reference is made to FIG. 3 A polishing process can be performed on the exposed surface of the lower insulating film 160 until a planarized surface is obtained at the lower surface 101B of the semiconductor substrate 101. The planarized bottom surfaces of the first via structure 110 and the second via structure 120 can be exposed at the lower surface 101B of the semiconductor substrate 101.

[0119] Thereafter, a conductive layer 172 and a coupling terminal 174 can be formed and connected to the first via structure 110 and the second via structure 120.

[0120] The conductive layer 172 can form an under bump metallization (UBM) film and include films having various compositions depending on the materials included in the coupling terminal 174. In some example embodiments of the present disclosure, the conductive layer 172 can include titanium (Ti), copper (Cu), nickel (Ni), gold (Au), nickel vanadium (NiV), nickel phosphide (NiP), titanium nickel (TiNi), titanium tungsten (TiW), tantalum nitride (TaN), aluminum (Al), palladium (Pd), chromium copper (CrCu), or combinations thereof. For example, the conductive layer 172 can have a Cr / Cu / Au stacked structure, a Cr / CrCu / Cu stacked structure, a TiWCu compound, a TiWCu / Cu stacked structure, a Ni / Cu stacked structure, a NiV / Cu stacked structure, a Ti / Ni stacked structure, a Ti / NiP stacked structure, a TiWNiV compound, an Al / Ni / Au stacked structure, an Al / NiP / Au stacked structure, a stacked structure of a Ti / TiNi / CuNi compound, a Ti / Ni / Pd stacked structure, a Ni / Pd / Au stacked structure, or a NiP / Pd / Au stacked structure.

[0121] The coupling terminals 174 can include conductive pads, solder balls, solder bumps, or a redistribution conductive layer. The coupling terminals 174 can be connected to the bottom surfaces of the first and second via structures 110 and 120 through the conductive layer 172. The coupling terminals 174 can include nickel (Ni), copper (Cu), aluminum (Al), or a combination thereof, but are not limited thereto.

[0122] FIG. 14 is a side cross-sectional view taken along line III-III' of the semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 2 The embodiments shown in FIG. 14 may be substantially the same as the embodiments shown in FIG. 3 . Therefore, the differences between the embodiments shown in FIG. 3 and FIG. 14 will be mainly described in detail, and it can be assumed that those elements not described with reference to FIG. 14 may be at least similar to the corresponding elements already described with reference to FIG. 3 .

[0123] The first via structure 110a can have a first diameter D1 that is smaller than a second diameter D2. The first via structure 110a can have the first diameter D1 throughout the entire depth of the semiconductor substrate. In addition, in the interlayer insulating film 134, the diameter of the first via structure 110a in the lateral direction can increase in a direction away from the semiconductor substrate 101, such that the first via structure 110a has a conical shape within the interlayer insulating film 134.

[0124] The first via structure 110a can include a first via plug 112a, a first barrier film 114a formed in a substantially constant thickness on a surface of the first via plug 112a, and a first via insulating film 116a formed in a substantially constant thickness on a surface of the first barrier film 114a.

[0125] FIG. 15A to FIG. 15F is a side view of a process sequence of a method of manufacturing the semiconductor device of FIG. 14 .

[0126] With reference to FIG. 15A , a first mask pattern 201 can be formed to expose the interlayer insulating film at the first position. Since the first mask pattern 210 is the same as described with reference to FIG. 11A , a detailed description thereof will be omitted here, and it can be assumed that, just as to the elements not described herein with reference to FIG. 15A , those elements can be at least similar to the corresponding elements already described with reference to FIG. 11A .

[0127] The interlayer insulating film 134 can be partially removed over a partial thickness thereof by using the first mask pattern 201 as an etching mask. In an exemplary embodiment of the present disclosure, as shown in FIG. 2B, the interlayer insulating film 134 can be completely removed over an entire thickness thereof using the first mask pattern 201 as an etching mask. FIG. 15B

[0128] In some exemplary embodiments of the present disclosure, the device isolation film 105 can be provided at the second position of the semiconductor substrate 101. The device isolation film 105 at the second position can be formed during definition of an active region for forming the semiconductor element 132. Accordingly, an additional process for forming the device isolation film 105 at the second position can not be needed.

[0129] Referring to FIG. 15C After the first mask pattern 201 is removed, a second mask pattern 202 can be formed. The first mask pattern 201 can be removed by a dissolution process using a solvent or an ashing process performed in an oxidizing atmosphere. Subsequently, a new photoresist film can be formed and patterned using an exposure process and a development process, thereby forming the second mask pattern 202.

[0130] The second mask pattern 202 can expose the interlayer insulating film 134 at the second position. Also, the second mask pattern 202 can have an opening exposing the interlayer insulating film 134 at the first position, and the opening of the second mask pattern 202 has the same width as the opening of the first mask pattern 201.

[0131] Thereafter, a portion of the interlayer insulating film 134 at the second position can be removed using the second mask pattern 202 as an etching mask. In a case where the interlayer insulating film 134 at the first position is partially removed as shown in FIG. 15A

[0132] Also, in a case where the interlayer insulating film 134 at the first position is completely removed as shown in FIG. 15B

[0133] Referring to FIG. 15D ​​​The exposed semiconductor substrate 101 can be etched to form a preliminary recess PR having a first depth H1. In this case, since the semiconductor substrate 101 at the first position has etching selectivity with respect to the interlayer insulating film 134 at the second position, the interlayer insulating film 134 at the second position can not be etched or can be etched only slightly while the preliminary recess PR is formed by etching the semiconductor substrate 101 at the first position.

[0134] In some example embodiments of the present disclosure, a DRIE process can be performed to form the preliminary recess PR at the first position.

[0135] Referring to FIG. 15E The upper surface of the semiconductor substrate 101 at the second position can be exposed. An anisotropic etching process can be performed to expose the upper surface of the semiconductor substrate 101 at the second position.

[0136] Since the semiconductor substrate 101 at the first position has etching selectivity with respect to the interlayer insulating film 134 at the second position as described above with reference to FIG. 15D , the preliminary recess PR at the first position can not be etched or can be etched only slightly while the interlayer insulating film 134 at the second position is etched and removed.

[0137] Referring to FIG. 15F The preliminary recess PR and the semiconductor substrate 101 at the second position can be etched simultaneously to form a via hole (referred to as "first via hole") 110H for the first via structure and a via hole (referred to as "second via hole") 120H for the second via structure 120H. The first via hole and the second via hole can each have a second depth greater than the first depth H1.

[0138] As described with reference to FIG. 11G , the above-described DRIE process can be performed to form the first via hole 110H and the second via hole 120H. The first via hole 110H can have a first diameter D1, and the second via hole 120H can have a second diameter D2. The second diameter D2 can be greater than the first diameter D1. Since the second diameter D2 is greater than the first diameter D1, the etching rate of the second via hole 120H can be greater than the etching rate of the first via hole 110H. Although the etching rate of the semiconductor substrate 101 at the first via hole 110H is lower than the etching rate of the semiconductor substrate 101 at the second via hole 120H, since the preliminary recess PR is formed in advance, the first via hole 110H can have the same depth as the second via hole 120H at the point in time at which etching stops.

[0139] Next, subsequent processes can be performed in the same manner as described with reference to FIG. 11H to FIG. 11K .

[0140] FIG. 16 is a cross-sectional view of main components of a semiconductor package 600 according to an exemplary embodiment of the disclosure.

[0141] Referring to FIG. 16 , the semiconductor package 600 can include a plurality of semiconductor chips 620 sequentially stacked on a package substrate 610. A control chip 630 can be located above the plurality of semiconductor chips 620 and connected to the plurality of semiconductor chips 620. The stacked structure including the plurality of semiconductor chips 620 and the control chip 630 can be sealed together on the package substrate 610 by a sealing agent 640 such as a thermosetting resin. Although a structure in which six semiconductor chips 620 are vertically stacked is illustrated in FIG. 16 , the number of semiconductor chips 620 and the stacking direction are not limited thereto. The number of semiconductor chips 620 can be determined to be less than or more than six, as needed. The plurality of semiconductor chips 620 can be arranged in a lateral direction, or can be arranged in a connection structure corresponding to a combination of a vertical mounting structure and a lateral mounting structure. In some exemplary embodiments of the disclosure, the control chip 630 can be omitted.

[0142] The package substrate 610 can include a flexible printed circuit board (PCB), a rigid PCB, or a combination thereof. The package substrate 610 can include in-substrate interconnections 612 and connection terminals 614. The connection terminals 614 can be formed on one surface of the package substrate 610. Solder balls 616 can be formed on the other surface of the package substrate 610. The connection terminals 614 can be electrically connected to the solder balls 616 through the in-substrate interconnections 612. In some exemplary embodiments of the disclosure, the solder balls 616 can be replaced by conductive bumps or a lead grid array (LGA).

[0143] The semiconductor package 600 can include via structure units 622 and 632. The via structure units 622 and 632 can be electrically connected to the connection terminals 614 of the package substrate 610 through coupling members 650 such as bumps. In some exemplary embodiments of the disclosure, the via structure unit 632 can be omitted from the control chip 630.

[0144] At least one of the plurality of semiconductor chips 620 and the control chip 630 can include at least one of the semiconductor device 100 described with reference to FIG. 1 to FIG. 9 and FIG. 14

[0145] ​Each of the plurality of semiconductor chips 620 can include a system LSI, a flash memory, a dynamic random access memory (DRAM), a static RAM (SRAM), an electrically erasable programmable read only memory (EEPROM), a phase change RAM (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM). For example, the control chip 630 can include a logic circuit, such as a serializer / deserializer (SER / DES) circuit.

[0146] While example embodiments of the inventive concept have been particularly shown and described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a semiconductor substrate including an active surface; a semiconductor element disposed on the active surface; an interlayer insulating film disposed on the semiconductor substrate; a first via structure passing through the semiconductor substrate, the first via structure having a first diameter; and a second via structure passing through the semiconductor substrate, the second via structure having a second diameter larger than the first diameter, wherein the first via structure includes: a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate; a body portion having a second width in the direction parallel to the upper surface of the semiconductor substrate, wherein the second width is smaller than the first width; and a step portion in contact with the interlayer insulating film, the step portion disposed between the head portion and the body portion, wherein a lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate, wherein the second via structure passes through a device isolation film in the semiconductor substrate. The second via structure does not include a step portion in contact with the interlayer insulating film.

2. The semiconductor device of claim 1, wherein, 3. The semiconductor device according to claim 1, wherein: the first via structure includes a first via insulating film having a substantially uniform thickness along a sidewall of a via hole and a first barrier film having a substantially uniform thickness along a sidewall of the first via insulating film, wherein the first barrier film has a first barrier width at the head portion, the first barrier film has a second barrier width at the body portion, and the second barrier width is smaller than the first barrier width. The interlayer insulating film is in contact with both a side surface and the lower surface of the head portion.

4. The semiconductor device of claim 1, wherein, The interlayer insulating film is in contact with a side surface of an upper portion of the body portion.

5. The semiconductor device of claim 4, wherein, The device isolation film, through which the second via structure passes, surrounds the second via structure in a lateral direction at a local height of the second via structure.

6. The semiconductor device of claim 1, wherein, The first via structure includes a signal via structure, and the second via structure includes a power via structure.

7. The semiconductor device of claim 1, wherein, 8. The semiconductor device according to claim 1, further comprising: a third via structure configured to pass through the semiconductor substrate, the third via structure having a third diameter larger than the second diameter, wherein a sidewall of a via hole of the first via structure includes at least two cut portions. The third via structure passes through the device isolation film in the semiconductor substrate.

9. The semiconductor device of claim 8, wherein, A sidewall of a via hole of the first via structure includes at least one cut portion.

10. The semiconductor device of claim 1, wherein, A planar shape of the head portion is circular, polygonal, or elliptical.

11. The semiconductor device of claim 1, wherein, 12. A semiconductor device comprising: a semiconductor substrate; an interlayer insulating film disposed on the semiconductor substrate; a signal via structure passing through the semiconductor substrate and the interlayer insulating film; and a power via structure passing through the semiconductor substrate and the interlayer insulating film, wherein the power via structure passes through a device isolation film in the semiconductor substrate, wherein the signal via structure includes: a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate; a body portion having a second width in the direction parallel to the upper surface of the semiconductor substrate, wherein the second width is smaller than the first width; and a step portion in contact with the interlayer insulating film, the step portion disposed between the head portion and the body portion, wherein a lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate. a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate; and a body portion having a second width in the direction parallel to the upper surface of the semiconductor substrate, the second width being smaller than the first width, wherein a lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate.

13. The semiconductor device of claim 12, wherein, The signal via structure has a first diameter in the semiconductor substrate, the power via structure has a second diameter in the semiconductor substrate, and the second diameter is larger than the first diameter.

14. The semiconductor device of claim 12, wherein, A side wall of a via hole of the signal via structure includes at least one cutout portion.

15. The semiconductor device of claim 14, wherein, The signal via structure has different diameters at an upper portion and a lower portion of the at least one cutout portion.

16. The semiconductor device of claim 12, wherein, In a direction perpendicular to the upper surface of the semiconductor substrate, the device isolation film through which the power via structure passes surrounds the power via structure at a local height of the power via structure.

17. The semiconductor device of claim 12, wherein, The signal via structure has a step portion in contact with the interlayer insulation film.

18. The semiconductor device of claim 17, wherein, The power via structure does not include a step portion.

19. A semiconductor package comprising: a first semiconductor device including a cell region and a peripheral region; and a second semiconductor device stacked on the first semiconductor device, the second semiconductor device electrically connected to the first semiconductor device, wherein the first semiconductor device includes a semiconductor substrate and an interlayer insulation film provided on the semiconductor substrate, wherein the first semiconductor device includes a first via structure and a second via structure located in the peripheral region, wherein the first via structure passes through the semiconductor substrate and has a first diameter, the second via structure passes through the semiconductor substrate and has a second diameter larger than the first diameter, wherein a side wall of a via hole of the first via structure includes at least one cutout portion, wherein the first via structure includes: a head portion having a first width in a direction parallel to an upper surface of the semiconductor substrate; and a body portion having a second width in the direction parallel to the upper surface of the semiconductor substrate, the second width being smaller than the first width, wherein a lower surface of the head portion is substantially parallel to the upper surface of the semiconductor substrate, wherein the second via structure passes through a device isolation film in the semiconductor substrate.

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