Three-dimensional semiconductor devices

Abstract

A three-dimensional semiconductor device includes: a lower substrate; a plurality of lower transistors disposed on the lower substrate; an upper substrate disposed on the lower transistors; a plurality of lower conductive lines disposed between the lower transistors and the upper substrate; and a plurality of upper transistors disposed on the upper substrate. At least one lower transistor is connected to a corresponding lower conductive line. Each upper transistor includes: an upper gate electrode disposed on the upper substrate; a first upper source / drain pattern disposed in the upper substrate on a first side of the upper gate electrode; and a second upper source / drain pattern disposed in the upper substrate on a opposite second side of the upper gate electrode. The upper gate electrode comprises silicon germanium (SiGe).

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0087351, filed with the Korean Intellectual Property Office on July 19, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor device, and more specifically, to a three-dimensional semiconductor device comprising a monolithically integrated three-dimensional circuit. Background Technology

[0004] Higher integration in semiconductor devices allows for meeting consumer demands for improved performance and lower prices, as higher integration is a key factor in determining product performance and price.

[0005] In the case of two-dimensional or planar semiconductor devices, their integration density is largely determined by the area occupied by a single memory cell, and therefore is greatly influenced by the level of fine patterning technology. However, due to the need for very expensive equipment to reduce the feature size of the patterns, there is still room for improvement despite the increasing integration density of two-dimensional semiconductor devices.

[0006] To overcome this limitation, three-dimensional semiconductor devices, including monolithically integrated three-dimensional circuits, have recently been proposed. Summary of the Invention

[0007] An exemplary embodiment of the present invention provides a three-dimensional semiconductor device with excellent properties.

[0008] An exemplary embodiment of the present invention provides a three-dimensional semiconductor device that can be easily manufactured.

[0009] According to an exemplary embodiment of the present invention, a three-dimensional semiconductor device includes: a lower substrate; a plurality of lower transistors disposed on the lower substrate; an upper substrate disposed on the lower transistors; a plurality of lower conductive lines disposed between the lower transistors and the upper substrate; and a plurality of upper transistors disposed on the upper substrate. At least one lower transistor is connected to a corresponding lower conductive line. Each upper transistor includes: an upper gate electrode disposed on the upper substrate; a first upper source / drain pattern disposed in the upper substrate on a first side of the upper gate electrode; and a second upper source / drain pattern disposed in the upper substrate on a second opposite side of the upper gate electrode. The upper gate electrode comprises silicon germanium (SiGe).

[0010] According to an exemplary embodiment of the present invention, a three-dimensional semiconductor device includes: a lower substrate; a plurality of lower transistors disposed on the lower substrate; an upper substrate disposed on the lower transistors; and a plurality of upper transistors disposed on the upper substrate. Each upper transistor includes: an upper gate electrode disposed on the upper substrate; a first upper source / drain pattern disposed in the upper substrate on a first side of the upper gate electrode; and a second upper source / drain pattern disposed in the upper substrate on a opposite second side of the upper gate electrode. The upper gate electrode includes a silicon-germanium (SiGe) layer doped with a dopant. The concentration of the dopant in the upper gate electrode is less than the concentration of germanium (Ge) in the upper gate electrode. Attached Figure Description

[0011] The above and other features of the inventive concept will become clearer by referring to the accompanying drawings, which describe exemplary embodiments of the inventive concept in detail, in which:

[0012] Figure 1 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention.

[0013] Figures 2 to 4 This is a cross-sectional view illustrating a method for manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the present invention.

[0014] Figure 5 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention.

[0015] Figure 6 This is a cross-sectional view illustrating a method for manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the present invention.

[0016] Figure 7 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention.

[0017] Figure 8 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention.

[0018] Figures 9 to 13 This illustrates an exemplary embodiment of the concept according to the present invention, which can be set up Figure 8 Circuit diagrams of some examples of memory cell arrays on an upper substrate.

[0019] Figure 14 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention. Detailed Implementation

[0020] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may denote the same elements.

[0021] Spatially relative terms such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature shown in the figures relative to one or more other elements or features(s). It should be understood that spatially relative terms are intended to include not only the orientation shown in the figures but also different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features would be oriented “above” those other elements or features. Thus, the exemplary terms “below” and “below” can encompass both “above” and “below” orientations.

[0022] It should be understood that when a component, such as a membrane, region, layer, or element, is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, the component may be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intermediate components present. It should also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may be one or more intermediate components present. Furthermore, it should be understood that when a component is referred to as "covering" another component, the component may be the only component covering the other component, or one or more intermediate components may also cover the other component. Other terms used to describe relationships between elements should be interpreted in a similar manner.

[0023] It should be understood that the terms "first," "second," "third," etc., are used herein to distinguish elements from each other, and the elements are not limited by these terms. Thus, a "first" element in one exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0024] The singular forms “a,” “one,” and “the” used in this article are intended to also include the plural forms unless the context explicitly indicates otherwise.

[0025] In this document, when a value is described as approximately equal to or substantially the same as or equal to another value, it should be understood that these values ​​are equal to each other within measurement error, or, if measurably unequal, are sufficiently close to be functionally equal to each other as understood by one of ordinary skill in the art. For example, the term “approximately” as used herein includes the stated value and indicates that it falls within an acceptable deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurements involved and the errors associated with a particular number of measurements (i.e., limitations of the measurement system). For example, “approximately” may mean within one or more standard deviations as understood by one of ordinary skill in the art. Furthermore, it should be understood that while a parameter may be described herein as having a particular value “approximately” according to exemplary embodiments, the parameter may be exactly that particular value, or substantially that particular value within measurement error as understood by one of ordinary skill in the art.

[0026] Figure 1 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention.

[0027] Reference Figure 1 The three-dimensional semiconductor device 10 may include a lower circuit layer 20 and an upper circuit layer 30 stacked on the lower circuit layer 20.

[0028] The lower circuit layer 20 may include a lower substrate 100 and a lower transistor TR1 disposed on the lower substrate 100. The lower substrate 100 may be a semiconductor substrate (e.g., a silicon wafer doped with p-type or n-type dopants). The lower transistor TR1 may be disposed on the top surface 100U of the lower substrate 100 and may constitute one or more electronic circuits. For example, the lower transistor TR1 may constitute a memory circuit (e.g., a DRAM circuit, an SRAM circuit, or a flash memory circuit) or a logic circuit. The logic circuit may be configured to function as a circuit with Boolean logic functions (e.g., an inverter, an AND gate, an OR gate, a NAND gate, or a NOR gate) or a circuit with storage functions (e.g., a flip-flop).

[0029] Each lower transistor TR1 may include a lower gate electrode GE1 disposed on a lower substrate 100, a lower gate insulating pattern G11 disposed between the lower substrate 100 and the lower gate electrode GE1, a lower gate spacer GSP1 disposed on a side surface of the lower gate electrode GE1, and lower source / drain patterns SD1 disposed on both sides of the lower gate electrode GE1. For example, a first lower gate spacer GSP1 may be disposed on a first side surface of the lower gate electrode GE1, and a second lower gate spacer GSP1 may be disposed on a opposite second side surface of the lower gate electrode GE1. For example, a first lower source / drain pattern SD1 may be disposed on the first side of the lower gate electrode GE1 in the lower substrate 100, and a second lower source / drain pattern SD1 may be disposed on the opposite second side of the lower gate electrode GE1 in the lower substrate 100. The lower source / drain patterns SD1 may be disposed in the lower substrate 100 and may be spaced apart from each other in a horizontal direction HD extending parallel to the top surface 100U of the lower substrate 100. For example, the lower source / drain patterns SD1 may be embedded within the lower substrate 100.

[0030] The lower gate electrode GE1 can be formed from at least one of a doped semiconductor, a conductive metal nitride, or a metal, or include at least one of a doped semiconductor, a conductive metal nitride, or a metal. For example, the lower gate electrode GE1 can include at least one of polycrystalline silicon (Si), polycrystalline silicon germanium (SiGe), or polycrystalline germanium (Ge), and in an exemplary embodiment, it can also include a dopant. The dopant can include at least one of, for example, boron (B), arsenic (As), phosphorus (P), antimony (Sb), aluminum (Al), or gallium (Ga). The lower gate insulating pattern GI1 can be formed from at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material, or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Here, the high-k dielectric material can include a material with a dielectric constant higher than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)). The lower gate spacer GSP1 may be formed of at least one of silicon oxide, silicon nitride, or silicon oxynitride, or may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0031] In an exemplary embodiment, the lower source / drain pattern SD1 can be an impurity region formed by implanting p-type or n-type dopants into the lower substrate 100. Therefore, the lower source / drain pattern SD1 can be embedded within the lower substrate 100. In an exemplary embodiment, the lower source / drain pattern SD1 can be an epitaxial pattern formed using the lower substrate 100 as a seed layer. In this case, the lower source / drain pattern SD1 can be formed from at least one of, for example, silicon germanium (SiGe), silicon (Si), or silicon carbide (SiC), or include at least one of, for example, silicon germanium (SiGe), silicon (Si), or silicon carbide (SiC), and may also include p-type or n-type dopants. The lower source / drain pattern SD1 may have a different conductivity type than the lower substrate 100.

[0032] The lower circuit layer 20 may include a first lower interlayer insulating layer 110 covering the lower transistor TR1. The first lower interlayer insulating layer 110 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0033] The lower circuit layer 20 may include a lower source / drain contact 120 and a lower gate contact 122 disposed in the first lower interlayer insulating layer 110. The lower source / drain pattern SD1 of each lower transistor TR1 may be connected to the corresponding lower source / drain contact 120, and the lower gate electrode GE1 of each lower transistor TR1 may be connected to the corresponding lower gate contact 122. The lower source / drain contact 120 and the lower gate contact 122 may be formed of, for example, metal nitrides (e.g., TiN, WN, and TaN) and / or metals (e.g., Ti, W, and Ta), or may include, for example, metal nitrides (e.g., TiN, WN, and TaN) and / or metals (e.g., Ti, W, and Ta).

[0034] The lower circuit layer 20 may include a first lower conductive line 130, a second lower conductive line 140, and a lower conductive contact 135 disposed on the first lower interlayer insulating layer 110. The second lower conductive line 140 may be spaced apart from the first lower conductive line 130 in a vertical direction VD extending perpendicularly to the top surface 100U of the lower substrate 100. For example, the vertical direction VD may intersect the horizontal direction HD. The second lower conductive line 140 may be located at a higher level than the first lower conductive line 130. In this specification, the term "level" refers to the height measured from the top surface 100U of the lower substrate 100. The lower conductive contact 135 may be disposed between the first lower conductive line 130 and the second lower conductive line 140. Each lower conductive contact 135 may connect a corresponding first lower conductive line 130 to a corresponding second lower conductive line 140. The lower source / drain contact 120 and the lower gate contact 122 may both be connected to the corresponding first lower conductive line 130. Therefore, the lower transistor TR1 can be connected to the corresponding conductive lines in the first lower conductive line 130 and the second lower conductive line 140. The first lower conductive line 130, the second lower conductive line 140, and the lower conductive contact 135 can be formed of at least one of the following: metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co), etc.) and / or conductive metal nitrides or metal carbides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbonitride (WCN), etc.), or include at least one of the following: metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co), etc.) and / or conductive metal nitrides or metal carbides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbonitride (WCN), etc.).

[0035] The lower circuit layer 20 may include a second lower interlayer insulating layer 150 disposed on the first lower interlayer insulating layer 110. The second lower interlayer insulating layer 150 may cover the first lower conductive line 130, the second lower conductive line 140, and the lower conductive contact 135. The second lower interlayer insulating layer 150 may be formed of at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, or may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0036] The upper circuit layer 30 can be stacked on the lower circuit layer 20 in the vertical direction VD. The upper circuit layer 30 may include an upper substrate 200 and an upper transistor TR2 disposed on the upper substrate 200. The upper substrate 200 may be disposed on the second lower interlayer insulating layer 150 of the lower circuit layer 20. Both the lower substrate 100 and the upper substrate 200 may have a certain thickness in the vertical direction VD. The thickness 200T of the upper substrate 200 may be less than the thickness 100T of the lower substrate 100. The upper substrate 200 may be a semiconductor substrate (e.g., a silicon wafer doped with p-type or n-type dopants). The upper transistor TR2 may be disposed on the top surface 200U of the upper substrate 200 and may constitute one or more electronic circuits. The upper transistor TR2 may constitute a memory circuit (e.g., a DRAM circuit, an SRAM circuit, or a flash memory circuit) or a logic circuit. Logic circuits can be configured to function as circuits with Boolean logic functions (e.g., inverters, AND gates, OR gates, NAND gates, or NOR gates) or circuits with storage functions (e.g., flip-flops).

[0037] Each upper transistor TR2 may include an upper gate electrode GE2 disposed on an upper substrate 200, an upper gate insulating pattern GI2 disposed between the upper substrate 200 and the upper gate electrode GE2, an upper gate spacer GSP2 disposed on a side surface of the upper gate electrode GE2, and upper source / drain patterns SD2 disposed on both sides of the upper gate electrode GE2. For example, a first upper gate spacer GSP2 may be disposed on a first side surface of the upper gate electrode GE2, and a second upper gate spacer GSP2 may be disposed on a opposite second side surface of the upper gate electrode GE2. For example, a first upper source / drain pattern SD2 may be disposed on the first side of the upper gate electrode GE2 in the upper substrate 200, and a second upper source / drain pattern SD2 may be disposed on the opposite second side of the upper gate electrode GE2 in the upper substrate 200. The upper source / drain patterns SD2 may be disposed in the upper substrate 200 and may be spaced apart from each other in the horizontal direction HD. For example, the upper source / drain patterns SD2 may be embedded within the upper substrate 200.

[0038] The upper substrate 200 may include a channel region CH, which is disposed vertically below the upper gate electrode GE2 and horizontally between the upper source / drain patterns SD2. The channel region CH may be formed of, for example, silicon, or comprise, for example, silicon. The channel region CH may serve as the channel region for each upper transistor TR2.

[0039] The upper gate electrode GE2 can be formed of, for example, polycrystalline silicon germanium (SiGe), or include, for example, polycrystalline silicon germanium (SiGe). In an exemplary embodiment, the concentration of germanium (Ge) in the upper gate electrode GE2 can be greater than or equal to about 10 at% (atomic percentage) and can be less than about 100 at%. When the concentration of germanium (Ge) in the upper gate electrode GE2 is less than about 10 at%, it may be difficult to crystallize the upper gate electrode layer at the desired process temperature during the process of depositing the upper gate electrode layer used to form the upper gate electrode GE2. The upper gate electrode GE2 may also include a dopant. The dopant may include at least one of, for example, boron (B), arsenic (As), phosphorus (P), antimony (Sb), aluminum (Al), or gallium (Ga). The concentration of the dopant in the upper gate electrode GE2 can be less than the concentration of germanium (Ge) in the upper gate electrode GE2. As an example, the dopant may be boron (B), and the concentration of boron in the upper gate electrode GE2 may be less than or equal to about 10 at%. In an exemplary embodiment, the concentration of boron in the upper gate electrode GE2 may be greater than or equal to about 1 × 10⁻⁶. 20 / cm 3 And it can be less than or equal to approximately 1 × 10 22 / cm 3 When the boron concentration in the upper gate electrode GE2 is greater than about 10 at%, it may be difficult to crystallize the upper gate electrode layer at the desired process temperature during the deposition process for forming the upper gate electrode GE2. The upper gate electrode GE2 may also include at least one of, for example, a conductive metal nitride and / or a metal.

[0040] The upper gate insulating pattern GI2 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material, or include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Here, the high-k dielectric material can include a material with a dielectric constant higher than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)). The upper gate spacer GSP2 can be formed of, for example, silicon oxide, silicon nitride, or silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0041] In an exemplary embodiment, the upper source / drain pattern SD2 can be an impurity region formed by implanting p-type or n-type dopants into the upper substrate 200. Therefore, the upper source / drain pattern SD2 can be embedded within the upper substrate 200. In an exemplary embodiment, the upper source / drain pattern SD2 can be an epitaxial pattern formed using the upper substrate 200 as a seed layer. In this case, the upper source / drain pattern SD2 can be formed from at least one of, for example, silicon germanium (SiGe), silicon (Si), or silicon carbide (SiC), or include at least one of, for example, silicon germanium (SiGe), silicon (Si), or silicon carbide (SiC), and may also include p-type or n-type dopants. The upper source / drain pattern SD2 may have a different conductivity type than the upper substrate 200.

[0042] The upper circuit layer 30 may include a first upper interlayer insulating layer 210 covering the upper transistor TR2. The first upper interlayer insulating layer 210 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0043] The upper circuit layer 30 may include upper source / drain contacts 220 and upper gate contacts 222 disposed in the first upper interlayer insulating layer 210. The upper source / drain pattern SD2 of each upper transistor TR2 may be connected to the corresponding upper source / drain contact 220, and the upper gate electrode GE2 of each upper transistor TR2 may be connected to the corresponding upper gate contact 222. The upper source / drain contacts 220 and upper gate contacts 222 may be formed of metal nitrides (e.g., TiN, WN, and TaN) and / or metals (e.g., Ti, W, and Ta), or may include metal nitrides (e.g., TiN, WN, and TaN) and / or metals (e.g., Ti, W, and Ta).

[0044] The upper circuit layer 30 may include a first upper conductive line 230, a second upper conductive line 240, and an upper conductive contact 235 disposed on the first upper interlayer insulating layer 210. The second upper conductive line 240 may be spaced apart from the first upper conductive line 230 in the vertical direction VD. The second upper conductive line 240 may be located at a higher layer than the first upper conductive line 230. The upper conductive contact 235 may be disposed between the first upper conductive line 230 and the second upper conductive line 240. Each upper conductive contact 235 can connect a corresponding first upper conductive line 230 to a corresponding second upper conductive line 240. The upper source / drain contact 220 and the upper gate contact 222 can both be connected to the corresponding first upper conductive line 230. Therefore, the upper transistor TR2 can be connected to the corresponding conductive line in the first upper conductive line 230 and the second upper conductive line 240. The first upper conductive line 230, the second upper conductive line 240, and the upper conductive contact 235 may be formed of at least one of the following: metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co) etc.) and / or conductive metal nitrides or metal carbides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbonitride (WCN) etc.), or include at least one of the following: metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co) etc.) and / or conductive metal nitrides or metal carbides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbonitride (WCN) etc.).

[0045] The upper circuit layer 30 may include a second upper interlayer insulating layer 250 disposed on the first upper interlayer insulating layer 210. The second upper interlayer insulating layer 250 may cover the first upper conductive line 230, the second upper conductive line 240, and the upper conductive contact 235. The second upper interlayer insulating layer 250 may be formed of at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, or may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0046] The three-dimensional semiconductor device 10 may include an upper through-hole 300 electrically connecting the lower circuit layer 20 to the upper circuit layer 30. The upper through-hole 300 may also be referred to herein as an upper through-hole electrode. As an example, the upper through-hole 300 may penetrate the upper substrate 200 and may be electrically disconnected from the upper substrate 200. At least one of a first lower conductive line 130 and a second lower conductive line 140 of the lower circuit layer 20 may be connected via the upper through-hole 300 to at least one of a first upper conductive line 230 and a second upper conductive line 240 of the upper circuit layer 30. As an example, at least one second lower conductive line 140 may be connected via the upper through-hole 300 to at least one first upper conductive line 230. In an exemplary embodiment, the upper through-hole 300 may be formed of at least one of, for example, a conductive metal nitride or a metal (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co)), or may include at least one of a conductive metal nitride or a metal (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co)).

[0047] In the lower circuit layer 20, the terminals of each lower transistor TR1 (e.g., the lower gate electrode GE1 and the lower source / drain pattern SD1) can be connected to the corresponding first lower conductive line 130 and the corresponding second lower conductive line 140. In the upper circuit layer 30, the terminals of each upper transistor TR2 (e.g., the upper gate electrode GE2 and the upper source / drain pattern SD2) can be connected to the corresponding first upper conductive line 230 and the corresponding second upper conductive line 240. At least one terminal of at least one lower transistor TR1 (e.g., one of the lower source / drain patterns SD1) can be electrically connected to at least one terminal of at least one upper transistor TR2 (e.g., one of the upper source / drain patterns SD2) via the corresponding first lower conductive line 130 and the second lower conductive line 140, the upper through-hole 300, and the corresponding first upper conductive line 230 and the second upper conductive line 240.

[0048] According to an exemplary embodiment of the present invention, the upper gate electrode GE2 of each upper transistor TR2 may be formed, for example, of polycrystalline silicon germanium (SiGe), or may include, for example, polycrystalline silicon germanium (SiGe). In this case, the deposition process for forming the upper gate electrode GE2 can be performed at a relatively low temperature (e.g., about 450°C or lower). Therefore, in the exemplary embodiment, the lower transistor TR1, the first lower conductive line 130 and the second lower conductive line 140, and the contacts 120, 122, and 135 in the lower circuit layer 20 can be prevented from deteriorating during the formation of the lower gate electrode GE2. Furthermore, the upper gate electrode GE2 may also include a dopant. In this case, by controlling the concentration of germanium and the dopant in the upper gate electrode GE2, the process temperature in the deposition process for forming the upper gate electrode GE2 and the electrical characteristics of the upper gate electrode GE2 can be adjusted in the exemplary embodiment. Therefore, the exemplary embodiment provides an improved process for manufacturing a three-dimensional semiconductor device with improved characteristics.

[0049] Figures 2 to 4 This is a cross-sectional view illustrating a method for manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the present invention. For ease of explanation, the previous reference... Figure 1 The described elements may be identified by the same reference numerals, and further description thereof may be omitted.

[0050] Reference Figure 2A lower transistor TR1 can be formed on the lower substrate 100. The formation of the lower transistor TR1 may include: forming a lower gate insulating pattern GI1 and a lower gate electrode GE1 sequentially stacked on the lower substrate 100; forming a lower gate spacer GSP1 on a side surface of the lower gate electrode GE1; and forming lower source / drain patterns SD1 on both sides of the lower gate electrode GE1 in the lower substrate 100. For example, a first lower gate spacer GSP1 may be formed on a first side surface of the lower gate electrode GE1, and a second lower gate spacer GSP1 may be formed on a opposite second side surface of the lower gate electrode GE1. For example, a first lower source / drain pattern SD1 may be formed on the first side of the lower gate electrode GE1 in the lower substrate 100, and a second lower source / drain pattern SD1 may be formed on the opposite second side of the lower gate electrode GE1 in the lower substrate 100. The formation of the lower gate insulating pattern GI1 and the lower gate electrode GE1 may include: depositing a lower gate insulating layer on the lower substrate 100; depositing a lower gate electrode layer on the lower gate insulating layer; and sequentially patterning the lower gate electrode layer and the lower gate insulating layer. The formation of the lower gate spacer GSP1 may include: forming a lower gate spacer layer on the lower substrate 100 on which the lower gate insulating pattern GI1 and the lower gate electrode GF1 are formed; and then anisotropically etching the lower gate spacer layer. The lower source / drain pattern SD1 may be formed, for example, by implanting p-type or n-type dopants into the lower substrate 100 or by performing a selective epitaxial growth process using the lower substrate 100 as a seed layer.

[0051] A first lower interlayer insulating layer 110 can be formed on the lower substrate 100 to cover the lower transistor TR1. The first lower interlayer insulating layer 110 can be formed by, for example, a chemical vapor deposition process.

[0052] Lower source / drain contacts 120 and lower gate contacts 122 can be formed in the first lower interlayer insulating layer 110. In an exemplary embodiment, the formation of the lower source / drain contacts 120 and lower gate contacts 122 may include: forming lower source / drain contact holes and lower gate contact holes to penetrate the first lower interlayer insulating layer 110; forming a conductive layer on the first lower interlayer insulating layer 110 to fill the lower source / drain contact holes and lower gate contact holes; and planarizing the conductive layer to expose the first lower interlayer insulating layer 110. The lower source / drain pattern SD1 of each lower transistor TR1 can be connected to the corresponding lower source / drain contact 120, and the lower gate electrode GE1 of each lower transistor TR1 can be connected to the corresponding lower gate contact 122.

[0053] A first lower conductive line 130 may be formed on the first lower interlayer insulating layer 110. As an example, the first lower conductive line 130 may be formed by depositing a first lower conductive layer on the first lower interlayer insulating layer 110 and patterning the first lower conductive layer. A portion 152 of a second lower interlayer insulating layer 150 may be formed on the first lower interlayer insulating layer 110 to cover the first lower conductive line 130. A lower conductive contact 135 may be formed on the first lower conductive line 130. In an exemplary embodiment, forming the lower conductive contact 135 may include: forming a lower conductive contact hole to penetrate a portion 152 of the second lower interlayer insulating layer 150; forming a conductive layer to fill the lower conductive contact hole; and planarizing the conductive layer to expose a portion 152 of the second lower interlayer insulating layer 150. A second lower conductive line 140 may be formed on the lower conductive contact 135. The second lower conductive line 140 may be formed by a method substantially the same as that used to form the first lower conductive line 130. The remaining portion 154 of the second lower interlayer insulation layer 150 can be formed to cover the second lower conductive line 140. The second lower interlayer insulation layer 150 can be formed, for example, by a chemical vapor deposition process.

[0054] The lower substrate 100, the lower transistor TR1, the first lower conductive line 130 and the second lower conductive line 140, the contacts 120, 122 and 135, and the first lower interlayer insulating layer 110 and the second lower interlayer insulating layer 150 can constitute the lower circuit layer 20.

[0055] A preliminary upper substrate 200P may be disposed on the second lower interlayer insulating layer 150 of the lower circuit layer 20. The preliminary upper substrate 200P may be, for example, a semiconductor substrate (e.g., a silicon wafer doped with p-type or n-type dopants). The preliminary upper substrate 200P may include a dicing layer 200A formed therein. The dicing layer 200A may be formed by implanting hydrogen or helium ions into the preliminary upper substrate 200P.

[0056] Reference Figure 3 The upper substrate 200 can be formed by removing the upper portion of the preliminary upper substrate 200P. The formation of the upper substrate 200 may include layering the upper portion of the preliminary upper substrate 200P and the lower portion of the preliminary upper substrate 200P along the dicing layer 200A. In an exemplary embodiment, a planarization process may be further performed to planarize the surface of the upper substrate 200.

[0057] An upper gate insulating layer (GIL) and an upper gate electrode layer (GEL) can be sequentially formed on the upper substrate 200. In an exemplary embodiment, both the upper gate insulating layer (GIL) and the upper gate electrode layer (GEL) can be formed using, for example, chemical vapor deposition, physical vapor deposition, and atomic layer deposition processes. The upper gate insulating layer (GIL) can be formed of at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material, or include, for example, at least one of, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Here, the high-k dielectric material can include a material with a dielectric constant higher than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)).

[0058] The upper gate electrode layer GEL can be formed of polycrystalline silicon germanium (SiGe), or include, for example, polycrystalline silicon germanium (SiGe). In an exemplary embodiment, the concentration of germanium (Ge) in the upper gate electrode layer GEL can be greater than or equal to about 10 at% and less than about 100 at%. The upper gate electrode layer GEL may also include a dopant. As an example, a dopant can be implanted into the upper gate electrode layer GEL during deposition. The upper gate electrode layer GEL may include, for example, a polycrystalline silicon germanium (SiGe) layer doped with a dopant. The dopant may include at least one of, for example, boron (B), arsenic (As), phosphorus (P), antimony (Sb), aluminum (Al), or gallium (Ga). The concentration of the dopant in the upper gate electrode layer GEL may be less than the concentration of germanium (Ge) in the upper gate electrode layer GEL. As an example, the dopant may be boron (B), and the concentration of boron in the upper gate electrode layer GEL may be less than or equal to about 10 at%. As an example, the concentration of boron in the upper gate electrode layer GEL may be greater than or equal to about 1 × 10⁻⁶. 20 / cm 3 And it can be less than or equal to approximately 1 × 10 22 / cm 3 The upper gate electrode layer (GEL) may also include at least one of a conductive metal nitride and / or a metal.

[0059] According to an exemplary embodiment of the present invention, the upper gate electrode layer GEL may be formed of silicon germanium (SiGe), or may include silicon germanium (SiGe). In this case, the deposition process for forming the upper gate electrode layer GEL can be performed at a relatively low temperature (e.g., about 450°C or lower), and the silicon germanium (SiGe) in the upper gate electrode layer GEL can be crystallized simultaneously with the deposition of the upper gate electrode layer GEL. Therefore, in the exemplary embodiment, it is not necessary to perform an additional heat treatment process for crystallizing the upper gate electrode layer GEL. Furthermore, since the deposition process for forming the upper gate electrode layer GEL is performed at a relatively low temperature (e.g., about 450°C or lower), degradation of the lower transistor TR1, the first lower conductive line 130 and the second lower conductive line 140, and the contacts 120, 122 and 135 in the lower circuit layer 20 can be prevented.

[0060] Alternatively, the upper gate electrode layer GEL may include, for example, a silicon-germanium (SiGe) layer doped with dopants. In this case, by controlling the concentrations of germanium (Ge) and dopants in the upper gate electrode layer GEL, the process temperature in the deposition process used to form the upper gate electrode layer GEL and the electrical characteristics of the upper gate electrode layer GEL can be adjusted.

[0061] Reference Figure 4 The upper gate electrode layer GEL and the upper gate insulating layer GIL can be patterned sequentially to form an upper gate electrode GE2 and an upper gate insulating pattern GI2, respectively. The upper gate electrode GE2 can be formed on the top surface 200U of the upper substrate 200, and the upper gate insulating pattern GI2 can be located between the top surface 200U of the upper substrate 200 and the upper gate electrode GE2. An upper gate spacer GSP2 can be formed on the side surface of the upper gate electrode GE2. For example, a first upper gate spacer GSP2 can be formed on a first side surface of the upper gate electrode GE2, and a second upper gate spacer GSP2 can be formed on a opposite second side surface of the upper gate electrode GE2. In an exemplary embodiment, the formation of the upper gate spacer GSP2 can include: forming an upper gate spacer layer on the upper substrate 200 on which the upper gate insulating pattern GI2 and the upper gate electrode GE2 are formed; and anisotropically etching the upper gate spacer layer.

[0062] Upper source / drain patterns SD2 can be formed in the upper substrate 200 on both sides of the upper gate electrode GE2. The upper source / drain patterns SD2 can be formed by implanting p-type or n-type dopants into the upper substrate 200 or by performing a selective epitaxial growth process using the upper substrate 200 as a seed layer. Therefore, the upper source / drain patterns SD2 can be embedded in the upper substrate 200 on the opposite side of the upper gate electrode GE2. The upper gate electrode GE2, the upper gate insulating pattern GI2, the upper gate spacer GSP2, and the upper source / drain patterns SD2 can constitute an upper transistor TR2. In an exemplary embodiment, multiple upper transistors TR2 can be formed on the top surface 200U of the upper substrate 200.

[0063] Return to reference Figure 1 A first upper interlayer insulating layer 210 can be formed on the upper substrate 200 to cover the upper transistor TR2. The first upper interlayer insulating layer 210 can be formed using, for example, a chemical vapor deposition process.

[0064] Upper source / drain contacts 220 and upper gate contacts 222 can be formed in the first upper interlayer insulating layer 210. The upper source / drain contacts 220 and upper gate contacts 222 can be formed using a method substantially the same as that used to form the lower source / drain contacts 120 and lower gate contacts 122. The upper source / drain pattern SD2 of each upper transistor TR2 can be connected to the corresponding upper source / drain contact 220, and the upper gate electrode GE2 of each upper transistor TR2 can be connected to the corresponding upper gate contact 222.

[0065] The upper through-hole 300 can penetrate the first upper interlayer insulating layer 210 and the upper substrate 200 and extend into the second lower interlayer insulating layer 150. In an exemplary embodiment, forming the upper through-hole 300 may include: forming an upper through-hole to penetrate the first upper interlayer insulating layer 210 and the upper substrate 200 and extend into the second lower interlayer insulating layer 150; forming a conductive layer on the first upper interlayer insulating layer 210 to fill the upper through-hole; and planarizing the conductive layer to expose the first upper interlayer insulating layer 210. The upper through-hole 300 can be electrically disconnected from the upper substrate 200 and can be connected to at least one of the first lower conductive line 130 and the second lower conductive line 140 of the lower circuit layer 20.

[0066] A first upper conductive line 230 may be formed on the first upper interlayer insulating layer 210. In an exemplary embodiment, the first upper conductive line 230 may be formed by a method substantially the same as that used to form the first lower conductive line 130. In an exemplary embodiment, at least one first upper conductive line 230 may be connected to an upper through-hole 300. As an example, at least one second lower conductive line 140 may be connected to at least one first upper conductive line 230 via the upper through-hole 300.

[0067] An upper conductive contact 235 and a second upper conductive line 240 can be formed on the first upper conductive line 230, and a second upper interlayer insulating layer 250 can be formed to cover the first upper conductive line 230, the second upper conductive line 240, and the upper conductive contact 235. The upper conductive contact 235, the second upper conductive line 240, and the second upper interlayer insulating layer 250 can be formed by a method substantially the same as that used to form the lower conductive contact 135, the second lower conductive line 140, and the second lower interlayer insulating layer 150.

[0068] Figure 5 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention. For ease of explanation, the following description will primarily refer to the references above. Figure 1 The description of the three-dimensional semiconductor device features different characteristics, and further descriptions of the previously described elements and techniques may be omitted.

[0069] Reference Figure 5 Each upper transistor TR2 of the upper circuit layer 30 may further include an ohmic contact CNT disposed on the upper gate electrode GE2. The ohmic contact CNT may be located between the upper gate electrode GE2 and the corresponding upper gate contact 222. The ohmic contact CNT may be used to achieve ohmic contact characteristics between the upper gate electrode GE2 and the corresponding upper gate contact 222. In an exemplary embodiment, the ohmic contact CNT may be formed of, for example, at least one of metal silicide and / or metal germanide, or include, for example, at least one of metal silicide and / or metal germanide. Apart from this difference, refer to Figure 5 The described three-dimensional semiconductor device can be compared with a reference. Figure 1 The three-dimensional semiconductor devices described are basically the same.

[0070] Figure 6 This is a cross-sectional view illustrating a method for manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the present invention. For ease of explanation, the following description will be primarily referenced to and understood by way of reference. Figures 1 to 4 The manufacturing method described has different features, and further descriptions of previously described components and technical aspects may be omitted.

[0071] Reference Figure 6 An upper substrate 200 can be formed on the lower circuit layer 20, and an upper gate insulating layer GIL and an upper gate electrode layer GEL can be sequentially formed on the upper substrate 200. The lower circuit layer 20, upper substrate 200, upper gate insulating layer GIL, and upper gate electrode layer GEL can be connected to a reference... Figure 2 and Figure 3The method described is substantially the same as that used in this study. In an exemplary embodiment, an ohmic contact layer CNL can be formed on the upper gate electrode layer GEL. The ohmic contact layer CNL can be formed using, for example, chemical vapor deposition, physical vapor deposition, and atomic layer deposition processes. The ohmic contact layer CNL can be formed from, for example, at least one of metal silicides and / or metal germanides, or includes, for example, at least one of metal silicides and / or metal germanides.

[0072] Return to reference Figure 5 The ohmic contact layer CNL, the upper gate electrode layer GEL, and the upper gate insulating layer GIL can be patterned sequentially to form the ohmic contact CNT, the upper gate electrode GE2, and the upper gate insulating pattern GI2, respectively. An upper gate spacer GSP2 can be formed on the side surface of the upper gate electrode GE2, and an upper source / drain pattern SD2 can be formed in the upper substrate 200 on both sides of the upper gate electrode GE2. For example, the upper source / drain pattern SD2 can be embedded in the upper substrate 200 on both sides of the upper gate electrode GE2. The ohmic contact CNT, the upper gate electrode GE2, the upper gate insulating pattern GI2, the upper gate spacer GSP2, and the upper source / drain pattern SD2 can constitute the upper transistor TR2. Apart from the differences described above, the method for manufacturing a three-dimensional semiconductor device according to this exemplary embodiment can be compared with the reference... Figures 1 to 4 The methods described are basically the same.

[0073] Figure 7 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention. For ease of explanation, the following description will primarily refer to the references above. Figure 1 The description of the three-dimensional semiconductor device features different characteristics, and further descriptions of the previously described elements and techniques may be omitted.

[0074] Reference Figure 7 The three-dimensional semiconductor device 10 may further include an interconnect layer 40 disposed below the lower circuit layer 20. The lower circuit layer 20 may be disposed between the interconnect layer 40 and the upper circuit layer 30. The lower circuit layer 20 and the upper circuit layer 30 may be stacked sequentially on the interconnect layer 40 in the vertical direction VD.

[0075] Interconnect layer 40 may include interconnect lines 160 and interconnect contacts 165. Some interconnect contacts 165 may connect interconnect lines 160 to each other, while other interconnect contacts 165 may connect some interconnect lines 160 to external devices. In an exemplary embodiment, interconnect lines 160 may include an uppermost interconnect line 162 disposed adjacent to the lower substrate 100 and a lowermost interconnect line 164 disposed further from the lower substrate 100 than the uppermost interconnect line 162. The uppermost interconnect line 162 may be spaced apart from the lowermost interconnect line 164 in the vertical direction VD.

[0076] Interconnect contacts 165 may be disposed between the uppermost interconnect 162 and the lowermost interconnect 164. Each uppermost interconnect 162 may be connected to a corresponding lowermost interconnect 164 via a corresponding interconnect contact 165. Other interconnect contacts 165 may connect the lowermost interconnect 164 to an external device. The interconnects 160 and interconnect contacts 165 may be formed of at least one of, for example, metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co)), or include at least one of, for example, metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co)). In an exemplary embodiment, the interconnects 160 and interconnect contacts 165 may be configured to supply power to the lower circuit layer 20 and the upper circuit layer 30. As an example, the interconnects 160 and interconnect contacts 165 may constitute a power distribution network (PDN).

[0077] Interconnect layer 40 may include an insulating layer 180 covering interconnect line 160 and interconnect contact 165. Insulating layer 180 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric material, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric material.

[0078] The lower substrate 100 of the lower circuit layer 20 may have a top surface 100U and a bottom surface 100L opposite to each other. The lower transistor TR1 of the lower circuit layer 20 may be disposed on the top surface 100U of the lower substrate 100, while the interconnect layer 40 may be disposed on the bottom surface 100L of the lower substrate 100.

[0079] The lower circuit layer 20 may include a first lower conductive line 130 disposed on the first lower interlayer insulating layer 110. The lower source / drain contact 120 and the lower gate contact 122 may both be connected to the corresponding first lower conductive line 130. In an exemplary embodiment, the second lower conductive line 140 and the lower conductive contact 135 may be omitted.

[0080] The three-dimensional semiconductor device 10 may include an upper through-hole 300 for electrically connecting the lower circuit layer 20 to the upper circuit layer 30 and a lower through-hole 310 for electrically connecting the lower circuit layer 20 to the interconnect layer 40. The lower through-hole 310 may also be referred to herein as a lower through-hole electrode. In an exemplary embodiment, the upper through-hole 300 may penetrate the upper substrate 200 of the upper circuit layer 30, and the lower through-hole 310 may penetrate the lower substrate 100 of the lower circuit layer 20. The upper through-hole 300 and the lower through-hole 310 may be electrically disconnected from the upper substrate 200 and the lower substrate 100, respectively.

[0081] At least one of the first lower conductive lines 130 of the lower circuit layer 20 can be connected to at least one of the first upper conductive lines 230 and the second upper conductive lines 240 of the upper circuit layer 30 via the upper through-via 300. As an example, at least one first lower conductive line 130 can be connected to at least one first upper conductive line 230 via the upper through-via 300. At least one first lower conductive line 130 of the lower circuit layer 20 can be connected to at least one interconnect line 160 of the interconnect layer 40 via the lower through-via 310. As an example, at least one first lower conductive line 130 can be connected to at least one uppermost interconnect line 160 via the lower through-via 310. Both the upper through-via 300 and the lower through-via 310 can be formed of at least one of, for example, conductive metal nitrides and / or metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co)), or include at least one of, for example, conductive metal nitrides and / or metals (e.g., copper (Cu), ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co)).

[0082] At least one terminal of a lower transistor TR1 (e.g., one of the lower source / drain patterns SD1) can be electrically connected to a terminal of at least one upper transistor TR2 (e.g., one of the upper source / drain patterns SD2) via a corresponding first lower conductive line 130, an upper through-via 300, and a corresponding first upper conductive line 230 and a second upper conductive line 240. At least one terminal of a lower transistor TR1 (e.g., one of the lower source / drain patterns SD1) can be connected to a corresponding first lower conductive line 130, a lower through-via 310, and a corresponding interconnect 160.

[0083] Apart from the differences described above, the three-dimensional semiconductor device according to this exemplary embodiment can be compared with the above-mentioned references. Figure 1 The three-dimensional semiconductor devices described are basically the same.

[0084] Figure 8 This is a cross-sectional view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention. Figures 9 to 13 This illustrates an exemplary embodiment of the concept according to the present invention, which can be set up Figure 8 The circuit diagrams show some examples of the memory cell array 50 on the upper substrate 200. For ease of illustration, the following description will primarily refer to the above references. Figure 1 The description of the three-dimensional semiconductor device features different characteristics, and further descriptions of the previously described elements and techniques may be omitted.

[0085] Reference Figure 8 The upper circuit layer 30 may include a memory cell array 50 disposed on the upper substrate 200. On the upper substrate 200, the memory cell array 50 may be horizontally spaced from the upper transistor TR2.

[0086] Reference Figure 8 and Figure 9 In an exemplary embodiment, the storage cell array 50 may be a two-dimensional NAND flash memory storage cell array. For example, the storage cell array 50 may include a plurality of cell strings CSTRs. Each cell string CSTR may include a string select transistor SST connected to a string select line SSL and multiple word lines WL0-WL respectively. n Multiple memory cell transistors (MCTs) (where n is a natural number) and a ground select transistor (GST) connected to the ground select line (GSL). The series select transistor (SST) can be connected to multiple bit lines BL0-BL1. m (where m is a natural number) and the ground selection transistor GST can be connected to the common source line CSL. Bit lines BL0-BL m It can be extended on the first direction D1, and the serial select line SSL and word lines WL0-WL can be selected. n The ground selection line GSL can extend in a second direction D2 that intersects the first direction D1. The first direction D1 and the second direction D2 can be parallel to the top surface 200U of the upper substrate 200.

[0087] Serial select line SSL, word lines WL0-WL n The ground select line GSL can be set on the upper substrate 200, and can be placed at approximately the same level as the upper substrate 200. Serial select line SSL, word lines WL0-WL n The ground select line (GSL) can be used as the gate electrode of the string select transistor (SST), the memory cell transistor (MCT), and the ground select transistor (GST), respectively. Each memory cell transistor (MCT) can include a data storage element.

[0088] Reference Figure 8 and Figure 10 In an exemplary embodiment, the storage cell array 50 may be a three-dimensional NAND flash memory storage cell array. For example, the storage cell array 50 may include a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0089] The common source line CSL can be, for example, a conductive thin film disposed on the upper substrate 200 or an impurity region formed in the upper substrate 200. The bit line BL can be a conductive pattern (e.g., a metal line) spaced apart from the upper substrate 200 on a third direction D3 perpendicular to the top surface 200U of the upper substrate 200. The bit lines BL can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. Multiple cell strings CSTRs can be connected in parallel to each bit line BL. The cell strings CSTRs can be collectively connected to the common source line CSL. In an exemplary embodiment, multiple common source lines CSL can be arranged two-dimensionally on the upper substrate 200. Here, the same voltage can be applied to the common source line CSL, but in an exemplary embodiment, the potential of the common source line CSL can be controlled independently.

[0090] Each cell string (CSTR) can consist of a ground select transistor (GST) coupled to the common source line (CSL), a string select transistor (SST) coupled to the bit line (BL), and multiple memory cell transistors (MCTs) disposed between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCTs) can be connected in series.

[0091] The common source line CSL can be connected to the source of the ground select transistor GST. The ground select line GSL, multiple word lines WL0-WL3, and string select line SSL, located between the common source line CSL and the bit line BL, can be used as the gate electrodes of the ground select transistor GST, the memory cell transistor MCT, and the string select transistor SST, respectively. The ground select line GSL, multiple word lines WL0-WL3, and string select line SSL can be stacked on the upper substrate 200 on the third-direction D3. Each memory cell transistor MCT can include a data storage element.

[0092] Reference Figure 8 and Figure 11 In an exemplary embodiment, the memory cell array 50 may be a three-dimensional flash memory cell array. For example, the memory cell array 50 may include a common source line CSL, a bit line BL, and a cell string CSTR between the common source line CSL and the bit line BL. The common source line CSL may be, for example, a conductive layer or conductive pattern disposed on the upper substrate 200, and the bit line BL may be, for example, a conductive pattern (e.g., a metal line) disposed on the upper substrate 200. The common source line CSL and the bit line BL may be spaced apart from the upper substrate 200 in a direction perpendicular to the top surface 200U of the upper substrate 200.

[0093] Cell strings (CSTRs) can be disposed between the upper substrate 200 and the common source line (CSL) and between the upper substrate 200 and the bit line (BL). A cell string (CSTR) may include an upper string (CSTR1) connected to the bit line (BL) and a lower string (CSTR2) connected to the common source line (CSL). The upper string (CSTR1) can be connected to the lower string (CSTR2) via a back gate transistor (BGT). The back gate transistor (BGT) can be controlled by a back gate line (BG) disposed on the upper substrate 200. The upper string (CSTR1) may include a string select transistor (SST) coupled to the bit line (BL) and multiple upper memory cell transistors (MCT1) disposed between the string select transistor (SST) and the back gate transistor (BGT). The string select transistor (SST) and the upper memory cell transistors (MCT1) may be connected in series. The lower string (CSTR2) may include a ground select transistor (GST) coupled to the common source line (CSL) and multiple lower memory cell transistors (MCT2) disposed between the ground select transistor (GST) and the back gate transistor (BGT). The ground select transistor (GST) and the lower memory cell transistors (MCT2) may be connected in series. Both the upper storage cell transistor MCT1 and the lower storage cell transistor MCT2 can include data storage elements.

[0094] Reference Figure 8 and Figure 12 In an exemplary embodiment, the memory cell array 50 may be a variable resistance memory cell array. The variable resistance memory cell array may include at least one of magnetic random access memory (MRAM), phase-change RAM (PRAM), or resistive RAM (RRAM) elements. The memory cell array 50 may include a first conductive line L1, a second conductive line L2 intersecting the first conductive line L1, and unit memory cells MC disposed at each intersection of the first conductive line L1 and the second conductive line L2. The first conductive line L1 and the second conductive line L2 may be disposed on an upper substrate 200 and may extend in a direction parallel to the top surface 200U of the upper substrate 200. The first conductive line L1 and the second conductive line L2 may intersect each other. When measured from the top surface 200U of the upper substrate 200, the second conductive line L2 may be disposed at a level higher than the first conductive line L1.

[0095] The storage cell MC may include a variable resistor element VR and a selection element SE. The variable resistor element VR and the selection element SE may be connected in series between the first conductive line L1 and the second conductive line L2.

[0096] A variable resistive element VR can include a data storage element. The variable resistive element VR can include a material with variable resistance properties, thus allowing it to be used as a data storage element. In an exemplary embodiment, the variable resistive element VR can include a magnetic tunnel junction pattern having a fixed layer, a free layer, and a tunnel barrier layer between the fixed and free layers. Here, the fixed layer can have a fixed magnetization direction, while the free layer can have a switchable magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the fixed layer. In this case, the memory cell MC can constitute an MRAM cell. In an exemplary embodiment, the variable resistive element VR can include a material whose phase can change to one of a crystalline structure and an amorphous structure depending on its temperature. For example, the variable resistive element VR can include a compound containing at least one of chalcogen elements (e.g., Te and Se) and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. The variable resistance element VR may include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, or InSbTe, or may have a superlattice structure in which Ge-containing layers (e.g., GeTe layers) and Ge-free layers (e.g., SbTe layers) are repeatedly stacked. In this case, the memory cell MC may constitute a PRAM cell.

[0097] The selection element SE can be configured to selectively control the current flowing through the variable resistive element VR. For example, the selection element SE may include a bipolar transistor or a metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, the memory cell MC may also include a third conductive line for controlling the selection element SE. In an exemplary embodiment, the selection element SE may include a bidirectional threshold switch (OTS) device having a nonlinear (e.g., S-shaped) IV curve based on the threshold switching phenomenon.

[0098] Reference Figure 8 and Figure 13In an exemplary embodiment, the memory cell array 50 may be a dynamic random access memory (DRAM) cell array. For example, the memory cell array 50 may include a word line WL, a bit line BL intersecting the word line WL, and a plurality of memory cells MC. Each memory cell MC may be connected to a corresponding word line WL and a corresponding bit line BL. Each memory cell MC may include a cell transistor CTR connected to the corresponding word line WL and a capacitor CA connected to a terminal of the cell transistor CTR. The drain region of the cell transistor CTR may be connected to the corresponding bit line BL, and the source region of the cell transistor CTR may be connected to the capacitor CA. The cell transistor CTR may be configured to selectively control the current flowing to the capacitor CA. Each memory cell MC may store data "0" or "1" depending on the amount of charge stored in the capacitor CA.

[0099] Return to reference Figure 8 Apart from the differences described above, the three-dimensional semiconductor device according to this exemplary embodiment can be compared with the reference... Figure 1 The three-dimensional semiconductor devices described are basically the same.

[0100] Figure 14 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention. For ease of explanation, the following description will primarily refer to [reference needed]. Figure 1 The description of the three-dimensional semiconductor device features different characteristics, and further descriptions of the previously described elements and techniques may be omitted.

[0101] Reference Figure 14 In an exemplary embodiment, the three-dimensional semiconductor device 10 may further include an intermediate transistor TR3 disposed below the upper circuit layer 30. The upper substrate 200 of the upper circuit layer 30 may have a top surface 200U and a bottom surface 200L opposite to each other. The upper transistor TR2 of the upper circuit layer 30 may be disposed on the top surface 200U of the upper substrate 200, while the intermediate transistor TR3 may be disposed on the bottom surface 200L of the upper substrate 200. The intermediate transistor TR3 may be disposed in a second lower interlayer insulating layer 150 of the lower circuit layer 20. The intermediate transistor TR3 may be configured to adjust the threshold voltage of the upper transistor TR2.

[0102] Each intermediate transistor TR3 may include a back gate electrode BGE disposed on the bottom surface 200L of the upper substrate 200 and a back gate insulating layer BGI between the back gate electrode BGE and the upper substrate 200. The back gate electrode BGE may be formed of, for example, at least one of a metal and / or a conductive metal nitride, or include at least one of a metal and / or a conductive metal nitride, and the back gate insulating layer BGI may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material, or include at least one of a silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Here, the high-k dielectric material may include a material with a dielectric constant higher than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)).

[0103] The intermediate transistor TR3 can be located at a higher level than the first lower conductive line 130 and the second lower conductive line 140 of the lower circuit layer 20. Apart from the differences mentioned above, refer to... Figure 14 The described three-dimensional semiconductor device can be compared with a reference. Figure 1 The three-dimensional semiconductor devices described are basically the same.

[0104] According to an exemplary embodiment of the present invention, the upper gate electrode of each upper transistor may be formed of or comprise polycrystalline silicon germanium (SiGe). In this case, the deposition process for forming the upper gate electrode can be performed at a relatively low temperature (e.g., about 450°C or lower). Therefore, in the exemplary embodiment, the structure constituting the lower circuit layer can be prevented from deteriorating during the formation of the upper gate electrode. Furthermore, the upper gate electrode also includes a dopant. In this case, by controlling the concentrations of germanium and dopant in the upper gate electrode, the process temperature in the deposition process for forming the upper gate electrode and the electrical characteristics of the upper gate electrode can be adjusted. Therefore, the exemplary embodiment provides an improved method for manufacturing a three-dimensional semiconductor device with improved characteristics.

[0105] In an exemplary embodiment of the present invention, a three-dimensional memory array is provided. The three-dimensional memory array is monolithically formed in an array of memory cells at one or more physical levels, the memory cell array having active regions disposed above a silicon substrate and circuitry associated with the operation of these memory cells, regardless of whether such associated circuitry is above or within the substrate. The term "monolithic" means that each layer of the array is deposited directly on the corresponding layer of the next lower level of the array.

[0106] In an exemplary embodiment of the present invention, the three-dimensional memory array includes vertically oriented vertical NAND strings, such that at least one memory cell is situated above another memory cell. The at least one memory cell may include a charge trap layer.

[0107] Configurations suitable for three-dimensional memory arrays are described by reference to the following patent documents incorporated herein: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0108] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: Lower substrate; Multiple lower transistors disposed on the lower substrate; An upper substrate disposed on the lower transistor; Multiple lower conductive lines are disposed between the lower transistor and the upper substrate; Multiple upper transistors disposed on the upper substrate; Multiple upper conductive lines are disposed on the upper transistor; as well as The upper through-hole penetrates the upper substrate. Wherein, at least one of the lower transistors is connected to a corresponding lower conductive line, and at least one of the upper transistors is connected to a corresponding upper conductive line. Each of the upper transistors includes: The upper gate electrode is disposed on the upper substrate; A first upper source / drain pattern is formed in the upper substrate on the first side of the upper gate electrode; and A second upper source / drain pattern is disposed in the upper substrate on the second side opposite to the upper gate electrode. Each of the lower transistors includes: The lower gate electrode is disposed on the lower substrate; A first lower source / drain pattern is formed in the lower substrate on the first side of the lower gate electrode; and A second lower source / drain pattern is disposed in the lower substrate on the second side opposite to the lower gate electrode. Wherein, the upper gate electrode comprises polycrystalline silicon germanium, and the lower gate electrode comprises polycrystalline silicon or polycrystalline germanium, and Wherein, at least one terminal of the lower transistor is electrically connected to at least one terminal of the upper transistor through a corresponding lower conductive line, an upper through-hole, and a corresponding upper conductive line.

2. The three-dimensional semiconductor device according to claim 1, wherein, The upper substrate includes a channel region disposed below the upper gate electrode, and the channel region includes silicon.

3. The three-dimensional semiconductor device according to claim 1, wherein, The concentration of germanium in the upper gate electrode is greater than or equal to 10 at% and less than 100 at%.

4. The three-dimensional semiconductor device according to claim 1, wherein, The upper gate electrode also includes a dopant.

5. The three-dimensional semiconductor device according to claim 4, wherein, The dopant includes at least one of boron, arsenic, phosphorus, antimony, aluminum, or gallium.

6. The three-dimensional semiconductor device according to claim 4, wherein, The dopant includes boron, and the concentration of boron in the upper gate electrode is less than or equal to 10 at%.

7. The three-dimensional semiconductor device according to claim 4, wherein, The concentration of the dopant in the upper gate electrode is less than the concentration of germanium in the upper gate electrode.

8. The three-dimensional semiconductor device according to claim 1, wherein, Each of the upper transistors includes an upper gate insulating pattern between the upper substrate and the upper gate electrode.

9. The three-dimensional semiconductor device according to claim 1, wherein, At least one of the lower conductive lines is connected to at least one of the upper conductive lines through the upper through-hole.

10. The three-dimensional semiconductor device according to claim 1, further comprising: Multiple interconnect lines disposed below the lower substrate; as well as The lower through-hole penetrates the lower substrate. At least one of the lower conductive lines is connected to at least one of the interconnect lines through the lower through-hole.

11. The three-dimensional semiconductor device according to claim 1, wherein, Each of the upper transistors also includes an ohmic contact disposed on the upper gate electrode.

12. A three-dimensional semiconductor device, comprising: Lower substrate; Multiple lower transistors disposed on the lower substrate; An upper substrate disposed on the lower transistor; A through-hole penetrating the upper substrate; Multiple lower conductive lines are disposed between the lower transistor and the upper substrate; Multiple upper transistors disposed on the upper substrate; as well as Multiple upper conductive lines disposed on the upper transistor, Each of the upper transistors includes: The upper gate electrode is disposed on the upper substrate; A first upper source / drain pattern is formed in the upper substrate on the first side of the upper gate electrode; and A second upper source / drain pattern is disposed in the upper substrate on the second side opposite to the upper gate electrode. Each of the lower transistors includes: The lower gate electrode is disposed on the lower substrate; A first lower source / drain pattern is formed in the lower substrate on the first side of the lower gate electrode; and A second lower source / drain pattern is disposed in the lower substrate on the second side opposite to the lower gate electrode. The upper gate electrode includes a polycrystalline silicon-germanium layer doped with a dopant, and the concentration of the dopant in the upper gate electrode is less than the concentration of germanium in the upper gate electrode. The lower gate electrode comprises polycrystalline silicon or polycrystalline germanium. In this configuration, at least one terminal of the lower transistor is directly connected to the corresponding lower conductive line via a lower conductive contact, and at least one terminal of the upper transistor is directly connected to the corresponding upper conductive line via an upper conductive contact. Wherein, at least one terminal of the lower transistor is electrically connected to at least one terminal of the upper transistor via a corresponding lower conductive line, the upper conductive contact, the lower conductive contact, and the corresponding upper conductive line, and The upper through-hole extends over the upper substrate and is configured to be adjacent to the upper gate electrode of at least one of the upper transistors over the upper substrate.

13. The three-dimensional semiconductor device according to claim 12, wherein, The upper substrate includes a channel region disposed below the upper gate electrode, and the channel region includes silicon.

14. The three-dimensional semiconductor device according to claim 12, wherein, Each of the upper transistors includes an upper gate insulating pattern between the upper substrate and the upper gate electrode.

15. The three-dimensional semiconductor device according to claim 12, in, At least one of the lower conductive lines is connected to at least one of the upper conductive lines through the upper through-hole.

16. The three-dimensional semiconductor device according to claim 15, further comprising: Multiple interconnect lines disposed below the lower substrate; as well as The lower through-hole penetrates the lower substrate. At least one of the lower conductive lines is connected to at least one of the interconnect lines through the lower through-hole.

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