Display device

Abstract

A display device includes a substrate, a transistor provided over the substrate, a first insulating layer provided over the transistor, and a first pixel electrode and a second pixel electrode provided over the first insulating layer so as to be adjacent to each other. The first insulating layer includes a first opening between the first pixel electrode and the second pixel electrode.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0085965, filed on July 16, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The disclosure relates to a display device capable of reducing the chance of its pixel shrinkage. BACKGROUND

[0004] An emissive display device can include light emitting diodes (LEDs) corresponding to pixels, and can display an image by controlling the brightness of each of the light emitting diodes. Unlike a light-receiving type display device such as a liquid crystal display, the emissive display device can not need a separate light source, thereby reducing its thickness and weight. The emissive display device exhibits characteristics such as high brightness, high contrast, high color reproducibility, and high response speed to display high-quality images.

[0005] Accordingly, the emissive display device can be applied to various electronic devices including mobile devices such as smartphones and tablet computers, monitors, and televisions, and can also be suitable for use as a display device for vehicles.

[0006] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and as such it can contain information that does not form the prior art that can be already known in this technical field prior to the filing date of the present application. SUMMARY

[0007] Embodiments provide a display device having improved reliability via a reduction in the chance of its pixel shrinkage.

[0008] A display device according to an embodiment can include a substrate, a transistor disposed on the substrate, a first insulating layer disposed on the transistor, and a first pixel electrode and a second pixel electrode disposed adjacent to each other on the first insulating layer. The first insulating layer can include a first opening disposed between the first pixel electrode and the second pixel electrode.

[0009] The first pixel electrode can not overlap the first opening, and the second pixel electrode can not overlap the first opening.

[0010] The first insulating layer can include a contact hole overlapping a source electrode or a drain electrode of the transistor, and the first opening can be spaced apart from the contact hole.

[0011] The first insulating layer can include an organic insulating material.

[0012] The first opening can be around a peripheral of at least one of the first pixel electrode and the second pixel electrode.

[0013] The display device can further include a third pixel electrode disposed on the first insulating layer adjacent to the first pixel electrode and the second pixel electrode. The first opening can be disposed outside a region between the first pixel electrode and the third pixel electrode.

[0014] The first insulating layer can be continuously disposed on the first pixel electrode and the third pixel electrode in a plan view.

[0015] The display device can further include a second insulating layer disposed between the transistor and the first insulating layer, and the second insulating layer can include a portion overlapping the first opening.

[0016] The display device can further include a third insulating layer disposed on the first insulating layer, and the third insulating layer can include a second opening overlapping the first pixel electrode and the second pixel electrode.

[0017] The third insulating layer can include a portion that can contact the second insulating layer.

[0018] The third insulating layer can have a groove overlapping the first opening.

[0019] The third insulating layer can have a third opening overlapping the first opening.

[0020] The display device can further include a first emission member disposed on the first pixel electrode, a second emission member disposed on the second pixel electrode, and a common electrode disposed on the first emission member and the second emission member. The common electrode can include a portion that can contact the second insulating layer through the third opening.

[0021] A display device according to an embodiment can include a substrate, a transistor disposed on the substrate, a first insulating layer disposed on the transistor, and a first light emitting diode and a second light emitting diode disposed adjacent to each other on the first insulating layer.

[0022] The first insulating layer can include an opening disposed between a first emission member of the first light emitting diode and a second emission member of the second light emitting diode.

[0023] The display device can include a second insulating layer disposed between the transistor and the first insulating layer, and the second insulating layer can include a portion overlapping the opening.

[0024] The first insulating layer and the second insulating layer can each include a contact hole overlapping the source electrode or the drain electrode of the transistor, and the opening can be spaced apart from the contact hole.

[0025] The first light emitting diode can include a first electrode disposed on the first insulating layer, and a second electrode disposed on the first emission member. The first electrode can be connected to the source electrode or the drain electrode through the contact hole.

[0026] The first electrode can not overlap the opening.

[0027] The opening can be around a periphery of the first electrode.

[0028] The display device can further include a third light emitting diode disposed on the first insulating layer adjacent to the first light emitting diode and the second light emitting diode, and the third light emitting diode can include a third emission member. The opening can be disposed outside a region between the first emission member and the third emission member.

[0029] In a plan view, the first insulating layer can be continuously disposed on the first emission member and the third emission member.

[0030] The display device can further include a third insulating layer disposed on the first insulating layer. The third insulating layer can include a portion that can contact the second insulating layer.

[0031] The third insulating layer can include a recess or an opening, and the recess or the opening of the third insulating layer can overlap the opening of the first insulating layer.

[0032] According to an embodiment, it is possible to provide a display device having improved reliability. In particular, it is possible to prevent pixel damage or a reduction in the light emitting area of a pixel due to outgassing that can occur in an insulating layer including an organic insulating material of a display device. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A plan view of a display device according to an embodiment is illustrated.

[0034] Figure 2 A plan view of a display area of a display device according to an embodiment is illustrated.

[0035] Figure 3 A schematic cross-sectional view taken along line A-A' of Figure 2

[0036] Figure 4 ​It shows along Figure 2 A schematic cross-sectional view of line B-B'.

[0037] Figure 5 The figures shown illustrate color changes of a display device according to an embodiment and a display device according to a comparative example.

[0038] Figures 6 to 10 Top views of the display area of ​​the display device according to an embodiment are shown.

[0039] Figure 11 A top view of the display area according to an embodiment is shown.

[0040] Figure 12 It shows along Figure 11 A schematic cross-sectional view of the line C-C'.

[0041] Figure 13 It shows along Figure 11 A schematic cross-sectional view of the line C-C'.

[0042] Figure 14 The figure shown illustrates the results of evaluating the luminous area ratio based on the reduction in the thickness of the insulating layer. Detailed Implementation

[0043] This disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit and scope of the embodiments described herein.

[0044] In order to clearly describe the inventive concept, parts that are not related to the description may be omitted, and throughout this disclosure, the same reference numerals denote the same or similar constituent elements.

[0045] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, the embodiments may not be limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, areas, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers, films, panels, and areas are exaggerated for better understanding and ease of description.

[0046] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may be (multiple) intermediate elements between them. In contrast, when an element is referred to as being "directly on" another element, there may be no intermediate elements between them. The terms "above" or "on" refer to being located on or below a portion of an object, and do not necessarily mean being on the upper side of the object based on the direction of gravity.

[0047] Unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. As used herein the term "and / or" can encompass any one or more of the associated listed items. Expressions such as "at least one of," when preceding the list of elements, modify the entire list of elements and do not modify the list of elements individually.

[0048] In the drawings, a reference symbol x for indicating a direction can indicate a first direction, y can be a second direction perpendicular to the first direction, and z can be a third direction perpendicular to the first direction and the second direction. The first direction x, the second direction y, and the third direction z can correspond to a horizontal direction, a vertical direction, and a thickness direction of a display device, respectively.

[0049] In situations in which particular embodiments can differ from the described order, particular process sequences can be performed in a different order from the described ordering. For example, two sequentially described processes can be executed substantially concurrently or in reverse order, depending upon the particular embodiments.

[0050] "About" or "approximately," as used herein, includes the recited value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0051] It will be understood that, although the terms "first," "second," etc. can be used herein to describe various components, these components should not be limited by these terms. The terms can be only used to distinguish one component from another.

[0052] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0053] In the following embodiments, it will be understood that when an element, region, or layer is referred to as being "on" or "connected to" another element, region, or layer, it can be directly on or connected to the other element, region, or layer, or intervening elements, regions, or layers can be present. For example, in the present specification, it will be understood that when an element, region, or layer is referred to as being in contact with or electrically connected to another element, region, or layer, it can be directly in contact with or electrically connected to the other element, region, or layer, or intervening elements, regions, or layers can be present.

[0054] Further, the phrase "in plan view" refers to a situation where the subject portion is viewed from above, and the phrase "in cross-section view" refers to a situation where a cross-section taken by cutting the subject portion vertically is viewed from the side. In addition, the term "overlapping" or "overlapped" means that a first object can be above or below a second object or can be to the side of the second object, and vice versa. In addition, the term "overlapping" can include layering, stacking, facing, extending over, covering or partially covering, or any other suitable term as would be recognized and understood by one of ordinary skill in the art. The terms "face" and "facing" mean that a first element can be directly or indirectly opposite a second element. A first element and a second element can be understood to be indirectly opposite each other, although still facing each other, in the case where a third element is interposed between the first element and the second element. When elements are described as "not overlapping" or "to not overlap" another element, this can include the elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as would be recognized and understood by one of ordinary skill in the art. When a layer, region, substrate, or area is referred to as "on" another layer, region, substrate, or area, it can be directly on the other layer, region, substrate, or area or an intervening layer, region, substrate, or area can exist therebetween. Conversely, when a layer, region, substrate, or area is referred to as "directly on" another layer, region, substrate, or area, there can not be an intervening layer, region, substrate, or area therebetween. Further, when a layer, region, substrate, or area is referred to as "under" another layer, region, substrate, or area, it can be directly under the other layer, region, substrate, or area or an intervening layer, region, substrate, or area can exist therebetween. Conversely, when a layer, region, substrate, or area is referred to as "directly under" another layer, region, substrate, or area, there can not be an intervening layer, region, substrate, or area therebetween. Further, "over" or "on" can include being positioned above or below and does not necessarily imply a direction based on gravity.

[0055] For ease of description, spatially relative terms, such as "below", "beneath", "lower", "above", "upper" and the like, can be used herein for the purpose of describing elemental relationships between one element or component and another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, in the event the device is inverted, elements described as "below" or "beneath" other elements or components would then be oriented "above" the other elements or components. Thus, the exemplary term "below" can encompass both a position and an orientation. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are to be interpreted accordingly.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.

[0057] Figure 1 A plan view of a display device according to an embodiment is illustrated.

[0058] Referring to Figure 1 , the display device can include a display panel 10, a flexible printed circuit film 20 bonded to the display panel 10, and a driving unit including an integrated circuit chip 30.

[0059] The display panel 10 can include a display area DA and a non-display area NA, the display area DA corresponding to a screen on which an image can be displayed. Circuits and / or signal lines for generating and / or transferring various signals and voltages applied to the display area DA can be disposed in the non-display area NA. The non-display area NA can surround a periphery of the display area DA or be around the periphery of the display area DA. In Figure 1 , the inside and outside of the dotted quadrangle correspond to the display area DA and the non-display area NA, respectively.

[0060] Pixels PX can be disposed in the display area DA of the display panel 10 in a matrix form. Signal lines such as gate lines (also referred to as scan lines), data lines, and driving voltage lines can also be disposed in the display area DA. Each of the pixels PX can be connected with the gate lines, the data lines, the driving voltage lines to receive gate signals (also referred to as scan signals), data signals, driving voltages ELVDD.

[0061] A touch sensor for detecting a touch and / or a non-contact touch of a user can be disposed in the display area DA. Although the display area DA can have a substantially rectangular shape, as illustrated, the display area DA can have various shapes such as a polygonal shape, a circular shape, and an elliptical shape, etc.

[0062] A pad portion PP can be disposed in the non-display area NA of the display panel 10, and pads for receiving signals from the outside of the display panel 10 can be arranged in the pad portion PP. The pad portion PP can be disposed to extend in a first direction x along one edge of the display panel 10. The flexible printed circuit film 20 can be bonded to the pad portion PP, and pads of the flexible printed circuit film 20 can be electrically connected to the pads of the pad portion PP.

[0063] The driving unit can be disposed in the non-display area NA of the display panel 10 to generate and / or process various signals for driving the display panel 10. The driving unit can include a data driver for applying a data signal to a data line, a gate driver for applying a gate signal to a gate line, and a signal controller for controlling the data driver and the gate driver. The pixels PX can receive the data signal in a predetermined timing depending on the gate signal generated by the gate driver. The gate driver can be integrated in the display panel 10 and can be disposed on at least one side of the display area DA. The data driver and the signal controller can be provided as an integrated circuit chip (also referred to as a driving IC chip) 30. The integrated circuit chip 30 can be mounted in the non-display area NA of the display panel 10. The integrated circuit chip 30 can be mounted on the flexible printed circuit film 20 or the like to be electrically connected to the display panel 10.

[0064] The following description will be made with reference to Figures 2 to 4 The display device according to the embodiments is described based on the display area DA.

[0065] Figure 2 A top view of the display area of the display device according to the embodiments is shown, Figure 3 a schematic cross-sectional view taken along Figure 2 the line A-A' of FIG. 1, and Figure 4 a schematic cross-sectional view taken along Figure 2 the line B-B' of FIG. 1.

[0066] Referring to Figure 2 , a display area DA in which, for example, approximately 12 pixels PX1, PX2, and PX3 are disposed is shown. In the display area DA shown in Figure 2 , the pixels PX1, PX2, and PX3 can be repeatedly disposed in a first direction x and a second direction y. The three adjacent pixels PX1, PX2, and PX3 can display different primary colors. The three pixels PX1, PX2, and PX3 can constitute one pixel unit PU. The primary colors can be red, green, and blue. Each of the pixels PX1, PX2, and PX3 can display one color, i.e., red, green, or blue. For example, the pixel PX1 can be a red pixel, the pixel PX2 can be a green pixel, and the pixel PX3 can be a blue pixel. The pixel unit PU can be repeatedly disposed in the display area DA in a matrix form.

[0067] In other embodiments, the pixel unit PU can include more than three pixels. The pixel unit PU can include pixels capable of displaying colors that can be different from any of the colors of the three pixels PX1, PX2, and PX3. The pixel unit PU can include pixels capable of displaying colors that are the same or similar to any of the colors of the three pixels PX1, PX2, and PX3. The pixel unit PU can not include any of the three pixels PX1, PX2, and PX3.

[0068] Each of the pixels PX1, PX2, PX3 can be referred to as a sub-pixel, and the pixel unit PU can be referred to as a pixel. Hereinafter, the pixels PX1, PX2, PX3 and the pixel unit PU are described with reference to the drawings cited.

[0069] Referring to Figures 2 to 4 , the display panel 10 can include several layers, wirings, and devices that can be stacked on the substrate 110 to configure and drive the pixels PX1, PX2, and PX3.

[0070] The substrate 110 can include an insulating material such as glass or plastic. The substrate 110 can include at least one barrier layer for preventing moisture or the like from permeating from the outside. The barrier layer can be an inorganic insulating material such as silicon oxide SiO x and silicon nitride SiN x .

[0071] A buffer layer 120 can be disposed on the substrate 110. The buffer layer 120 can block impurities that can be diffused from the substrate 110 to the semiconductor layer ACT, and reduce stress that can be applied to the substrate 110 during formation of the semiconductor layer ACT. The buffer layer 120 can include an inorganic insulating material such as silicon oxide (SiO x ) and silicon nitride (SiN x ).

[0072] The semiconductor layer ACT of the transistor TR can be disposed on the buffer layer 120. The semiconductor layer ACT can include a channel region that can overlap or face the gate electrode G of the transistor TR, and a source region and a drain region located at opposite sides of the channel region. The semiconductor layer ACT can include polysilicon, amorphous silicon, or an oxide semiconductor.

[0073] An insulating layer 141 can be disposed on the semiconductor layer ACT. The insulating layer 141 can be referred to as a first gate insulating layer. The insulating layer 141 can include an inorganic insulating material such as silicon oxide (SiO x ) and silicon nitride (SiN x ).

[0074] A first gate conductor that can include the gate line 121, the gate electrode G, and the first electrode C1 of the capacitor CS can be disposed on the insulating layer 141.

[0075] Another insulating layer 142 can be disposed on the insulating layer 141 and the first gate conductor. The insulating layer 142 can be referred to as a second gate insulating layer. The insulating layer 142 can include an inorganic insulating material such as silicon oxide (SiO x ) and silicon nitride (SiN x ).

[0076] The second gate conductor can include a second electrode C2 of the capacitor CS disposed on the insulating layer 142. The first gate conductor and / or the second gate conductor can include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti), or a metal alloy thereof. The first gate conductor and / or the second gate conductor can include a single layer or multiple layers.

[0077] Another insulating layer 160 can be disposed on the insulating layer 142 and the second gate conductor. The insulating layer 160 can be referred to as an interlayer insulating layer. The insulating layer 160 can include an inorganic insulating material such as silicon oxide (SiO x ) and silicon nitride (SiN x ).

[0078] Data conductors that can include data lines 171, driving voltage lines 172, and source and drain electrodes S and D of the transistor TR can be disposed on the insulating layer 160. The source and drain electrodes S and D can be connected to source and drain regions of the semiconductor layer ACT, respectively, through contact holes formed in the insulating layers 141, 142, and 160. The data conductors can include aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta), etc. The data conductors can include a single layer or multiple layers.

[0079] The transistor TR can include a gate electrode G, source and drain electrodes S and D, and a semiconductor layer ACT. The gate electrode G can form a control terminal of the transistor TR, one of the source and drain electrodes S and D can form an input terminal, and the other of the source and drain electrodes S and D can form an output terminal. Because the gate electrode G can be disposed above the semiconductor layer ACT, the transistor TR can be a top-gate transistor. The transistor TR can be a bottom-gate transistor in which the gate electrode G can be disposed below the semiconductor layer ACT. The transistor TR can be a vertical transistor in which the source and drain electrodes can overlap or face each other.

[0080] Another insulating layer 181 can be disposed on the insulating layer 160 and the data conductors. The insulating layer 181 can be referred to as a passivation layer. The insulating layer 181 can include a material such as silicon oxide (SiOx ) and silicon nitride (SiN x ) and the like.

[0081] Another insulating layer 182 can be disposed on the insulating layer 181. The insulating layer 182 can be referred to as a planarization layer. The insulating layer 182 can planarize a surface on which light emitting diodes LEDs can be formed, thereby improving light emitting efficiency of the light emitting diodes LEDs. The insulating layer 182 can include an organic insulating material such as polyimide, an acrylic-based polymer, or a siloxane-based polymer.

[0082] The insulating layer 182 can include an opening 80 between adjacent pixels PX1, PX2, and PX3. The opening 80 can be a region in which a portion of the insulating layer 182 can be removed, and can correspond to a hatched region as shown in Figure 2 The opening 80 can be formed in a region of the insulating layer 182 that does not overlap or is offset from the pixels PX1, PX2, and PX3. The opening 80 can not overlap or be offset from the first electrode E1 or the emission member EM of the light emitting diode LED. For example, the opening 80 can be positioned at least about 1 µm from the emission member EM. The opening 80 can be formed to completely surround or be around a peripheral portion of at least one pixel PX1 in the pixel unit PU. For example, the opening 80 can completely surround or be around a peripheral portion of each of the emission member EM and the first electrode E1 that can be included in the pixel PX1.

[0083] The insulating layer 182 can be formed via coating and curing a polymer solution including materials such as solvents, initiators, and binders. It can be the case that, once the insulating layer 182 is formed, the material of the insulating layer 182, for example, decomposed material of the insulating layer 182, can be emitted as a gas during the rest of the manufacturing of the display device and / or during the use of the display device. This phenomenon can be referred to as outgassing. The emitted gas can propagate to the pixels PX1, PX2, and PX3. The propagation can cause shrinkage, which reduces the light emitting area of the pixels PX1, PX2, and PX3 by denaturing or deteriorating the second electrode E2 and / or the emission member EM of the pixels PX1, PX2, and PX3. Since the opening 80 is provided, the gas can escape through the opening 80 without propagating to the pixels PX1, PX2, and PX3. Since the gas can be smoothly emitted through the opening 80 once the insulating layer 182 can be formed, the amount of shrinkage of the light emitting area that can be caused by the outgassing can be suppressed. Since the area and / or volume of the insulating layer 182 can be reduced based on the formation of the opening 80, the outgassing of the insulating layer 182 itself can be reduced.

[0084] The insulating layer 181 between the data conductor and the insulating layer 182 can prevent the data conductor from being exposed through the opening 80 of the insulating layer 182. Thus, the data conductor can be prevented from being damaged or short-circuited with respect to another conductor.

[0085] The first electrode E1 of the light emitting diode LED can be disposed on the insulating layer 182. The first electrode E1 can be a pixel electrode. The first electrode E1 can be connected to the source electrode S or the drain electrode D through a contact hole 81 formed in the insulating layers 181 and 182. The contact hole 81 can be positioned separately from the opening 80 of the insulating layer 182. The contact hole 81 and the opening 80 of the insulating layer 182 can be formed together through the same process or at the same time. For example, the opening 80 and the contact hole 81 can be formed together in the insulating layer 182 through a photolithography process using one mask. Thus, separate formation of the opening 80 and the contact hole 81 can be avoided. However, since the contact hole 81 also extends through the insulating layer 181, a photolithography for forming the contact hole 81 in the insulating layer 181 can be required. The first electrode E1 can include a portion that overlaps or faces the contact hole 81 without overlapping the opening 80. In other words, the first electrode E1 can be offset from, and thus not aligned with, the opening 80.

[0086] The transistor TR to which the first electrode E1 can be connected can be a driving transistor, or the transistor TR can be a light emission control transistor that can be electrically connected to the driving transistor. The first electrode E1 can include a metal such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum neodymium (AlNd), aluminum nickel lanthanum (AlNiLa), and a metal alloy. The first electrode E1 can include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0087] Another insulating layer 190 having an opening 90 overlapping or facing the first electrode E1 can be disposed on the insulating layer 182. The opening 90 of the insulating layer 190 can define a region corresponding to the light emission region of each of the pixels PX1, PX2, and PX3. The insulating layer 190 can be referred to as a pixel definition layer. In Figure 2 In the middle, the gray shaded region can correspond to the opening 90 in which the insulating layer 190 can be removed. The insulating layer 190 can include an organic insulating material such as polyimide, polyacrylate, and polyamide. The insulating layer 190 can include a portion that contacts the insulating layer 181 via the opening 80 of the insulating layer 182.

[0088] An emission member EM can be disposed on the first electrode E1. The emission member EM can include a first organic common layer, an emission layer, and a second organic common layer that can be sequentially stacked. The first organic common layer can include at least one of a hole injection layer and a hole transport layer. The emission layer can include an organic material that uniquely emits a primary color such as red, green, and blue. The emission layer can have a structure in which layers of organic materials that emit different colors of light can be stacked. The emission layer can be a blue emission layer that emits blue light. The display device can include a color conversion layer and / or a color filter overlapping or facing the emission layer. The second organic common layer can include at least one of an electron transport layer and an electron injection layer.

[0089] A second electrode E2 can be disposed on the emission member EM. The second electrode E2 can be disposed over several pixels. With respect to a pixel, the second electrode E2 can be referred to as a common electrode. The second electrode E2 can be electrically connected to a common voltage line that can deliver a common voltage (ELVSS). The second electrode E2 can include a low work function metal such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), or a thin layer of silver (Ag) capable of achieving light transmission. The second electrode E2 can include a transparent conductive material such as ITO or IZO.

[0090] The first electrode E1, the emission member EM, and the second electrode E2 of each of the pixels PX1, PX2, and PX3 can form a light emitting diode LED, which can be an organic light emitting diode (OLED). Each of the pixels PX1, PX2, and PX3 can include a respective light emitting diode LED. The first electrode E1 can be an anode that is a hole injection electrode and the second electrode E2 can be a cathode that is an electron injection electrode, or vice versa. In a case where holes and electrons can be injected from the first electrode E1 and the second electrode E2 into the emission member EM, they can be emitted when excitons formed by the combination of the injected holes and electrons transition from an excited state to a ground state.

[0091] An encapsulation layer can be disposed on the second electrode E2. The encapsulation layer can encapsulate the light emitting diode LED to prevent moisture or oxygen from penetrating from the outside of the display device. The encapsulation layer can be stacked on the second electrode E2 or provided as a substrate.

[0092] As described, outgassing of the insulating layer 182 can not only occur during the manufacturing of the display device, but also during use after the manufacturing of the display device. In a case where the display device can be exposed to external light such as sunlight for a long period of time, as can occur in a vehicle, due to ultraviolet exposure, decomposition products can be emitted as a gas. Referring to Figure 5 In a case of a display device according to a comparative example in which an opening is not formed in the insulating layer 182, during evaluation of exposure to ultraviolet light at a high temperature (about 85°C), reliability of the display device with respect to shrinkage of the light emitting area of the pixels was ensured for about 280 hours, and after about 320 hours, a stain strongly appeared on the screen. However, according to the embodiment herein, even when exposed to ultraviolet light for about 400 hours under the same conditions as in the comparative example, the display device having the opening 80 formed in the insulating layer 182 had a color change (ΔT c ) that was determined to be at an acceptable level, and no stain appeared on the screen. Thus, according to the embodiment, it can be seen that damage to the pixels due to outgassing of the insulating layer 182, particularly shrinkage, can be prevented. Thus, the display device according to the embodiment can significantly improve reliability, and particularly sunlight reliability with respect to the amount of shrinkage caused by ultraviolet exposure.

[0093] Based on one pixel unit PU, the opening 80 of the insulating layer 182 can be formed differently than the opening 80 of the insulating layer 182 shown in Figure 2

[0094] Figures 6 to 10 Each shows a top view of a display area of a display device according to an embodiment. In each drawing, the hatched area corresponds to the opening 80 of the insulating layer 182. ​

[0095] Referring to Figure 6 The opening 80 of the insulating layer 182 can be formed around or around the periphery of each of the pixels PX1, PX2, and PX3. Accordingly, each of the pixels PX1, PX2, and PX3 can be divided or separated from each other by the opening 80. The first electrode E1 of each of the pixels PX1, PX2, and PX3 can also be surrounded by the opening 80. In other words, the opening 80 can be formed around or around the periphery of the first electrode E1 of each of the pixels PX1, PX2, and PX3. As described above, the opening 80 can be formed by removing the insulating layer 182 in the region of the insulating layer 182 that does not overlap with the first electrode E1, thereby reducing outgassing of the insulating layer 182 and improving gas emission. In the case where the insulating layer 181 can be formed under the insulating layer 182 to cover the data conductor, the data conductor can be prevented from being short-circuited with respect to another conductor. Otherwise, the data conductor can be damaged in the case where there is no coverage thereon.

[0096] Referring to Figure 7 The opening 80 of the insulating layer 182 can surround or around the periphery of two pixels PX1 and PX2 at the same time, and separately surround or around the periphery of one pixel PX3. For example, the pixels PX1 and PX2 can not be divided or separated based on the opening 80, and the insulating layer 182 can be continuously formed in the pixels PX1 and PX2. The pixel PX3 can be separated from the pixels PX1 and PX2 based on the opening 80.

[0097] Referring to Figure 8 The opening 80 of the insulating layer 182 can surround or around the periphery of two pixels PX1 and PX3 at the same time, and separately surround or around the periphery of one pixel PX2. For example, the pixels PX1 and PX3 can not be divided or separated based on the opening 80, but the pixel PX2 can be separated from the pixels PX1 and PX3 based on the opening 80. In other words, the opening 80 can be outside a region between the pixels PX1 and PX3, where the region can include a sub-region along which the pixels PX1 and PX3 overlap or face each other in a plan view. Accordingly, the insulating layer 182 can be continuously formed on the pixels PX1 and PX3.

[0098] Referring to Figure 9The opening 80 of the insulating layer 182 can surround or be around the periphery of both of the pixels PX2 and PX3, and separately surround or be around the periphery of one of the pixels PX1. The pixels PX2 and PX3 can not be divided or separated based on the opening 80, but the pixel PX1 can be separated from the pixels PX2 and PX3 based on the opening 80. Accordingly, the insulating layer 182 can be continuously formed on the pixels PX2 and PX3.

[0099] Referring to Figure 10 The opening 80 of the insulating layer 182 can surround or be around the periphery of all of the three pixels PX1, PX2, and PX3. Accordingly, the three pixels PX1, PX2, and PX3 can not be divided or separated from each other due to the opening 80, although the adjacent pixel units PU can be separated from the three pixels PX1, PX2, and PX3 based on the opening 80. Accordingly, the insulating layer 182 can be continuously formed on the pixels PX1, PX2, and PX3.

[0100] Depending on the pixel design such as the number, arrangement, and shape of the pixels included in one pixel unit PU, the area in which the opening 80 can be formed in the insulating layer 182 and defined by the opening 80 can be variously changed.

[0101] Figure 11 A plan view of a display area according to an embodiment is illustrated, and Figure 12 and Figure 13 each illustrates a schematic cross-sectional view taken along the line C-C’ of Figure 11 In Figure 11 , the gray-shaded area can define an area in which the insulating layer 190 can be removed.

[0102] Referring to Figure 11 and Figure 12 The display apparatus differs from the display apparatus of the above-described embodiments in terms of the shape of the insulating layer 190. The insulating layer 190 can include a groove 91, such as a trench, in an area overlapping the opening 80 of the insulating layer 182. The insulating layer 190 can not be completely separated based on the groove 91, thereby including a continuous portion of the insulating layer 190 on either side of the groove 91. The lower end of the groove 91 can be slightly apart from the insulating layer 181. The second electrode E2 can be disposed in or on the groove 91, and can not be in contact with the insulating layer 181 or the insulating layer 182.

[0103] Thus, in the case where the recess 91 can be formed in the insulating layer 190, the gas discharged through the opening 80 of the insulating layer 182 can be prevented from propagating to the pixels PX1, PX2, and PX3 through the insulating layer 190, and thus, can not be discharged to the outside. Since the volume of the insulating layer 190 can be reduced due to the formation of the recess 91, the outgassing of the insulating layer 190, which can be formed of an organic insulating material, can be reduced.

[0104] Referring to Figure 13 , the insulating layer 190 can include an opening 92 in a region overlapping or facing the opening 80 of the insulating layer 182. Unlike the recess 91 shown in Figure 12 , the opening 92 can be formed to penetrate the insulating layer 190 through the thickness direction of the insulating layer 190. In a plan view, the opening 92 can be located within the opening 80. The second electrode E2 can include a portion contacting the insulating layer 181 based on the opening 92 of the insulating layer 190. Thus, in the case where the opening 92 can be formed in the insulating layer 190, the gas that can be discharged through the opening 80 of the insulating layer 182 can be prevented from propagating to the pixels PX1, PX2, and PX3 through the insulating layer 190 due to the portion of the second electrode E2 contacting the insulating layer 181. Since the volume of the insulating layer 190 can be reduced based on the formation of the opening 92, the outgassing of the insulating layer 190, which can be formed of an organic insulating material, can be reduced.

[0105] Figure 14 The graph shown in the drawing shows the result of evaluating the light emitting area ratio depending on the reduction in the thickness of the insulating layer.

[0106] Figure 14 The graph of FIG. 1 shows how much the light emitting area of the blue pixel can be reduced in the case where the thickness of the insulating layer 190 and / or the insulating layer 182 can be reduced in the display device according to the embodiment, in which the insulating layer 190 and / or the insulating layer 182 can each include an organic insulating material. In the graph, the light emitting area ratio representing no shrinkage can be represented as 100%.

[0107] REF indicates the case where the insulating layer 182, which can be a planarization layer, can be formed to have a thickness of about 2.15 μm, and the insulating layer 190, which can be a pixel definition layer, can be formed to have a thickness of about 4.05 μm, and the average value of the light emitting area ratio can be about 79%. This indicates that the shrinkage occurs to reduce the light emitting area ratio by about 21%.

[0108] T1 indicates a case where the thickness of the insulating layer 182 can be maintained (at about 2.15 μm), and the thickness of the insulating layer 190 can be reduced to about 3.0 μm, and the average value of the light emitting area ratio can be about 86%. T2 indicates a case where the thickness of the insulating layer 190 can be maintained (at about 4.05 μm), and the thickness of the insulating layer 182 can be reduced to about 1.5 μm, and the average value of the light emitting area ratio can be about 89%. Although the insulating layer 190 can be thicker than the insulating layer 182, the opening 90 overlapping or facing the first electrode E1 can be formed in the insulating layer 190. Thus, the volume reduction caused by the thickness reduction of the insulating layer 182 and the inhibition of outgassing caused thereby based on the opening 80 in the insulating layer 182 can be greater than in the insulating layer 190. For this reason, the light emitting area ratio caused by the thickness reduction of the insulating layer 182 can be higher than that caused by the thickness reduction of the insulating layer 190.

[0109] T3 indicates a case where the thickness of the insulating layer 190 can be reduced to about 3.0 μm, and the thickness of the insulating layer 182 can be reduced to about 1.5 μm, and the average value of the light emitting area ratio can be about 96%. As compared with a case where the thickness of only one of the insulating layers 182 and 190 can be reduced, in a case where the thickness of both of the insulating layers 182 and 190 can be reduced, it is possible to further inhibit the light emitting area reduction. Thus, the volume of the insulating layer 182 and / or the insulating layer 190 can be reduced by forming the opening 80 and the opening 92 and / or the groove 91 in the insulating layer 182 and the insulating layer 190, respectively, thereby inhibiting the outgassing and shrinkage of the light emitting area.

[0110] While the disclosure has been described in connection with embodiments thereof, it will be understood that the embodiments are not limited by the description provided and are instead intended to cover any modifications and equivalents included within the spirit and scope of the disclosure.

Claims

1. A display device comprising: a substrate; a transistor provided over the substrate; a first insulating layer provided over the transistor; a first pixel electrode and a second pixel electrode provided over the first insulating layer adjacent to each other; and a third insulating layer provided over the first insulating layer, wherein the first insulating layer includes an organic insulating material, and the first insulating layer includes a first opening provided between the first pixel electrode and the second pixel electrode and penetrating the first insulating layer, and wherein the third insulating layer fills the first opening and contacts a side surface of the first insulating layer in the first opening, to cause the first insulating layer to be broken at the first opening.

2. The display device according to claim 1, wherein the first pixel electrode does not overlap with the first opening, and the second pixel electrode does not overlap with the first opening.

3. The display device according to claim 1, wherein the first insulating layer includes a contact hole overlapping with a source electrode or a drain electrode of the transistor, and the first opening is spaced apart from the contact hole.

4. The display device according to claim 1, wherein the first opening is around a periphery of at least one of the first pixel electrode and the second pixel electrode. the display device further comprises:

5. The display device according to claim 1, wherein a third pixel electrode provided over the first insulating layer adjacent to the first pixel electrode and the second pixel electrode, wherein the first opening is provided outside a region between the first pixel electrode and the third pixel electrode.

6. The display device according to claim 5, wherein in a plan view, the first insulating layer is continuously provided under the first pixel electrode and the third pixel electrode. the display device further comprises:

7. The display device according to claim 1, wherein a second insulating layer provided between the transistor and the first insulating layer, wherein the second insulating layer includes a portion overlapping with the first opening.

8. The display device according to claim 7, wherein the third insulating layer includes a second opening overlapping with the first pixel electrode and the second pixel electrode, and the third insulating layer includes a portion contacting the second insulating layer in the first opening.

9. The display device according to claim 8, wherein the third insulating layer includes a groove overlapping with the first opening.

10. The display device according to claim 7, wherein the third insulating layer includes a second opening overlapping with the first pixel electrode and the second pixel electrode, and the third insulating layer includes a third opening overlapping with the first opening. the display device further comprises:

11. The display device of claim 10, wherein, a first emission member provided over the first pixel electrode; a second emission member provided over the second pixel electrode; and a common electrode provided over the first emission member and the second emission member, wherein the common electrode includes a portion contacting the second insulating layer through the third opening.

12. A display device comprising: a substrate; a transistor provided over the substrate; a first insulating layer provided over the transistor; ​ a first light-emitting diode and a second light-emitting diode are provided on the first insulating layer adjacent to each other; and a third insulating layer is provided on the first insulating layer, wherein the first insulating layer includes an organic insulating material and includes an opening between a first emission member of the first light-emitting diode and a second emission member of the second light-emitting diode and penetrating the organic insulating layer, and wherein the third insulating layer fills the opening and contacts a side surface of the first insulating layer in the opening, so that the first insulating layer is broken at the opening.

13. The display device of claim 12, wherein, The display device further includes: a second insulating layer is provided between the transistor and the first insulating layer, wherein the second insulating layer includes a portion overlapping the opening.

14. The display device according to claim 13, wherein the first insulating layer and the second insulating layer each include a contact hole overlapping a source electrode or a drain electrode of the transistor, and the opening is spaced apart from the contact hole.

15. The display device of claim 14, wherein, The first light-emitting diode includes: a first electrode provided on the first insulating layer; and a second electrode provided on the first emission member, wherein the first electrode is connected to the source electrode or the drain electrode through the contact hole.

16. The display device according to claim 15, wherein the first electrode does not overlap the opening.

17. The display device according to claim 15, wherein the opening is around a periphery of the first electrode.

18. The display device of claim 12, wherein, The display device further includes: a third light-emitting diode provided on the first insulating layer adjacent to the first light-emitting diode and the second light-emitting diode, wherein the third light-emitting diode includes a third emission member, and the opening is provided outside a region between the first emission member and the third emission member.

19. The display device according to claim 18, wherein in a plan view, the first insulating layer is continuously provided under the first emission member and the third emission member.

20. The display device according to claim 13, wherein the third insulating layer includes a portion contacting the second insulating layer in the opening.

21. The display device according to claim 20, wherein the third insulating layer includes a recess or an opening, and the recess or the opening of the third insulating layer overlaps the opening of the first insulating layer.

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